diff --git a/src/drivers/rp-reset.adb b/src/devices/rp2040/rp-reset.adb similarity index 100% rename from src/drivers/rp-reset.adb rename to src/devices/rp2040/rp-reset.adb diff --git a/src/drivers/rp-reset.ads b/src/devices/rp2040/rp-reset.ads similarity index 100% rename from src/drivers/rp-reset.ads rename to src/devices/rp2040/rp-reset.ads diff --git a/src/drivers/rp-rtc.adb b/src/devices/rp2040/rp-rtc.adb similarity index 100% rename from src/drivers/rp-rtc.adb rename to src/devices/rp2040/rp-rtc.adb diff --git a/src/drivers/rp-rtc.ads b/src/devices/rp2040/rp-rtc.ads similarity index 100% rename from src/drivers/rp-rtc.ads rename to src/devices/rp2040/rp-rtc.ads diff --git a/src/devices/rp2350/rp-device.ads b/src/devices/rp2350/rp-device.ads index ba82dcf..e83303d 100644 --- a/src/devices/rp2350/rp-device.ads +++ b/src/devices/rp2350/rp-device.ads @@ -3,6 +3,60 @@ -- -- SPDX-License-Identifier: BSD-3-Clause -- +with RP2040_SVD.SPI; +with RP2040_SVD.I2C; +with RP2040_SVD.UART; +with RP2350_SVD; +with RP.I2C; +with RP.I2C_Master; +with RP.SPI; +with RP.UART; +with RP.Timer.Interrupts; +with RP.PIO; + package RP.Device is + SPI0_Periph : aliased RP2040_SVD.SPI.SPI_Peripheral + with Import, Address => RP2350_SVD.SPI0_Base; + SPI1_Periph : aliased RP2040_SVD.SPI.SPI_Peripheral + with Import, Address => RP2350_SVD.SPI1_Base; + + SPI_0 : aliased RP.SPI.SPI_Port (0, SPI0_Periph'Access); + SPI_1 : aliased RP.SPI.SPI_Port (1, SPI1_Periph'Access); + + I2C0_Periph : aliased RP2040_SVD.I2C.I2C_Peripheral + with Import, Address => RP2350_SVD.I2C0_Base; + I2C1_Periph : aliased RP2040_SVD.I2C.I2C_Peripheral + with Import, Address => RP2350_SVD.I2C1_Base; + + I2C_0 : aliased RP.I2C.I2C_Port (0, I2C0_Periph'Access); + I2C_1 : aliased RP.I2C.I2C_Port (1, I2C1_Periph'Access); + + I2CM_0 : aliased RP.I2C_Master.I2C_Master_Port (0, I2C0_Periph'Access); + I2CM_1 : aliased RP.I2C_Master.I2C_Master_Port (1, I2C1_Periph'Access); + + UART0_Periph : aliased RP2040_SVD.UART.UART_Peripheral + with Import, Address => RP2350_SVD.UART0_Base; + UART1_Periph : aliased RP2040_SVD.UART.UART_Peripheral + with Import, Address => RP2350_SVD.UART1_Base; + + UART_0 : aliased RP.UART.UART_Port (0, UART0_Periph'Access); + UART_1 : aliased RP.UART.UART_Port (1, UART1_Periph'Access); + + Timer_0 : aliased RP.Timer.Interrupts.Delays; + Timer_1 : aliased RP.Timer.Interrupts.Delays; + Timer : RP.Timer.Interrupts.Delays renames Timer_0; + -- RP2040 only had one timer, rename it to Timer_0 here. RP2350 timers have + -- new registers too, but we don't do anything with that yet. + + PIO0_Periph : aliased RP.PIO.PIO_Peripheral + with Import, Address => RP2350_SVD.PIO0_Base; + PIO1_Periph : aliased RP.PIO.PIO_Peripheral + with Import, Address => RP2350_SVD.PIO1_Base; + PIO2_Periph : aliased RP.PIO.PIO_Peripheral + with Import, Address => RP2350_SVD.PIO2_Base; + + PIO_0 : aliased RP.PIO.PIO_Device (0, PIO0_Periph'Access); + PIO_1 : aliased RP.PIO.PIO_Device (1, PIO1_Periph'Access); + PIO_2 : aliased RP.PIO.PIO_Device (2, PIO2_Periph'Access); end RP.Device; diff --git a/src/drivers/rp-gpio.adb b/src/devices/rp2350/rp-gpio.adb similarity index 98% rename from src/drivers/rp-gpio.adb rename to src/devices/rp2350/rp-gpio.adb index 65ba6f3..1ef1ef0 100644 --- a/src/drivers/rp-gpio.adb +++ b/src/devices/rp2350/rp-gpio.adb @@ -26,9 +26,9 @@ package body RP.GPIO is -- on these pads. This is unlikely to cause a problem as the digital -- inputs have hysteresis enabled by default. - for Pin in ADC_Pin'Range loop - PADS_BANK_Periph.GPIO (Pin).IE := False; - PADS_BANK_Periph.GPIO (Pin).OD := True; + for Pin in 26 .. 29 loop + PADS_BANK_Periph.GPIO (GPIO_Pin (Pin)).IE := False; + PADS_BANK_Periph.GPIO (GPIO_Pin (Pin)).OD := True; end loop; -- Mask all pin interrupts diff --git a/src/drivers/rp-gpio.ads b/src/devices/rp2350/rp-gpio.ads similarity index 84% rename from src/drivers/rp-gpio.ads rename to src/devices/rp2350/rp-gpio.ads index 0bc83c0..747e548 100644 --- a/src/drivers/rp-gpio.ads +++ b/src/devices/rp2350/rp-gpio.ads @@ -4,17 +4,18 @@ -- SPDX-License-Identifier: BSD-3-Clause -- -with RP2040_SVD.IO_BANK0; use RP2040_SVD.IO_BANK0; -with RP2040_SVD.PADS_BANK0; use RP2040_SVD.PADS_BANK0; -with RP2040_SVD; use RP2040_SVD; +with RP2350_SVD.IO_BANK0; use RP2350_SVD.IO_BANK0; +with RP2350_SVD.PADS_BANK0; use RP2350_SVD.PADS_BANK0; +with RP2350_SVD; use RP2350_SVD; with HAL; use HAL; with HAL.GPIO; use HAL.GPIO; package RP.GPIO with Preelaborate is - type GPIO_Pin is range 0 .. 29; - subtype ADC_Pin is GPIO_Pin range 26 .. 29; + type GPIO_Pin is range 0 .. 47; + subtype ADC_Pin is GPIO_Pin + with Static_Predicate => ADC_Pin in 26 .. 29 | 40 .. 47; type GPIO_Point is new HAL.GPIO.GPIO_Point with record @@ -23,24 +24,39 @@ is type GPIO_Config_Mode is (Input, Output, Analog); - type GPIO_Function is - (SPI, UART, I2C, PWM, SIO, PIO0, PIO1, CLOCK, USB, HI_Z); - type GPIO_Pull_Mode is (Floating, Pull_Up, Pull_Down, Pull_Both); type GPIO_Drive is (Drive_2mA, Drive_4mA, Drive_8mA, Drive_12mA); + type GPIO_Function is + (HSTX, + SPI, + UART, + I2C, + PWM, + SIO, + PIO0, + PIO1, + PIO2, + CLOCK, + USB, + UART_ALT, + HI_Z); + for GPIO_Function use - (SPI => 1, - UART => 2, - I2C => 3, - PWM => 4, - SIO => 5, - PIO0 => 6, - PIO1 => 7, - CLOCK => 8, - USB => 9, - HI_Z => 31); + (HSTX => 0, + SPI => 1, + UART => 2, + I2C => 3, + PWM => 4, + SIO => 5, + PIO0 => 6, + PIO1 => 7, + PIO2 => 8, + CLOCK => 9, + USB => 10, + UART_ALT => 11, + HI_Z => 31); type Interrupt_Triggers is (Low_Level, High_Level, Falling_Edge, Rising_Edge) with Size => 4; @@ -187,10 +203,10 @@ private end record with Volatile; for IO_BANK use record - GPIO at 16#0000# range 0 .. 1919; + GPIO at 16#0000# range 0 .. 3071; end record; - type PADS_BANK_GPIO_Registers is array (GPIO_Pin) of RP2040_SVD.PADS_BANK0.GPIO_Register; + type PADS_BANK_GPIO_Registers is array (GPIO_Pin) of RP2350_SVD.PADS_BANK0.GPIO_Register; type PADS_BANK is record VOLTAGE_SELECT : VOLTAGE_SELECT_Register; diff --git a/src/devices/rp2350/rp-reset.adb b/src/devices/rp2350/rp-reset.adb new file mode 100644 index 0000000..9049f34 --- /dev/null +++ b/src/devices/rp2350/rp-reset.adb @@ -0,0 +1,61 @@ +-- +-- Copyright 2021 (C) Jeremy Grosser +-- +-- SPDX-License-Identifier: BSD-3-Clause +-- +with RP2040_SVD; +with RP.Timer; + +package body RP.Reset is + + type RESET_Register is array (Reset_Id) of Boolean + with Component_Size => 1, + Size => 32; + + type RESETS_Peripheral is record + RESET : aliased RESET_Register; + WDSEL : aliased RESET_Register; + RESET_DONE : aliased RESET_Register; + end record + with Volatile; + + for RESETS_Peripheral use record + RESET at 0 range 0 .. 31; + WDSEL at 4 range 0 .. 31; + RESET_DONE at 8 range 0 .. 31; + end record; + + RESETS_Periph : aliased RESETS_Peripheral + with Import, Address => RP2040_SVD.RESETS_Base; + + procedure Reset_Peripheral + (Peripheral : Reset_Id) + is + begin + RESETS_Periph.RESET (Peripheral) := True; + RESETS_Periph.RESET (Peripheral) := False; + while not RESETS_Periph.RESET_DONE (Peripheral) loop + null; + end loop; + end Reset_Peripheral; + + procedure Reset_Peripheral + (Peripheral : Reset_Id; + Status : out Reset_Status; + Timeout : Natural := 100) + is + use RP.Timer; + Deadline : constant Time := Clock + Milliseconds (Timeout); + begin + RESETS_Periph.RESET (Peripheral) := True; + RESETS_Periph.RESET (Peripheral) := False; + while not RESETS_Periph.RESET_DONE (Peripheral) loop + if Timeout > 0 and then Clock >= Deadline then + Status := Reset_Timeout; + return; + end if; + end loop; + Status := Reset_Ok; + end Reset_Peripheral; + +end RP.Reset; diff --git a/src/devices/rp2350/rp-reset.ads b/src/devices/rp2350/rp-reset.ads new file mode 100644 index 0000000..c716684 --- /dev/null +++ b/src/devices/rp2350/rp-reset.ads @@ -0,0 +1,57 @@ +-- +-- Copyright 2021 (C) Jeremy Grosser +-- +-- SPDX-License-Identifier: BSD-3-Clause +-- +package RP.Reset + with Preelaborate +is + + type Reset_Id is + (Reset_ADC, + Reset_BUSCTRL, + Reset_DMA, + Reset_HSTX, + Reset_I2C0, + Reset_I2C1, + Reset_IO_BANK0, + Reset_QSPI, + Reset_JTAG, + Reset_PADS_BANK0, + Reset_PADS_QSPI, + Reset_PIO0, + Reset_PIO1, + Reset_PIO2, + Reset_PLL_SYS, + Reset_PLL_USB, + Reset_PWM, + Reset_SHA256, + Reset_SPI0, + Reset_SPI1, + Reset_SYSCFG, + Reset_SYSINFO, + Reset_TBMAN, + Reset_TIMER0, + Reset_TIMER1, + Reset_TRNG, + Reset_UART0, + Reset_UART1, + Reset_USBCTRL); + + type Reset_Status is + (Reset_Ok, + Reset_Timeout); + + -- This will hang if the reset fails. Most drivers use this version. + procedure Reset_Peripheral + (Peripheral : Reset_Id); + + -- Timeout is specified in Milliseconds. No peripheral should take more + -- than a few cycles to reset. + procedure Reset_Peripheral + (Peripheral : Reset_Id; + Status : out Reset_Status; + Timeout : Natural := 100) + with Pre => Peripheral /= Reset_TIMER0; + +end RP.Reset; diff --git a/src/drivers/rp-pio-audio_i2s.adb b/src/drivers/rp-pio-audio_i2s.adb index 44a6036..8c04272 100644 --- a/src/drivers/rp-pio-audio_i2s.adb +++ b/src/drivers/rp-pio-audio_i2s.adb @@ -78,7 +78,7 @@ package body RP.PIO.Audio_I2S is Set_Enabled (This.PIO.all, This.SM, True); DMA_Config.Trigger := DMA_Request_Trigger'Val - (DMA_Request_Trigger'Pos (PIO0_TX0) + (This.PIO.Num * 8) + Natural (This.SM)); + (DMA_Request_Trigger'Pos (PIO0_TX0) + (Natural (This.PIO.Num) * 8) + Natural (This.SM)); if Channels = 1 then DMA_Config.Data_Size := Transfer_16; else diff --git a/src/drivers/rp-pio.adb b/src/drivers/rp-pio.adb index dbf22f2..4930003 100644 --- a/src/drivers/rp-pio.adb +++ b/src/drivers/rp-pio.adb @@ -6,7 +6,6 @@ with Ada.Unchecked_Conversion; with RP.Clock; with RP.Reset; -with RP2040_SVD.Interrupts; package body RP.PIO is procedure Enable @@ -17,6 +16,7 @@ package body RP.PIO is case This.Num is when 0 => Reset_Peripheral (Reset_PIO0); when 1 => Reset_Peripheral (Reset_PIO1); + when 2 => Reset_Peripheral (Reset_PIO2); end case; end Enable; @@ -254,6 +254,7 @@ package body RP.PIO is case PIO.Num is when 0 => return RP.GPIO.PIO0; when 1 => return RP.GPIO.PIO1; + when 2 => return RP.GPIO.PIO2; end case; end GPIO_Function; @@ -513,22 +514,7 @@ package body RP.PIO is (This : PIO_Device; IRQ : PIO_IRQ_ID) return Cortex_M.NVIC.Interrupt_ID - is - use RP2040_SVD.Interrupts; - begin - case This.Num is - when 0 => - case IRQ is - when 0 => return PIO0_IRQ_0_Interrupt; - when 1 => return PIO0_IRQ_1_Interrupt; - end case; - when 1 => - case IRQ is - when 0 => return PIO1_IRQ_0_Interrupt; - when 1 => return PIO1_IRQ_1_Interrupt; - end case; - end case; - end NVIC_IRQ_Line; + is (Cortex_M.NVIC.Interrupt_ID (This.Interrupt_Base + (Natural (This.Num) * 2) + Natural (IRQ))); procedure Enable_IRQ (This : in out PIO_Device; IRQ : PIO_IRQ_ID) @@ -666,12 +652,12 @@ package body RP.PIO is (This : PIO_Device; SM : PIO_SM) return RP.DMA.DMA_Request_Trigger - is (RP.DMA.DMA_Request_Trigger'Val (This.Num * 8 + Natural (SM))); + is (RP.DMA.DMA_Request_Trigger'Val (Natural (This.Num) * 8 + Natural (SM))); function DMA_RX_Trigger (This : PIO_Device; SM : PIO_SM) return RP.DMA.DMA_Request_Trigger - is (RP.DMA.DMA_Request_Trigger'Val (This.Num * 8 + Natural (SM) + 4)); + is (RP.DMA.DMA_Request_Trigger'Val (Natural (This.Num) * 8 + Natural (SM) + 4)); end RP.PIO; diff --git a/src/drivers/rp-pio.ads b/src/drivers/rp-pio.ads index c50ee5c..2e4730f 100644 --- a/src/drivers/rp-pio.ads +++ b/src/drivers/rp-pio.ads @@ -15,11 +15,13 @@ package RP.PIO with Preelaborate is type PIO_Peripheral is private; - subtype PIO_Number is Natural range 0 .. 1; + type PIO_Number is range 0 .. 2; type PIO_Device (Num : PIO_Number; Periph : not null access PIO_Peripheral) - is tagged null record; + is tagged record + Interrupt_Base : Natural := 7; + end record; type PIO_SM is range 0 .. 3; type PIO_SM_Mask is array (PIO_SM) of Boolean diff --git a/src/svd/handler.S b/src/svd/handler.S new file mode 100644 index 0000000..c672dad --- /dev/null +++ b/src/svd/handler.S @@ -0,0 +1,110 @@ +## -*- asm -*- ############################# +# Automatically generated by SVD2Ada +# For the target +############################################ + + .syntax unified + .cpu cortex-m4 + .thumb + + .text + .globl __vectors + .p2align 8 +__vectors: + /* Cortex-M core interrupts */ + .word 0 /* stack top address */ + .word fault /* 1 Reset. */ + .word fault /* 2 NMI. */ + .word fault /* 3 Hard fault. */ + .word fault /* 4 Mem manage. */ + .word fault /* 5 Bus fault. */ + .word fault /* 6 Usage fault. */ + .word fault /* 7 reserved. */ + .word fault /* 8 reserved. */ + .word fault /* 9 reserved. */ + .word fault /* 10 reserved. */ + .word __gnat_sv_call_trap /* 11 SVCall. */ + .word __gnat_bkpt_trap /* 12 Breakpoint. */ + .word fault /* 13 reserved. */ + .word __gnat_pend_sv_trap /* 14 PendSV. */ + .word __gnat_sys_tick_trap /* 15 Systick. */ + /* MCU interrupts */ + .word __gnat_irq_trap /* 16 TIMER0_IRQ_0 */ + .word __gnat_irq_trap /* 17 TIMER0_IRQ_1 */ + .word __gnat_irq_trap /* 18 TIMER0_IRQ_2 */ + .word __gnat_irq_trap /* 19 TIMER0_IRQ_3 */ + .word __gnat_irq_trap /* 20 TIMER1_IRQ_0 */ + .word __gnat_irq_trap /* 21 TIMER1_IRQ_1 */ + .word __gnat_irq_trap /* 22 TIMER1_IRQ_2 */ + .word __gnat_irq_trap /* 23 TIMER1_IRQ_3 */ + .word __gnat_irq_trap /* 24 PWM_IRQ_WRAP_0 */ + .word __gnat_irq_trap /* 25 PWM_IRQ_WRAP_1 */ + .word __gnat_irq_trap /* 26 DMA_IRQ_0 */ + .word __gnat_irq_trap /* 27 DMA_IRQ_1 */ + .word __gnat_irq_trap /* 28 DMA_IRQ_2 */ + .word __gnat_irq_trap /* 29 DMA_IRQ_3 */ + .word __gnat_irq_trap /* 30 USBCTRL_IRQ */ + .word __gnat_irq_trap /* 31 PIO0_IRQ_0 */ + .word __gnat_irq_trap /* 32 PIO0_IRQ_1 */ + .word __gnat_irq_trap /* 33 PIO1_IRQ_0 */ + .word __gnat_irq_trap /* 34 PIO1_IRQ_1 */ + .word __gnat_irq_trap /* 35 PIO2_IRQ_0 */ + .word __gnat_irq_trap /* 36 PIO2_IRQ_1 */ + .word __gnat_irq_trap /* 37 IO_IRQ_BANK0 */ + .word __gnat_irq_trap /* 38 IO_IRQ_BANK0_NS */ + .word __gnat_irq_trap /* 39 IO_IRQ_QSPI */ + .word __gnat_irq_trap /* 40 IO_IRQ_QSPI_NS */ + .word __gnat_irq_trap /* 41 SIO_IRQ_FIFO */ + .word __gnat_irq_trap /* 42 SIO_IRQ_BELL */ + .word __gnat_irq_trap /* 43 SIO_IRQ_FIFO_NS */ + .word __gnat_irq_trap /* 44 SIO_IRQ_BELL_NS */ + .word __gnat_irq_trap /* 45 SIO_IRQ_MTIMECMP */ + .word __gnat_irq_trap /* 46 CLOCKS_IRQ */ + .word __gnat_irq_trap /* 47 SPI0_IRQ */ + .word __gnat_irq_trap /* 48 SPI1_IRQ */ + .word __gnat_irq_trap /* 49 UART0_IRQ */ + .word __gnat_irq_trap /* 50 UART1_IRQ */ + .word __gnat_irq_trap /* 51 ADC_IRQ_FIFO */ + .word __gnat_irq_trap /* 52 I2C0_IRQ */ + .word __gnat_irq_trap /* 53 I2C1_IRQ */ + .word __gnat_irq_trap /* 54 OTP_IRQ */ + .word __gnat_irq_trap /* 55 TRNG_IRQ */ + .word __gnat_irq_trap /* 56 IRQ 40. */ + .word __gnat_irq_trap /* 57 IRQ 41. */ + .word __gnat_irq_trap /* 58 PLL_SYS_IRQ */ + .word __gnat_irq_trap /* 59 PLL_USB_IRQ */ + .word __gnat_irq_trap /* 60 POWMAN_IRQ_POW */ + .word __gnat_irq_trap /* 61 POWMAN_IRQ_TIMER */ + + .text + + .thumb_func +.weak __gnat_irq_trap +.type __gnat_irq_trap, %function +__gnat_irq_trap: +0: b 0b + .size __gnat_irq_trap, . - __gnat_irq_trap + + .thumb_func +.weak __gnat_sv_call_trap +.type __gnat_sv_call_trap, %function +__gnat_sv_call_trap: +0: b 0b + .size __gnat_sv_call_trap, . - __gnat_sv_call_trap + + .thumb_func +.weak __gnat_pend_sv_trap +.type __gnat_pend_sv_trap, %function +__gnat_pend_sv_trap: +0: b 0b + .size __gnat_pend_sv_trap, . - __gnat_pend_sv_trap + + .thumb_func +.weak __gnat_sys_tick_trap +.type __gnat_sys_tick_trap, %function +__gnat_sys_tick_trap: +0: b 0b + .size __gnat_sys_tick_trap, . - __gnat_sys_tick_trap + + .thumb_func +fault: b fault diff --git a/src/svd/rp2350_svd-accessctrl.ads b/src/svd/rp2350_svd-accessctrl.ads new file mode 100644 index 0000000..d123a36 --- /dev/null +++ b/src/svd/rp2350_svd-accessctrl.ads @@ -0,0 +1,3180 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Hardware access control registers +package RP2350_SVD.ACCESSCTRL is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- LOCK_CORE array + type LOCK_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for LOCK_CORE + type LOCK_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : LOCK_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for LOCK_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from + -- that master. LOCK is writable only by a Secure, Privileged processor or + -- debugger. LOCK bits are only writable when their value is zero. Once + -- set, they can never be cleared, except by a full reset of ACCESSCTRL + -- Setting the LOCK bit does not affect whether an access raises a bus + -- error. Unprivileged writes, or writes from the DMA, will continue to + -- raise bus errors. All other accesses will continue not to. + type LOCK_Register is record + CORE : LOCK_CORE_Field := (As_Array => False, Val => 16#0#); + -- Read-only. + DMA : Boolean := True; + DEBUG : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCK_Register use record + CORE at 0 range 0 .. 1; + DMA at 0 range 2 .. 2; + DEBUG at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Force core 1's bus accesses to always be Non-secure, no matter the + -- core's internal state. Useful for schemes where one core is designated + -- as the Non-secure core, since some peripherals may filter individual + -- registers internally based on security state but not on master ID. + type FORCE_CORE_NS_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + CORE1 : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FORCE_CORE_NS_Register use record + Reserved_0_0 at 0 range 0 .. 0; + CORE1 at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and + -- FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to + -- quickly restore ACCESSCTRL to a known state during the boot path. Note + -- that, like all registers in ACCESSCTRL, this register is not writable + -- when the writer's corresponding LOCK bit is set, therefore a master + -- which has been locked out of ACCESSCTRL can not use the CFGRESET + -- register to disturb its contents. + type CFGRESET_Register is record + -- Write-only. + CFGRESET : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFGRESET_Register use record + CFGRESET at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype GPIO_NSMASK1_GPIO_Field is HAL.UInt16; + subtype GPIO_NSMASK1_QSPI_SD_Field is HAL.UInt4; + + -- Control whether GPIO32..47 are accessible to Non-secure code, and + -- whether QSPI and USB bitbang are accessible through the Non-secure SIO. + -- Writable only by a Secure, Privileged processor or debugger. + type GPIO_NSMASK1_Register is record + GPIO : GPIO_NSMASK1_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + USB_DP : Boolean := False; + USB_DM : Boolean := False; + QSPI_SCK : Boolean := False; + QSPI_CSN : Boolean := False; + QSPI_SD : GPIO_NSMASK1_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_NSMASK1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + -- ROM_CORE array + type ROM_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for ROM_CORE + type ROM_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : ROM_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for ROM_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access ROM, and at + -- what security/privilege levels they can do so. Defaults to fully open + -- access. This register is writable only from a Secure, Privileged + -- processor or debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type ROM_Register is record + -- If 1, and NSP is also set, ROM can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := True; + -- If 1, ROM can be accessed from a Non-secure, Privileged context. + NSP : Boolean := True; + -- If 1, and SP is also set, ROM can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, ROM can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, ROM can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : ROM_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, ROM can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, ROM can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ROM_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- XIP_MAIN_CORE array + type XIP_MAIN_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for XIP_MAIN_CORE + type XIP_MAIN_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : XIP_MAIN_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for XIP_MAIN_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, + -- and at what security/privilege levels they can do so. Defaults to fully + -- open access. This register is writable only from a Secure, Privileged + -- processor or debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type XIP_MAIN_Register is record + -- If 1, and NSP is also set, XIP_MAIN can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := True; + -- If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + NSP : Boolean := True; + -- If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, XIP_MAIN can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : XIP_MAIN_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, XIP_MAIN can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, XIP_MAIN can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XIP_MAIN_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- SRAM_CORE array + type SRAM_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SRAM_CORE + type SRAM_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : SRAM_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SRAM_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and + -- at what security/privilege levels they can do so. Defaults to fully open + -- access. This register is writable only from a Secure, Privileged + -- processor or debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type SRAM_Register is record + -- If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := True; + -- If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := True; + -- If 1, and SP is also set, SRAM0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, SRAM0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, SRAM0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : SRAM_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, SRAM0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, SRAM0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SRAM_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- DMA_CORE array + type DMA_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DMA_CORE + type DMA_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : DMA_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DMA_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access DMA, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type DMA_Register is record + -- If 1, and NSP is also set, DMA can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, DMA can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, DMA can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, DMA can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, DMA can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : DMA_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, DMA can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, DMA can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DMA_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- USBCTRL_CORE array + type USBCTRL_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for USBCTRL_CORE + type USBCTRL_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : USBCTRL_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for USBCTRL_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type USBCTRL_Register is record + -- If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, USBCTRL can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, USBCTRL can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, USBCTRL can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : USBCTRL_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, USBCTRL can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, USBCTRL can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBCTRL_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PIO_CORE array + type PIO_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PIO_CORE + type PIO_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PIO_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PIO_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type PIO_Register is record + -- If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PIO0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, PIO0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, PIO0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PIO0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : PIO_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, PIO0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, PIO0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CORESIGHT_TRACE_CORE array + type CORESIGHT_TRACE_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CORESIGHT_TRACE_CORE + type CORESIGHT_TRACE_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : CORESIGHT_TRACE_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CORESIGHT_TRACE_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access + -- CORESIGHT_TRACE, and at what security/privilege levels they can do so. + -- Defaults to Secure, Privileged processor or debug access only. This + -- register is writable only from a Secure, Privileged processor or + -- debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type CORESIGHT_TRACE_Register is record + -- If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged + -- context. + NSP : Boolean := False; + -- If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a + -- Secure, Unprivileged context. + SU : Boolean := False; + -- If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged + -- context. + SP : Boolean := True; + -- If 1, CORESIGHT_TRACE can be accessed by core 0, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + CORE : CORESIGHT_TRACE_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, CORESIGHT_TRACE can be accessed by the DMA, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DMA : Boolean := False; + -- If 1, CORESIGHT_TRACE can be accessed by the debugger, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CORESIGHT_TRACE_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CORESIGHT_PERIPH_CORE array + type CORESIGHT_PERIPH_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CORESIGHT_PERIPH_CORE + type CORESIGHT_PERIPH_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : CORESIGHT_PERIPH_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CORESIGHT_PERIPH_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access + -- CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + -- Defaults to Secure, Privileged processor or debug access only. This + -- register is writable only from a Secure, Privileged processor or + -- debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type CORESIGHT_PERIPH_Register is record + -- If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged + -- context. + NSP : Boolean := False; + -- If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a + -- Secure, Unprivileged context. + SU : Boolean := False; + -- If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged + -- context. + SP : Boolean := True; + -- If 1, CORESIGHT_PERIPH can be accessed by core 0, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + CORE : CORESIGHT_PERIPH_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, CORESIGHT_PERIPH can be accessed by the DMA, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DMA : Boolean := False; + -- If 1, CORESIGHT_PERIPH can be accessed by the debugger, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CORESIGHT_PERIPH_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- SYSINFO_CORE array + type SYSINFO_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SYSINFO_CORE + type SYSINFO_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : SYSINFO_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SYSINFO_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and + -- at what security/privilege levels they can do so. Defaults to fully open + -- access. This register is writable only from a Secure, Privileged + -- processor or debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + type SYSINFO_Register is record + -- If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := True; + -- If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + NSP : Boolean := True; + -- If 1, and SP is also set, SYSINFO can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, SYSINFO can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, SYSINFO can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : SYSINFO_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, SYSINFO can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, SYSINFO can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYSINFO_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- RESETS_CORE array + type RESETS_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESETS_CORE + type RESETS_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : RESETS_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESETS_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access RESETS, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type RESETS_Register is record + -- If 1, and NSP is also set, RESETS can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, RESETS can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, RESETS can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, RESETS can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, RESETS can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : RESETS_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, RESETS can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, RESETS can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESETS_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IO_BANK_CORE array + type IO_BANK_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for IO_BANK_CORE + type IO_BANK_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : IO_BANK_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for IO_BANK_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, + -- and at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type IO_BANK_Register is record + -- If 1, and NSP is also set, IO_BANK0 can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, IO_BANK0 can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : IO_BANK_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, IO_BANK0 can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, IO_BANK0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IO_BANK_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PADS_BANK0_CORE array + type PADS_BANK0_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PADS_BANK0_CORE + type PADS_BANK0_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PADS_BANK0_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PADS_BANK0_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, + -- and at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type PADS_BANK0_Register is record + -- If 1, and NSP is also set, PADS_BANK0 can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged + -- context. + NSP : Boolean := False; + -- If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PADS_BANK0 can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : PADS_BANK0_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, PADS_BANK0 can be accessed by the debugger, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PADS_BANK0_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PADS_QSPI_CORE array + type PADS_QSPI_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PADS_QSPI_CORE + type PADS_QSPI_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PADS_QSPI_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PADS_QSPI_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, + -- and at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type PADS_QSPI_Register is record + -- If 1, and NSP is also set, PADS_QSPI can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PADS_QSPI can be accessed from a Non-secure, Privileged + -- context. + NSP : Boolean := False; + -- If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PADS_QSPI can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : PADS_QSPI_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, PADS_QSPI can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, PADS_QSPI can be accessed by the debugger, at + -- security/privilege levels permitted by SP/NSP/SU/NSU in this + -- register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PADS_QSPI_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- BUSCTRL_CORE array + type BUSCTRL_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for BUSCTRL_CORE + type BUSCTRL_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : BUSCTRL_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for BUSCTRL_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type BUSCTRL_Register is record + -- If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, BUSCTRL can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, BUSCTRL can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, BUSCTRL can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : BUSCTRL_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, BUSCTRL can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, BUSCTRL can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BUSCTRL_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- ADC0_CORE array + type ADC0_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for ADC0_CORE + type ADC0_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : ADC0_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for ADC0_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type ADC0_Register is record + -- If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, ADC0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, ADC0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, ADC0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, ADC0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : ADC0_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, ADC0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, ADC0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADC0_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- HSTX_CORE array + type HSTX_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for HSTX_CORE + type HSTX_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : HSTX_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for HSTX_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type HSTX_Register is record + -- If 1, and NSP is also set, HSTX can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, HSTX can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, HSTX can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, HSTX can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, HSTX can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : HSTX_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, HSTX can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, HSTX can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HSTX_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- I2C_CORE array + type I2C_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for I2C_CORE + type I2C_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : I2C_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for I2C_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type I2C_Register is record + -- If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, I2C0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, I2C0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, I2C0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, I2C0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : I2C_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, I2C0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, I2C0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for I2C_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PWM_CORE array + type PWM_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PWM_CORE + type PWM_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PWM_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PWM_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PWM, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type PWM_Register is record + -- If 1, and NSP is also set, PWM can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PWM can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, PWM can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, PWM can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PWM can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : PWM_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, PWM can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, PWM can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- SPI_CORE array + type SPI_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SPI_CORE + type SPI_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : SPI_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SPI_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type SPI_Register is record + -- If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, SPI0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, SPI0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, SPI0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, SPI0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : SPI_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, SPI0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, SPI0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TIMER_CORE array + type TIMER_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TIMER_CORE + type TIMER_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : TIMER_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TIMER_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type TIMER_Register is record + -- If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, TIMER0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, TIMER0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, TIMER0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : TIMER_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, TIMER0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, TIMER0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- UART_CORE array + type UART_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for UART_CORE + type UART_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : UART_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for UART_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access UART0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type UART_Register is record + -- If 1, and NSP is also set, UART0 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, UART0 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, UART0 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, UART0 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, UART0 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : UART_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, UART0 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, UART0 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- OTP_CORE array + type OTP_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for OTP_CORE + type OTP_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : OTP_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for OTP_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access OTP, and at + -- what security/privilege levels they can do so. Defaults to Secure access + -- from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type OTP_Register is record + -- If 1, and NSP is also set, OTP can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, OTP can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, OTP can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, OTP can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, OTP can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : OTP_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, OTP can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, OTP can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTP_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TBMAN_CORE array + type TBMAN_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TBMAN_CORE + type TBMAN_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : TBMAN_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TBMAN_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type TBMAN_Register is record + -- If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, TBMAN can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, TBMAN can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := True; + -- If 1, TBMAN can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, TBMAN can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : TBMAN_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, TBMAN can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, TBMAN can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TBMAN_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- POWMAN_CORE array + type POWMAN_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for POWMAN_CORE + type POWMAN_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : POWMAN_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for POWMAN_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type POWMAN_Register is record + -- If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, POWMAN can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, POWMAN can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, POWMAN can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, POWMAN can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : POWMAN_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, POWMAN can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, POWMAN can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POWMAN_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TRNG_CORE array + type TRNG_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TRNG_CORE + type TRNG_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : TRNG_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TRNG_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at + -- what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type TRNG_Register is record + -- If 1, and NSP is also set, TRNG can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, TRNG can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, TRNG can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, TRNG can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, TRNG can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : TRNG_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, TRNG can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, TRNG can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- SHA256_CORE array + type SHA256_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SHA256_CORE + type SHA256_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : SHA256_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SHA256_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access SHA256, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged access only. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type SHA256_Register is record + -- If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, SHA256 can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, SHA256 can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, SHA256 can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, SHA256 can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : SHA256_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, SHA256 can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, SHA256 can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHA256_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- SYSCFG_CORE array + type SYSCFG_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SYSCFG_CORE + type SYSCFG_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : SYSCFG_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SYSCFG_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type SYSCFG_Register is record + -- If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, SYSCFG can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, SYSCFG can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, SYSCFG can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : SYSCFG_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, SYSCFG can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, SYSCFG can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYSCFG_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CLOCKS_CORE array + type CLOCKS_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CLOCKS_CORE + type CLOCKS_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : CLOCKS_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CLOCKS_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type CLOCKS_Register is record + -- If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, CLOCKS can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, CLOCKS can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, CLOCKS can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : CLOCKS_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, CLOCKS can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, CLOCKS can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLOCKS_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- XOSC_CORE array + type XOSC_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for XOSC_CORE + type XOSC_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : XOSC_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for XOSC_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at + -- what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type XOSC_Register is record + -- If 1, and NSP is also set, XOSC can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, XOSC can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, XOSC can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, XOSC can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, XOSC can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : XOSC_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, XOSC can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, XOSC can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XOSC_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- ROSC_CORE array + type ROSC_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for ROSC_CORE + type ROSC_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : ROSC_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for ROSC_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at + -- what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type ROSC_Register is record + -- If 1, and NSP is also set, ROSC can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, ROSC can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, ROSC can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, ROSC can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, ROSC can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : ROSC_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, ROSC can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, ROSC can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ROSC_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PLL_SYS_CORE array + type PLL_SYS_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PLL_SYS_CORE + type PLL_SYS_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PLL_SYS_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PLL_SYS_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type PLL_SYS_Register is record + -- If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, PLL_SYS can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, PLL_SYS can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PLL_SYS can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : PLL_SYS_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, PLL_SYS can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, PLL_SYS can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLL_SYS_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PLL_USB_CORE array + type PLL_USB_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PLL_USB_CORE + type PLL_USB_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : PLL_USB_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PLL_USB_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type PLL_USB_Register is record + -- If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, PLL_USB can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, PLL_USB can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, PLL_USB can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : PLL_USB_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, PLL_USB can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, PLL_USB can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLL_USB_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TICKS_CORE array + type TICKS_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TICKS_CORE + type TICKS_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : TICKS_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TICKS_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access TICKS, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type TICKS_Register is record + -- If 1, and NSP is also set, TICKS can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, TICKS can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, TICKS can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, TICKS can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, TICKS can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : TICKS_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, TICKS can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, TICKS can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TICKS_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- WATCHDOG_CORE array + type WATCHDOG_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WATCHDOG_CORE + type WATCHDOG_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : WATCHDOG_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WATCHDOG_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes Non-secure-Privileged-writable + -- when the NSP bit is set. + type WATCHDOG_Register is record + -- If 1, and NSP is also set, WATCHDOG can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, WATCHDOG can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, WATCHDOG can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, WATCHDOG can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : WATCHDOG_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, WATCHDOG can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, WATCHDOG can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WATCHDOG_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- RSM_CORE array + type RSM_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RSM_CORE + type RSM_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : RSM_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RSM_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access RSM, and at + -- what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type RSM_Register is record + -- If 1, and NSP is also set, RSM can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, RSM can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, RSM can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, RSM can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, RSM can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : RSM_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, RSM can be accessed by the DMA, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, RSM can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RSM_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- XIP_CTRL_CORE array + type XIP_CTRL_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for XIP_CTRL_CORE + type XIP_CTRL_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : XIP_CTRL_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for XIP_CTRL_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes Non-secure-Privileged-writable + -- when the NSP bit is set. + type XIP_CTRL_Register is record + -- If 1, and NSP is also set, XIP_CTRL can be accessed from a + -- Non-secure, Unprivileged context. This bit is writable from a + -- Non-secure, Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, XIP_CTRL can be accessed by core 0, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + CORE : XIP_CTRL_CORE_Field := + (As_Array => False, Val => 16#1#); + -- If 1, XIP_CTRL can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, XIP_CTRL can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XIP_CTRL_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- XIP_QMI_CORE array + type XIP_QMI_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for XIP_QMI_CORE + type XIP_QMI_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : XIP_QMI_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for XIP_QMI_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the exception + -- of the NSU bit, which becomes Non-secure-Privileged-writable when the + -- NSP bit is set. + type XIP_QMI_Register is record + -- If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, XIP_QMI can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, XIP_QMI can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, XIP_QMI can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : XIP_QMI_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, XIP_QMI can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := False; + -- If 1, XIP_QMI can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XIP_QMI_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- XIP_AUX_CORE array + type XIP_AUX_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for XIP_AUX_CORE + type XIP_AUX_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CORE as a value + Val : HAL.UInt2; + when True => + -- CORE as an array + Arr : XIP_AUX_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for XIP_AUX_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged access only. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + type XIP_AUX_Register is record + -- If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, + -- Unprivileged context. This bit is writable from a Non-secure, + -- Privileged context, if and only if the NSP bit is set. + NSU : Boolean := False; + -- If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + NSP : Boolean := False; + -- If 1, and SP is also set, XIP_AUX can be accessed from a Secure, + -- Unprivileged context. + SU : Boolean := False; + -- If 1, XIP_AUX can be accessed from a Secure, Privileged context. + SP : Boolean := True; + -- If 1, XIP_AUX can be accessed by core 0, at security/privilege levels + -- permitted by SP/NSP/SU/NSU in this register. + CORE : XIP_AUX_CORE_Field := (As_Array => False, Val => 16#1#); + -- If 1, XIP_AUX can be accessed by the DMA, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DMA : Boolean := True; + -- If 1, XIP_AUX can be accessed by the debugger, at security/privilege + -- levels permitted by SP/NSP/SU/NSU in this register. + DBG : Boolean := True; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XIP_AUX_Register use record + NSU at 0 range 0 .. 0; + NSP at 0 range 1 .. 1; + SU at 0 range 2 .. 2; + SP at 0 range 3 .. 3; + CORE at 0 range 4 .. 5; + DMA at 0 range 6 .. 6; + DBG at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Hardware access control registers + type ACCESSCTRL_Peripheral is record + -- Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes + -- from that master. LOCK is writable only by a Secure, Privileged + -- processor or debugger. LOCK bits are only writable when their value + -- is zero. Once set, they can never be cleared, except by a full reset + -- of ACCESSCTRL Setting the LOCK bit does not affect whether an access + -- raises a bus error. Unprivileged writes, or writes from the DMA, will + -- continue to raise bus errors. All other accesses will continue not + -- to. + LOCK : aliased LOCK_Register; + -- Force core 1's bus accesses to always be Non-secure, no matter the + -- core's internal state. Useful for schemes where one core is + -- designated as the Non-secure core, since some peripherals may filter + -- individual registers internally based on security state but not on + -- master ID. + FORCE_CORE_NS : aliased FORCE_CORE_NS_Register; + -- Write 1 to reset all ACCESSCTRL configuration, except for the LOCK + -- and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom + -- to quickly restore ACCESSCTRL to a known state during the boot path. + -- Note that, like all registers in ACCESSCTRL, this register is not + -- writable when the writer's corresponding LOCK bit is set, therefore a + -- master which has been locked out of ACCESSCTRL can not use the + -- CFGRESET register to disturb its contents. + CFGRESET : aliased CFGRESET_Register; + -- Control whether GPIO0...31 are accessible to Non-secure code. + -- Writable only by a Secure, Privileged processor or debugger. 0 -> + -- Secure access only 1 -> Secure + Non-secure access + GPIO_NSMASK0 : aliased HAL.UInt32; + -- Control whether GPIO32..47 are accessible to Non-secure code, and + -- whether QSPI and USB bitbang are accessible through the Non-secure + -- SIO. Writable only by a Secure, Privileged processor or debugger. + GPIO_NSMASK1 : aliased GPIO_NSMASK1_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access ROM, and + -- at what security/privilege levels they can do so. Defaults to fully + -- open access. This register is writable only from a Secure, Privileged + -- processor or debugger, with the exception of the NSU bit, which + -- becomes Non-secure-Privileged-writable when the NSP bit is set. + ROM : aliased ROM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + XIP_MAIN : aliased XIP_MAIN_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM0, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM0 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM1, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM1 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM2, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM2 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM3, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM3 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM4, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM4 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM5, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM5 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM6, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM6 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM7, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM7 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM8, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM8 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SRAM9, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SRAM9 : aliased SRAM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access DMA, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + DMA : aliased DMA_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + USBCTRL : aliased USBCTRL_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PIO0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + PIO0 : aliased PIO_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PIO1, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + PIO1 : aliased PIO_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PIO2, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + PIO2 : aliased PIO_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access + -- CORESIGHT_TRACE, and at what security/privilege levels they can do + -- so. Defaults to Secure, Privileged processor or debug access only. + -- This register is writable only from a Secure, Privileged processor or + -- debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + CORESIGHT_TRACE : aliased CORESIGHT_TRACE_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access + -- CORESIGHT_PERIPH, and at what security/privilege levels they can do + -- so. Defaults to Secure, Privileged processor or debug access only. + -- This register is writable only from a Secure, Privileged processor or + -- debugger, with the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + CORESIGHT_PERIPH : aliased CORESIGHT_PERIPH_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, + -- and at what security/privilege levels they can do so. Defaults to + -- fully open access. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SYSINFO : aliased SYSINFO_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access RESETS, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + RESETS : aliased RESETS_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + IO_BANK0 : aliased IO_BANK_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + IO_BANK1 : aliased IO_BANK_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access + -- PADS_BANK0, and at what security/privilege levels they can do so. + -- Defaults to Secure access from any master. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + PADS_BANK0 : aliased PADS_BANK0_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access + -- PADS_QSPI, and at what security/privilege levels they can do so. + -- Defaults to Secure access from any master. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + PADS_QSPI : aliased PADS_QSPI_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + BUSCTRL : aliased BUSCTRL_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access ADC0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + ADC0 : aliased ADC0_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access HSTX, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + HSTX : aliased HSTX_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access I2C0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + I2C0 : aliased I2C_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access I2C1, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + I2C1 : aliased I2C_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PWM, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + PWM : aliased PWM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SPI0, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SPI0 : aliased SPI_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SPI1, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + SPI1 : aliased SPI_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access TIMER0, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + TIMER0 : aliased TIMER_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access TIMER1, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + TIMER1 : aliased TIMER_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access UART0, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + UART0 : aliased UART_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access UART1, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + UART1 : aliased UART_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access OTP, and + -- at what security/privilege levels they can do so. Defaults to Secure + -- access from any master. This register is writable only from a Secure, + -- Privileged processor or debugger, with the exception of the NSU bit, + -- which becomes Non-secure-Privileged-writable when the NSP bit is set. + OTP : aliased OTP_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access TBMAN, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure access from any master. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + TBMAN : aliased TBMAN_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access POWMAN, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + POWMAN : aliased POWMAN_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access TRNG, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + TRNG : aliased TRNG_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SHA256, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged access only. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + SHA256 : aliased SHA256_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + SYSCFG : aliased SYSCFG_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + CLOCKS : aliased CLOCKS_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access XOSC, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + XOSC : aliased XOSC_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access ROSC, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + ROSC : aliased ROSC_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + PLL_SYS : aliased PLL_SYS_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + PLL_USB : aliased PLL_USB_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access TICKS, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + TICKS : aliased TICKS_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + WATCHDOG : aliased WATCHDOG_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access RSM, and + -- at what security/privilege levels they can do so. Defaults to Secure, + -- Privileged processor or debug access only. This register is writable + -- only from a Secure, Privileged processor or debugger, with the + -- exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + RSM : aliased RSM_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + XIP_CTRL : aliased XIP_CTRL_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged processor or debug access only. This register is + -- writable only from a Secure, Privileged processor or debugger, with + -- the exception of the NSU bit, which becomes + -- Non-secure-Privileged-writable when the NSP bit is set. + XIP_QMI : aliased XIP_QMI_Register; + -- Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, + -- and at what security/privilege levels they can do so. Defaults to + -- Secure, Privileged access only. This register is writable only from a + -- Secure, Privileged processor or debugger, with the exception of the + -- NSU bit, which becomes Non-secure-Privileged-writable when the NSP + -- bit is set. + XIP_AUX : aliased XIP_AUX_Register; + end record + with Volatile; + + for ACCESSCTRL_Peripheral use record + LOCK at 16#0# range 0 .. 31; + FORCE_CORE_NS at 16#4# range 0 .. 31; + CFGRESET at 16#8# range 0 .. 31; + GPIO_NSMASK0 at 16#C# range 0 .. 31; + GPIO_NSMASK1 at 16#10# range 0 .. 31; + ROM at 16#14# range 0 .. 31; + XIP_MAIN at 16#18# range 0 .. 31; + SRAM0 at 16#1C# range 0 .. 31; + SRAM1 at 16#20# range 0 .. 31; + SRAM2 at 16#24# range 0 .. 31; + SRAM3 at 16#28# range 0 .. 31; + SRAM4 at 16#2C# range 0 .. 31; + SRAM5 at 16#30# range 0 .. 31; + SRAM6 at 16#34# range 0 .. 31; + SRAM7 at 16#38# range 0 .. 31; + SRAM8 at 16#3C# range 0 .. 31; + SRAM9 at 16#40# range 0 .. 31; + DMA at 16#44# range 0 .. 31; + USBCTRL at 16#48# range 0 .. 31; + PIO0 at 16#4C# range 0 .. 31; + PIO1 at 16#50# range 0 .. 31; + PIO2 at 16#54# range 0 .. 31; + CORESIGHT_TRACE at 16#58# range 0 .. 31; + CORESIGHT_PERIPH at 16#5C# range 0 .. 31; + SYSINFO at 16#60# range 0 .. 31; + RESETS at 16#64# range 0 .. 31; + IO_BANK0 at 16#68# range 0 .. 31; + IO_BANK1 at 16#6C# range 0 .. 31; + PADS_BANK0 at 16#70# range 0 .. 31; + PADS_QSPI at 16#74# range 0 .. 31; + BUSCTRL at 16#78# range 0 .. 31; + ADC0 at 16#7C# range 0 .. 31; + HSTX at 16#80# range 0 .. 31; + I2C0 at 16#84# range 0 .. 31; + I2C1 at 16#88# range 0 .. 31; + PWM at 16#8C# range 0 .. 31; + SPI0 at 16#90# range 0 .. 31; + SPI1 at 16#94# range 0 .. 31; + TIMER0 at 16#98# range 0 .. 31; + TIMER1 at 16#9C# range 0 .. 31; + UART0 at 16#A0# range 0 .. 31; + UART1 at 16#A4# range 0 .. 31; + OTP at 16#A8# range 0 .. 31; + TBMAN at 16#AC# range 0 .. 31; + POWMAN at 16#B0# range 0 .. 31; + TRNG at 16#B4# range 0 .. 31; + SHA256 at 16#B8# range 0 .. 31; + SYSCFG at 16#BC# range 0 .. 31; + CLOCKS at 16#C0# range 0 .. 31; + XOSC at 16#C4# range 0 .. 31; + ROSC at 16#C8# range 0 .. 31; + PLL_SYS at 16#CC# range 0 .. 31; + PLL_USB at 16#D0# range 0 .. 31; + TICKS at 16#D4# range 0 .. 31; + WATCHDOG at 16#D8# range 0 .. 31; + RSM at 16#DC# range 0 .. 31; + XIP_CTRL at 16#E0# range 0 .. 31; + XIP_QMI at 16#E4# range 0 .. 31; + XIP_AUX at 16#E8# range 0 .. 31; + end record; + + -- Hardware access control registers + ACCESSCTRL_Periph : aliased ACCESSCTRL_Peripheral + with Import, Address => ACCESSCTRL_Base; + +end RP2350_SVD.ACCESSCTRL; diff --git a/src/svd/rp2350_svd-adc.ads b/src/svd/rp2350_svd-adc.ads new file mode 100644 index 0000000..9419ffe --- /dev/null +++ b/src/svd/rp2350_svd-adc.ads @@ -0,0 +1,314 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Control and data interface to SAR ADC +package RP2350_SVD.ADC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CS_AINSEL_Field is HAL.UInt4; + subtype CS_RROBIN_Field is HAL.UInt9; + + -- ADC Control and Status + type CS_Register is record + -- Power on ADC and enable its clock. 1 - enabled. 0 - disabled. + EN : Boolean := False; + -- Power on temperature sensor. 1 - enabled. 0 - disabled. + TS_EN : Boolean := False; + -- Write-only. Start a single conversion. Self-clearing. Ignored if + -- start_many is asserted. + START_ONCE : Boolean := False; + -- Continuously perform conversions whilst this bit is 1. A new + -- conversion will start immediately after the previous finishes. + START_MANY : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Read-only. 1 if the ADC is ready to start a new conversion. Implies + -- any previous conversion has completed. 0 whilst conversion in + -- progress. + READY : Boolean := False; + -- Read-only. The most recent ADC conversion encountered an error; + -- result is undefined or noisy. + ERR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Some past ADC conversion encountered an error. Write 1 + -- to clear. + ERR_STICKY : Boolean := False; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Select analog mux input. Updated automatically in round-robin mode. + -- This is corrected for the package option so only ADC channels which + -- are bonded are available, and in the correct order + AINSEL : CS_AINSEL_Field := 16#0#; + -- Round-robin sampling. 1 bit per channel. Set all bits to 0 to + -- disable. Otherwise, the ADC will cycle through each enabled channel + -- in a round-robin fashion. The first channel to be sampled will be the + -- one currently indicated by AINSEL. AINSEL will be updated after each + -- conversion with the newly-selected channel. + RROBIN : CS_RROBIN_Field := 16#0#; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CS_Register use record + EN at 0 range 0 .. 0; + TS_EN at 0 range 1 .. 1; + START_ONCE at 0 range 2 .. 2; + START_MANY at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + READY at 0 range 8 .. 8; + ERR at 0 range 9 .. 9; + ERR_STICKY at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + AINSEL at 0 range 12 .. 15; + RROBIN at 0 range 16 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype RESULT_RESULT_Field is HAL.UInt12; + + -- Result of most recent ADC conversion + type RESULT_Register is record + -- Read-only. + RESULT : RESULT_RESULT_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESULT_Register use record + RESULT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype FCS_LEVEL_Field is HAL.UInt4; + subtype FCS_THRESH_Field is HAL.UInt4; + + -- FIFO control and status + type FCS_Register is record + -- If 1: write result to the FIFO after each conversion. + EN : Boolean := False; + -- If 1: FIFO results are right-shifted to be one byte in size. Enables + -- DMA to byte buffers. + SHIFT : Boolean := False; + -- If 1: conversion error bit appears in the FIFO alongside the result + ERR : Boolean := False; + -- If 1: assert DMA requests when FIFO contains data + DREQ_EN : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Read-only. + EMPTY : Boolean := False; + -- Read-only. + FULL : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. 1 if the FIFO has been underflowed. Write 1 to clear. + UNDER : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. 1 if the FIFO has been overflowed. Write 1 to clear. + OVER : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Read-only. The number of conversion results currently waiting in the + -- FIFO + LEVEL : FCS_LEVEL_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- DREQ/IRQ asserted when level >= threshold + THRESH : FCS_THRESH_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FCS_Register use record + EN at 0 range 0 .. 0; + SHIFT at 0 range 1 .. 1; + ERR at 0 range 2 .. 2; + DREQ_EN at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + EMPTY at 0 range 8 .. 8; + FULL at 0 range 9 .. 9; + UNDER at 0 range 10 .. 10; + OVER at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + LEVEL at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + THRESH at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FIFO_VAL_Field is HAL.UInt12; + + -- Conversion result FIFO + type FIFO_Register is record + -- Read-only. *** This field is modified following a read operation ***. + VAL : FIFO_VAL_Field; + -- unspecified + Reserved_12_14 : HAL.UInt3; + -- Read-only. *** This field is modified following a read operation ***. + -- 1 if this particular sample experienced a conversion error. Remains + -- in the same location if the sample is shifted. + ERR : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIFO_Register use record + VAL at 0 range 0 .. 11; + Reserved_12_14 at 0 range 12 .. 14; + ERR at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DIV_FRAC_Field is HAL.UInt8; + subtype DIV_INT_Field is HAL.UInt16; + + -- Clock divider. If non-zero, CS_START_MANY will start conversions at + -- regular intervals rather than back-to-back. The divider is reset when + -- either of these fields are written. Total period is 1 + INT + FRAC / 256 + type DIV_Register is record + -- Fractional part of clock divisor. First-order delta-sigma. + FRAC : DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor. + INT : DIV_INT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIV_Register use record + FRAC at 0 range 0 .. 7; + INT at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. Triggered when the sample FIFO reaches a certain level. + -- This level can be programmed via the FCS_THRESH field. + FIFO : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + FIFO at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + -- Triggered when the sample FIFO reaches a certain level. This level + -- can be programmed via the FCS_THRESH field. + FIFO : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + FIFO at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + -- Triggered when the sample FIFO reaches a certain level. This level + -- can be programmed via the FCS_THRESH field. + FIFO : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + FIFO at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. Triggered when the sample FIFO reaches a certain level. + -- This level can be programmed via the FCS_THRESH field. + FIFO : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + FIFO at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Control and data interface to SAR ADC + type ADC_Peripheral is record + -- ADC Control and Status + CS : aliased CS_Register; + -- Result of most recent ADC conversion + RESULT : aliased RESULT_Register; + -- FIFO control and status + FCS : aliased FCS_Register; + -- Conversion result FIFO + FIFO : aliased FIFO_Register; + -- Clock divider. If non-zero, CS_START_MANY will start conversions at + -- regular intervals rather than back-to-back. The divider is reset when + -- either of these fields are written. Total period is 1 + INT + FRAC / + -- 256 + DIV : aliased DIV_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for ADC_Peripheral use record + CS at 16#0# range 0 .. 31; + RESULT at 16#4# range 0 .. 31; + FCS at 16#8# range 0 .. 31; + FIFO at 16#C# range 0 .. 31; + DIV at 16#10# range 0 .. 31; + INTR at 16#14# range 0 .. 31; + INTE at 16#18# range 0 .. 31; + INTF at 16#1C# range 0 .. 31; + INTS at 16#20# range 0 .. 31; + end record; + + -- Control and data interface to SAR ADC + ADC_Periph : aliased ADC_Peripheral + with Import, Address => ADC_Base; + +end RP2350_SVD.ADC; diff --git a/src/svd/rp2350_svd-bootram.ads b/src/svd/rp2350_svd-bootram.ads new file mode 100644 index 0000000..090dbca --- /dev/null +++ b/src/svd/rp2350_svd-bootram.ads @@ -0,0 +1,101 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Additional registers mapped adjacent to the bootram, for use by the +-- bootrom. +package RP2350_SVD.BOOTRAM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype BOOTLOCK_STAT_BOOTLOCK_STAT_Field is HAL.UInt8; + + -- Bootlock status register. 1=unclaimed, 0=claimed. These locks function + -- identically to the SIO spinlocks, but are reserved for bootrom use. + type BOOTLOCK_STAT_Register is record + BOOTLOCK_STAT : BOOTLOCK_STAT_BOOTLOCK_STAT_Field := 16#FF#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTLOCK_STAT_Register use record + BOOTLOCK_STAT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Additional registers mapped adjacent to the bootram, for use by the + -- bootrom. + type BOOTRAM_Peripheral is record + -- This registers always ORs writes into its current contents. Once a + -- bit is set, it can only be cleared by a reset. + WRITE_ONCE0 : aliased HAL.UInt32; + -- This registers always ORs writes into its current contents. Once a + -- bit is set, it can only be cleared by a reset. + WRITE_ONCE1 : aliased HAL.UInt32; + -- Bootlock status register. 1=unclaimed, 0=claimed. These locks + -- function identically to the SIO spinlocks, but are reserved for + -- bootrom use. + BOOTLOCK_STAT : aliased BOOTLOCK_STAT_Register; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK0 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK1 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK2 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK3 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK4 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK5 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK6 : aliased HAL.UInt32; + -- Read to claim and check. Write to unclaim. The value returned on + -- successful claim is 1 << n, and on failed claim is zero. + BOOTLOCK7 : aliased HAL.UInt32; + end record + with Volatile; + + for BOOTRAM_Peripheral use record + WRITE_ONCE0 at 16#800# range 0 .. 31; + WRITE_ONCE1 at 16#804# range 0 .. 31; + BOOTLOCK_STAT at 16#808# range 0 .. 31; + BOOTLOCK0 at 16#80C# range 0 .. 31; + BOOTLOCK1 at 16#810# range 0 .. 31; + BOOTLOCK2 at 16#814# range 0 .. 31; + BOOTLOCK3 at 16#818# range 0 .. 31; + BOOTLOCK4 at 16#81C# range 0 .. 31; + BOOTLOCK5 at 16#820# range 0 .. 31; + BOOTLOCK6 at 16#824# range 0 .. 31; + BOOTLOCK7 at 16#828# range 0 .. 31; + end record; + + -- Additional registers mapped adjacent to the bootram, for use by the + -- bootrom. + BOOTRAM_Periph : aliased BOOTRAM_Peripheral + with Import, Address => BOOTRAM_Base; + +end RP2350_SVD.BOOTRAM; diff --git a/src/svd/rp2350_svd-busctrl.ads b/src/svd/rp2350_svd-busctrl.ads new file mode 100644 index 0000000..49d4ffb --- /dev/null +++ b/src/svd/rp2350_svd-busctrl.ads @@ -0,0 +1,896 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Register block for busfabric control signals and performance counters +package RP2350_SVD.BUSCTRL is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Set the priority of each master for bus arbitration. + type BUS_PRIORITY_Register is record + -- 0 - low priority, 1 - high priority + PROC0 : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- 0 - low priority, 1 - high priority + PROC1 : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- 0 - low priority, 1 - high priority + DMA_R : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- 0 - low priority, 1 - high priority + DMA_W : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BUS_PRIORITY_Register use record + PROC0 at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + PROC1 at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + DMA_R at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + DMA_W at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Bus priority acknowledge + type BUS_PRIORITY_ACK_Register is record + -- Read-only. Goes to 1 once all arbiters have registered the new global + -- priority levels. Arbiters update their local priority when servicing + -- a new nonsequential access. In normal circumstances this will happen + -- almost immediately. + BUS_PRIORITY_ACK : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BUS_PRIORITY_ACK_Register use record + BUS_PRIORITY_ACK at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Enable the performance counters. If 0, the performance counters do not + -- increment. This can be used to precisely start/stop event sampling + -- around the profiled section of code. The performance counters are + -- initially disabled, to save energy. + type PERFCTR_EN_Register is record + PERFCTR_EN : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFCTR_EN_Register use record + PERFCTR_EN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype PERFCTR0_PERFCTR0_Field is HAL.UInt24; + + -- Bus fabric performance counter 0 + type PERFCTR0_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Busfabric saturating performance counter 0 Count some + -- event signal from the busfabric arbiters, if PERFCTR_EN is set. Write + -- any value to clear. Select an event to count using PERFSEL0 + PERFCTR0 : PERFCTR0_PERFCTR0_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFCTR0_Register use record + PERFCTR0 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Select an event for PERFCTR0. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where any + -- master stalled due to a stall on the downstream bus; STALL_UPSTREAM, + -- count cycles where any master stalled for any reason, including + -- contention from other masters. + type PERFSEL0_PERFSEL0_Field is + (siob_proc1_stall_upstream, + siob_proc1_stall_downstream, + siob_proc1_access_contested, + siob_proc1_access, + siob_proc0_stall_upstream, + siob_proc0_stall_downstream, + siob_proc0_access_contested, + siob_proc0_access, + apb_stall_upstream, + apb_stall_downstream, + apb_access_contested, + apb_access, + fastperi_stall_upstream, + fastperi_stall_downstream, + fastperi_access_contested, + fastperi_access, + sram9_stall_upstream, + sram9_stall_downstream, + sram9_access_contested, + sram9_access, + sram8_stall_upstream, + sram8_stall_downstream, + sram8_access_contested, + sram8_access, + sram7_stall_upstream, + sram7_stall_downstream, + sram7_access_contested, + sram7_access, + sram6_stall_upstream, + sram6_stall_downstream, + sram6_access_contested, + sram6_access, + sram5_stall_upstream, + sram5_stall_downstream, + sram5_access_contested, + sram5_access, + sram4_stall_upstream, + sram4_stall_downstream, + sram4_access_contested, + sram4_access, + sram3_stall_upstream, + sram3_stall_downstream, + sram3_access_contested, + sram3_access, + sram2_stall_upstream, + sram2_stall_downstream, + sram2_access_contested, + sram2_access, + sram1_stall_upstream, + sram1_stall_downstream, + sram1_access_contested, + sram1_access, + sram0_stall_upstream, + sram0_stall_downstream, + sram0_access_contested, + sram0_access, + xip_main1_stall_upstream, + xip_main1_stall_downstream, + xip_main1_access_contested, + xip_main1_access, + xip_main0_stall_upstream, + xip_main0_stall_downstream, + xip_main0_access_contested, + xip_main0_access, + rom_stall_upstream, + rom_stall_downstream, + rom_access_contested, + rom_access) + with Size => 7; + for PERFSEL0_PERFSEL0_Field use + (siob_proc1_stall_upstream => 0, + siob_proc1_stall_downstream => 1, + siob_proc1_access_contested => 2, + siob_proc1_access => 3, + siob_proc0_stall_upstream => 4, + siob_proc0_stall_downstream => 5, + siob_proc0_access_contested => 6, + siob_proc0_access => 7, + apb_stall_upstream => 8, + apb_stall_downstream => 9, + apb_access_contested => 10, + apb_access => 11, + fastperi_stall_upstream => 12, + fastperi_stall_downstream => 13, + fastperi_access_contested => 14, + fastperi_access => 15, + sram9_stall_upstream => 16, + sram9_stall_downstream => 17, + sram9_access_contested => 18, + sram9_access => 19, + sram8_stall_upstream => 20, + sram8_stall_downstream => 21, + sram8_access_contested => 22, + sram8_access => 23, + sram7_stall_upstream => 24, + sram7_stall_downstream => 25, + sram7_access_contested => 26, + sram7_access => 27, + sram6_stall_upstream => 28, + sram6_stall_downstream => 29, + sram6_access_contested => 30, + sram6_access => 31, + sram5_stall_upstream => 32, + sram5_stall_downstream => 33, + sram5_access_contested => 34, + sram5_access => 35, + sram4_stall_upstream => 36, + sram4_stall_downstream => 37, + sram4_access_contested => 38, + sram4_access => 39, + sram3_stall_upstream => 40, + sram3_stall_downstream => 41, + sram3_access_contested => 42, + sram3_access => 43, + sram2_stall_upstream => 44, + sram2_stall_downstream => 45, + sram2_access_contested => 46, + sram2_access => 47, + sram1_stall_upstream => 48, + sram1_stall_downstream => 49, + sram1_access_contested => 50, + sram1_access => 51, + sram0_stall_upstream => 52, + sram0_stall_downstream => 53, + sram0_access_contested => 54, + sram0_access => 55, + xip_main1_stall_upstream => 56, + xip_main1_stall_downstream => 57, + xip_main1_access_contested => 58, + xip_main1_access => 59, + xip_main0_stall_upstream => 60, + xip_main0_stall_downstream => 61, + xip_main0_access_contested => 62, + xip_main0_access => 63, + rom_stall_upstream => 64, + rom_stall_downstream => 65, + rom_access_contested => 66, + rom_access => 67); + + -- Bus fabric performance event select for PERFCTR0 + type PERFSEL0_Register is record + -- Select an event for PERFCTR0. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where + -- any master stalled due to a stall on the downstream bus; + -- STALL_UPSTREAM, count cycles where any master stalled for any reason, + -- including contention from other masters. + PERFSEL0 : PERFSEL0_PERFSEL0_Field := + RP2350_SVD.BUSCTRL.sram6_access; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFSEL0_Register use record + PERFSEL0 at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype PERFCTR1_PERFCTR1_Field is HAL.UInt24; + + -- Bus fabric performance counter 1 + type PERFCTR1_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Busfabric saturating performance counter 1 Count some + -- event signal from the busfabric arbiters, if PERFCTR_EN is set. Write + -- any value to clear. Select an event to count using PERFSEL1 + PERFCTR1 : PERFCTR1_PERFCTR1_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFCTR1_Register use record + PERFCTR1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Select an event for PERFCTR1. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where any + -- master stalled due to a stall on the downstream bus; STALL_UPSTREAM, + -- count cycles where any master stalled for any reason, including + -- contention from other masters. + type PERFSEL1_PERFSEL1_Field is + (siob_proc1_stall_upstream, + siob_proc1_stall_downstream, + siob_proc1_access_contested, + siob_proc1_access, + siob_proc0_stall_upstream, + siob_proc0_stall_downstream, + siob_proc0_access_contested, + siob_proc0_access, + apb_stall_upstream, + apb_stall_downstream, + apb_access_contested, + apb_access, + fastperi_stall_upstream, + fastperi_stall_downstream, + fastperi_access_contested, + fastperi_access, + sram9_stall_upstream, + sram9_stall_downstream, + sram9_access_contested, + sram9_access, + sram8_stall_upstream, + sram8_stall_downstream, + sram8_access_contested, + sram8_access, + sram7_stall_upstream, + sram7_stall_downstream, + sram7_access_contested, + sram7_access, + sram6_stall_upstream, + sram6_stall_downstream, + sram6_access_contested, + sram6_access, + sram5_stall_upstream, + sram5_stall_downstream, + sram5_access_contested, + sram5_access, + sram4_stall_upstream, + sram4_stall_downstream, + sram4_access_contested, + sram4_access, + sram3_stall_upstream, + sram3_stall_downstream, + sram3_access_contested, + sram3_access, + sram2_stall_upstream, + sram2_stall_downstream, + sram2_access_contested, + sram2_access, + sram1_stall_upstream, + sram1_stall_downstream, + sram1_access_contested, + sram1_access, + sram0_stall_upstream, + sram0_stall_downstream, + sram0_access_contested, + sram0_access, + xip_main1_stall_upstream, + xip_main1_stall_downstream, + xip_main1_access_contested, + xip_main1_access, + xip_main0_stall_upstream, + xip_main0_stall_downstream, + xip_main0_access_contested, + xip_main0_access, + rom_stall_upstream, + rom_stall_downstream, + rom_access_contested, + rom_access) + with Size => 7; + for PERFSEL1_PERFSEL1_Field use + (siob_proc1_stall_upstream => 0, + siob_proc1_stall_downstream => 1, + siob_proc1_access_contested => 2, + siob_proc1_access => 3, + siob_proc0_stall_upstream => 4, + siob_proc0_stall_downstream => 5, + siob_proc0_access_contested => 6, + siob_proc0_access => 7, + apb_stall_upstream => 8, + apb_stall_downstream => 9, + apb_access_contested => 10, + apb_access => 11, + fastperi_stall_upstream => 12, + fastperi_stall_downstream => 13, + fastperi_access_contested => 14, + fastperi_access => 15, + sram9_stall_upstream => 16, + sram9_stall_downstream => 17, + sram9_access_contested => 18, + sram9_access => 19, + sram8_stall_upstream => 20, + sram8_stall_downstream => 21, + sram8_access_contested => 22, + sram8_access => 23, + sram7_stall_upstream => 24, + sram7_stall_downstream => 25, + sram7_access_contested => 26, + sram7_access => 27, + sram6_stall_upstream => 28, + sram6_stall_downstream => 29, + sram6_access_contested => 30, + sram6_access => 31, + sram5_stall_upstream => 32, + sram5_stall_downstream => 33, + sram5_access_contested => 34, + sram5_access => 35, + sram4_stall_upstream => 36, + sram4_stall_downstream => 37, + sram4_access_contested => 38, + sram4_access => 39, + sram3_stall_upstream => 40, + sram3_stall_downstream => 41, + sram3_access_contested => 42, + sram3_access => 43, + sram2_stall_upstream => 44, + sram2_stall_downstream => 45, + sram2_access_contested => 46, + sram2_access => 47, + sram1_stall_upstream => 48, + sram1_stall_downstream => 49, + sram1_access_contested => 50, + sram1_access => 51, + sram0_stall_upstream => 52, + sram0_stall_downstream => 53, + sram0_access_contested => 54, + sram0_access => 55, + xip_main1_stall_upstream => 56, + xip_main1_stall_downstream => 57, + xip_main1_access_contested => 58, + xip_main1_access => 59, + xip_main0_stall_upstream => 60, + xip_main0_stall_downstream => 61, + xip_main0_access_contested => 62, + xip_main0_access => 63, + rom_stall_upstream => 64, + rom_stall_downstream => 65, + rom_access_contested => 66, + rom_access => 67); + + -- Bus fabric performance event select for PERFCTR1 + type PERFSEL1_Register is record + -- Select an event for PERFCTR1. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where + -- any master stalled due to a stall on the downstream bus; + -- STALL_UPSTREAM, count cycles where any master stalled for any reason, + -- including contention from other masters. + PERFSEL1 : PERFSEL1_PERFSEL1_Field := + RP2350_SVD.BUSCTRL.sram6_access; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFSEL1_Register use record + PERFSEL1 at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype PERFCTR2_PERFCTR2_Field is HAL.UInt24; + + -- Bus fabric performance counter 2 + type PERFCTR2_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Busfabric saturating performance counter 2 Count some + -- event signal from the busfabric arbiters, if PERFCTR_EN is set. Write + -- any value to clear. Select an event to count using PERFSEL2 + PERFCTR2 : PERFCTR2_PERFCTR2_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFCTR2_Register use record + PERFCTR2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Select an event for PERFCTR2. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where any + -- master stalled due to a stall on the downstream bus; STALL_UPSTREAM, + -- count cycles where any master stalled for any reason, including + -- contention from other masters. + type PERFSEL2_PERFSEL2_Field is + (siob_proc1_stall_upstream, + siob_proc1_stall_downstream, + siob_proc1_access_contested, + siob_proc1_access, + siob_proc0_stall_upstream, + siob_proc0_stall_downstream, + siob_proc0_access_contested, + siob_proc0_access, + apb_stall_upstream, + apb_stall_downstream, + apb_access_contested, + apb_access, + fastperi_stall_upstream, + fastperi_stall_downstream, + fastperi_access_contested, + fastperi_access, + sram9_stall_upstream, + sram9_stall_downstream, + sram9_access_contested, + sram9_access, + sram8_stall_upstream, + sram8_stall_downstream, + sram8_access_contested, + sram8_access, + sram7_stall_upstream, + sram7_stall_downstream, + sram7_access_contested, + sram7_access, + sram6_stall_upstream, + sram6_stall_downstream, + sram6_access_contested, + sram6_access, + sram5_stall_upstream, + sram5_stall_downstream, + sram5_access_contested, + sram5_access, + sram4_stall_upstream, + sram4_stall_downstream, + sram4_access_contested, + sram4_access, + sram3_stall_upstream, + sram3_stall_downstream, + sram3_access_contested, + sram3_access, + sram2_stall_upstream, + sram2_stall_downstream, + sram2_access_contested, + sram2_access, + sram1_stall_upstream, + sram1_stall_downstream, + sram1_access_contested, + sram1_access, + sram0_stall_upstream, + sram0_stall_downstream, + sram0_access_contested, + sram0_access, + xip_main1_stall_upstream, + xip_main1_stall_downstream, + xip_main1_access_contested, + xip_main1_access, + xip_main0_stall_upstream, + xip_main0_stall_downstream, + xip_main0_access_contested, + xip_main0_access, + rom_stall_upstream, + rom_stall_downstream, + rom_access_contested, + rom_access) + with Size => 7; + for PERFSEL2_PERFSEL2_Field use + (siob_proc1_stall_upstream => 0, + siob_proc1_stall_downstream => 1, + siob_proc1_access_contested => 2, + siob_proc1_access => 3, + siob_proc0_stall_upstream => 4, + siob_proc0_stall_downstream => 5, + siob_proc0_access_contested => 6, + siob_proc0_access => 7, + apb_stall_upstream => 8, + apb_stall_downstream => 9, + apb_access_contested => 10, + apb_access => 11, + fastperi_stall_upstream => 12, + fastperi_stall_downstream => 13, + fastperi_access_contested => 14, + fastperi_access => 15, + sram9_stall_upstream => 16, + sram9_stall_downstream => 17, + sram9_access_contested => 18, + sram9_access => 19, + sram8_stall_upstream => 20, + sram8_stall_downstream => 21, + sram8_access_contested => 22, + sram8_access => 23, + sram7_stall_upstream => 24, + sram7_stall_downstream => 25, + sram7_access_contested => 26, + sram7_access => 27, + sram6_stall_upstream => 28, + sram6_stall_downstream => 29, + sram6_access_contested => 30, + sram6_access => 31, + sram5_stall_upstream => 32, + sram5_stall_downstream => 33, + sram5_access_contested => 34, + sram5_access => 35, + sram4_stall_upstream => 36, + sram4_stall_downstream => 37, + sram4_access_contested => 38, + sram4_access => 39, + sram3_stall_upstream => 40, + sram3_stall_downstream => 41, + sram3_access_contested => 42, + sram3_access => 43, + sram2_stall_upstream => 44, + sram2_stall_downstream => 45, + sram2_access_contested => 46, + sram2_access => 47, + sram1_stall_upstream => 48, + sram1_stall_downstream => 49, + sram1_access_contested => 50, + sram1_access => 51, + sram0_stall_upstream => 52, + sram0_stall_downstream => 53, + sram0_access_contested => 54, + sram0_access => 55, + xip_main1_stall_upstream => 56, + xip_main1_stall_downstream => 57, + xip_main1_access_contested => 58, + xip_main1_access => 59, + xip_main0_stall_upstream => 60, + xip_main0_stall_downstream => 61, + xip_main0_access_contested => 62, + xip_main0_access => 63, + rom_stall_upstream => 64, + rom_stall_downstream => 65, + rom_access_contested => 66, + rom_access => 67); + + -- Bus fabric performance event select for PERFCTR2 + type PERFSEL2_Register is record + -- Select an event for PERFCTR2. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where + -- any master stalled due to a stall on the downstream bus; + -- STALL_UPSTREAM, count cycles where any master stalled for any reason, + -- including contention from other masters. + PERFSEL2 : PERFSEL2_PERFSEL2_Field := + RP2350_SVD.BUSCTRL.sram6_access; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFSEL2_Register use record + PERFSEL2 at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype PERFCTR3_PERFCTR3_Field is HAL.UInt24; + + -- Bus fabric performance counter 3 + type PERFCTR3_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Busfabric saturating performance counter 3 Count some + -- event signal from the busfabric arbiters, if PERFCTR_EN is set. Write + -- any value to clear. Select an event to count using PERFSEL3 + PERFCTR3 : PERFCTR3_PERFCTR3_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFCTR3_Register use record + PERFCTR3 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Select an event for PERFCTR3. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where any + -- master stalled due to a stall on the downstream bus; STALL_UPSTREAM, + -- count cycles where any master stalled for any reason, including + -- contention from other masters. + type PERFSEL3_PERFSEL3_Field is + (siob_proc1_stall_upstream, + siob_proc1_stall_downstream, + siob_proc1_access_contested, + siob_proc1_access, + siob_proc0_stall_upstream, + siob_proc0_stall_downstream, + siob_proc0_access_contested, + siob_proc0_access, + apb_stall_upstream, + apb_stall_downstream, + apb_access_contested, + apb_access, + fastperi_stall_upstream, + fastperi_stall_downstream, + fastperi_access_contested, + fastperi_access, + sram9_stall_upstream, + sram9_stall_downstream, + sram9_access_contested, + sram9_access, + sram8_stall_upstream, + sram8_stall_downstream, + sram8_access_contested, + sram8_access, + sram7_stall_upstream, + sram7_stall_downstream, + sram7_access_contested, + sram7_access, + sram6_stall_upstream, + sram6_stall_downstream, + sram6_access_contested, + sram6_access, + sram5_stall_upstream, + sram5_stall_downstream, + sram5_access_contested, + sram5_access, + sram4_stall_upstream, + sram4_stall_downstream, + sram4_access_contested, + sram4_access, + sram3_stall_upstream, + sram3_stall_downstream, + sram3_access_contested, + sram3_access, + sram2_stall_upstream, + sram2_stall_downstream, + sram2_access_contested, + sram2_access, + sram1_stall_upstream, + sram1_stall_downstream, + sram1_access_contested, + sram1_access, + sram0_stall_upstream, + sram0_stall_downstream, + sram0_access_contested, + sram0_access, + xip_main1_stall_upstream, + xip_main1_stall_downstream, + xip_main1_access_contested, + xip_main1_access, + xip_main0_stall_upstream, + xip_main0_stall_downstream, + xip_main0_access_contested, + xip_main0_access, + rom_stall_upstream, + rom_stall_downstream, + rom_access_contested, + rom_access) + with Size => 7; + for PERFSEL3_PERFSEL3_Field use + (siob_proc1_stall_upstream => 0, + siob_proc1_stall_downstream => 1, + siob_proc1_access_contested => 2, + siob_proc1_access => 3, + siob_proc0_stall_upstream => 4, + siob_proc0_stall_downstream => 5, + siob_proc0_access_contested => 6, + siob_proc0_access => 7, + apb_stall_upstream => 8, + apb_stall_downstream => 9, + apb_access_contested => 10, + apb_access => 11, + fastperi_stall_upstream => 12, + fastperi_stall_downstream => 13, + fastperi_access_contested => 14, + fastperi_access => 15, + sram9_stall_upstream => 16, + sram9_stall_downstream => 17, + sram9_access_contested => 18, + sram9_access => 19, + sram8_stall_upstream => 20, + sram8_stall_downstream => 21, + sram8_access_contested => 22, + sram8_access => 23, + sram7_stall_upstream => 24, + sram7_stall_downstream => 25, + sram7_access_contested => 26, + sram7_access => 27, + sram6_stall_upstream => 28, + sram6_stall_downstream => 29, + sram6_access_contested => 30, + sram6_access => 31, + sram5_stall_upstream => 32, + sram5_stall_downstream => 33, + sram5_access_contested => 34, + sram5_access => 35, + sram4_stall_upstream => 36, + sram4_stall_downstream => 37, + sram4_access_contested => 38, + sram4_access => 39, + sram3_stall_upstream => 40, + sram3_stall_downstream => 41, + sram3_access_contested => 42, + sram3_access => 43, + sram2_stall_upstream => 44, + sram2_stall_downstream => 45, + sram2_access_contested => 46, + sram2_access => 47, + sram1_stall_upstream => 48, + sram1_stall_downstream => 49, + sram1_access_contested => 50, + sram1_access => 51, + sram0_stall_upstream => 52, + sram0_stall_downstream => 53, + sram0_access_contested => 54, + sram0_access => 55, + xip_main1_stall_upstream => 56, + xip_main1_stall_downstream => 57, + xip_main1_access_contested => 58, + xip_main1_access => 59, + xip_main0_stall_upstream => 60, + xip_main0_stall_downstream => 61, + xip_main0_access_contested => 62, + xip_main0_access => 63, + rom_stall_upstream => 64, + rom_stall_downstream => 65, + rom_access_contested => 66, + rom_access => 67); + + -- Bus fabric performance event select for PERFCTR3 + type PERFSEL3_Register is record + -- Select an event for PERFCTR3. For each downstream port of the main + -- crossbar, four events are available: ACCESS, an access took place; + -- ACCESS_CONTESTED, an access took place that previously stalled due to + -- contention from other masters; STALL_DOWNSTREAM, count cycles where + -- any master stalled due to a stall on the downstream bus; + -- STALL_UPSTREAM, count cycles where any master stalled for any reason, + -- including contention from other masters. + PERFSEL3 : PERFSEL3_PERFSEL3_Field := + RP2350_SVD.BUSCTRL.sram6_access; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERFSEL3_Register use record + PERFSEL3 at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Register block for busfabric control signals and performance counters + type BUSCTRL_Peripheral is record + -- Set the priority of each master for bus arbitration. + BUS_PRIORITY : aliased BUS_PRIORITY_Register; + -- Bus priority acknowledge + BUS_PRIORITY_ACK : aliased BUS_PRIORITY_ACK_Register; + -- Enable the performance counters. If 0, the performance counters do + -- not increment. This can be used to precisely start/stop event + -- sampling around the profiled section of code. The performance + -- counters are initially disabled, to save energy. + PERFCTR_EN : aliased PERFCTR_EN_Register; + -- Bus fabric performance counter 0 + PERFCTR0 : aliased PERFCTR0_Register; + -- Bus fabric performance event select for PERFCTR0 + PERFSEL0 : aliased PERFSEL0_Register; + -- Bus fabric performance counter 1 + PERFCTR1 : aliased PERFCTR1_Register; + -- Bus fabric performance event select for PERFCTR1 + PERFSEL1 : aliased PERFSEL1_Register; + -- Bus fabric performance counter 2 + PERFCTR2 : aliased PERFCTR2_Register; + -- Bus fabric performance event select for PERFCTR2 + PERFSEL2 : aliased PERFSEL2_Register; + -- Bus fabric performance counter 3 + PERFCTR3 : aliased PERFCTR3_Register; + -- Bus fabric performance event select for PERFCTR3 + PERFSEL3 : aliased PERFSEL3_Register; + end record + with Volatile; + + for BUSCTRL_Peripheral use record + BUS_PRIORITY at 16#0# range 0 .. 31; + BUS_PRIORITY_ACK at 16#4# range 0 .. 31; + PERFCTR_EN at 16#8# range 0 .. 31; + PERFCTR0 at 16#C# range 0 .. 31; + PERFSEL0 at 16#10# range 0 .. 31; + PERFCTR1 at 16#14# range 0 .. 31; + PERFSEL1 at 16#18# range 0 .. 31; + PERFCTR2 at 16#1C# range 0 .. 31; + PERFSEL2 at 16#20# range 0 .. 31; + PERFCTR3 at 16#24# range 0 .. 31; + PERFSEL3 at 16#28# range 0 .. 31; + end record; + + -- Register block for busfabric control signals and performance counters + BUSCTRL_Periph : aliased BUSCTRL_Peripheral + with Import, Address => BUSCTRL_Base; + +end RP2350_SVD.BUSCTRL; diff --git a/src/svd/rp2350_svd-clocks.ads b/src/svd/rp2350_svd-clocks.ads new file mode 100644 index 0000000..dcfb141 --- /dev/null +++ b/src/svd/rp2350_svd-clocks.ads @@ -0,0 +1,2358 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.CLOCKS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_GPOUT0_CTRL_AUXSRC_Field is + (clksrc_pll_sys, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb, + clksrc_pll_usb_primary_ref_opcg, + rosc_clksrc, + xosc_clksrc, + lposc_clksrc, + clk_sys, + clk_usb, + clk_adc, + clk_ref, + clk_peri, + clk_hstx, + otp_clk2fc) + with Size => 4; + for CLK_GPOUT0_CTRL_AUXSRC_Field use + (clksrc_pll_sys => 0, + clksrc_gpin0 => 1, + clksrc_gpin1 => 2, + clksrc_pll_usb => 3, + clksrc_pll_usb_primary_ref_opcg => 4, + rosc_clksrc => 5, + xosc_clksrc => 6, + lposc_clksrc => 7, + clk_sys => 8, + clk_usb => 9, + clk_adc => 10, + clk_ref => 11, + clk_peri => 12, + clk_hstx => 13, + otp_clk2fc => 14); + + subtype CLK_GPOUT0_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_GPOUT0_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_GPOUT0_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_sys; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- Enables duty cycle correction for odd divisors, can be changed + -- on-the-fly + DC50 : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_GPOUT0_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT0_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + DC50 at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_GPOUT0_DIV_FRAC_Field is HAL.UInt16; + subtype CLK_GPOUT0_DIV_INT_Field is HAL.UInt16; + + type CLK_GPOUT0_DIV_Register is record + -- Fractional component of the divisor, can be changed on-the-fly + FRAC : CLK_GPOUT0_DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_GPOUT0_DIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT0_DIV_Register use record + FRAC at 0 range 0 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_GPOUT0_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_GPOUT0_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT0_SELECTED_Register use record + CLK_GPOUT0_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_GPOUT1_CTRL_AUXSRC_Field is + (clksrc_pll_sys, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb, + clksrc_pll_usb_primary_ref_opcg, + rosc_clksrc, + xosc_clksrc, + lposc_clksrc, + clk_sys, + clk_usb, + clk_adc, + clk_ref, + clk_peri, + clk_hstx, + otp_clk2fc) + with Size => 4; + for CLK_GPOUT1_CTRL_AUXSRC_Field use + (clksrc_pll_sys => 0, + clksrc_gpin0 => 1, + clksrc_gpin1 => 2, + clksrc_pll_usb => 3, + clksrc_pll_usb_primary_ref_opcg => 4, + rosc_clksrc => 5, + xosc_clksrc => 6, + lposc_clksrc => 7, + clk_sys => 8, + clk_usb => 9, + clk_adc => 10, + clk_ref => 11, + clk_peri => 12, + clk_hstx => 13, + otp_clk2fc => 14); + + subtype CLK_GPOUT1_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_GPOUT1_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_GPOUT1_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_sys; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- Enables duty cycle correction for odd divisors, can be changed + -- on-the-fly + DC50 : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_GPOUT1_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT1_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + DC50 at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_GPOUT1_DIV_FRAC_Field is HAL.UInt16; + subtype CLK_GPOUT1_DIV_INT_Field is HAL.UInt16; + + type CLK_GPOUT1_DIV_Register is record + -- Fractional component of the divisor, can be changed on-the-fly + FRAC : CLK_GPOUT1_DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_GPOUT1_DIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT1_DIV_Register use record + FRAC at 0 range 0 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_GPOUT1_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_GPOUT1_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT1_SELECTED_Register use record + CLK_GPOUT1_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_GPOUT2_CTRL_AUXSRC_Field is + (clksrc_pll_sys, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb, + clksrc_pll_usb_primary_ref_opcg, + rosc_clksrc_ph, + xosc_clksrc, + lposc_clksrc, + clk_sys, + clk_usb, + clk_adc, + clk_ref, + clk_peri, + clk_hstx, + otp_clk2fc) + with Size => 4; + for CLK_GPOUT2_CTRL_AUXSRC_Field use + (clksrc_pll_sys => 0, + clksrc_gpin0 => 1, + clksrc_gpin1 => 2, + clksrc_pll_usb => 3, + clksrc_pll_usb_primary_ref_opcg => 4, + rosc_clksrc_ph => 5, + xosc_clksrc => 6, + lposc_clksrc => 7, + clk_sys => 8, + clk_usb => 9, + clk_adc => 10, + clk_ref => 11, + clk_peri => 12, + clk_hstx => 13, + otp_clk2fc => 14); + + subtype CLK_GPOUT2_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_GPOUT2_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_GPOUT2_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_sys; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- Enables duty cycle correction for odd divisors, can be changed + -- on-the-fly + DC50 : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_GPOUT2_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT2_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + DC50 at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_GPOUT2_DIV_FRAC_Field is HAL.UInt16; + subtype CLK_GPOUT2_DIV_INT_Field is HAL.UInt16; + + type CLK_GPOUT2_DIV_Register is record + -- Fractional component of the divisor, can be changed on-the-fly + FRAC : CLK_GPOUT2_DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_GPOUT2_DIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT2_DIV_Register use record + FRAC at 0 range 0 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_GPOUT2_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_GPOUT2_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT2_SELECTED_Register use record + CLK_GPOUT2_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_GPOUT3_CTRL_AUXSRC_Field is + (clksrc_pll_sys, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb, + clksrc_pll_usb_primary_ref_opcg, + rosc_clksrc_ph, + xosc_clksrc, + lposc_clksrc, + clk_sys, + clk_usb, + clk_adc, + clk_ref, + clk_peri, + clk_hstx, + otp_clk2fc) + with Size => 4; + for CLK_GPOUT3_CTRL_AUXSRC_Field use + (clksrc_pll_sys => 0, + clksrc_gpin0 => 1, + clksrc_gpin1 => 2, + clksrc_pll_usb => 3, + clksrc_pll_usb_primary_ref_opcg => 4, + rosc_clksrc_ph => 5, + xosc_clksrc => 6, + lposc_clksrc => 7, + clk_sys => 8, + clk_usb => 9, + clk_adc => 10, + clk_ref => 11, + clk_peri => 12, + clk_hstx => 13, + otp_clk2fc => 14); + + subtype CLK_GPOUT3_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_GPOUT3_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_GPOUT3_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_sys; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- Enables duty cycle correction for odd divisors, can be changed + -- on-the-fly + DC50 : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_GPOUT3_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT3_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + DC50 at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_GPOUT3_DIV_FRAC_Field is HAL.UInt16; + subtype CLK_GPOUT3_DIV_INT_Field is HAL.UInt16; + + type CLK_GPOUT3_DIV_Register is record + -- Fractional component of the divisor, can be changed on-the-fly + FRAC : CLK_GPOUT3_DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_GPOUT3_DIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT3_DIV_Register use record + FRAC at 0 range 0 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_GPOUT3_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_GPOUT3_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_GPOUT3_SELECTED_Register use record + CLK_GPOUT3_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the clock source glitchlessly, can be changed on-the-fly + type CLK_REF_CTRL_SRC_Field is + (rosc_clksrc_ph, + clksrc_clk_ref_aux, + xosc_clksrc, + lposc_clksrc) + with Size => 2; + for CLK_REF_CTRL_SRC_Field use + (rosc_clksrc_ph => 0, + clksrc_clk_ref_aux => 1, + xosc_clksrc => 2, + lposc_clksrc => 3); + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_REF_CTRL_AUXSRC_Field is + (clksrc_pll_usb, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb_primary_ref_opcg) + with Size => 2; + for CLK_REF_CTRL_AUXSRC_Field use + (clksrc_pll_usb => 0, + clksrc_gpin0 => 1, + clksrc_gpin1 => 2, + clksrc_pll_usb_primary_ref_opcg => 3); + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_REF_CTRL_Register is record + -- Selects the clock source glitchlessly, can be changed on-the-fly + SRC : CLK_REF_CTRL_SRC_Field := + RP2350_SVD.CLOCKS.rosc_clksrc_ph; + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_REF_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_usb; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_REF_CTRL_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + AUXSRC at 0 range 5 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype CLK_REF_DIV_INT_Field is HAL.UInt8; + + type CLK_REF_DIV_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_REF_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_REF_DIV_Register use record + Reserved_0_15 at 0 range 0 .. 15; + INT at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CLK_REF_SELECTED_CLK_REF_SELECTED_Field is HAL.UInt4; + + -- Indicates which src is currently selected (one-hot) + type CLK_REF_SELECTED_Register is record + -- Read-only. The glitchless multiplexer does not switch instantaneously + -- (to avoid glitches), so software should poll this register to wait + -- for the switch to complete. This register contains one decoded bit + -- for each of the clock sources enumerated in the CTRL SRC field. At + -- most one of these bits will be set at any time, indicating that clock + -- is currently present at the output of the glitchless mux. Whilst + -- switching is in progress, this register may briefly show all-0s. + CLK_REF_SELECTED : CLK_REF_SELECTED_CLK_REF_SELECTED_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_REF_SELECTED_Register use record + CLK_REF_SELECTED at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Selects the clock source glitchlessly, can be changed on-the-fly + type CLK_SYS_CTRL_SRC_Field is + (clk_ref, + clksrc_clk_sys_aux) + with Size => 1; + for CLK_SYS_CTRL_SRC_Field use + (clk_ref => 0, + clksrc_clk_sys_aux => 1); + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_SYS_CTRL_AUXSRC_Field is + (clksrc_pll_sys, + clksrc_pll_usb, + rosc_clksrc, + xosc_clksrc, + clksrc_gpin0, + clksrc_gpin1) + with Size => 3; + for CLK_SYS_CTRL_AUXSRC_Field use + (clksrc_pll_sys => 0, + clksrc_pll_usb => 1, + rosc_clksrc => 2, + xosc_clksrc => 3, + clksrc_gpin0 => 4, + clksrc_gpin1 => 5); + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_SYS_CTRL_Register is record + -- Selects the clock source glitchlessly, can be changed on-the-fly + SRC : CLK_SYS_CTRL_SRC_Field := RP2350_SVD.CLOCKS.clk_ref; + -- unspecified + Reserved_1_4 : HAL.UInt4 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_SYS_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_sys; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_SYS_CTRL_Register use record + SRC at 0 range 0 .. 0; + Reserved_1_4 at 0 range 1 .. 4; + AUXSRC at 0 range 5 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CLK_SYS_DIV_FRAC_Field is HAL.UInt16; + subtype CLK_SYS_DIV_INT_Field is HAL.UInt16; + + type CLK_SYS_DIV_Register is record + -- Fractional component of the divisor, can be changed on-the-fly + FRAC : CLK_SYS_DIV_FRAC_Field := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_SYS_DIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_SYS_DIV_Register use record + FRAC at 0 range 0 .. 15; + INT at 0 range 16 .. 31; + end record; + + subtype CLK_SYS_SELECTED_CLK_SYS_SELECTED_Field is HAL.UInt2; + + -- Indicates which src is currently selected (one-hot) + type CLK_SYS_SELECTED_Register is record + -- Read-only. The glitchless multiplexer does not switch instantaneously + -- (to avoid glitches), so software should poll this register to wait + -- for the switch to complete. This register contains one decoded bit + -- for each of the clock sources enumerated in the CTRL SRC field. At + -- most one of these bits will be set at any time, indicating that clock + -- is currently present at the output of the glitchless mux. Whilst + -- switching is in progress, this register may briefly show all-0s. + CLK_SYS_SELECTED : CLK_SYS_SELECTED_CLK_SYS_SELECTED_Field; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_SYS_SELECTED_Register use record + CLK_SYS_SELECTED at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_PERI_CTRL_AUXSRC_Field is + (clk_sys, + clksrc_pll_sys, + clksrc_pll_usb, + rosc_clksrc_ph, + xosc_clksrc, + clksrc_gpin0, + clksrc_gpin1) + with Size => 3; + for CLK_PERI_CTRL_AUXSRC_Field use + (clk_sys => 0, + clksrc_pll_sys => 1, + clksrc_pll_usb => 2, + rosc_clksrc_ph => 3, + xosc_clksrc => 4, + clksrc_gpin0 => 5, + clksrc_gpin1 => 6); + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_PERI_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_PERI_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clk_sys; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- unspecified + Reserved_12_27 : HAL.UInt16 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_PERI_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + Reserved_12_27 at 0 range 12 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_PERI_DIV_INT_Field is HAL.UInt2; + + type CLK_PERI_DIV_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_PERI_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_PERI_DIV_Register use record + Reserved_0_15 at 0 range 0 .. 15; + INT at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_PERI_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_PERI_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_PERI_SELECTED_Register use record + CLK_PERI_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_HSTX_CTRL_AUXSRC_Field is + (clk_sys, + clksrc_pll_sys, + clksrc_pll_usb, + clksrc_gpin0, + clksrc_gpin1) + with Size => 3; + for CLK_HSTX_CTRL_AUXSRC_Field use + (clk_sys => 0, + clksrc_pll_sys => 1, + clksrc_pll_usb => 2, + clksrc_gpin0 => 3, + clksrc_gpin1 => 4); + + subtype CLK_HSTX_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_HSTX_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_HSTX_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clk_sys; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_HSTX_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_HSTX_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_HSTX_DIV_INT_Field is HAL.UInt2; + + type CLK_HSTX_DIV_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_HSTX_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_HSTX_DIV_Register use record + Reserved_0_15 at 0 range 0 .. 15; + INT at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_HSTX_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_HSTX_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_HSTX_SELECTED_Register use record + CLK_HSTX_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_USB_CTRL_AUXSRC_Field is + (clksrc_pll_usb, + clksrc_pll_sys, + rosc_clksrc_ph, + xosc_clksrc, + clksrc_gpin0, + clksrc_gpin1) + with Size => 3; + for CLK_USB_CTRL_AUXSRC_Field use + (clksrc_pll_usb => 0, + clksrc_pll_sys => 1, + rosc_clksrc_ph => 2, + xosc_clksrc => 3, + clksrc_gpin0 => 4, + clksrc_gpin1 => 5); + + subtype CLK_USB_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_USB_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_USB_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_usb; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_USB_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_USB_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_USB_DIV_INT_Field is HAL.UInt4; + + type CLK_USB_DIV_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_USB_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_USB_DIV_Register use record + Reserved_0_15 at 0 range 0 .. 15; + INT at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_USB_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_USB_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_USB_SELECTED_Register use record + CLK_USB_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selects the auxiliary clock source, will glitch when switching + type CLK_ADC_CTRL_AUXSRC_Field is + (clksrc_pll_usb, + clksrc_pll_sys, + rosc_clksrc_ph, + xosc_clksrc, + clksrc_gpin0, + clksrc_gpin1) + with Size => 3; + for CLK_ADC_CTRL_AUXSRC_Field use + (clksrc_pll_usb => 0, + clksrc_pll_sys => 1, + rosc_clksrc_ph => 2, + xosc_clksrc => 3, + clksrc_gpin0 => 4, + clksrc_gpin1 => 5); + + subtype CLK_ADC_CTRL_PHASE_Field is HAL.UInt2; + + -- Clock control, can be changed on-the-fly (except for auxsrc) + type CLK_ADC_CTRL_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Selects the auxiliary clock source, will glitch when switching + AUXSRC : CLK_ADC_CTRL_AUXSRC_Field := + RP2350_SVD.CLOCKS.clksrc_pll_usb; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Asynchronously kills the clock generator, enable must be set low + -- before deasserting kill + KILL : Boolean := False; + -- Starts and stops the clock generator cleanly + ENABLE : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- This delays the enable signal by up to 3 cycles of the input clock + -- This must be set before the clock is enabled to have any effect + PHASE : CLK_ADC_CTRL_PHASE_Field := 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- An edge on this signal shifts the phase of the output by 1 cycle of + -- the input clock This can be done at any time + NUDGE : Boolean := False; + -- unspecified + Reserved_21_27 : HAL.UInt7 := 16#0#; + -- Read-only. clock generator is enabled + ENABLED : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_ADC_CTRL_Register use record + Reserved_0_4 at 0 range 0 .. 4; + AUXSRC at 0 range 5 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + KILL at 0 range 10 .. 10; + ENABLE at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PHASE at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + NUDGE at 0 range 20 .. 20; + Reserved_21_27 at 0 range 21 .. 27; + ENABLED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype CLK_ADC_DIV_INT_Field is HAL.UInt4; + + type CLK_ADC_DIV_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + INT : CLK_ADC_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_ADC_DIV_Register use record + Reserved_0_15 at 0 range 0 .. 15; + INT at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Indicates which src is currently selected (one-hot) + type CLK_ADC_SELECTED_Register is record + -- Read-only. This slice does not have a glitchless mux (only the + -- AUX_SRC field is present, not SRC) so this register is hardwired to + -- 0x1. + CLK_ADC_SELECTED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_ADC_SELECTED_Register use record + CLK_ADC_SELECTED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + type DFTCLK_XOSC_CTRL_SRC_Field is + (NULL_k, + clksrc_pll_usb_primary, + clksrc_gpin0) + with Size => 2; + for DFTCLK_XOSC_CTRL_SRC_Field use + (NULL_k => 0, + clksrc_pll_usb_primary => 1, + clksrc_gpin0 => 2); + + type DFTCLK_XOSC_CTRL_Register is record + SRC : DFTCLK_XOSC_CTRL_SRC_Field := RP2350_SVD.CLOCKS.NULL_k; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DFTCLK_XOSC_CTRL_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + type DFTCLK_ROSC_CTRL_SRC_Field is + (NULL_k, + clksrc_pll_sys_primary_rosc, + clksrc_gpin1) + with Size => 2; + for DFTCLK_ROSC_CTRL_SRC_Field use + (NULL_k => 0, + clksrc_pll_sys_primary_rosc => 1, + clksrc_gpin1 => 2); + + type DFTCLK_ROSC_CTRL_Register is record + SRC : DFTCLK_ROSC_CTRL_SRC_Field := RP2350_SVD.CLOCKS.NULL_k; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DFTCLK_ROSC_CTRL_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + type DFTCLK_LPOSC_CTRL_SRC_Field is + (NULL_k, + clksrc_pll_usb_primary_lposc, + clksrc_gpin1) + with Size => 2; + for DFTCLK_LPOSC_CTRL_SRC_Field use + (NULL_k => 0, + clksrc_pll_usb_primary_lposc => 1, + clksrc_gpin1 => 2); + + type DFTCLK_LPOSC_CTRL_Register is record + SRC : DFTCLK_LPOSC_CTRL_SRC_Field := RP2350_SVD.CLOCKS.NULL_k; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DFTCLK_LPOSC_CTRL_Register use record + SRC at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype CLK_SYS_RESUS_CTRL_TIMEOUT_Field is HAL.UInt8; + + type CLK_SYS_RESUS_CTRL_Register is record + -- This is expressed as a number of clk_ref cycles and must be >= 2x + -- clk_ref_freq/min_clk_tst_freq + TIMEOUT : CLK_SYS_RESUS_CTRL_TIMEOUT_Field := 16#FF#; + -- Enable resus + ENABLE : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Force a resus, for test purposes only + FRCE : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- For clearing the resus after the fault that triggered it has been + -- corrected + CLEAR : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_SYS_RESUS_CTRL_Register use record + TIMEOUT at 0 range 0 .. 7; + ENABLE at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + FRCE at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + CLEAR at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + type CLK_SYS_RESUS_STATUS_Register is record + -- Read-only. Clock has been resuscitated, correct the error then send + -- ctrl_clear=1 + RESUSSED : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CLK_SYS_RESUS_STATUS_Register use record + RESUSSED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype FC0_REF_KHZ_FC0_REF_KHZ_Field is HAL.UInt20; + + -- Reference clock frequency in kHz + type FC0_REF_KHZ_Register is record + FC0_REF_KHZ : FC0_REF_KHZ_FC0_REF_KHZ_Field := 16#0#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_REF_KHZ_Register use record + FC0_REF_KHZ at 0 range 0 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype FC0_MIN_KHZ_FC0_MIN_KHZ_Field is HAL.UInt25; + + -- Minimum pass frequency in kHz. This is optional. Set to 0 if you are not + -- using the pass/fail flags + type FC0_MIN_KHZ_Register is record + FC0_MIN_KHZ : FC0_MIN_KHZ_FC0_MIN_KHZ_Field := 16#0#; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_MIN_KHZ_Register use record + FC0_MIN_KHZ at 0 range 0 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype FC0_MAX_KHZ_FC0_MAX_KHZ_Field is HAL.UInt25; + + -- Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you + -- are not using the pass/fail flags + type FC0_MAX_KHZ_Register is record + FC0_MAX_KHZ : FC0_MAX_KHZ_FC0_MAX_KHZ_Field := 16#1FFFFFF#; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_MAX_KHZ_Register use record + FC0_MAX_KHZ at 0 range 0 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype FC0_DELAY_FC0_DELAY_Field is HAL.UInt3; + + -- Delays the start of frequency counting to allow the mux to settle Delay + -- is measured in multiples of the reference clock period + type FC0_DELAY_Register is record + FC0_DELAY : FC0_DELAY_FC0_DELAY_Field := 16#1#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_DELAY_Register use record + FC0_DELAY at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype FC0_INTERVAL_FC0_INTERVAL_Field is HAL.UInt4; + + -- The test interval is 0.98us * 2**interval, but let's call it 1us * + -- 2**interval The default gives a test interval of 250us + type FC0_INTERVAL_Register is record + FC0_INTERVAL : FC0_INTERVAL_FC0_INTERVAL_Field := 16#8#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_INTERVAL_Register use record + FC0_INTERVAL at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + type FC0_SRC_FC0_SRC_Field is + (NULL_k, + pll_sys_clksrc_primary, + pll_usb_clksrc_primary, + rosc_clksrc, + rosc_clksrc_ph, + xosc_clksrc, + clksrc_gpin0, + clksrc_gpin1, + clk_ref, + clk_sys, + clk_peri, + clk_usb, + clk_adc, + clk_hstx, + lposc_clksrc, + otp_clk2fc, + pll_usb_clksrc_primary_dft) + with Size => 8; + for FC0_SRC_FC0_SRC_Field use + (NULL_k => 0, + pll_sys_clksrc_primary => 1, + pll_usb_clksrc_primary => 2, + rosc_clksrc => 3, + rosc_clksrc_ph => 4, + xosc_clksrc => 5, + clksrc_gpin0 => 6, + clksrc_gpin1 => 7, + clk_ref => 8, + clk_sys => 9, + clk_peri => 10, + clk_usb => 11, + clk_adc => 12, + clk_hstx => 13, + lposc_clksrc => 14, + otp_clk2fc => 15, + pll_usb_clksrc_primary_dft => 16); + + -- Clock sent to frequency counter, set to 0 when not required Writing to + -- this register initiates the frequency count + type FC0_SRC_Register is record + FC0_SRC : FC0_SRC_FC0_SRC_Field := RP2350_SVD.CLOCKS.NULL_k; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_SRC_Register use record + FC0_SRC at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Frequency counter status + type FC0_STATUS_Register is record + -- Read-only. Test passed + PASS : Boolean; + -- unspecified + Reserved_1_3 : HAL.UInt3; + -- Read-only. Test complete + DONE : Boolean; + -- unspecified + Reserved_5_7 : HAL.UInt3; + -- Read-only. Test running + RUNNING : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. Waiting for test clock to start + WAITING : Boolean; + -- unspecified + Reserved_13_15 : HAL.UInt3; + -- Read-only. Test failed + FAIL : Boolean; + -- unspecified + Reserved_17_19 : HAL.UInt3; + -- Read-only. Test clock slower than expected, only valid when + -- status_done=1 + SLOW : Boolean; + -- unspecified + Reserved_21_23 : HAL.UInt3; + -- Read-only. Test clock faster than expected, only valid when + -- status_done=1 + FAST : Boolean; + -- unspecified + Reserved_25_27 : HAL.UInt3; + -- Read-only. Test clock stopped during test + DIED : Boolean; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_STATUS_Register use record + PASS at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + DONE at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + RUNNING at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + WAITING at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + FAIL at 0 range 16 .. 16; + Reserved_17_19 at 0 range 17 .. 19; + SLOW at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + FAST at 0 range 24 .. 24; + Reserved_25_27 at 0 range 25 .. 27; + DIED at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype FC0_RESULT_FRAC_Field is HAL.UInt5; + subtype FC0_RESULT_KHZ_Field is HAL.UInt25; + + -- Result of frequency measurement, only valid when status_done=1 + type FC0_RESULT_Register is record + -- Read-only. + FRAC : FC0_RESULT_FRAC_Field; + -- Read-only. + KHZ : FC0_RESULT_KHZ_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FC0_RESULT_Register use record + FRAC at 0 range 0 .. 4; + KHZ at 0 range 5 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- WAKE_EN0_CLK_SYS_I2C array + type WAKE_EN0_CLK_SYS_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WAKE_EN0_CLK_SYS_I2C + type WAKE_EN0_CLK_SYS_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_I2C as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_I2C as an array + Arr : WAKE_EN0_CLK_SYS_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WAKE_EN0_CLK_SYS_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- WAKE_EN0_CLK_SYS_PIO array + type WAKE_EN0_CLK_SYS_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for WAKE_EN0_CLK_SYS_PIO + type WAKE_EN0_CLK_SYS_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_PIO as a value + Val : HAL.UInt3; + when True => + -- CLK_SYS_PIO as an array + Arr : WAKE_EN0_CLK_SYS_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for WAKE_EN0_CLK_SYS_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- enable clock in wake mode + type WAKE_EN0_Register is record + CLK_SYS_CLOCKS : Boolean := True; + CLK_SYS_ACCESSCTRL : Boolean := True; + CLK_ADC : Boolean := True; + CLK_SYS_ADC : Boolean := True; + CLK_SYS_BOOTRAM : Boolean := True; + CLK_SYS_BUSCTRL : Boolean := True; + CLK_SYS_BUSFABRIC : Boolean := True; + CLK_SYS_DMA : Boolean := True; + CLK_SYS_GLITCH_DETECTOR : Boolean := True; + CLK_HSTX : Boolean := True; + CLK_SYS_HSTX : Boolean := True; + CLK_SYS_I2C : WAKE_EN0_CLK_SYS_I2C_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_IO : Boolean := True; + CLK_SYS_JTAG : Boolean := True; + CLK_REF_OTP : Boolean := True; + CLK_SYS_OTP : Boolean := True; + CLK_SYS_PADS : Boolean := True; + CLK_SYS_PIO : WAKE_EN0_CLK_SYS_PIO_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_PLL_SYS : Boolean := True; + CLK_SYS_PLL_USB : Boolean := True; + CLK_REF_POWMAN : Boolean := True; + CLK_SYS_POWMAN : Boolean := True; + CLK_SYS_PWM : Boolean := True; + CLK_SYS_RESETS : Boolean := True; + CLK_SYS_ROM : Boolean := True; + CLK_SYS_ROSC : Boolean := True; + CLK_SYS_PSM : Boolean := True; + CLK_SYS_SHA256 : Boolean := True; + CLK_SYS_SIO : Boolean := True; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WAKE_EN0_Register use record + CLK_SYS_CLOCKS at 0 range 0 .. 0; + CLK_SYS_ACCESSCTRL at 0 range 1 .. 1; + CLK_ADC at 0 range 2 .. 2; + CLK_SYS_ADC at 0 range 3 .. 3; + CLK_SYS_BOOTRAM at 0 range 4 .. 4; + CLK_SYS_BUSCTRL at 0 range 5 .. 5; + CLK_SYS_BUSFABRIC at 0 range 6 .. 6; + CLK_SYS_DMA at 0 range 7 .. 7; + CLK_SYS_GLITCH_DETECTOR at 0 range 8 .. 8; + CLK_HSTX at 0 range 9 .. 9; + CLK_SYS_HSTX at 0 range 10 .. 10; + CLK_SYS_I2C at 0 range 11 .. 12; + CLK_SYS_IO at 0 range 13 .. 13; + CLK_SYS_JTAG at 0 range 14 .. 14; + CLK_REF_OTP at 0 range 15 .. 15; + CLK_SYS_OTP at 0 range 16 .. 16; + CLK_SYS_PADS at 0 range 17 .. 17; + CLK_SYS_PIO at 0 range 18 .. 20; + CLK_SYS_PLL_SYS at 0 range 21 .. 21; + CLK_SYS_PLL_USB at 0 range 22 .. 22; + CLK_REF_POWMAN at 0 range 23 .. 23; + CLK_SYS_POWMAN at 0 range 24 .. 24; + CLK_SYS_PWM at 0 range 25 .. 25; + CLK_SYS_RESETS at 0 range 26 .. 26; + CLK_SYS_ROM at 0 range 27 .. 27; + CLK_SYS_ROSC at 0 range 28 .. 28; + CLK_SYS_PSM at 0 range 29 .. 29; + CLK_SYS_SHA256 at 0 range 30 .. 30; + CLK_SYS_SIO at 0 range 31 .. 31; + end record; + + -- WAKE_EN1_CLK_SYS_SRAM array + type WAKE_EN1_CLK_SYS_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for WAKE_EN1_CLK_SYS_SRAM + type WAKE_EN1_CLK_SYS_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_SRAM as a value + Val : HAL.UInt10; + when True => + -- CLK_SYS_SRAM as an array + Arr : WAKE_EN1_CLK_SYS_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for WAKE_EN1_CLK_SYS_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- WAKE_EN1_CLK_SYS_TIMER array + type WAKE_EN1_CLK_SYS_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WAKE_EN1_CLK_SYS_TIMER + type WAKE_EN1_CLK_SYS_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_TIMER as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_TIMER as an array + Arr : WAKE_EN1_CLK_SYS_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WAKE_EN1_CLK_SYS_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- enable clock in wake mode + type WAKE_EN1_Register is record + CLK_PERI_SPI0 : Boolean := True; + CLK_SYS_SPI0 : Boolean := True; + CLK_PERI_SPI1 : Boolean := True; + CLK_SYS_SPI1 : Boolean := True; + CLK_SYS_SRAM : WAKE_EN1_CLK_SYS_SRAM_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_SYSCFG : Boolean := True; + CLK_SYS_SYSINFO : Boolean := True; + CLK_SYS_TBMAN : Boolean := True; + CLK_REF_TICKS : Boolean := True; + CLK_SYS_TICKS : Boolean := True; + CLK_SYS_TIMER : WAKE_EN1_CLK_SYS_TIMER_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_TRNG : Boolean := True; + CLK_PERI_UART0 : Boolean := True; + CLK_SYS_UART0 : Boolean := True; + CLK_PERI_UART1 : Boolean := True; + CLK_SYS_UART1 : Boolean := True; + CLK_SYS_USBCTRL : Boolean := True; + CLK_USB : Boolean := True; + CLK_SYS_WATCHDOG : Boolean := True; + CLK_SYS_XIP : Boolean := True; + CLK_SYS_XOSC : Boolean := True; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WAKE_EN1_Register use record + CLK_PERI_SPI0 at 0 range 0 .. 0; + CLK_SYS_SPI0 at 0 range 1 .. 1; + CLK_PERI_SPI1 at 0 range 2 .. 2; + CLK_SYS_SPI1 at 0 range 3 .. 3; + CLK_SYS_SRAM at 0 range 4 .. 13; + CLK_SYS_SYSCFG at 0 range 14 .. 14; + CLK_SYS_SYSINFO at 0 range 15 .. 15; + CLK_SYS_TBMAN at 0 range 16 .. 16; + CLK_REF_TICKS at 0 range 17 .. 17; + CLK_SYS_TICKS at 0 range 18 .. 18; + CLK_SYS_TIMER at 0 range 19 .. 20; + CLK_SYS_TRNG at 0 range 21 .. 21; + CLK_PERI_UART0 at 0 range 22 .. 22; + CLK_SYS_UART0 at 0 range 23 .. 23; + CLK_PERI_UART1 at 0 range 24 .. 24; + CLK_SYS_UART1 at 0 range 25 .. 25; + CLK_SYS_USBCTRL at 0 range 26 .. 26; + CLK_USB at 0 range 27 .. 27; + CLK_SYS_WATCHDOG at 0 range 28 .. 28; + CLK_SYS_XIP at 0 range 29 .. 29; + CLK_SYS_XOSC at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- SLEEP_EN0_CLK_SYS_I2C array + type SLEEP_EN0_CLK_SYS_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SLEEP_EN0_CLK_SYS_I2C + type SLEEP_EN0_CLK_SYS_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_I2C as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_I2C as an array + Arr : SLEEP_EN0_CLK_SYS_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SLEEP_EN0_CLK_SYS_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- SLEEP_EN0_CLK_SYS_PIO array + type SLEEP_EN0_CLK_SYS_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for SLEEP_EN0_CLK_SYS_PIO + type SLEEP_EN0_CLK_SYS_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_PIO as a value + Val : HAL.UInt3; + when True => + -- CLK_SYS_PIO as an array + Arr : SLEEP_EN0_CLK_SYS_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for SLEEP_EN0_CLK_SYS_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- enable clock in sleep mode + type SLEEP_EN0_Register is record + CLK_SYS_CLOCKS : Boolean := True; + CLK_SYS_ACCESSCTRL : Boolean := True; + CLK_ADC : Boolean := True; + CLK_SYS_ADC : Boolean := True; + CLK_SYS_BOOTRAM : Boolean := True; + CLK_SYS_BUSCTRL : Boolean := True; + CLK_SYS_BUSFABRIC : Boolean := True; + CLK_SYS_DMA : Boolean := True; + CLK_SYS_GLITCH_DETECTOR : Boolean := True; + CLK_HSTX : Boolean := True; + CLK_SYS_HSTX : Boolean := True; + CLK_SYS_I2C : SLEEP_EN0_CLK_SYS_I2C_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_IO : Boolean := True; + CLK_SYS_JTAG : Boolean := True; + CLK_REF_OTP : Boolean := True; + CLK_SYS_OTP : Boolean := True; + CLK_SYS_PADS : Boolean := True; + CLK_SYS_PIO : SLEEP_EN0_CLK_SYS_PIO_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_PLL_SYS : Boolean := True; + CLK_SYS_PLL_USB : Boolean := True; + CLK_REF_POWMAN : Boolean := True; + CLK_SYS_POWMAN : Boolean := True; + CLK_SYS_PWM : Boolean := True; + CLK_SYS_RESETS : Boolean := True; + CLK_SYS_ROM : Boolean := True; + CLK_SYS_ROSC : Boolean := True; + CLK_SYS_PSM : Boolean := True; + CLK_SYS_SHA256 : Boolean := True; + CLK_SYS_SIO : Boolean := True; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SLEEP_EN0_Register use record + CLK_SYS_CLOCKS at 0 range 0 .. 0; + CLK_SYS_ACCESSCTRL at 0 range 1 .. 1; + CLK_ADC at 0 range 2 .. 2; + CLK_SYS_ADC at 0 range 3 .. 3; + CLK_SYS_BOOTRAM at 0 range 4 .. 4; + CLK_SYS_BUSCTRL at 0 range 5 .. 5; + CLK_SYS_BUSFABRIC at 0 range 6 .. 6; + CLK_SYS_DMA at 0 range 7 .. 7; + CLK_SYS_GLITCH_DETECTOR at 0 range 8 .. 8; + CLK_HSTX at 0 range 9 .. 9; + CLK_SYS_HSTX at 0 range 10 .. 10; + CLK_SYS_I2C at 0 range 11 .. 12; + CLK_SYS_IO at 0 range 13 .. 13; + CLK_SYS_JTAG at 0 range 14 .. 14; + CLK_REF_OTP at 0 range 15 .. 15; + CLK_SYS_OTP at 0 range 16 .. 16; + CLK_SYS_PADS at 0 range 17 .. 17; + CLK_SYS_PIO at 0 range 18 .. 20; + CLK_SYS_PLL_SYS at 0 range 21 .. 21; + CLK_SYS_PLL_USB at 0 range 22 .. 22; + CLK_REF_POWMAN at 0 range 23 .. 23; + CLK_SYS_POWMAN at 0 range 24 .. 24; + CLK_SYS_PWM at 0 range 25 .. 25; + CLK_SYS_RESETS at 0 range 26 .. 26; + CLK_SYS_ROM at 0 range 27 .. 27; + CLK_SYS_ROSC at 0 range 28 .. 28; + CLK_SYS_PSM at 0 range 29 .. 29; + CLK_SYS_SHA256 at 0 range 30 .. 30; + CLK_SYS_SIO at 0 range 31 .. 31; + end record; + + -- SLEEP_EN1_CLK_SYS_SRAM array + type SLEEP_EN1_CLK_SYS_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for SLEEP_EN1_CLK_SYS_SRAM + type SLEEP_EN1_CLK_SYS_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_SRAM as a value + Val : HAL.UInt10; + when True => + -- CLK_SYS_SRAM as an array + Arr : SLEEP_EN1_CLK_SYS_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for SLEEP_EN1_CLK_SYS_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- SLEEP_EN1_CLK_SYS_TIMER array + type SLEEP_EN1_CLK_SYS_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SLEEP_EN1_CLK_SYS_TIMER + type SLEEP_EN1_CLK_SYS_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_TIMER as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_TIMER as an array + Arr : SLEEP_EN1_CLK_SYS_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SLEEP_EN1_CLK_SYS_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- enable clock in sleep mode + type SLEEP_EN1_Register is record + CLK_PERI_SPI0 : Boolean := True; + CLK_SYS_SPI0 : Boolean := True; + CLK_PERI_SPI1 : Boolean := True; + CLK_SYS_SPI1 : Boolean := True; + CLK_SYS_SRAM : SLEEP_EN1_CLK_SYS_SRAM_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_SYSCFG : Boolean := True; + CLK_SYS_SYSINFO : Boolean := True; + CLK_SYS_TBMAN : Boolean := True; + CLK_REF_TICKS : Boolean := True; + CLK_SYS_TICKS : Boolean := True; + CLK_SYS_TIMER : SLEEP_EN1_CLK_SYS_TIMER_Field := + (As_Array => False, Val => 16#1#); + CLK_SYS_TRNG : Boolean := True; + CLK_PERI_UART0 : Boolean := True; + CLK_SYS_UART0 : Boolean := True; + CLK_PERI_UART1 : Boolean := True; + CLK_SYS_UART1 : Boolean := True; + CLK_SYS_USBCTRL : Boolean := True; + CLK_USB : Boolean := True; + CLK_SYS_WATCHDOG : Boolean := True; + CLK_SYS_XIP : Boolean := True; + CLK_SYS_XOSC : Boolean := True; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SLEEP_EN1_Register use record + CLK_PERI_SPI0 at 0 range 0 .. 0; + CLK_SYS_SPI0 at 0 range 1 .. 1; + CLK_PERI_SPI1 at 0 range 2 .. 2; + CLK_SYS_SPI1 at 0 range 3 .. 3; + CLK_SYS_SRAM at 0 range 4 .. 13; + CLK_SYS_SYSCFG at 0 range 14 .. 14; + CLK_SYS_SYSINFO at 0 range 15 .. 15; + CLK_SYS_TBMAN at 0 range 16 .. 16; + CLK_REF_TICKS at 0 range 17 .. 17; + CLK_SYS_TICKS at 0 range 18 .. 18; + CLK_SYS_TIMER at 0 range 19 .. 20; + CLK_SYS_TRNG at 0 range 21 .. 21; + CLK_PERI_UART0 at 0 range 22 .. 22; + CLK_SYS_UART0 at 0 range 23 .. 23; + CLK_PERI_UART1 at 0 range 24 .. 24; + CLK_SYS_UART1 at 0 range 25 .. 25; + CLK_SYS_USBCTRL at 0 range 26 .. 26; + CLK_USB at 0 range 27 .. 27; + CLK_SYS_WATCHDOG at 0 range 28 .. 28; + CLK_SYS_XIP at 0 range 29 .. 29; + CLK_SYS_XOSC at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- ENABLED0_CLK_SYS_I2C array + type ENABLED0_CLK_SYS_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for ENABLED0_CLK_SYS_I2C + type ENABLED0_CLK_SYS_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_I2C as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_I2C as an array + Arr : ENABLED0_CLK_SYS_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for ENABLED0_CLK_SYS_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- ENABLED0_CLK_SYS_PIO array + type ENABLED0_CLK_SYS_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for ENABLED0_CLK_SYS_PIO + type ENABLED0_CLK_SYS_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_PIO as a value + Val : HAL.UInt3; + when True => + -- CLK_SYS_PIO as an array + Arr : ENABLED0_CLK_SYS_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for ENABLED0_CLK_SYS_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- indicates the state of the clock enable + type ENABLED0_Register is record + -- Read-only. + CLK_SYS_CLOCKS : Boolean; + -- Read-only. + CLK_SYS_ACCESSCTRL : Boolean; + -- Read-only. + CLK_ADC : Boolean; + -- Read-only. + CLK_SYS_ADC : Boolean; + -- Read-only. + CLK_SYS_BOOTRAM : Boolean; + -- Read-only. + CLK_SYS_BUSCTRL : Boolean; + -- Read-only. + CLK_SYS_BUSFABRIC : Boolean; + -- Read-only. + CLK_SYS_DMA : Boolean; + -- Read-only. + CLK_SYS_GLITCH_DETECTOR : Boolean; + -- Read-only. + CLK_HSTX : Boolean; + -- Read-only. + CLK_SYS_HSTX : Boolean; + -- Read-only. + CLK_SYS_I2C : ENABLED0_CLK_SYS_I2C_Field; + -- Read-only. + CLK_SYS_IO : Boolean; + -- Read-only. + CLK_SYS_JTAG : Boolean; + -- Read-only. + CLK_REF_OTP : Boolean; + -- Read-only. + CLK_SYS_OTP : Boolean; + -- Read-only. + CLK_SYS_PADS : Boolean; + -- Read-only. + CLK_SYS_PIO : ENABLED0_CLK_SYS_PIO_Field; + -- Read-only. + CLK_SYS_PLL_SYS : Boolean; + -- Read-only. + CLK_SYS_PLL_USB : Boolean; + -- Read-only. + CLK_REF_POWMAN : Boolean; + -- Read-only. + CLK_SYS_POWMAN : Boolean; + -- Read-only. + CLK_SYS_PWM : Boolean; + -- Read-only. + CLK_SYS_RESETS : Boolean; + -- Read-only. + CLK_SYS_ROM : Boolean; + -- Read-only. + CLK_SYS_ROSC : Boolean; + -- Read-only. + CLK_SYS_PSM : Boolean; + -- Read-only. + CLK_SYS_SHA256 : Boolean; + -- Read-only. + CLK_SYS_SIO : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLED0_Register use record + CLK_SYS_CLOCKS at 0 range 0 .. 0; + CLK_SYS_ACCESSCTRL at 0 range 1 .. 1; + CLK_ADC at 0 range 2 .. 2; + CLK_SYS_ADC at 0 range 3 .. 3; + CLK_SYS_BOOTRAM at 0 range 4 .. 4; + CLK_SYS_BUSCTRL at 0 range 5 .. 5; + CLK_SYS_BUSFABRIC at 0 range 6 .. 6; + CLK_SYS_DMA at 0 range 7 .. 7; + CLK_SYS_GLITCH_DETECTOR at 0 range 8 .. 8; + CLK_HSTX at 0 range 9 .. 9; + CLK_SYS_HSTX at 0 range 10 .. 10; + CLK_SYS_I2C at 0 range 11 .. 12; + CLK_SYS_IO at 0 range 13 .. 13; + CLK_SYS_JTAG at 0 range 14 .. 14; + CLK_REF_OTP at 0 range 15 .. 15; + CLK_SYS_OTP at 0 range 16 .. 16; + CLK_SYS_PADS at 0 range 17 .. 17; + CLK_SYS_PIO at 0 range 18 .. 20; + CLK_SYS_PLL_SYS at 0 range 21 .. 21; + CLK_SYS_PLL_USB at 0 range 22 .. 22; + CLK_REF_POWMAN at 0 range 23 .. 23; + CLK_SYS_POWMAN at 0 range 24 .. 24; + CLK_SYS_PWM at 0 range 25 .. 25; + CLK_SYS_RESETS at 0 range 26 .. 26; + CLK_SYS_ROM at 0 range 27 .. 27; + CLK_SYS_ROSC at 0 range 28 .. 28; + CLK_SYS_PSM at 0 range 29 .. 29; + CLK_SYS_SHA256 at 0 range 30 .. 30; + CLK_SYS_SIO at 0 range 31 .. 31; + end record; + + -- ENABLED1_CLK_SYS_SRAM array + type ENABLED1_CLK_SYS_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for ENABLED1_CLK_SYS_SRAM + type ENABLED1_CLK_SYS_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_SRAM as a value + Val : HAL.UInt10; + when True => + -- CLK_SYS_SRAM as an array + Arr : ENABLED1_CLK_SYS_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for ENABLED1_CLK_SYS_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- ENABLED1_CLK_SYS_TIMER array + type ENABLED1_CLK_SYS_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for ENABLED1_CLK_SYS_TIMER + type ENABLED1_CLK_SYS_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLK_SYS_TIMER as a value + Val : HAL.UInt2; + when True => + -- CLK_SYS_TIMER as an array + Arr : ENABLED1_CLK_SYS_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for ENABLED1_CLK_SYS_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- indicates the state of the clock enable + type ENABLED1_Register is record + -- Read-only. + CLK_PERI_SPI0 : Boolean; + -- Read-only. + CLK_SYS_SPI0 : Boolean; + -- Read-only. + CLK_PERI_SPI1 : Boolean; + -- Read-only. + CLK_SYS_SPI1 : Boolean; + -- Read-only. + CLK_SYS_SRAM : ENABLED1_CLK_SYS_SRAM_Field; + -- Read-only. + CLK_SYS_SYSCFG : Boolean; + -- Read-only. + CLK_SYS_SYSINFO : Boolean; + -- Read-only. + CLK_SYS_TBMAN : Boolean; + -- Read-only. + CLK_REF_TICKS : Boolean; + -- Read-only. + CLK_SYS_TICKS : Boolean; + -- Read-only. + CLK_SYS_TIMER : ENABLED1_CLK_SYS_TIMER_Field; + -- Read-only. + CLK_SYS_TRNG : Boolean; + -- Read-only. + CLK_PERI_UART0 : Boolean; + -- Read-only. + CLK_SYS_UART0 : Boolean; + -- Read-only. + CLK_PERI_UART1 : Boolean; + -- Read-only. + CLK_SYS_UART1 : Boolean; + -- Read-only. + CLK_SYS_USBCTRL : Boolean; + -- Read-only. + CLK_USB : Boolean; + -- Read-only. + CLK_SYS_WATCHDOG : Boolean; + -- Read-only. + CLK_SYS_XIP : Boolean; + -- Read-only. + CLK_SYS_XOSC : Boolean; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ENABLED1_Register use record + CLK_PERI_SPI0 at 0 range 0 .. 0; + CLK_SYS_SPI0 at 0 range 1 .. 1; + CLK_PERI_SPI1 at 0 range 2 .. 2; + CLK_SYS_SPI1 at 0 range 3 .. 3; + CLK_SYS_SRAM at 0 range 4 .. 13; + CLK_SYS_SYSCFG at 0 range 14 .. 14; + CLK_SYS_SYSINFO at 0 range 15 .. 15; + CLK_SYS_TBMAN at 0 range 16 .. 16; + CLK_REF_TICKS at 0 range 17 .. 17; + CLK_SYS_TICKS at 0 range 18 .. 18; + CLK_SYS_TIMER at 0 range 19 .. 20; + CLK_SYS_TRNG at 0 range 21 .. 21; + CLK_PERI_UART0 at 0 range 22 .. 22; + CLK_SYS_UART0 at 0 range 23 .. 23; + CLK_PERI_UART1 at 0 range 24 .. 24; + CLK_SYS_UART1 at 0 range 25 .. 25; + CLK_SYS_USBCTRL at 0 range 26 .. 26; + CLK_USB at 0 range 27 .. 27; + CLK_SYS_WATCHDOG at 0 range 28 .. 28; + CLK_SYS_XIP at 0 range 29 .. 29; + CLK_SYS_XOSC at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + CLK_SYS_RESUS : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + CLK_SYS_RESUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + CLK_SYS_RESUS : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + CLK_SYS_RESUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + CLK_SYS_RESUS : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + CLK_SYS_RESUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + CLK_SYS_RESUS : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + CLK_SYS_RESUS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type CLOCKS_Peripheral is record + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_GPOUT0_CTRL : aliased CLK_GPOUT0_CTRL_Register; + CLK_GPOUT0_DIV : aliased CLK_GPOUT0_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_GPOUT0_SELECTED : aliased CLK_GPOUT0_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_GPOUT1_CTRL : aliased CLK_GPOUT1_CTRL_Register; + CLK_GPOUT1_DIV : aliased CLK_GPOUT1_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_GPOUT1_SELECTED : aliased CLK_GPOUT1_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_GPOUT2_CTRL : aliased CLK_GPOUT2_CTRL_Register; + CLK_GPOUT2_DIV : aliased CLK_GPOUT2_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_GPOUT2_SELECTED : aliased CLK_GPOUT2_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_GPOUT3_CTRL : aliased CLK_GPOUT3_CTRL_Register; + CLK_GPOUT3_DIV : aliased CLK_GPOUT3_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_GPOUT3_SELECTED : aliased CLK_GPOUT3_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_REF_CTRL : aliased CLK_REF_CTRL_Register; + CLK_REF_DIV : aliased CLK_REF_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_REF_SELECTED : aliased CLK_REF_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_SYS_CTRL : aliased CLK_SYS_CTRL_Register; + CLK_SYS_DIV : aliased CLK_SYS_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_SYS_SELECTED : aliased CLK_SYS_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_PERI_CTRL : aliased CLK_PERI_CTRL_Register; + CLK_PERI_DIV : aliased CLK_PERI_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_PERI_SELECTED : aliased CLK_PERI_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_HSTX_CTRL : aliased CLK_HSTX_CTRL_Register; + CLK_HSTX_DIV : aliased CLK_HSTX_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_HSTX_SELECTED : aliased CLK_HSTX_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_USB_CTRL : aliased CLK_USB_CTRL_Register; + CLK_USB_DIV : aliased CLK_USB_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_USB_SELECTED : aliased CLK_USB_SELECTED_Register; + -- Clock control, can be changed on-the-fly (except for auxsrc) + CLK_ADC_CTRL : aliased CLK_ADC_CTRL_Register; + CLK_ADC_DIV : aliased CLK_ADC_DIV_Register; + -- Indicates which src is currently selected (one-hot) + CLK_ADC_SELECTED : aliased CLK_ADC_SELECTED_Register; + DFTCLK_XOSC_CTRL : aliased DFTCLK_XOSC_CTRL_Register; + DFTCLK_ROSC_CTRL : aliased DFTCLK_ROSC_CTRL_Register; + DFTCLK_LPOSC_CTRL : aliased DFTCLK_LPOSC_CTRL_Register; + CLK_SYS_RESUS_CTRL : aliased CLK_SYS_RESUS_CTRL_Register; + CLK_SYS_RESUS_STATUS : aliased CLK_SYS_RESUS_STATUS_Register; + -- Reference clock frequency in kHz + FC0_REF_KHZ : aliased FC0_REF_KHZ_Register; + -- Minimum pass frequency in kHz. This is optional. Set to 0 if you are + -- not using the pass/fail flags + FC0_MIN_KHZ : aliased FC0_MIN_KHZ_Register; + -- Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if + -- you are not using the pass/fail flags + FC0_MAX_KHZ : aliased FC0_MAX_KHZ_Register; + -- Delays the start of frequency counting to allow the mux to settle + -- Delay is measured in multiples of the reference clock period + FC0_DELAY : aliased FC0_DELAY_Register; + -- The test interval is 0.98us * 2**interval, but let's call it 1us * + -- 2**interval The default gives a test interval of 250us + FC0_INTERVAL : aliased FC0_INTERVAL_Register; + -- Clock sent to frequency counter, set to 0 when not required Writing + -- to this register initiates the frequency count + FC0_SRC : aliased FC0_SRC_Register; + -- Frequency counter status + FC0_STATUS : aliased FC0_STATUS_Register; + -- Result of frequency measurement, only valid when status_done=1 + FC0_RESULT : aliased FC0_RESULT_Register; + -- enable clock in wake mode + WAKE_EN0 : aliased WAKE_EN0_Register; + -- enable clock in wake mode + WAKE_EN1 : aliased WAKE_EN1_Register; + -- enable clock in sleep mode + SLEEP_EN0 : aliased SLEEP_EN0_Register; + -- enable clock in sleep mode + SLEEP_EN1 : aliased SLEEP_EN1_Register; + -- indicates the state of the clock enable + ENABLED0 : aliased ENABLED0_Register; + -- indicates the state of the clock enable + ENABLED1 : aliased ENABLED1_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for CLOCKS_Peripheral use record + CLK_GPOUT0_CTRL at 16#0# range 0 .. 31; + CLK_GPOUT0_DIV at 16#4# range 0 .. 31; + CLK_GPOUT0_SELECTED at 16#8# range 0 .. 31; + CLK_GPOUT1_CTRL at 16#C# range 0 .. 31; + CLK_GPOUT1_DIV at 16#10# range 0 .. 31; + CLK_GPOUT1_SELECTED at 16#14# range 0 .. 31; + CLK_GPOUT2_CTRL at 16#18# range 0 .. 31; + CLK_GPOUT2_DIV at 16#1C# range 0 .. 31; + CLK_GPOUT2_SELECTED at 16#20# range 0 .. 31; + CLK_GPOUT3_CTRL at 16#24# range 0 .. 31; + CLK_GPOUT3_DIV at 16#28# range 0 .. 31; + CLK_GPOUT3_SELECTED at 16#2C# range 0 .. 31; + CLK_REF_CTRL at 16#30# range 0 .. 31; + CLK_REF_DIV at 16#34# range 0 .. 31; + CLK_REF_SELECTED at 16#38# range 0 .. 31; + CLK_SYS_CTRL at 16#3C# range 0 .. 31; + CLK_SYS_DIV at 16#40# range 0 .. 31; + CLK_SYS_SELECTED at 16#44# range 0 .. 31; + CLK_PERI_CTRL at 16#48# range 0 .. 31; + CLK_PERI_DIV at 16#4C# range 0 .. 31; + CLK_PERI_SELECTED at 16#50# range 0 .. 31; + CLK_HSTX_CTRL at 16#54# range 0 .. 31; + CLK_HSTX_DIV at 16#58# range 0 .. 31; + CLK_HSTX_SELECTED at 16#5C# range 0 .. 31; + CLK_USB_CTRL at 16#60# range 0 .. 31; + CLK_USB_DIV at 16#64# range 0 .. 31; + CLK_USB_SELECTED at 16#68# range 0 .. 31; + CLK_ADC_CTRL at 16#6C# range 0 .. 31; + CLK_ADC_DIV at 16#70# range 0 .. 31; + CLK_ADC_SELECTED at 16#74# range 0 .. 31; + DFTCLK_XOSC_CTRL at 16#78# range 0 .. 31; + DFTCLK_ROSC_CTRL at 16#7C# range 0 .. 31; + DFTCLK_LPOSC_CTRL at 16#80# range 0 .. 31; + CLK_SYS_RESUS_CTRL at 16#84# range 0 .. 31; + CLK_SYS_RESUS_STATUS at 16#88# range 0 .. 31; + FC0_REF_KHZ at 16#8C# range 0 .. 31; + FC0_MIN_KHZ at 16#90# range 0 .. 31; + FC0_MAX_KHZ at 16#94# range 0 .. 31; + FC0_DELAY at 16#98# range 0 .. 31; + FC0_INTERVAL at 16#9C# range 0 .. 31; + FC0_SRC at 16#A0# range 0 .. 31; + FC0_STATUS at 16#A4# range 0 .. 31; + FC0_RESULT at 16#A8# range 0 .. 31; + WAKE_EN0 at 16#AC# range 0 .. 31; + WAKE_EN1 at 16#B0# range 0 .. 31; + SLEEP_EN0 at 16#B4# range 0 .. 31; + SLEEP_EN1 at 16#B8# range 0 .. 31; + ENABLED0 at 16#BC# range 0 .. 31; + ENABLED1 at 16#C0# range 0 .. 31; + INTR at 16#C4# range 0 .. 31; + INTE at 16#C8# range 0 .. 31; + INTF at 16#CC# range 0 .. 31; + INTS at 16#D0# range 0 .. 31; + end record; + + CLOCKS_Periph : aliased CLOCKS_Peripheral + with Import, Address => CLOCKS_Base; + +end RP2350_SVD.CLOCKS; diff --git a/src/svd/rp2350_svd-coresight_trace.ads b/src/svd/rp2350_svd-coresight_trace.ads new file mode 100644 index 0000000..812a941 --- /dev/null +++ b/src/svd/rp2350_svd-coresight_trace.ads @@ -0,0 +1,69 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Coresight block - RP specific registers +package RP2350_SVD.CORESIGHT_TRACE is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control and status register + type CTRL_STATUS_Register is record + -- Set to 1 to continuously hold the trace FIFO in a flushed state and + -- prevent overflow. Before clearing this flag, configure and start a + -- DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO + -- register. Clear this flag to begin sampling trace data, and set once + -- again once the trace capture buffer is full. You must configure the + -- TPIU in order to generate trace packets to be captured, as well as + -- components like the ETM further upstream to generate the event stream + -- propagated to the TPIU. + TRACE_CAPTURE_FIFO_FLUSH : Boolean := True; + -- This status flag is set high when trace data has been dropped due to + -- the FIFO being full at the point trace data was sampled. Write 1 to + -- acknowledge and clear the bit. + TRACE_CAPTURE_FIFO_OVERFLOW : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_STATUS_Register use record + TRACE_CAPTURE_FIFO_FLUSH at 0 range 0 .. 0; + TRACE_CAPTURE_FIFO_OVERFLOW at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Coresight block - RP specific registers + type CORESIGHT_TRACE_Peripheral is record + -- Control and status register + CTRL_STATUS : aliased CTRL_STATUS_Register; + -- FIFO for trace data captured from the TPIU + TRACE_CAPTURE_FIFO : aliased HAL.UInt32; + end record + with Volatile; + + for CORESIGHT_TRACE_Peripheral use record + CTRL_STATUS at 16#0# range 0 .. 31; + TRACE_CAPTURE_FIFO at 16#4# range 0 .. 31; + end record; + + -- Coresight block - RP specific registers + CORESIGHT_TRACE_Periph : aliased CORESIGHT_TRACE_Peripheral + with Import, Address => CORESIGHT_TRACE_Base; + +end RP2350_SVD.CORESIGHT_TRACE; diff --git a/src/svd/rp2350_svd-dma.ads b/src/svd/rp2350_svd-dma.ads new file mode 100644 index 0000000..83cb328 --- /dev/null +++ b/src/svd/rp2350_svd-dma.ads @@ -0,0 +1,8904 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- DMA with separate read and write masters +package RP2350_SVD.DMA is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CH0_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH0_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH0_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 0 Transfer Count + type CH0_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH0_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH0_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH0_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH0_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH0_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH0_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH0_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH0_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH0_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 0 Control and Status + type CH0_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH0_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH0_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH0_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH0_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH1_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH1_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH1_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 1 Transfer Count + type CH1_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH1_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH1_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH1_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH1_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH1_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH1_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH1_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH1_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH1_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 1 Control and Status + type CH1_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH1_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH1_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH1_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH1_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH2_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH2_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH2_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 2 Transfer Count + type CH2_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH2_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH2_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH2_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH2_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH2_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH2_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH2_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH2_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH2_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 2 Control and Status + type CH2_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH2_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH2_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH2_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH2_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH3_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH3_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH3_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 3 Transfer Count + type CH3_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH3_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH3_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH3_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH3_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH3_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH3_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH3_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH3_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH3_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 3 Control and Status + type CH3_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH3_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH3_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH3_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH3_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH4_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH4_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH4_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 4 Transfer Count + type CH4_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH4_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH4_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH4_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH4_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH4_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH4_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH4_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH4_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH4_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 4 Control and Status + type CH4_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH4_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH4_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH4_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH4_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH5_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH5_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH5_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 5 Transfer Count + type CH5_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH5_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH5_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH5_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH5_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH5_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH5_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH5_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH5_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH5_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 5 Control and Status + type CH5_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH5_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH5_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH5_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH5_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH6_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH6_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH6_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 6 Transfer Count + type CH6_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH6_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH6_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH6_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH6_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH6_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH6_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH6_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH6_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH6_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 6 Control and Status + type CH6_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH6_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH6_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH6_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH6_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH7_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH7_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH7_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 7 Transfer Count + type CH7_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH7_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH7_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH7_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH7_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH7_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH7_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH7_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH7_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH7_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 7 Control and Status + type CH7_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH7_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH7_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH7_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH7_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH8_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH8_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH8_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 8 Transfer Count + type CH8_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH8_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH8_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH8_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH8_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH8_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH8_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH8_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH8_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH8_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 8 Control and Status + type CH8_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH8_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH8_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH8_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH8_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH9_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH9_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH9_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 9 Transfer Count + type CH9_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH9_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH9_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH9_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH9_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH9_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH9_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH9_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH9_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH9_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 9 Control and Status + type CH9_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH9_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH9_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH9_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH9_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH10_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH10_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH10_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 10 Transfer Count + type CH10_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH10_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH10_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH10_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH10_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH10_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH10_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH10_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH10_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH10_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 10 Control and Status + type CH10_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH10_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH10_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH10_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH10_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH11_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH11_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH11_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 11 Transfer Count + type CH11_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH11_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH11_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH11_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH11_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH11_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH11_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH11_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH11_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH11_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 11 Control and Status + type CH11_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH11_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH11_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH11_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH11_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH12_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH12_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH12_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 12 Transfer Count + type CH12_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH12_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH12_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH12_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH12_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH12_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH12_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH12_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH12_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH12_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH12_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 12 Control and Status + type CH12_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH12_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH12_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH12_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH12_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH12_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH13_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH13_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH13_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 13 Transfer Count + type CH13_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH13_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH13_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH13_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH13_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH13_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH13_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH13_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH13_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH13_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH13_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 13 Control and Status + type CH13_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH13_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH13_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH13_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH13_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH13_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH14_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH14_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH14_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 14 Transfer Count + type CH14_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH14_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH14_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH14_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH14_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH14_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH14_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH14_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH14_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH14_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH14_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 14 Control and Status + type CH14_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH14_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH14_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH14_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH14_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH14_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype CH15_TRANS_COUNT_COUNT_Field is HAL.UInt28; + + -- When MODE is 0x0, the transfer count decrements with each transfer until + -- 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each + -- transfer until 0, and then the channel re-triggers itself, in addition + -- to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an + -- endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the + -- transfer count does not decrement. The DMA channel performs an endless + -- sequence of transfers, never triggering other channels or raising + -- interrupts, until an ABORT is raised. All other values are reserved. + type CH15_TRANS_COUNT_MODE_Field is + (NORMAL, + TRIGGER_SELF, + ENDLESS) + with Size => 4; + for CH15_TRANS_COUNT_MODE_Field use + (NORMAL => 0, + TRIGGER_SELF => 1, + ENDLESS => 15); + + -- DMA Channel 15 Transfer Count + type CH15_TRANS_COUNT_Register is record + -- 28-bit transfer count (256 million transfers maximum). Program the + -- number of bus transfers a channel will perform before halting. Note + -- that, if transfers are larger than one byte in size, this is not + -- equal to the number of bytes transferred (see CTRL_DATA_SIZE). When + -- the channel is active, reading this register shows the number of + -- transfers remaining, updating automatically each time a write + -- transfer completes. Writing this register sets the RELOAD value for + -- the transfer counter. Each time this channel is triggered, the RELOAD + -- value is copied into the live transfer counter. The channel can be + -- started multiple times, and will perform the same number of transfers + -- each time, as programmed by most recent write. The RELOAD value can + -- be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the + -- written value is used immediately as the length of the new transfer + -- sequence, as well as being written to RELOAD. + COUNT : CH15_TRANS_COUNT_COUNT_Field := 16#0#; + -- When MODE is 0x0, the transfer count decrements with each transfer + -- until 0, and then the channel triggers the next channel indicated by + -- CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with + -- each transfer until 0, and then the channel re-triggers itself, in + -- addition to the trigger indicated by CTRL_CHAIN_TO. This is useful + -- for e.g. an endless ring-buffer DMA with periodic interrupts. When + -- MODE is 0xf, the transfer count does not decrement. The DMA channel + -- performs an endless sequence of transfers, never triggering other + -- channels or raising interrupts, until an ABORT is raised. All other + -- values are reserved. + MODE : CH15_TRANS_COUNT_MODE_Field := RP2350_SVD.DMA.NORMAL; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH15_TRANS_COUNT_Register use record + COUNT at 0 range 0 .. 27; + MODE at 0 range 28 .. 31; + end record; + + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + type CH15_CTRL_TRIG_DATA_SIZE_Field is + (SIZE_BYTE, + SIZE_HALFWORD, + SIZE_WORD) + with Size => 2; + for CH15_CTRL_TRIG_DATA_SIZE_Field use + (SIZE_BYTE => 0, + SIZE_HALFWORD => 1, + SIZE_WORD => 2); + + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address on a + -- (1 << n) byte boundary, facilitating access to naturally-aligned ring + -- buffers. Ring sizes between 2 and 32768 bytes are possible. This can + -- apply to either read or write addresses, based on value of RING_SEL. + type CH15_CTRL_TRIG_RING_SIZE_Field is + (RING_NONE) + with Size => 4; + for CH15_CTRL_TRIG_RING_SIZE_Field use + (RING_NONE => 0); + + subtype CH15_CTRL_TRIG_CHAIN_TO_Field is HAL.UInt4; + + -- Select a Transfer Request signal. The channel uses the transfer request + -- signal to pace its data transfer rate. Sources for TREQ signals are + -- internal (TIMERS) or external (DREQ, a Data Request from the system). + -- 0x0 to 0x3a -> select DREQ n as TREQ + type CH15_CTRL_TRIG_TREQ_SEL_Field is + (-- Select PIO0's TX FIFO 0 as TREQ + PIO0_TX0, + -- Select PIO0's TX FIFO 1 as TREQ + PIO0_TX1, + -- Select PIO0's TX FIFO 2 as TREQ + PIO0_TX2, + -- Select PIO0's TX FIFO 3 as TREQ + PIO0_TX3, + -- Select PIO0's RX FIFO 0 as TREQ + PIO0_RX0, + -- Select PIO0's RX FIFO 1 as TREQ + PIO0_RX1, + -- Select PIO0's RX FIFO 2 as TREQ + PIO0_RX2, + -- Select PIO0's RX FIFO 3 as TREQ + PIO0_RX3, + -- Select PIO1's TX FIFO 0 as TREQ + PIO1_TX0, + -- Select PIO1's TX FIFO 1 as TREQ + PIO1_TX1, + -- Select PIO1's TX FIFO 2 as TREQ + PIO1_TX2, + -- Select PIO1's TX FIFO 3 as TREQ + PIO1_TX3, + -- Select PIO1's RX FIFO 0 as TREQ + PIO1_RX0, + -- Select PIO1's RX FIFO 1 as TREQ + PIO1_RX1, + -- Select PIO1's RX FIFO 2 as TREQ + PIO1_RX2, + -- Select PIO1's RX FIFO 3 as TREQ + PIO1_RX3, + -- Select PIO2's TX FIFO 0 as TREQ + PIO2_TX0, + -- Select PIO2's TX FIFO 1 as TREQ + PIO2_TX1, + -- Select PIO2's TX FIFO 2 as TREQ + PIO2_TX2, + -- Select PIO2's TX FIFO 3 as TREQ + PIO2_TX3, + -- Select PIO2's RX FIFO 0 as TREQ + PIO2_RX0, + -- Select PIO2's RX FIFO 1 as TREQ + PIO2_RX1, + -- Select PIO2's RX FIFO 2 as TREQ + PIO2_RX2, + -- Select PIO2's RX FIFO 3 as TREQ + PIO2_RX3, + -- Select SPI0's TX FIFO as TREQ + SPI0_TX, + -- Select SPI0's RX FIFO as TREQ + SPI0_RX, + -- Select SPI1's TX FIFO as TREQ + SPI1_TX, + -- Select SPI1's RX FIFO as TREQ + SPI1_RX, + -- Select UART0's TX FIFO as TREQ + UART0_TX, + -- Select UART0's RX FIFO as TREQ + UART0_RX, + -- Select UART1's TX FIFO as TREQ + UART1_TX, + -- Select UART1's RX FIFO as TREQ + UART1_RX, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP0, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP1, + -- Select PWM Counter 2's Wrap Value as TREQ + PWM_WRAP2, + -- Select PWM Counter 3's Wrap Value as TREQ + PWM_WRAP3, + -- Select PWM Counter 4's Wrap Value as TREQ + PWM_WRAP4, + -- Select PWM Counter 5's Wrap Value as TREQ + PWM_WRAP5, + -- Select PWM Counter 6's Wrap Value as TREQ + PWM_WRAP6, + -- Select PWM Counter 7's Wrap Value as TREQ + PWM_WRAP7, + -- Select PWM Counter 8's Wrap Value as TREQ + PWM_WRAP8, + -- Select PWM Counter 9's Wrap Value as TREQ + PWM_WRAP9, + -- Select PWM Counter 0's Wrap Value as TREQ + PWM_WRAP10, + -- Select PWM Counter 1's Wrap Value as TREQ + PWM_WRAP11, + -- Select I2C0's TX FIFO as TREQ + I2C0_TX, + -- Select I2C0's RX FIFO as TREQ + I2C0_RX, + -- Select I2C1's TX FIFO as TREQ + I2C1_TX, + -- Select I2C1's RX FIFO as TREQ + I2C1_RX, + -- Select the ADC as TREQ + ADC, + -- Select the XIP Streaming FIFO as TREQ + XIP_STREAM, + -- Select XIP_QMITX as TREQ + XIP_QMITX, + -- Select XIP_QMIRX as TREQ + XIP_QMIRX, + -- Select HSTX as TREQ + HSTX, + -- Select CORESIGHT as TREQ + CORESIGHT, + -- Select SHA256 as TREQ + SHA256, + -- Select Timer 0 as TREQ + TIMER0, + -- Select Timer 1 as TREQ + TIMER1, + -- Select Timer 2 as TREQ (Optional) + TIMER2, + -- Select Timer 3 as TREQ (Optional) + TIMER3, + -- Permanent request, for unpaced transfers. + PERMANENT) + with Size => 6; + for CH15_CTRL_TRIG_TREQ_SEL_Field use + (PIO0_TX0 => 0, + PIO0_TX1 => 1, + PIO0_TX2 => 2, + PIO0_TX3 => 3, + PIO0_RX0 => 4, + PIO0_RX1 => 5, + PIO0_RX2 => 6, + PIO0_RX3 => 7, + PIO1_TX0 => 8, + PIO1_TX1 => 9, + PIO1_TX2 => 10, + PIO1_TX3 => 11, + PIO1_RX0 => 12, + PIO1_RX1 => 13, + PIO1_RX2 => 14, + PIO1_RX3 => 15, + PIO2_TX0 => 16, + PIO2_TX1 => 17, + PIO2_TX2 => 18, + PIO2_TX3 => 19, + PIO2_RX0 => 20, + PIO2_RX1 => 21, + PIO2_RX2 => 22, + PIO2_RX3 => 23, + SPI0_TX => 24, + SPI0_RX => 25, + SPI1_TX => 26, + SPI1_RX => 27, + UART0_TX => 28, + UART0_RX => 29, + UART1_TX => 30, + UART1_RX => 31, + PWM_WRAP0 => 32, + PWM_WRAP1 => 33, + PWM_WRAP2 => 34, + PWM_WRAP3 => 35, + PWM_WRAP4 => 36, + PWM_WRAP5 => 37, + PWM_WRAP6 => 38, + PWM_WRAP7 => 39, + PWM_WRAP8 => 40, + PWM_WRAP9 => 41, + PWM_WRAP10 => 42, + PWM_WRAP11 => 43, + I2C0_TX => 44, + I2C0_RX => 45, + I2C1_TX => 46, + I2C1_RX => 47, + ADC => 48, + XIP_STREAM => 49, + XIP_QMITX => 50, + XIP_QMIRX => 51, + HSTX => 52, + CORESIGHT => 53, + SHA256 => 54, + TIMER0 => 59, + TIMER1 => 60, + TIMER2 => 61, + TIMER3 => 62, + PERMANENT => 63); + + -- DMA Channel 15 Control and Status + type CH15_CTRL_TRIG_Register is record + -- DMA Channel Enable. When 1, the channel will respond to triggering + -- events, which will cause it to become BUSY and start transferring + -- data. When 0, the channel will ignore triggers, stop issuing + -- transfers, and pause the current transfer sequence (i.e. BUSY will + -- remain high if already high) + EN : Boolean := False; + -- HIGH_PRIORITY gives a channel preferential treatment in issue + -- scheduling: in each scheduling round, all high priority channels are + -- considered first, and then only a single low priority channel, before + -- returning to the high priority channels. This only affects the order + -- in which the DMA schedules channels. The DMA's bus priority is not + -- changed. If the DMA is not saturated then a low priority channel will + -- see no loss of throughput. + HIGH_PRIORITY : Boolean := False; + -- Set the size of each bus transfer (byte/halfword/word). READ_ADDR and + -- WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE : CH15_CTRL_TRIG_DATA_SIZE_Field := + RP2350_SVD.DMA.SIZE_BYTE; + -- If 1, the read address increments with each transfer. If 0, each read + -- is directed to the same, initial address. Generally this should be + -- disabled for peripheral-to-memory transfers. + INCR_READ : Boolean := False; + -- If 1, and INCR_READ is 1, the read address is decremented rather than + -- incremented with each transfer. If 1, and INCR_READ is 0, this + -- otherwise-unused combination causes the read address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_READ_REV : Boolean := False; + -- If 1, the write address increments with each transfer. If 0, each + -- write is directed to the same, initial address. Generally this should + -- be disabled for memory-to-peripheral transfers. + INCR_WRITE : Boolean := False; + -- If 1, and INCR_WRITE is 1, the write address is decremented rather + -- than incremented with each transfer. If 1, and INCR_WRITE is 0, this + -- otherwise-unused combination causes the write address to be + -- incremented by twice the transfer size, i.e. skipping over alternate + -- addresses. + INCR_WRITE_REV : Boolean := False; + -- Size of address wrap region. If 0, don't wrap. For values n > 0, only + -- the lower n bits of the address will change. This wraps the address + -- on a (1 << n) byte boundary, facilitating access to naturally-aligned + -- ring buffers. Ring sizes between 2 and 32768 bytes are possible. This + -- can apply to either read or write addresses, based on value of + -- RING_SEL. + RING_SIZE : CH15_CTRL_TRIG_RING_SIZE_Field := + RP2350_SVD.DMA.RING_NONE; + -- Select whether RING_SIZE applies to read or write addresses. If 0, + -- read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, + -- write addresses are wrapped. + RING_SEL : Boolean := False; + -- When this channel completes, it will trigger the channel indicated by + -- CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Note this + -- field resets to 0, so channels 1 and above will chain to channel 0 by + -- default. Set this field to avoid this behaviour. + CHAIN_TO : CH15_CTRL_TRIG_CHAIN_TO_Field := 16#0#; + -- Select a Transfer Request signal. The channel uses the transfer + -- request signal to pace its data transfer rate. Sources for TREQ + -- signals are internal (TIMERS) or external (DREQ, a Data Request from + -- the system). 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL : CH15_CTRL_TRIG_TREQ_SEL_Field := + RP2350_SVD.DMA.PIO0_TX0; + -- In QUIET mode, the channel does not generate IRQs at the end of every + -- transfer block. Instead, an IRQ is raised when NULL is written to a + -- trigger register, indicating the end of a control block chain. This + -- reduces the number of interrupts to be serviced by the CPU when + -- transferring a DMA chain of many small control blocks. + IRQ_QUIET : Boolean := False; + -- Apply byte-swap transformation to DMA data. For byte data, this has + -- no effect. For halfword data, the two bytes of each halfword are + -- swapped. For word data, the four bytes of each word are swapped to + -- reverse order. + BSWAP : Boolean := False; + -- If 1, this channel's data transfers are visible to the sniff + -- hardware, and each transfer will advance the state of the checksum. + -- This only applies if the sniff hardware is enabled, and has this + -- channel selected. This allows checksum to be enabled or disabled on a + -- per-control- block basis. + SNIFF_EN : Boolean := False; + -- Read-only. This flag goes high when the channel starts a new transfer + -- sequence, and low when the last transfer of that sequence completes. + -- Clearing EN while BUSY is high pauses the channel, and BUSY will stay + -- high while paused. To terminate a sequence early (and clear the BUSY + -- flag), see CHAN_ABORT. + BUSY : Boolean := False; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a write bus error. Write one + -- to clear. WRITE_ADDR shows the approximate address where the bus + -- error was encountered (will not be earlier, or more than 5 transfers + -- later) + WRITE_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. If 1, the channel received a read bus error. Write one + -- to clear. READ_ADDR shows the approximate address where the bus error + -- was encountered (will not be earlier, or more than 3 transfers later) + READ_ERROR : Boolean := False; + -- Read-only. Logical OR of the READ_ERROR and WRITE_ERROR flags. The + -- channel halts when it encounters any bus error, and always raises its + -- channel IRQ flag. + AHB_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH15_CTRL_TRIG_Register use record + EN at 0 range 0 .. 0; + HIGH_PRIORITY at 0 range 1 .. 1; + DATA_SIZE at 0 range 2 .. 3; + INCR_READ at 0 range 4 .. 4; + INCR_READ_REV at 0 range 5 .. 5; + INCR_WRITE at 0 range 6 .. 6; + INCR_WRITE_REV at 0 range 7 .. 7; + RING_SIZE at 0 range 8 .. 11; + RING_SEL at 0 range 12 .. 12; + CHAIN_TO at 0 range 13 .. 16; + TREQ_SEL at 0 range 17 .. 22; + IRQ_QUIET at 0 range 23 .. 23; + BSWAP at 0 range 24 .. 24; + SNIFF_EN at 0 range 25 .. 25; + BUSY at 0 range 26 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + WRITE_ERROR at 0 range 29 .. 29; + READ_ERROR at 0 range 30 .. 30; + AHB_ERROR at 0 range 31 .. 31; + end record; + + subtype INTR_INTR_Field is HAL.UInt16; + + -- Interrupt Status (raw) + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Raw interrupt status for DMA Channels 0..15. Bit n + -- corresponds to channel n. Ignores any masking or forcing. Channel + -- interrupts can be cleared by writing a bit mask to INTR or + -- INTS0/1/2/3. Channel interrupts can be routed to either of four + -- system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The + -- multiple system-level interrupts might be used to allow NVIC IRQ + -- preemption for more time-critical channels, to spread IRQ load across + -- different cores, or to target IRQs to different security domains. It + -- is also valid to ignore the multiple IRQs, and just use + -- INTE0/INTS0/IRQ 0. If this register is accessed at a + -- security/privilege level less than that of a given channel (as + -- defined by that channel's SECCFG_CHx register), then that channel's + -- interrupt status will read as 0, ignore writes. + INTR : INTR_INTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + INTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTE0_INTE0_Field is HAL.UInt16; + + -- Interrupt Enables for IRQ 0 + type INTE0_Register is record + -- Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this + -- bit has no effect if the channel security/privilege level, defined by + -- SECCFG_CHx, is greater than the IRQ security/privilege defined by + -- SECCFG_IRQ0. + INTE0 : INTE0_INTE0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE0_Register use record + INTE0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTF0_INTF0_Field is HAL.UInt16; + + -- Force Interrupts + type INTF0_Register is record + -- Write 1s to force the corresponding bits in INTS0. The interrupt + -- remains asserted until INTF0 is cleared. + INTF0 : INTF0_INTF0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF0_Register use record + INTF0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTS0_INTS0_Field is HAL.UInt16; + + -- Interrupt Status for IRQ 0 + type INTS0_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Indicates active channel interrupt requests which are + -- currently causing IRQ 0 to be asserted. Channel interrupts can be + -- cleared by writing a bit mask here. Channels with a + -- security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in + -- this register, and ignore writes. + INTS0 : INTS0_INTS0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS0_Register use record + INTS0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTR1_INTR1_Field is HAL.UInt16; + + -- Interrupt Status (raw) + type INTR1_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Raw interrupt status for DMA Channels 0..15. Bit n + -- corresponds to channel n. Ignores any masking or forcing. Channel + -- interrupts can be cleared by writing a bit mask to INTR or + -- INTS0/1/2/3. Channel interrupts can be routed to either of four + -- system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The + -- multiple system-level interrupts might be used to allow NVIC IRQ + -- preemption for more time-critical channels, to spread IRQ load across + -- different cores, or to target IRQs to different security domains. It + -- is also valid to ignore the multiple IRQs, and just use + -- INTE0/INTS0/IRQ 0. If this register is accessed at a + -- security/privilege level less than that of a given channel (as + -- defined by that channel's SECCFG_CHx register), then that channel's + -- interrupt status will read as 0, ignore writes. + INTR1 : INTR1_INTR1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR1_Register use record + INTR1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTE1_INTE1_Field is HAL.UInt16; + + -- Interrupt Enables for IRQ 1 + type INTE1_Register is record + -- Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this + -- bit has no effect if the channel security/privilege level, defined by + -- SECCFG_CHx, is greater than the IRQ security/privilege defined by + -- SECCFG_IRQ1. + INTE1 : INTE1_INTE1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE1_Register use record + INTE1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTF1_INTF1_Field is HAL.UInt16; + + -- Force Interrupts + type INTF1_Register is record + -- Write 1s to force the corresponding bits in INTS1. The interrupt + -- remains asserted until INTF1 is cleared. + INTF1 : INTF1_INTF1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF1_Register use record + INTF1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTS1_INTS1_Field is HAL.UInt16; + + -- Interrupt Status for IRQ 1 + type INTS1_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Indicates active channel interrupt requests which are + -- currently causing IRQ 1 to be asserted. Channel interrupts can be + -- cleared by writing a bit mask here. Channels with a + -- security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in + -- this register, and ignore writes. + INTS1 : INTS1_INTS1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS1_Register use record + INTS1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTR2_INTR2_Field is HAL.UInt16; + + -- Interrupt Status (raw) + type INTR2_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Raw interrupt status for DMA Channels 0..15. Bit n + -- corresponds to channel n. Ignores any masking or forcing. Channel + -- interrupts can be cleared by writing a bit mask to INTR or + -- INTS0/1/2/3. Channel interrupts can be routed to either of four + -- system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The + -- multiple system-level interrupts might be used to allow NVIC IRQ + -- preemption for more time-critical channels, to spread IRQ load across + -- different cores, or to target IRQs to different security domains. It + -- is also valid to ignore the multiple IRQs, and just use + -- INTE0/INTS0/IRQ 0. If this register is accessed at a + -- security/privilege level less than that of a given channel (as + -- defined by that channel's SECCFG_CHx register), then that channel's + -- interrupt status will read as 0, ignore writes. + INTR2 : INTR2_INTR2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR2_Register use record + INTR2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTE2_INTE2_Field is HAL.UInt16; + + -- Interrupt Enables for IRQ 2 + type INTE2_Register is record + -- Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this + -- bit has no effect if the channel security/privilege level, defined by + -- SECCFG_CHx, is greater than the IRQ security/privilege defined by + -- SECCFG_IRQ2. + INTE2 : INTE2_INTE2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE2_Register use record + INTE2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTF2_INTF2_Field is HAL.UInt16; + + -- Force Interrupts + type INTF2_Register is record + -- Write 1s to force the corresponding bits in INTS2. The interrupt + -- remains asserted until INTF2 is cleared. + INTF2 : INTF2_INTF2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF2_Register use record + INTF2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTS2_INTS2_Field is HAL.UInt16; + + -- Interrupt Status for IRQ 2 + type INTS2_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Indicates active channel interrupt requests which are + -- currently causing IRQ 2 to be asserted. Channel interrupts can be + -- cleared by writing a bit mask here. Channels with a + -- security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in + -- this register, and ignore writes. + INTS2 : INTS2_INTS2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS2_Register use record + INTS2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTR3_INTR3_Field is HAL.UInt16; + + -- Interrupt Status (raw) + type INTR3_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Raw interrupt status for DMA Channels 0..15. Bit n + -- corresponds to channel n. Ignores any masking or forcing. Channel + -- interrupts can be cleared by writing a bit mask to INTR or + -- INTS0/1/2/3. Channel interrupts can be routed to either of four + -- system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The + -- multiple system-level interrupts might be used to allow NVIC IRQ + -- preemption for more time-critical channels, to spread IRQ load across + -- different cores, or to target IRQs to different security domains. It + -- is also valid to ignore the multiple IRQs, and just use + -- INTE0/INTS0/IRQ 0. If this register is accessed at a + -- security/privilege level less than that of a given channel (as + -- defined by that channel's SECCFG_CHx register), then that channel's + -- interrupt status will read as 0, ignore writes. + INTR3 : INTR3_INTR3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR3_Register use record + INTR3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTE3_INTE3_Field is HAL.UInt16; + + -- Interrupt Enables for IRQ 3 + type INTE3_Register is record + -- Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this + -- bit has no effect if the channel security/privilege level, defined by + -- SECCFG_CHx, is greater than the IRQ security/privilege defined by + -- SECCFG_IRQ3. + INTE3 : INTE3_INTE3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE3_Register use record + INTE3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTF3_INTF3_Field is HAL.UInt16; + + -- Force Interrupts + type INTF3_Register is record + -- Write 1s to force the corresponding bits in INTS3. The interrupt + -- remains asserted until INTF3 is cleared. + INTF3 : INTF3_INTF3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF3_Register use record + INTF3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INTS3_INTS3_Field is HAL.UInt16; + + -- Interrupt Status for IRQ 3 + type INTS3_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Indicates active channel interrupt requests which are + -- currently causing IRQ 3 to be asserted. Channel interrupts can be + -- cleared by writing a bit mask here. Channels with a + -- security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in + -- this register, and ignore writes. + INTS3 : INTS3_INTS3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS3_Register use record + INTS3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TIMER_Y_Field is HAL.UInt16; + subtype TIMER_X_Field is HAL.UInt16; + + -- Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions + -- at a rate set by ((X/Y) * sys_clk). This equation is evaluated every + -- sys_clk cycles and therefore can only generate TREQs at a rate of 1 per + -- sys_clk (i.e. permanent TREQ) or less. + type TIMER_Register is record + -- Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional + -- timer. + Y : TIMER_Y_Field := 16#0#; + -- Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional + -- timer. + X : TIMER_X_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER_Register use record + Y at 0 range 0 .. 15; + X at 0 range 16 .. 31; + end record; + + subtype MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field is HAL.UInt16; + + -- Trigger one or more channels simultaneously + type MULTI_CHAN_TRIGGER_Register is record + -- Write-only. Each bit in this register corresponds to a DMA channel. + -- Writing a 1 to the relevant bit is the same as writing to that + -- channel's trigger register; the channel will start if it is currently + -- enabled and not already busy. + MULTI_CHAN_TRIGGER : MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Field := + 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MULTI_CHAN_TRIGGER_Register use record + MULTI_CHAN_TRIGGER at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SNIFF_CTRL_DMACH_Field is HAL.UInt4; + + type SNIFF_CTRL_CALC_Field is + (-- Calculate a CRC-32 (IEEE802.3 polynomial) + CRC32, + -- Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + CRC32R, + -- Calculate a CRC-16-CCITT + CRC16, + -- Calculate a CRC-16-CCITT with bit reversed data + CRC16R, + -- XOR reduction over all data. == 1 if the total 1 population count is odd. + EVEN, + -- Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + SUM) + with Size => 4; + for SNIFF_CTRL_CALC_Field use + (CRC32 => 0, + CRC32R => 1, + CRC16 => 2, + CRC16R => 3, + EVEN => 14, + SUM => 15); + + -- Sniffer Control + type SNIFF_CTRL_Register is record + -- Enable sniffer + EN : Boolean := False; + -- DMA channel for Sniffer to observe + DMACH : SNIFF_CTRL_DMACH_Field := 16#0#; + CALC : SNIFF_CTRL_CALC_Field := RP2350_SVD.DMA.CRC32; + -- Locally perform a byte reverse on the sniffed data, before feeding + -- into checksum. Note that the sniff hardware is downstream of the DMA + -- channel byteswap performed in the read master: if channel CTRL_BSWAP + -- and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the + -- sniffer's point of view. + BSWAP : Boolean := False; + -- If set, the result appears bit-reversed when read. This does not + -- affect the way the checksum is calculated; the result is transformed + -- on-the-fly between the result register and the bus. + OUT_REV : Boolean := False; + -- If set, the result appears inverted (bitwise complement) when read. + -- This does not affect the way the checksum is calculated; the result + -- is transformed on-the-fly between the result register and the bus. + OUT_INV : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SNIFF_CTRL_Register use record + EN at 0 range 0 .. 0; + DMACH at 0 range 1 .. 4; + CALC at 0 range 5 .. 8; + BSWAP at 0 range 9 .. 9; + OUT_REV at 0 range 10 .. 10; + OUT_INV at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype FIFO_LEVELS_TDF_LVL_Field is HAL.UInt8; + subtype FIFO_LEVELS_WAF_LVL_Field is HAL.UInt8; + subtype FIFO_LEVELS_RAF_LVL_Field is HAL.UInt8; + + -- Debug RAF, WAF, TDF levels + type FIFO_LEVELS_Register is record + -- Read-only. Current Transfer-Data-FIFO fill level + TDF_LVL : FIFO_LEVELS_TDF_LVL_Field; + -- Read-only. Current Write-Address-FIFO fill level + WAF_LVL : FIFO_LEVELS_WAF_LVL_Field; + -- Read-only. Current Read-Address-FIFO fill level + RAF_LVL : FIFO_LEVELS_RAF_LVL_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIFO_LEVELS_Register use record + TDF_LVL at 0 range 0 .. 7; + WAF_LVL at 0 range 8 .. 15; + RAF_LVL at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CHAN_ABORT_CHAN_ABORT_Field is HAL.UInt16; + + -- Abort an in-progress transfer sequence on one or more channels + type CHAN_ABORT_Register is record + -- Write-only. Each bit corresponds to a channel. Writing a 1 aborts + -- whatever transfer sequence is in progress on that channel. The bit + -- will remain high until any in-flight transfers have been flushed + -- through the address and data FIFOs. After writing, this register must + -- be polled until it returns all-zero. Until this point, it is unsafe + -- to restart the channel. + CHAN_ABORT : CHAN_ABORT_CHAN_ABORT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHAN_ABORT_Register use record + CHAN_ABORT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype N_CHANNELS_N_CHANNELS_Field is HAL.UInt5; + + -- The number of channels this DMA instance is equipped with. This DMA + -- supports up to 16 hardware channels, but can be configured with as few + -- as one, to minimise silicon area. + type N_CHANNELS_Register is record + -- Read-only. + N_CHANNELS : N_CHANNELS_N_CHANNELS_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for N_CHANNELS_Register use record + N_CHANNELS at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Security configuration for channel 0. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If + -- this channel generates bus accesses of some security level, an access of + -- at least that level (in the order S+P > S+U > NS+P > NS+U) is required + -- to program, trigger, abort, check the status of, interrupt on or + -- acknowledge the interrupt of this channel. This register automatically + -- locks down (becomes read-only) once software starts to configure the + -- channel. This register is world-readable, but is writable only from a + -- Secure, Privileged context. + type SECCFG_CH_Register is record + -- Privileged channel. If 1, this channel performs Privileged bus + -- accesses. If 0, it performs Unprivileged bus accesses. If 1, this + -- channel is controllable only from a Privileged context of the same + -- Secure/Non-secure level, or any context of a higher Secure/Non-secure + -- level. + P : Boolean := True; + -- Secure channel. If 1, this channel performs Secure bus accesses. If + -- 0, it performs Non-secure bus accesses. If 1, this channel is + -- controllable only from a Secure context. + S : Boolean := True; + -- LOCK is 0 at reset, and is set to 1 automatically upon a successful + -- write to this channel's control registers. That is, a write to CTRL, + -- READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK + -- bit is set, this register becomes read-only. A failed write, for + -- example due to the write's privilege being lower than that specified + -- in the channel's SECCFG register, will not set the LOCK bit. + LOCK : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SECCFG_CH_Register use record + P at 0 range 0 .. 0; + S at 0 range 1 .. 1; + LOCK at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Security configuration for IRQ 0. Control whether the IRQ permits + -- configuration by Non-secure/Unprivileged contexts, and whether it can + -- observe Secure/Privileged channel interrupt flags. + type SECCFG_IRQ_Register is record + -- Privileged IRQ. If 1, this IRQ's control registers can only be + -- accessed from a Privileged context. If 0, this IRQ's control + -- registers can be accessed from an Unprivileged context, but + -- Privileged channels (as per SECCFG_CHx) are masked from the IRQ + -- status, and this IRQ's registers can not be used to acknowledge the + -- channel interrupts of Privileged channels. + P : Boolean := True; + -- Secure IRQ. If 1, this IRQ's control registers can only be accessed + -- from a Secure context. If 0, this IRQ's control registers can be + -- accessed from a Non-secure context, but Secure channels (as per + -- SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers + -- can not be used to acknowledge the channel interrupts of Secure + -- channels. + S : Boolean := True; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SECCFG_IRQ_Register use record + P at 0 range 0 .. 0; + S at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Miscellaneous security configuration + type SECCFG_MISC_Register is record + -- If 1, the sniffer can see data transfers from Privileged channels, + -- and can itself only be accessed from a privileged context, or from a + -- Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed + -- from either a Privileged or Unprivileged context (with sufficient + -- security level) but can not see transfers from Privileged channels. + SNIFF_P : Boolean := True; + -- If 1, the sniffer can see data transfers from Secure channels, and + -- can itself only be accessed from a Secure context. If 0, the sniffer + -- can be accessed from either a Secure or Non-secure context, but can + -- not see data transfers of Secure channels. + SNIFF_S : Boolean := True; + -- If 1, the TIMER0 register is only accessible from a Privileged (or + -- more Secure) context, and timer DREQ 0 is only visible to Privileged + -- (or more Secure) channels. + TIMER0_P : Boolean := True; + -- If 1, the TIMER0 register is only accessible from a Secure context, + -- and timer DREQ 0 is only visible to Secure channels. + TIMER0_S : Boolean := True; + -- If 1, the TIMER1 register is only accessible from a Privileged (or + -- more Secure) context, and timer DREQ 1 is only visible to Privileged + -- (or more Secure) channels. + TIMER1_P : Boolean := True; + -- If 1, the TIMER1 register is only accessible from a Secure context, + -- and timer DREQ 1 is only visible to Secure channels. + TIMER1_S : Boolean := True; + -- If 1, the TIMER2 register is only accessible from a Privileged (or + -- more Secure) context, and timer DREQ 2 is only visible to Privileged + -- (or more Secure) channels. + TIMER2_P : Boolean := True; + -- If 1, the TIMER2 register is only accessible from a Secure context, + -- and timer DREQ 2 is only visible to Secure channels. + TIMER2_S : Boolean := True; + -- If 1, the TIMER3 register is only accessible from a Privileged (or + -- more Secure) context, and timer DREQ 3 is only visible to Privileged + -- (or more Secure) channels. + TIMER3_P : Boolean := True; + -- If 1, the TIMER3 register is only accessible from a Secure context, + -- and timer DREQ 3 is only visible to Secure channels. + TIMER3_S : Boolean := True; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SECCFG_MISC_Register use record + SNIFF_P at 0 range 0 .. 0; + SNIFF_S at 0 range 1 .. 1; + TIMER0_P at 0 range 2 .. 2; + TIMER0_S at 0 range 3 .. 3; + TIMER1_P at 0 range 4 .. 4; + TIMER1_S at 0 range 5 .. 5; + TIMER2_P at 0 range 6 .. 6; + TIMER2_S at 0 range 7 .. 7; + TIMER3_P at 0 range 8 .. 8; + TIMER3_S at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- Control register for DMA MPU. Accessible only from a Privileged context. + type MPU_CTRL_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Determine whether an address not covered by an active MPU region is + -- Privileged (1) or Unprivileged (0) + P : Boolean := False; + -- Determine whether an address not covered by an active MPU region is + -- Secure (1) or Non-secure (0) + S : Boolean := False; + -- By default, when a region's S bit is clear, Non-secure-Privileged + -- reads can see the region's base address and limit address. Set this + -- bit to make the addresses appear as 0 to Non-secure reads, even when + -- the region is Non-secure, to avoid leaking information about the + -- processor SAU map. + NS_HIDE_ADDR : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_CTRL_Register use record + Reserved_0_0 at 0 range 0 .. 0; + P at 0 range 1 .. 1; + S at 0 range 2 .. 2; + NS_HIDE_ADDR at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype MPU_BAR_ADDR_Field is HAL.UInt27; + + -- Base address register for MPU region 0. Writable only from a Secure, + -- Privileged context. + type MPU_BAR_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- This MPU region matches addresses where addr[31:5] (the 27 most + -- significant bits) are greater than or equal to BAR_ADDR, and less + -- than or equal to LAR_ADDR. Readable from any Privileged context, if + -- and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR + -- is clear. Otherwise readable only from a Secure, Privileged context. + ADDR : MPU_BAR_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_BAR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + ADDR at 0 range 5 .. 31; + end record; + + subtype MPU_LAR_ADDR_Field is HAL.UInt27; + + -- Limit address register for MPU region 0. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + type MPU_LAR_Register is record + -- Region enable. If 1, any address within range specified by the base + -- address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes + -- specified by S and P. + EN : Boolean := False; + -- Determines the Privileged/Unprivileged (=1/0) status of addresses + -- matching this region, if this region is enabled. Writable from any + -- Privileged context, if and only if the S bit is clear. Otherwise, + -- writable only from a Secure, Privileged context. + P : Boolean := False; + -- Determines the Secure/Non-secure (=1/0) status of addresses matching + -- this region, if this region is enabled. + S : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Limit address bits 31:5. Readable from any Privileged context, if and + -- only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is + -- clear. Otherwise readable only from a Secure, Privileged context. + ADDR : MPU_LAR_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_LAR_Register use record + EN at 0 range 0 .. 0; + P at 0 range 1 .. 1; + S at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + ADDR at 0 range 5 .. 31; + end record; + + subtype CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH0_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH0_DBG_CTDREQ : CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_DBG_CTDREQ_Register use record + CH0_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH1_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH1_DBG_CTDREQ : CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_DBG_CTDREQ_Register use record + CH1_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH2_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH2_DBG_CTDREQ : CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_DBG_CTDREQ_Register use record + CH2_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH3_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH3_DBG_CTDREQ : CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_DBG_CTDREQ_Register use record + CH3_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH4_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH4_DBG_CTDREQ : CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_DBG_CTDREQ_Register use record + CH4_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH5_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH5_DBG_CTDREQ : CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_DBG_CTDREQ_Register use record + CH5_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH6_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH6_DBG_CTDREQ : CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_DBG_CTDREQ_Register use record + CH6_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH7_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH7_DBG_CTDREQ : CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_DBG_CTDREQ_Register use record + CH7_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH8_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH8_DBG_CTDREQ : CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_DBG_CTDREQ_Register use record + CH8_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH9_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH9_DBG_CTDREQ : CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_DBG_CTDREQ_Register use record + CH9_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH10_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH10_DBG_CTDREQ : CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_DBG_CTDREQ_Register use record + CH10_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH11_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH11_DBG_CTDREQ : CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_DBG_CTDREQ_Register use record + CH11_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH12_DBG_CTDREQ_CH12_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH12_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH12_DBG_CTDREQ : CH12_DBG_CTDREQ_CH12_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH12_DBG_CTDREQ_Register use record + CH12_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH13_DBG_CTDREQ_CH13_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH13_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH13_DBG_CTDREQ : CH13_DBG_CTDREQ_CH13_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH13_DBG_CTDREQ_Register use record + CH13_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH14_DBG_CTDREQ_CH14_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH14_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH14_DBG_CTDREQ : CH14_DBG_CTDREQ_CH14_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH14_DBG_CTDREQ_Register use record + CH14_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype CH15_DBG_CTDREQ_CH15_DBG_CTDREQ_Field is HAL.UInt6; + + -- Read: get channel DREQ counter (i.e. how many accesses the DMA expects + -- it can perform on the peripheral without overflow/underflow. Write any + -- value: clears the counter, and cause channel to re-initiate DREQ + -- handshake. + type CH15_DBG_CTDREQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH15_DBG_CTDREQ : CH15_DBG_CTDREQ_CH15_DBG_CTDREQ_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH15_DBG_CTDREQ_Register use record + CH15_DBG_CTDREQ at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- DMA with separate read and write masters + type DMA_Peripheral is record + -- DMA Channel 0 Read Address pointer + CH0_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 0 Write Address pointer + CH0_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 0 Transfer Count + CH0_TRANS_COUNT : aliased CH0_TRANS_COUNT_Register; + -- DMA Channel 0 Control and Status + CH0_CTRL_TRIG : aliased CH0_CTRL_TRIG_Register; + -- Alias for channel 0 CTRL register + CH0_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 0 READ_ADDR register + CH0_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 0 WRITE_ADDR register + CH0_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 0 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH0_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 0 CTRL register + CH0_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 0 TRANS_COUNT register + CH0_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 0 READ_ADDR register + CH0_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 0 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH0_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 0 CTRL register + CH0_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 0 WRITE_ADDR register + CH0_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 0 TRANS_COUNT register + CH0_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 0 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH0_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 1 Read Address pointer + CH1_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 1 Write Address pointer + CH1_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 1 Transfer Count + CH1_TRANS_COUNT : aliased CH1_TRANS_COUNT_Register; + -- DMA Channel 1 Control and Status + CH1_CTRL_TRIG : aliased CH1_CTRL_TRIG_Register; + -- Alias for channel 1 CTRL register + CH1_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 1 READ_ADDR register + CH1_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 1 WRITE_ADDR register + CH1_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 1 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH1_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 1 CTRL register + CH1_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 1 TRANS_COUNT register + CH1_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 1 READ_ADDR register + CH1_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 1 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH1_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 1 CTRL register + CH1_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 1 WRITE_ADDR register + CH1_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 1 TRANS_COUNT register + CH1_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 1 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH1_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 2 Read Address pointer + CH2_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 2 Write Address pointer + CH2_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 2 Transfer Count + CH2_TRANS_COUNT : aliased CH2_TRANS_COUNT_Register; + -- DMA Channel 2 Control and Status + CH2_CTRL_TRIG : aliased CH2_CTRL_TRIG_Register; + -- Alias for channel 2 CTRL register + CH2_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 2 READ_ADDR register + CH2_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 2 WRITE_ADDR register + CH2_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 2 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH2_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 2 CTRL register + CH2_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 2 TRANS_COUNT register + CH2_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 2 READ_ADDR register + CH2_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 2 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH2_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 2 CTRL register + CH2_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 2 WRITE_ADDR register + CH2_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 2 TRANS_COUNT register + CH2_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 2 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH2_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 3 Read Address pointer + CH3_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 3 Write Address pointer + CH3_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 3 Transfer Count + CH3_TRANS_COUNT : aliased CH3_TRANS_COUNT_Register; + -- DMA Channel 3 Control and Status + CH3_CTRL_TRIG : aliased CH3_CTRL_TRIG_Register; + -- Alias for channel 3 CTRL register + CH3_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 3 READ_ADDR register + CH3_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 3 WRITE_ADDR register + CH3_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 3 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH3_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 3 CTRL register + CH3_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 3 TRANS_COUNT register + CH3_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 3 READ_ADDR register + CH3_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 3 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH3_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 3 CTRL register + CH3_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 3 WRITE_ADDR register + CH3_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 3 TRANS_COUNT register + CH3_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 3 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH3_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 4 Read Address pointer + CH4_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 4 Write Address pointer + CH4_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 4 Transfer Count + CH4_TRANS_COUNT : aliased CH4_TRANS_COUNT_Register; + -- DMA Channel 4 Control and Status + CH4_CTRL_TRIG : aliased CH4_CTRL_TRIG_Register; + -- Alias for channel 4 CTRL register + CH4_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 4 READ_ADDR register + CH4_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 4 WRITE_ADDR register + CH4_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 4 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH4_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 4 CTRL register + CH4_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 4 TRANS_COUNT register + CH4_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 4 READ_ADDR register + CH4_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 4 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH4_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 4 CTRL register + CH4_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 4 WRITE_ADDR register + CH4_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 4 TRANS_COUNT register + CH4_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 4 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH4_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 5 Read Address pointer + CH5_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 5 Write Address pointer + CH5_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 5 Transfer Count + CH5_TRANS_COUNT : aliased CH5_TRANS_COUNT_Register; + -- DMA Channel 5 Control and Status + CH5_CTRL_TRIG : aliased CH5_CTRL_TRIG_Register; + -- Alias for channel 5 CTRL register + CH5_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 5 READ_ADDR register + CH5_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 5 WRITE_ADDR register + CH5_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 5 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH5_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 5 CTRL register + CH5_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 5 TRANS_COUNT register + CH5_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 5 READ_ADDR register + CH5_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 5 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH5_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 5 CTRL register + CH5_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 5 WRITE_ADDR register + CH5_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 5 TRANS_COUNT register + CH5_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 5 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH5_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 6 Read Address pointer + CH6_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 6 Write Address pointer + CH6_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 6 Transfer Count + CH6_TRANS_COUNT : aliased CH6_TRANS_COUNT_Register; + -- DMA Channel 6 Control and Status + CH6_CTRL_TRIG : aliased CH6_CTRL_TRIG_Register; + -- Alias for channel 6 CTRL register + CH6_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 6 READ_ADDR register + CH6_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 6 WRITE_ADDR register + CH6_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 6 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH6_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 6 CTRL register + CH6_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 6 TRANS_COUNT register + CH6_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 6 READ_ADDR register + CH6_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 6 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH6_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 6 CTRL register + CH6_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 6 WRITE_ADDR register + CH6_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 6 TRANS_COUNT register + CH6_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 6 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH6_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 7 Read Address pointer + CH7_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 7 Write Address pointer + CH7_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 7 Transfer Count + CH7_TRANS_COUNT : aliased CH7_TRANS_COUNT_Register; + -- DMA Channel 7 Control and Status + CH7_CTRL_TRIG : aliased CH7_CTRL_TRIG_Register; + -- Alias for channel 7 CTRL register + CH7_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 7 READ_ADDR register + CH7_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 7 WRITE_ADDR register + CH7_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 7 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH7_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 7 CTRL register + CH7_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 7 TRANS_COUNT register + CH7_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 7 READ_ADDR register + CH7_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 7 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH7_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 7 CTRL register + CH7_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 7 WRITE_ADDR register + CH7_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 7 TRANS_COUNT register + CH7_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 7 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH7_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 8 Read Address pointer + CH8_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 8 Write Address pointer + CH8_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 8 Transfer Count + CH8_TRANS_COUNT : aliased CH8_TRANS_COUNT_Register; + -- DMA Channel 8 Control and Status + CH8_CTRL_TRIG : aliased CH8_CTRL_TRIG_Register; + -- Alias for channel 8 CTRL register + CH8_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 8 READ_ADDR register + CH8_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 8 WRITE_ADDR register + CH8_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 8 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH8_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 8 CTRL register + CH8_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 8 TRANS_COUNT register + CH8_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 8 READ_ADDR register + CH8_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 8 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH8_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 8 CTRL register + CH8_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 8 WRITE_ADDR register + CH8_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 8 TRANS_COUNT register + CH8_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 8 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH8_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 9 Read Address pointer + CH9_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 9 Write Address pointer + CH9_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 9 Transfer Count + CH9_TRANS_COUNT : aliased CH9_TRANS_COUNT_Register; + -- DMA Channel 9 Control and Status + CH9_CTRL_TRIG : aliased CH9_CTRL_TRIG_Register; + -- Alias for channel 9 CTRL register + CH9_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 9 READ_ADDR register + CH9_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 9 WRITE_ADDR register + CH9_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 9 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH9_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 9 CTRL register + CH9_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 9 TRANS_COUNT register + CH9_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 9 READ_ADDR register + CH9_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 9 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH9_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 9 CTRL register + CH9_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 9 WRITE_ADDR register + CH9_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 9 TRANS_COUNT register + CH9_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 9 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH9_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 10 Read Address pointer + CH10_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 10 Write Address pointer + CH10_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 10 Transfer Count + CH10_TRANS_COUNT : aliased CH10_TRANS_COUNT_Register; + -- DMA Channel 10 Control and Status + CH10_CTRL_TRIG : aliased CH10_CTRL_TRIG_Register; + -- Alias for channel 10 CTRL register + CH10_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 10 READ_ADDR register + CH10_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 10 WRITE_ADDR register + CH10_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 10 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH10_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 10 CTRL register + CH10_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 10 TRANS_COUNT register + CH10_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 10 READ_ADDR register + CH10_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 10 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH10_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 10 CTRL register + CH10_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 10 WRITE_ADDR register + CH10_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 10 TRANS_COUNT register + CH10_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 10 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH10_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 11 Read Address pointer + CH11_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 11 Write Address pointer + CH11_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 11 Transfer Count + CH11_TRANS_COUNT : aliased CH11_TRANS_COUNT_Register; + -- DMA Channel 11 Control and Status + CH11_CTRL_TRIG : aliased CH11_CTRL_TRIG_Register; + -- Alias for channel 11 CTRL register + CH11_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 11 READ_ADDR register + CH11_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 11 WRITE_ADDR register + CH11_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 11 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH11_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 11 CTRL register + CH11_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 11 TRANS_COUNT register + CH11_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 11 READ_ADDR register + CH11_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 11 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH11_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 11 CTRL register + CH11_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 11 WRITE_ADDR register + CH11_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 11 TRANS_COUNT register + CH11_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 11 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH11_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 12 Read Address pointer + CH12_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 12 Write Address pointer + CH12_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 12 Transfer Count + CH12_TRANS_COUNT : aliased CH12_TRANS_COUNT_Register; + -- DMA Channel 12 Control and Status + CH12_CTRL_TRIG : aliased CH12_CTRL_TRIG_Register; + -- Alias for channel 12 CTRL register + CH12_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 12 READ_ADDR register + CH12_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 12 WRITE_ADDR register + CH12_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 12 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH12_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 12 CTRL register + CH12_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 12 TRANS_COUNT register + CH12_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 12 READ_ADDR register + CH12_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 12 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH12_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 12 CTRL register + CH12_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 12 WRITE_ADDR register + CH12_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 12 TRANS_COUNT register + CH12_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 12 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH12_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 13 Read Address pointer + CH13_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 13 Write Address pointer + CH13_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 13 Transfer Count + CH13_TRANS_COUNT : aliased CH13_TRANS_COUNT_Register; + -- DMA Channel 13 Control and Status + CH13_CTRL_TRIG : aliased CH13_CTRL_TRIG_Register; + -- Alias for channel 13 CTRL register + CH13_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 13 READ_ADDR register + CH13_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 13 WRITE_ADDR register + CH13_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 13 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH13_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 13 CTRL register + CH13_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 13 TRANS_COUNT register + CH13_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 13 READ_ADDR register + CH13_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 13 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH13_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 13 CTRL register + CH13_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 13 WRITE_ADDR register + CH13_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 13 TRANS_COUNT register + CH13_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 13 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH13_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 14 Read Address pointer + CH14_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 14 Write Address pointer + CH14_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 14 Transfer Count + CH14_TRANS_COUNT : aliased CH14_TRANS_COUNT_Register; + -- DMA Channel 14 Control and Status + CH14_CTRL_TRIG : aliased CH14_CTRL_TRIG_Register; + -- Alias for channel 14 CTRL register + CH14_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 14 READ_ADDR register + CH14_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 14 WRITE_ADDR register + CH14_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 14 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH14_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 14 CTRL register + CH14_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 14 TRANS_COUNT register + CH14_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 14 READ_ADDR register + CH14_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 14 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH14_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 14 CTRL register + CH14_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 14 WRITE_ADDR register + CH14_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 14 TRANS_COUNT register + CH14_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 14 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH14_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- DMA Channel 15 Read Address pointer + CH15_READ_ADDR : aliased HAL.UInt32; + -- DMA Channel 15 Write Address pointer + CH15_WRITE_ADDR : aliased HAL.UInt32; + -- DMA Channel 15 Transfer Count + CH15_TRANS_COUNT : aliased CH15_TRANS_COUNT_Register; + -- DMA Channel 15 Control and Status + CH15_CTRL_TRIG : aliased CH15_CTRL_TRIG_Register; + -- Alias for channel 15 CTRL register + CH15_AL1_CTRL : aliased HAL.UInt32; + -- Alias for channel 15 READ_ADDR register + CH15_AL1_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 15 WRITE_ADDR register + CH15_AL1_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 15 TRANS_COUNT register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH15_AL1_TRANS_COUNT_TRIG : aliased HAL.UInt32; + -- Alias for channel 15 CTRL register + CH15_AL2_CTRL : aliased HAL.UInt32; + -- Alias for channel 15 TRANS_COUNT register + CH15_AL2_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 15 READ_ADDR register + CH15_AL2_READ_ADDR : aliased HAL.UInt32; + -- Alias for channel 15 WRITE_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH15_AL2_WRITE_ADDR_TRIG : aliased HAL.UInt32; + -- Alias for channel 15 CTRL register + CH15_AL3_CTRL : aliased HAL.UInt32; + -- Alias for channel 15 WRITE_ADDR register + CH15_AL3_WRITE_ADDR : aliased HAL.UInt32; + -- Alias for channel 15 TRANS_COUNT register + CH15_AL3_TRANS_COUNT : aliased HAL.UInt32; + -- Alias for channel 15 READ_ADDR register This is a trigger register + -- (0xc). Writing a nonzero value will reload the channel counter and + -- start the channel. + CH15_AL3_READ_ADDR_TRIG : aliased HAL.UInt32; + -- Interrupt Status (raw) + INTR : aliased INTR_Register; + -- Interrupt Enables for IRQ 0 + INTE0 : aliased INTE0_Register; + -- Force Interrupts + INTF0 : aliased INTF0_Register; + -- Interrupt Status for IRQ 0 + INTS0 : aliased INTS0_Register; + -- Interrupt Status (raw) + INTR1 : aliased INTR1_Register; + -- Interrupt Enables for IRQ 1 + INTE1 : aliased INTE1_Register; + -- Force Interrupts + INTF1 : aliased INTF1_Register; + -- Interrupt Status for IRQ 1 + INTS1 : aliased INTS1_Register; + -- Interrupt Status (raw) + INTR2 : aliased INTR2_Register; + -- Interrupt Enables for IRQ 2 + INTE2 : aliased INTE2_Register; + -- Force Interrupts + INTF2 : aliased INTF2_Register; + -- Interrupt Status for IRQ 2 + INTS2 : aliased INTS2_Register; + -- Interrupt Status (raw) + INTR3 : aliased INTR3_Register; + -- Interrupt Enables for IRQ 3 + INTE3 : aliased INTE3_Register; + -- Force Interrupts + INTF3 : aliased INTF3_Register; + -- Interrupt Status for IRQ 3 + INTS3 : aliased INTS3_Register; + -- Pacing (X/Y) fractional timer The pacing timer produces TREQ + -- assertions at a rate set by ((X/Y) * sys_clk). This equation is + -- evaluated every sys_clk cycles and therefore can only generate TREQs + -- at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + TIMER0 : aliased TIMER_Register; + -- Pacing (X/Y) fractional timer The pacing timer produces TREQ + -- assertions at a rate set by ((X/Y) * sys_clk). This equation is + -- evaluated every sys_clk cycles and therefore can only generate TREQs + -- at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + TIMER1 : aliased TIMER_Register; + -- Pacing (X/Y) fractional timer The pacing timer produces TREQ + -- assertions at a rate set by ((X/Y) * sys_clk). This equation is + -- evaluated every sys_clk cycles and therefore can only generate TREQs + -- at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + TIMER2 : aliased TIMER_Register; + -- Pacing (X/Y) fractional timer The pacing timer produces TREQ + -- assertions at a rate set by ((X/Y) * sys_clk). This equation is + -- evaluated every sys_clk cycles and therefore can only generate TREQs + -- at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + TIMER3 : aliased TIMER_Register; + -- Trigger one or more channels simultaneously + MULTI_CHAN_TRIGGER : aliased MULTI_CHAN_TRIGGER_Register; + -- Sniffer Control + SNIFF_CTRL : aliased SNIFF_CTRL_Register; + -- Data accumulator for sniff hardware + SNIFF_DATA : aliased HAL.UInt32; + -- Debug RAF, WAF, TDF levels + FIFO_LEVELS : aliased FIFO_LEVELS_Register; + -- Abort an in-progress transfer sequence on one or more channels + CHAN_ABORT : aliased CHAN_ABORT_Register; + -- The number of channels this DMA instance is equipped with. This DMA + -- supports up to 16 hardware channels, but can be configured with as + -- few as one, to minimise silicon area. + N_CHANNELS : aliased N_CHANNELS_Register; + -- Security configuration for channel 0. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH0 : aliased SECCFG_CH_Register; + -- Security configuration for channel 1. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH1 : aliased SECCFG_CH_Register; + -- Security configuration for channel 2. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH2 : aliased SECCFG_CH_Register; + -- Security configuration for channel 3. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH3 : aliased SECCFG_CH_Register; + -- Security configuration for channel 4. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH4 : aliased SECCFG_CH_Register; + -- Security configuration for channel 5. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH5 : aliased SECCFG_CH_Register; + -- Security configuration for channel 6. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH6 : aliased SECCFG_CH_Register; + -- Security configuration for channel 7. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH7 : aliased SECCFG_CH_Register; + -- Security configuration for channel 8. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH8 : aliased SECCFG_CH_Register; + -- Security configuration for channel 9. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH9 : aliased SECCFG_CH_Register; + -- Security configuration for channel 10. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH10 : aliased SECCFG_CH_Register; + -- Security configuration for channel 11. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH11 : aliased SECCFG_CH_Register; + -- Security configuration for channel 12. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH12 : aliased SECCFG_CH_Register; + -- Security configuration for channel 13. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH13 : aliased SECCFG_CH_Register; + -- Security configuration for channel 14. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH14 : aliased SECCFG_CH_Register; + -- Security configuration for channel 15. Control whether this channel + -- performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + -- If this channel generates bus accesses of some security level, an + -- access of at least that level (in the order S+P > S+U > NS+P > NS+U) + -- is required to program, trigger, abort, check the status of, + -- interrupt on or acknowledge the interrupt of this channel. This + -- register automatically locks down (becomes read-only) once software + -- starts to configure the channel. This register is world-readable, but + -- is writable only from a Secure, Privileged context. + SECCFG_CH15 : aliased SECCFG_CH_Register; + -- Security configuration for IRQ 0. Control whether the IRQ permits + -- configuration by Non-secure/Unprivileged contexts, and whether it can + -- observe Secure/Privileged channel interrupt flags. + SECCFG_IRQ0 : aliased SECCFG_IRQ_Register; + -- Security configuration for IRQ 1. Control whether the IRQ permits + -- configuration by Non-secure/Unprivileged contexts, and whether it can + -- observe Secure/Privileged channel interrupt flags. + SECCFG_IRQ1 : aliased SECCFG_IRQ_Register; + -- Security configuration for IRQ 2. Control whether the IRQ permits + -- configuration by Non-secure/Unprivileged contexts, and whether it can + -- observe Secure/Privileged channel interrupt flags. + SECCFG_IRQ2 : aliased SECCFG_IRQ_Register; + -- Security configuration for IRQ 3. Control whether the IRQ permits + -- configuration by Non-secure/Unprivileged contexts, and whether it can + -- observe Secure/Privileged channel interrupt flags. + SECCFG_IRQ3 : aliased SECCFG_IRQ_Register; + -- Miscellaneous security configuration + SECCFG_MISC : aliased SECCFG_MISC_Register; + -- Control register for DMA MPU. Accessible only from a Privileged + -- context. + MPU_CTRL : aliased MPU_CTRL_Register; + -- Base address register for MPU region 0. Writable only from a Secure, + -- Privileged context. + MPU_BAR0 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 0. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR0 : aliased MPU_LAR_Register; + -- Base address register for MPU region 1. Writable only from a Secure, + -- Privileged context. + MPU_BAR1 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 1. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR1 : aliased MPU_LAR_Register; + -- Base address register for MPU region 2. Writable only from a Secure, + -- Privileged context. + MPU_BAR2 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 2. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR2 : aliased MPU_LAR_Register; + -- Base address register for MPU region 3. Writable only from a Secure, + -- Privileged context. + MPU_BAR3 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 3. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR3 : aliased MPU_LAR_Register; + -- Base address register for MPU region 4. Writable only from a Secure, + -- Privileged context. + MPU_BAR4 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 4. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR4 : aliased MPU_LAR_Register; + -- Base address register for MPU region 5. Writable only from a Secure, + -- Privileged context. + MPU_BAR5 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 5. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR5 : aliased MPU_LAR_Register; + -- Base address register for MPU region 6. Writable only from a Secure, + -- Privileged context. + MPU_BAR6 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 6. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR6 : aliased MPU_LAR_Register; + -- Base address register for MPU region 7. Writable only from a Secure, + -- Privileged context. + MPU_BAR7 : aliased MPU_BAR_Register; + -- Limit address register for MPU region 7. Writable only from a Secure, + -- Privileged context, with the exception of the P bit. + MPU_LAR7 : aliased MPU_LAR_Register; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH0_DBG_CTDREQ : aliased CH0_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH0_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH1_DBG_CTDREQ : aliased CH1_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH1_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH2_DBG_CTDREQ : aliased CH2_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH2_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH3_DBG_CTDREQ : aliased CH3_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH3_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH4_DBG_CTDREQ : aliased CH4_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH4_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH5_DBG_CTDREQ : aliased CH5_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH5_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH6_DBG_CTDREQ : aliased CH6_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH6_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH7_DBG_CTDREQ : aliased CH7_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH7_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH8_DBG_CTDREQ : aliased CH8_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH8_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH9_DBG_CTDREQ : aliased CH9_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH9_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH10_DBG_CTDREQ : aliased CH10_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH10_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH11_DBG_CTDREQ : aliased CH11_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH11_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH12_DBG_CTDREQ : aliased CH12_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH12_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH13_DBG_CTDREQ : aliased CH13_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH13_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH14_DBG_CTDREQ : aliased CH14_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH14_DBG_TCR : aliased HAL.UInt32; + -- Read: get channel DREQ counter (i.e. how many accesses the DMA + -- expects it can perform on the peripheral without overflow/underflow. + -- Write any value: clears the counter, and cause channel to re-initiate + -- DREQ handshake. + CH15_DBG_CTDREQ : aliased CH15_DBG_CTDREQ_Register; + -- Read to get channel TRANS_COUNT reload value, i.e. the length of the + -- next transfer + CH15_DBG_TCR : aliased HAL.UInt32; + end record + with Volatile; + + for DMA_Peripheral use record + CH0_READ_ADDR at 16#0# range 0 .. 31; + CH0_WRITE_ADDR at 16#4# range 0 .. 31; + CH0_TRANS_COUNT at 16#8# range 0 .. 31; + CH0_CTRL_TRIG at 16#C# range 0 .. 31; + CH0_AL1_CTRL at 16#10# range 0 .. 31; + CH0_AL1_READ_ADDR at 16#14# range 0 .. 31; + CH0_AL1_WRITE_ADDR at 16#18# range 0 .. 31; + CH0_AL1_TRANS_COUNT_TRIG at 16#1C# range 0 .. 31; + CH0_AL2_CTRL at 16#20# range 0 .. 31; + CH0_AL2_TRANS_COUNT at 16#24# range 0 .. 31; + CH0_AL2_READ_ADDR at 16#28# range 0 .. 31; + CH0_AL2_WRITE_ADDR_TRIG at 16#2C# range 0 .. 31; + CH0_AL3_CTRL at 16#30# range 0 .. 31; + CH0_AL3_WRITE_ADDR at 16#34# range 0 .. 31; + CH0_AL3_TRANS_COUNT at 16#38# range 0 .. 31; + CH0_AL3_READ_ADDR_TRIG at 16#3C# range 0 .. 31; + CH1_READ_ADDR at 16#40# range 0 .. 31; + CH1_WRITE_ADDR at 16#44# range 0 .. 31; + CH1_TRANS_COUNT at 16#48# range 0 .. 31; + CH1_CTRL_TRIG at 16#4C# range 0 .. 31; + CH1_AL1_CTRL at 16#50# range 0 .. 31; + CH1_AL1_READ_ADDR at 16#54# range 0 .. 31; + CH1_AL1_WRITE_ADDR at 16#58# range 0 .. 31; + CH1_AL1_TRANS_COUNT_TRIG at 16#5C# range 0 .. 31; + CH1_AL2_CTRL at 16#60# range 0 .. 31; + CH1_AL2_TRANS_COUNT at 16#64# range 0 .. 31; + CH1_AL2_READ_ADDR at 16#68# range 0 .. 31; + CH1_AL2_WRITE_ADDR_TRIG at 16#6C# range 0 .. 31; + CH1_AL3_CTRL at 16#70# range 0 .. 31; + CH1_AL3_WRITE_ADDR at 16#74# range 0 .. 31; + CH1_AL3_TRANS_COUNT at 16#78# range 0 .. 31; + CH1_AL3_READ_ADDR_TRIG at 16#7C# range 0 .. 31; + CH2_READ_ADDR at 16#80# range 0 .. 31; + CH2_WRITE_ADDR at 16#84# range 0 .. 31; + CH2_TRANS_COUNT at 16#88# range 0 .. 31; + CH2_CTRL_TRIG at 16#8C# range 0 .. 31; + CH2_AL1_CTRL at 16#90# range 0 .. 31; + CH2_AL1_READ_ADDR at 16#94# range 0 .. 31; + CH2_AL1_WRITE_ADDR at 16#98# range 0 .. 31; + CH2_AL1_TRANS_COUNT_TRIG at 16#9C# range 0 .. 31; + CH2_AL2_CTRL at 16#A0# range 0 .. 31; + CH2_AL2_TRANS_COUNT at 16#A4# range 0 .. 31; + CH2_AL2_READ_ADDR at 16#A8# range 0 .. 31; + CH2_AL2_WRITE_ADDR_TRIG at 16#AC# range 0 .. 31; + CH2_AL3_CTRL at 16#B0# range 0 .. 31; + CH2_AL3_WRITE_ADDR at 16#B4# range 0 .. 31; + CH2_AL3_TRANS_COUNT at 16#B8# range 0 .. 31; + CH2_AL3_READ_ADDR_TRIG at 16#BC# range 0 .. 31; + CH3_READ_ADDR at 16#C0# range 0 .. 31; + CH3_WRITE_ADDR at 16#C4# range 0 .. 31; + CH3_TRANS_COUNT at 16#C8# range 0 .. 31; + CH3_CTRL_TRIG at 16#CC# range 0 .. 31; + CH3_AL1_CTRL at 16#D0# range 0 .. 31; + CH3_AL1_READ_ADDR at 16#D4# range 0 .. 31; + CH3_AL1_WRITE_ADDR at 16#D8# range 0 .. 31; + CH3_AL1_TRANS_COUNT_TRIG at 16#DC# range 0 .. 31; + CH3_AL2_CTRL at 16#E0# range 0 .. 31; + CH3_AL2_TRANS_COUNT at 16#E4# range 0 .. 31; + CH3_AL2_READ_ADDR at 16#E8# range 0 .. 31; + CH3_AL2_WRITE_ADDR_TRIG at 16#EC# range 0 .. 31; + CH3_AL3_CTRL at 16#F0# range 0 .. 31; + CH3_AL3_WRITE_ADDR at 16#F4# range 0 .. 31; + CH3_AL3_TRANS_COUNT at 16#F8# range 0 .. 31; + CH3_AL3_READ_ADDR_TRIG at 16#FC# range 0 .. 31; + CH4_READ_ADDR at 16#100# range 0 .. 31; + CH4_WRITE_ADDR at 16#104# range 0 .. 31; + CH4_TRANS_COUNT at 16#108# range 0 .. 31; + CH4_CTRL_TRIG at 16#10C# range 0 .. 31; + CH4_AL1_CTRL at 16#110# range 0 .. 31; + CH4_AL1_READ_ADDR at 16#114# range 0 .. 31; + CH4_AL1_WRITE_ADDR at 16#118# range 0 .. 31; + CH4_AL1_TRANS_COUNT_TRIG at 16#11C# range 0 .. 31; + CH4_AL2_CTRL at 16#120# range 0 .. 31; + CH4_AL2_TRANS_COUNT at 16#124# range 0 .. 31; + CH4_AL2_READ_ADDR at 16#128# range 0 .. 31; + CH4_AL2_WRITE_ADDR_TRIG at 16#12C# range 0 .. 31; + CH4_AL3_CTRL at 16#130# range 0 .. 31; + CH4_AL3_WRITE_ADDR at 16#134# range 0 .. 31; + CH4_AL3_TRANS_COUNT at 16#138# range 0 .. 31; + CH4_AL3_READ_ADDR_TRIG at 16#13C# range 0 .. 31; + CH5_READ_ADDR at 16#140# range 0 .. 31; + CH5_WRITE_ADDR at 16#144# range 0 .. 31; + CH5_TRANS_COUNT at 16#148# range 0 .. 31; + CH5_CTRL_TRIG at 16#14C# range 0 .. 31; + CH5_AL1_CTRL at 16#150# range 0 .. 31; + CH5_AL1_READ_ADDR at 16#154# range 0 .. 31; + CH5_AL1_WRITE_ADDR at 16#158# range 0 .. 31; + CH5_AL1_TRANS_COUNT_TRIG at 16#15C# range 0 .. 31; + CH5_AL2_CTRL at 16#160# range 0 .. 31; + CH5_AL2_TRANS_COUNT at 16#164# range 0 .. 31; + CH5_AL2_READ_ADDR at 16#168# range 0 .. 31; + CH5_AL2_WRITE_ADDR_TRIG at 16#16C# range 0 .. 31; + CH5_AL3_CTRL at 16#170# range 0 .. 31; + CH5_AL3_WRITE_ADDR at 16#174# range 0 .. 31; + CH5_AL3_TRANS_COUNT at 16#178# range 0 .. 31; + CH5_AL3_READ_ADDR_TRIG at 16#17C# range 0 .. 31; + CH6_READ_ADDR at 16#180# range 0 .. 31; + CH6_WRITE_ADDR at 16#184# range 0 .. 31; + CH6_TRANS_COUNT at 16#188# range 0 .. 31; + CH6_CTRL_TRIG at 16#18C# range 0 .. 31; + CH6_AL1_CTRL at 16#190# range 0 .. 31; + CH6_AL1_READ_ADDR at 16#194# range 0 .. 31; + CH6_AL1_WRITE_ADDR at 16#198# range 0 .. 31; + CH6_AL1_TRANS_COUNT_TRIG at 16#19C# range 0 .. 31; + CH6_AL2_CTRL at 16#1A0# range 0 .. 31; + CH6_AL2_TRANS_COUNT at 16#1A4# range 0 .. 31; + CH6_AL2_READ_ADDR at 16#1A8# range 0 .. 31; + CH6_AL2_WRITE_ADDR_TRIG at 16#1AC# range 0 .. 31; + CH6_AL3_CTRL at 16#1B0# range 0 .. 31; + CH6_AL3_WRITE_ADDR at 16#1B4# range 0 .. 31; + CH6_AL3_TRANS_COUNT at 16#1B8# range 0 .. 31; + CH6_AL3_READ_ADDR_TRIG at 16#1BC# range 0 .. 31; + CH7_READ_ADDR at 16#1C0# range 0 .. 31; + CH7_WRITE_ADDR at 16#1C4# range 0 .. 31; + CH7_TRANS_COUNT at 16#1C8# range 0 .. 31; + CH7_CTRL_TRIG at 16#1CC# range 0 .. 31; + CH7_AL1_CTRL at 16#1D0# range 0 .. 31; + CH7_AL1_READ_ADDR at 16#1D4# range 0 .. 31; + CH7_AL1_WRITE_ADDR at 16#1D8# range 0 .. 31; + CH7_AL1_TRANS_COUNT_TRIG at 16#1DC# range 0 .. 31; + CH7_AL2_CTRL at 16#1E0# range 0 .. 31; + CH7_AL2_TRANS_COUNT at 16#1E4# range 0 .. 31; + CH7_AL2_READ_ADDR at 16#1E8# range 0 .. 31; + CH7_AL2_WRITE_ADDR_TRIG at 16#1EC# range 0 .. 31; + CH7_AL3_CTRL at 16#1F0# range 0 .. 31; + CH7_AL3_WRITE_ADDR at 16#1F4# range 0 .. 31; + CH7_AL3_TRANS_COUNT at 16#1F8# range 0 .. 31; + CH7_AL3_READ_ADDR_TRIG at 16#1FC# range 0 .. 31; + CH8_READ_ADDR at 16#200# range 0 .. 31; + CH8_WRITE_ADDR at 16#204# range 0 .. 31; + CH8_TRANS_COUNT at 16#208# range 0 .. 31; + CH8_CTRL_TRIG at 16#20C# range 0 .. 31; + CH8_AL1_CTRL at 16#210# range 0 .. 31; + CH8_AL1_READ_ADDR at 16#214# range 0 .. 31; + CH8_AL1_WRITE_ADDR at 16#218# range 0 .. 31; + CH8_AL1_TRANS_COUNT_TRIG at 16#21C# range 0 .. 31; + CH8_AL2_CTRL at 16#220# range 0 .. 31; + CH8_AL2_TRANS_COUNT at 16#224# range 0 .. 31; + CH8_AL2_READ_ADDR at 16#228# range 0 .. 31; + CH8_AL2_WRITE_ADDR_TRIG at 16#22C# range 0 .. 31; + CH8_AL3_CTRL at 16#230# range 0 .. 31; + CH8_AL3_WRITE_ADDR at 16#234# range 0 .. 31; + CH8_AL3_TRANS_COUNT at 16#238# range 0 .. 31; + CH8_AL3_READ_ADDR_TRIG at 16#23C# range 0 .. 31; + CH9_READ_ADDR at 16#240# range 0 .. 31; + CH9_WRITE_ADDR at 16#244# range 0 .. 31; + CH9_TRANS_COUNT at 16#248# range 0 .. 31; + CH9_CTRL_TRIG at 16#24C# range 0 .. 31; + CH9_AL1_CTRL at 16#250# range 0 .. 31; + CH9_AL1_READ_ADDR at 16#254# range 0 .. 31; + CH9_AL1_WRITE_ADDR at 16#258# range 0 .. 31; + CH9_AL1_TRANS_COUNT_TRIG at 16#25C# range 0 .. 31; + CH9_AL2_CTRL at 16#260# range 0 .. 31; + CH9_AL2_TRANS_COUNT at 16#264# range 0 .. 31; + CH9_AL2_READ_ADDR at 16#268# range 0 .. 31; + CH9_AL2_WRITE_ADDR_TRIG at 16#26C# range 0 .. 31; + CH9_AL3_CTRL at 16#270# range 0 .. 31; + CH9_AL3_WRITE_ADDR at 16#274# range 0 .. 31; + CH9_AL3_TRANS_COUNT at 16#278# range 0 .. 31; + CH9_AL3_READ_ADDR_TRIG at 16#27C# range 0 .. 31; + CH10_READ_ADDR at 16#280# range 0 .. 31; + CH10_WRITE_ADDR at 16#284# range 0 .. 31; + CH10_TRANS_COUNT at 16#288# range 0 .. 31; + CH10_CTRL_TRIG at 16#28C# range 0 .. 31; + CH10_AL1_CTRL at 16#290# range 0 .. 31; + CH10_AL1_READ_ADDR at 16#294# range 0 .. 31; + CH10_AL1_WRITE_ADDR at 16#298# range 0 .. 31; + CH10_AL1_TRANS_COUNT_TRIG at 16#29C# range 0 .. 31; + CH10_AL2_CTRL at 16#2A0# range 0 .. 31; + CH10_AL2_TRANS_COUNT at 16#2A4# range 0 .. 31; + CH10_AL2_READ_ADDR at 16#2A8# range 0 .. 31; + CH10_AL2_WRITE_ADDR_TRIG at 16#2AC# range 0 .. 31; + CH10_AL3_CTRL at 16#2B0# range 0 .. 31; + CH10_AL3_WRITE_ADDR at 16#2B4# range 0 .. 31; + CH10_AL3_TRANS_COUNT at 16#2B8# range 0 .. 31; + CH10_AL3_READ_ADDR_TRIG at 16#2BC# range 0 .. 31; + CH11_READ_ADDR at 16#2C0# range 0 .. 31; + CH11_WRITE_ADDR at 16#2C4# range 0 .. 31; + CH11_TRANS_COUNT at 16#2C8# range 0 .. 31; + CH11_CTRL_TRIG at 16#2CC# range 0 .. 31; + CH11_AL1_CTRL at 16#2D0# range 0 .. 31; + CH11_AL1_READ_ADDR at 16#2D4# range 0 .. 31; + CH11_AL1_WRITE_ADDR at 16#2D8# range 0 .. 31; + CH11_AL1_TRANS_COUNT_TRIG at 16#2DC# range 0 .. 31; + CH11_AL2_CTRL at 16#2E0# range 0 .. 31; + CH11_AL2_TRANS_COUNT at 16#2E4# range 0 .. 31; + CH11_AL2_READ_ADDR at 16#2E8# range 0 .. 31; + CH11_AL2_WRITE_ADDR_TRIG at 16#2EC# range 0 .. 31; + CH11_AL3_CTRL at 16#2F0# range 0 .. 31; + CH11_AL3_WRITE_ADDR at 16#2F4# range 0 .. 31; + CH11_AL3_TRANS_COUNT at 16#2F8# range 0 .. 31; + CH11_AL3_READ_ADDR_TRIG at 16#2FC# range 0 .. 31; + CH12_READ_ADDR at 16#300# range 0 .. 31; + CH12_WRITE_ADDR at 16#304# range 0 .. 31; + CH12_TRANS_COUNT at 16#308# range 0 .. 31; + CH12_CTRL_TRIG at 16#30C# range 0 .. 31; + CH12_AL1_CTRL at 16#310# range 0 .. 31; + CH12_AL1_READ_ADDR at 16#314# range 0 .. 31; + CH12_AL1_WRITE_ADDR at 16#318# range 0 .. 31; + CH12_AL1_TRANS_COUNT_TRIG at 16#31C# range 0 .. 31; + CH12_AL2_CTRL at 16#320# range 0 .. 31; + CH12_AL2_TRANS_COUNT at 16#324# range 0 .. 31; + CH12_AL2_READ_ADDR at 16#328# range 0 .. 31; + CH12_AL2_WRITE_ADDR_TRIG at 16#32C# range 0 .. 31; + CH12_AL3_CTRL at 16#330# range 0 .. 31; + CH12_AL3_WRITE_ADDR at 16#334# range 0 .. 31; + CH12_AL3_TRANS_COUNT at 16#338# range 0 .. 31; + CH12_AL3_READ_ADDR_TRIG at 16#33C# range 0 .. 31; + CH13_READ_ADDR at 16#340# range 0 .. 31; + CH13_WRITE_ADDR at 16#344# range 0 .. 31; + CH13_TRANS_COUNT at 16#348# range 0 .. 31; + CH13_CTRL_TRIG at 16#34C# range 0 .. 31; + CH13_AL1_CTRL at 16#350# range 0 .. 31; + CH13_AL1_READ_ADDR at 16#354# range 0 .. 31; + CH13_AL1_WRITE_ADDR at 16#358# range 0 .. 31; + CH13_AL1_TRANS_COUNT_TRIG at 16#35C# range 0 .. 31; + CH13_AL2_CTRL at 16#360# range 0 .. 31; + CH13_AL2_TRANS_COUNT at 16#364# range 0 .. 31; + CH13_AL2_READ_ADDR at 16#368# range 0 .. 31; + CH13_AL2_WRITE_ADDR_TRIG at 16#36C# range 0 .. 31; + CH13_AL3_CTRL at 16#370# range 0 .. 31; + CH13_AL3_WRITE_ADDR at 16#374# range 0 .. 31; + CH13_AL3_TRANS_COUNT at 16#378# range 0 .. 31; + CH13_AL3_READ_ADDR_TRIG at 16#37C# range 0 .. 31; + CH14_READ_ADDR at 16#380# range 0 .. 31; + CH14_WRITE_ADDR at 16#384# range 0 .. 31; + CH14_TRANS_COUNT at 16#388# range 0 .. 31; + CH14_CTRL_TRIG at 16#38C# range 0 .. 31; + CH14_AL1_CTRL at 16#390# range 0 .. 31; + CH14_AL1_READ_ADDR at 16#394# range 0 .. 31; + CH14_AL1_WRITE_ADDR at 16#398# range 0 .. 31; + CH14_AL1_TRANS_COUNT_TRIG at 16#39C# range 0 .. 31; + CH14_AL2_CTRL at 16#3A0# range 0 .. 31; + CH14_AL2_TRANS_COUNT at 16#3A4# range 0 .. 31; + CH14_AL2_READ_ADDR at 16#3A8# range 0 .. 31; + CH14_AL2_WRITE_ADDR_TRIG at 16#3AC# range 0 .. 31; + CH14_AL3_CTRL at 16#3B0# range 0 .. 31; + CH14_AL3_WRITE_ADDR at 16#3B4# range 0 .. 31; + CH14_AL3_TRANS_COUNT at 16#3B8# range 0 .. 31; + CH14_AL3_READ_ADDR_TRIG at 16#3BC# range 0 .. 31; + CH15_READ_ADDR at 16#3C0# range 0 .. 31; + CH15_WRITE_ADDR at 16#3C4# range 0 .. 31; + CH15_TRANS_COUNT at 16#3C8# range 0 .. 31; + CH15_CTRL_TRIG at 16#3CC# range 0 .. 31; + CH15_AL1_CTRL at 16#3D0# range 0 .. 31; + CH15_AL1_READ_ADDR at 16#3D4# range 0 .. 31; + CH15_AL1_WRITE_ADDR at 16#3D8# range 0 .. 31; + CH15_AL1_TRANS_COUNT_TRIG at 16#3DC# range 0 .. 31; + CH15_AL2_CTRL at 16#3E0# range 0 .. 31; + CH15_AL2_TRANS_COUNT at 16#3E4# range 0 .. 31; + CH15_AL2_READ_ADDR at 16#3E8# range 0 .. 31; + CH15_AL2_WRITE_ADDR_TRIG at 16#3EC# range 0 .. 31; + CH15_AL3_CTRL at 16#3F0# range 0 .. 31; + CH15_AL3_WRITE_ADDR at 16#3F4# range 0 .. 31; + CH15_AL3_TRANS_COUNT at 16#3F8# range 0 .. 31; + CH15_AL3_READ_ADDR_TRIG at 16#3FC# range 0 .. 31; + INTR at 16#400# range 0 .. 31; + INTE0 at 16#404# range 0 .. 31; + INTF0 at 16#408# range 0 .. 31; + INTS0 at 16#40C# range 0 .. 31; + INTR1 at 16#410# range 0 .. 31; + INTE1 at 16#414# range 0 .. 31; + INTF1 at 16#418# range 0 .. 31; + INTS1 at 16#41C# range 0 .. 31; + INTR2 at 16#420# range 0 .. 31; + INTE2 at 16#424# range 0 .. 31; + INTF2 at 16#428# range 0 .. 31; + INTS2 at 16#42C# range 0 .. 31; + INTR3 at 16#430# range 0 .. 31; + INTE3 at 16#434# range 0 .. 31; + INTF3 at 16#438# range 0 .. 31; + INTS3 at 16#43C# range 0 .. 31; + TIMER0 at 16#440# range 0 .. 31; + TIMER1 at 16#444# range 0 .. 31; + TIMER2 at 16#448# range 0 .. 31; + TIMER3 at 16#44C# range 0 .. 31; + MULTI_CHAN_TRIGGER at 16#450# range 0 .. 31; + SNIFF_CTRL at 16#454# range 0 .. 31; + SNIFF_DATA at 16#458# range 0 .. 31; + FIFO_LEVELS at 16#460# range 0 .. 31; + CHAN_ABORT at 16#464# range 0 .. 31; + N_CHANNELS at 16#468# range 0 .. 31; + SECCFG_CH0 at 16#480# range 0 .. 31; + SECCFG_CH1 at 16#484# range 0 .. 31; + SECCFG_CH2 at 16#488# range 0 .. 31; + SECCFG_CH3 at 16#48C# range 0 .. 31; + SECCFG_CH4 at 16#490# range 0 .. 31; + SECCFG_CH5 at 16#494# range 0 .. 31; + SECCFG_CH6 at 16#498# range 0 .. 31; + SECCFG_CH7 at 16#49C# range 0 .. 31; + SECCFG_CH8 at 16#4A0# range 0 .. 31; + SECCFG_CH9 at 16#4A4# range 0 .. 31; + SECCFG_CH10 at 16#4A8# range 0 .. 31; + SECCFG_CH11 at 16#4AC# range 0 .. 31; + SECCFG_CH12 at 16#4B0# range 0 .. 31; + SECCFG_CH13 at 16#4B4# range 0 .. 31; + SECCFG_CH14 at 16#4B8# range 0 .. 31; + SECCFG_CH15 at 16#4BC# range 0 .. 31; + SECCFG_IRQ0 at 16#4C0# range 0 .. 31; + SECCFG_IRQ1 at 16#4C4# range 0 .. 31; + SECCFG_IRQ2 at 16#4C8# range 0 .. 31; + SECCFG_IRQ3 at 16#4CC# range 0 .. 31; + SECCFG_MISC at 16#4D0# range 0 .. 31; + MPU_CTRL at 16#500# range 0 .. 31; + MPU_BAR0 at 16#504# range 0 .. 31; + MPU_LAR0 at 16#508# range 0 .. 31; + MPU_BAR1 at 16#50C# range 0 .. 31; + MPU_LAR1 at 16#510# range 0 .. 31; + MPU_BAR2 at 16#514# range 0 .. 31; + MPU_LAR2 at 16#518# range 0 .. 31; + MPU_BAR3 at 16#51C# range 0 .. 31; + MPU_LAR3 at 16#520# range 0 .. 31; + MPU_BAR4 at 16#524# range 0 .. 31; + MPU_LAR4 at 16#528# range 0 .. 31; + MPU_BAR5 at 16#52C# range 0 .. 31; + MPU_LAR5 at 16#530# range 0 .. 31; + MPU_BAR6 at 16#534# range 0 .. 31; + MPU_LAR6 at 16#538# range 0 .. 31; + MPU_BAR7 at 16#53C# range 0 .. 31; + MPU_LAR7 at 16#540# range 0 .. 31; + CH0_DBG_CTDREQ at 16#800# range 0 .. 31; + CH0_DBG_TCR at 16#804# range 0 .. 31; + CH1_DBG_CTDREQ at 16#840# range 0 .. 31; + CH1_DBG_TCR at 16#844# range 0 .. 31; + CH2_DBG_CTDREQ at 16#880# range 0 .. 31; + CH2_DBG_TCR at 16#884# range 0 .. 31; + CH3_DBG_CTDREQ at 16#8C0# range 0 .. 31; + CH3_DBG_TCR at 16#8C4# range 0 .. 31; + CH4_DBG_CTDREQ at 16#900# range 0 .. 31; + CH4_DBG_TCR at 16#904# range 0 .. 31; + CH5_DBG_CTDREQ at 16#940# range 0 .. 31; + CH5_DBG_TCR at 16#944# range 0 .. 31; + CH6_DBG_CTDREQ at 16#980# range 0 .. 31; + CH6_DBG_TCR at 16#984# range 0 .. 31; + CH7_DBG_CTDREQ at 16#9C0# range 0 .. 31; + CH7_DBG_TCR at 16#9C4# range 0 .. 31; + CH8_DBG_CTDREQ at 16#A00# range 0 .. 31; + CH8_DBG_TCR at 16#A04# range 0 .. 31; + CH9_DBG_CTDREQ at 16#A40# range 0 .. 31; + CH9_DBG_TCR at 16#A44# range 0 .. 31; + CH10_DBG_CTDREQ at 16#A80# range 0 .. 31; + CH10_DBG_TCR at 16#A84# range 0 .. 31; + CH11_DBG_CTDREQ at 16#AC0# range 0 .. 31; + CH11_DBG_TCR at 16#AC4# range 0 .. 31; + CH12_DBG_CTDREQ at 16#B00# range 0 .. 31; + CH12_DBG_TCR at 16#B04# range 0 .. 31; + CH13_DBG_CTDREQ at 16#B40# range 0 .. 31; + CH13_DBG_TCR at 16#B44# range 0 .. 31; + CH14_DBG_CTDREQ at 16#B80# range 0 .. 31; + CH14_DBG_TCR at 16#B84# range 0 .. 31; + CH15_DBG_CTDREQ at 16#BC0# range 0 .. 31; + CH15_DBG_TCR at 16#BC4# range 0 .. 31; + end record; + + -- DMA with separate read and write masters + DMA_Periph : aliased DMA_Peripheral + with Import, Address => DMA_Base; + +end RP2350_SVD.DMA; diff --git a/src/svd/rp2350_svd-eppb.ads b/src/svd/rp2350_svd-eppb.ads new file mode 100644 index 0000000..21c29f3 --- /dev/null +++ b/src/svd/rp2350_svd-eppb.ads @@ -0,0 +1,93 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Cortex-M33 EPPB vendor register block for RP2350 +package RP2350_SVD.EPPB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype NMI_MASK1_NMI_MASK1_Field is HAL.UInt20; + + -- NMI mask for IRQs 0 though 51. This register is core-local, and is reset + -- by a processor warm reset. + type NMI_MASK1_Register is record + NMI_MASK1 : NMI_MASK1_NMI_MASK1_Field := 16#0#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NMI_MASK1_Register use record + NMI_MASK1 at 0 range 0 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Nonstandard sleep control register + type SLEEPCTRL_Register is record + -- By default, any processor sleep will deassert the system-level clock + -- request. Reenabling the clocks incurs 5 cycles of additional latency + -- on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted + -- during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. + -- Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and + -- will always deassert the system-level clock request. + LIGHT_SLEEP : Boolean := False; + -- Request that the next processor deep sleep is a WIC sleep. After + -- setting this bit, before sleeping, poll WICENACK to ensure the + -- processor interrupt controller has acknowledged the change. + WICENREQ : Boolean := True; + -- Read-only. Status signal from the processor's interrupt controller. + -- Changes to WICENREQ are eventually reflected in WICENACK. + WICENACK : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SLEEPCTRL_Register use record + LIGHT_SLEEP at 0 range 0 .. 0; + WICENREQ at 0 range 1 .. 1; + WICENACK at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Cortex-M33 EPPB vendor register block for RP2350 + type EPPB_Peripheral is record + -- NMI mask for IRQs 0 through 31. This register is core-local, and is + -- reset by a processor warm reset. + NMI_MASK0 : aliased HAL.UInt32; + -- NMI mask for IRQs 0 though 51. This register is core-local, and is + -- reset by a processor warm reset. + NMI_MASK1 : aliased NMI_MASK1_Register; + -- Nonstandard sleep control register + SLEEPCTRL : aliased SLEEPCTRL_Register; + end record + with Volatile; + + for EPPB_Peripheral use record + NMI_MASK0 at 16#0# range 0 .. 31; + NMI_MASK1 at 16#4# range 0 .. 31; + SLEEPCTRL at 16#8# range 0 .. 31; + end record; + + -- Cortex-M33 EPPB vendor register block for RP2350 + EPPB_Periph : aliased EPPB_Peripheral + with Import, Address => EPPB_Base; + +end RP2350_SVD.EPPB; diff --git a/src/svd/rp2350_svd-glitch_detector.ads b/src/svd/rp2350_svd-glitch_detector.ads new file mode 100644 index 0000000..45fe532 --- /dev/null +++ b/src/svd/rp2350_svd-glitch_detector.ads @@ -0,0 +1,284 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Glitch detector controls +package RP2350_SVD.GLITCH_DETECTOR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type ARM_ARM_Field is + (-- Force the glitch detectors to be armed. (Any value other than ARM_NO counts +-- as YES) + yes, + -- Do not force the glitch detectors to be armed + no) + with Size => 16; + for ARM_ARM_Field use + (yes => 0, + no => 23469); + + -- Forcibly arm the glitch detectors, if they are not already armed by OTP. + -- When armed, any individual detector trigger will cause a restart of the + -- switched core power domain's power-on reset state machine. Glitch + -- detector triggers are recorded accumulatively in TRIG_STATUS. If the + -- system is reset by a glitch detector trigger, this is recorded in + -- POWMAN_CHIP_RESET. This register is Secure read/write only. + type ARM_Register is record + ARM : ARM_ARM_Field := RP2350_SVD.GLITCH_DETECTOR.no; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARM_Register use record + ARM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored + -- if ARM is YES. This register is Secure read/write only. + type DISARM_DISARM_Field is + (-- Do not disarm the glitch detectors. (Any value other than DISARM_YES counts +-- as NO) + no, + -- Disarm the glitch detectors + yes) + with Size => 16; + for DISARM_DISARM_Field use + (no => 0, + yes => 56495); + + type DISARM_Register is record + -- Forcibly disarm the glitch detectors, if they are armed by OTP. + -- Ignored if ARM is YES. This register is Secure read/write only. + DISARM : DISARM_DISARM_Field := RP2350_SVD.GLITCH_DETECTOR.no; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DISARM_Register use record + DISARM at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- SENSITIVITY_DET array element + subtype SENSITIVITY_DET_Element is HAL.UInt2; + + -- SENSITIVITY_DET array + type SENSITIVITY_DET_Field_Array is array (0 .. 3) + of SENSITIVITY_DET_Element + with Component_Size => 2, Size => 8; + + -- Type definition for SENSITIVITY_DET + type SENSITIVITY_DET_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DET as a value + Val : HAL.UInt8; + when True => + -- DET as an array + Arr : SENSITIVITY_DET_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for SENSITIVITY_DET_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + subtype SENSITIVITY_DET0_INV_Field is HAL.UInt2; + subtype SENSITIVITY_DET1_INV_Field is HAL.UInt2; + subtype SENSITIVITY_DET2_INV_Field is HAL.UInt2; + subtype SENSITIVITY_DET3_INV_Field is HAL.UInt2; + + type SENSITIVITY_DEFAULT_Field is + (-- Use the default sensitivity configured in OTP for all detectors. (Any value +-- other than DEFAULT_NO counts as YES) + yes, + -- Do not use the default sensitivity configured in OTP. Instead use the value +-- from this register. + no) + with Size => 8; + for SENSITIVITY_DEFAULT_Field use + (yes => 0, + no => 222); + + -- Adjust the sensitivity of glitch detectors to values other than their + -- OTP-provided defaults. This register is Secure read/write only. + type SENSITIVITY_Register is record + -- Set sensitivity for detector 0. Higher values are more sensitive. + DET : SENSITIVITY_DET_Field := + (As_Array => False, Val => 16#0#); + -- Must be the inverse of DET0, else the default value is used. + DET0_INV : SENSITIVITY_DET0_INV_Field := 16#0#; + -- Must be the inverse of DET1, else the default value is used. + DET1_INV : SENSITIVITY_DET1_INV_Field := 16#0#; + -- Must be the inverse of DET2, else the default value is used. + DET2_INV : SENSITIVITY_DET2_INV_Field := 16#0#; + -- Must be the inverse of DET3, else the default value is used. + DET3_INV : SENSITIVITY_DET3_INV_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + DEFAULT : SENSITIVITY_DEFAULT_Field := + RP2350_SVD.GLITCH_DETECTOR.yes; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SENSITIVITY_Register use record + DET at 0 range 0 .. 7; + DET0_INV at 0 range 8 .. 9; + DET1_INV at 0 range 10 .. 11; + DET2_INV at 0 range 12 .. 13; + DET3_INV at 0 range 14 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + DEFAULT at 0 range 24 .. 31; + end record; + + subtype LOCK_LOCK_Field is HAL.UInt8; + + type LOCK_Register is record + -- Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY + -- and LOCK. This register is Secure read/write only. + LOCK : LOCK_LOCK_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCK_Register use record + LOCK at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- TRIG_STATUS_DET array + type TRIG_STATUS_DET_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for TRIG_STATUS_DET + type TRIG_STATUS_DET_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DET as a value + Val : HAL.UInt4; + when True => + -- DET as an array + Arr : TRIG_STATUS_DET_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for TRIG_STATUS_DET_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Set when a detector output triggers. Write-1-clear. (May immediately + -- return high if the detector remains in a failed state. Detectors can + -- only be cleared by a full reset of the switched core power domain.) This + -- register is Secure read/write only. + type TRIG_STATUS_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + DET : TRIG_STATUS_DET_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRIG_STATUS_Register use record + DET at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRIG_FORCE_TRIG_FORCE_Field is HAL.UInt4; + + -- Simulate the firing of one or more detectors. Writing ones to this + -- register will set the matching bits in STATUS_TRIG. If the glitch + -- detectors are currently armed, writing ones will also immediately reset + -- the switched core power domain, and set the reset reason latches in + -- POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is + -- Secure read/write only. + type TRIG_FORCE_Register is record + -- Write-only. + TRIG_FORCE : TRIG_FORCE_TRIG_FORCE_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRIG_FORCE_Register use record + TRIG_FORCE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Glitch detector controls + type GLITCH_DETECTOR_Peripheral is record + -- Forcibly arm the glitch detectors, if they are not already armed by + -- OTP. When armed, any individual detector trigger will cause a restart + -- of the switched core power domain's power-on reset state machine. + -- Glitch detector triggers are recorded accumulatively in TRIG_STATUS. + -- If the system is reset by a glitch detector trigger, this is recorded + -- in POWMAN_CHIP_RESET. This register is Secure read/write only. + ARM : aliased ARM_Register; + DISARM : aliased DISARM_Register; + -- Adjust the sensitivity of glitch detectors to values other than their + -- OTP-provided defaults. This register is Secure read/write only. + SENSITIVITY : aliased SENSITIVITY_Register; + LOCK : aliased LOCK_Register; + -- Set when a detector output triggers. Write-1-clear. (May immediately + -- return high if the detector remains in a failed state. Detectors can + -- only be cleared by a full reset of the switched core power domain.) + -- This register is Secure read/write only. + TRIG_STATUS : aliased TRIG_STATUS_Register; + -- Simulate the firing of one or more detectors. Writing ones to this + -- register will set the matching bits in STATUS_TRIG. If the glitch + -- detectors are currently armed, writing ones will also immediately + -- reset the switched core power domain, and set the reset reason + -- latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + -- This register is Secure read/write only. + TRIG_FORCE : aliased TRIG_FORCE_Register; + end record + with Volatile; + + for GLITCH_DETECTOR_Peripheral use record + ARM at 16#0# range 0 .. 31; + DISARM at 16#4# range 0 .. 31; + SENSITIVITY at 16#8# range 0 .. 31; + LOCK at 16#C# range 0 .. 31; + TRIG_STATUS at 16#10# range 0 .. 31; + TRIG_FORCE at 16#14# range 0 .. 31; + end record; + + -- Glitch detector controls + GLITCH_DETECTOR_Periph : aliased GLITCH_DETECTOR_Peripheral + with Import, Address => GLITCH_DETECTOR_Base; + +end RP2350_SVD.GLITCH_DETECTOR; diff --git a/src/svd/rp2350_svd-hstx_ctrl.ads b/src/svd/rp2350_svd-hstx_ctrl.ads new file mode 100644 index 0000000..01f41ea --- /dev/null +++ b/src/svd/rp2350_svd-hstx_ctrl.ads @@ -0,0 +1,298 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Control interface to HSTX. For FIFO write access and status, see the +-- HSTX_FIFO register block. +package RP2350_SVD.HSTX_CTRL is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CSR_COUPLED_SEL_Field is HAL.UInt2; + subtype CSR_SHIFT_Field is HAL.UInt5; + subtype CSR_N_SHIFTS_Field is HAL.UInt5; + subtype CSR_CLKPHASE_Field is HAL.UInt4; + subtype CSR_CLKDIV_Field is HAL.UInt4; + + type CSR_Register is record + -- When EN is 1, the HSTX will shift out data as it appears in the FIFO. + -- As long as there is data, the HSTX shift register will shift once per + -- clock cycle, and the frequency of popping from the FIFO is determined + -- by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not + -- popped. The shift counter and clock generator are also reset to their + -- initial state for as long as EN is low. Note the initial phase of the + -- clock generator can be configured by the CLKPHASE field. Once the + -- HSTX is enabled again, and data is pushed to the FIFO, the generated + -- clock's first rising edge will be one half-period after the first + -- data is launched. + EN : Boolean := False; + -- Enable the command expander. When 0, raw FIFO data is passed directly + -- to the output shift register. When 1, the command expander can + -- perform simple operations such as run length decoding on data between + -- the FIFO and the shift register. Do not change CXPD_EN whilst EN is + -- set. It's safe to set CXPD_EN simultaneously with setting EN. + EXPAND_EN : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked + -- *directly* from the system clock (not just from some other clock + -- source of the same frequency) for this synchronous interface to + -- function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N + -- indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX + -- path, rather than shifter bits. Indices of 0 through 23 will still + -- index the shift register as normal. The PIO outputs connected to the + -- PIO-to-HSTX bus are those same outputs that would appear on the + -- HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of + -- HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO + -- outputs 12 through 19 are connected to the HSTX when coupled mode is + -- engaged. + COUPLED_MODE : Boolean := False; + -- Select which PIO to use for coupled mode operation. + COUPLED_SEL : CSR_COUPLED_SEL_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- How many bits to right-rotate the shift register by each cycle. The + -- use of a rotate rather than a shift allows left shifts to be + -- emulated, by subtracting the left-shift amount from 32. It also + -- allows data to be repeated, when the product of SHIFT and N_SHIFTS is + -- greater than 32. + SHIFT : CSR_SHIFT_Field := 16#6#; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Number of times to shift the shift register before refilling it from + -- the FIFO. (A count of how many times it has been shifted, *not* the + -- total shift distance.) A register value of 0 means shift 32 times. + N_SHIFTS : CSR_N_SHIFTS_Field := 16#5#; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Set the initial phase of the generated clock. A CLKPHASE of 0 means + -- the clock is initially low, and the first rising edge occurs after + -- one half period of the generated clock (i.e. CLKDIV/2 cycles of + -- clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock + -- phase by one half clk_hstx period. For example, if CLKDIV=2 and + -- CLKPHASE=1: * The clock will be initially low * The first rising edge + -- will be 0.5 clk_hstx cycles after asserting first data * The first + -- falling edge will be 1.5 clk_hstx cycles after asserting first data + -- This configuration would be suitable for serialising at a bit rate of + -- clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by + -- clearing CSR_EN, the clock generator will return to its initial phase + -- as configured by the CLKPHASE field. Note CLKPHASE must be strictly + -- less than double the value of CLKDIV (one full period), else its + -- operation is undefined. + CLKPHASE : CSR_CLKPHASE_Field := 16#0#; + -- Clock period of the generated clock, measured in HSTX clock cycles. + -- Can be odd or even. The generated clock advances only on cycles where + -- the shift register shifts. For example, a clkdiv of 5 would generate + -- a complete output clock period for every 5 HSTX clocks (or every 10 + -- half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX + -- clock cycles. + CLKDIV : CSR_CLKDIV_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSR_Register use record + EN at 0 range 0 .. 0; + EXPAND_EN at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + COUPLED_MODE at 0 range 4 .. 4; + COUPLED_SEL at 0 range 5 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SHIFT at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + N_SHIFTS at 0 range 16 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + CLKPHASE at 0 range 24 .. 27; + CLKDIV at 0 range 28 .. 31; + end record; + + subtype BIT_SEL_P_Field is HAL.UInt5; + subtype BIT_SEL_N_Field is HAL.UInt5; + + -- Data control register for output bit 0 + type BIT_Register is record + -- Shift register data bit select for the first half of the HSTX clock + -- cycle + SEL_P : BIT_SEL_P_Field := 16#0#; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Shift register data bit select for the second half of the HSTX clock + -- cycle + SEL_N : BIT_SEL_N_Field := 16#0#; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Invert this data output (logical NOT) + INV : Boolean := False; + -- Connect this output to the generated clock, rather than the data + -- shift register. SEL_P and SEL_N are ignored if this bit is set, but + -- INV can still be set to generate an antiphase clock. + CLK : Boolean := False; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BIT_Register use record + SEL_P at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + SEL_N at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + INV at 0 range 16 .. 16; + CLK at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype EXPAND_SHIFT_RAW_SHIFT_Field is HAL.UInt5; + subtype EXPAND_SHIFT_RAW_N_SHIFTS_Field is HAL.UInt5; + subtype EXPAND_SHIFT_ENC_SHIFT_Field is HAL.UInt5; + subtype EXPAND_SHIFT_ENC_N_SHIFTS_Field is HAL.UInt5; + + -- Configure the optional shifter inside the command expander + type EXPAND_SHIFT_Register is record + -- How many bits to right-rotate the shift register by each time data is + -- pushed to the output shifter, when the current command is a raw data + -- command. + RAW_SHIFT : EXPAND_SHIFT_RAW_SHIFT_Field := 16#0#; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Number of times to consume from the shift register before refilling + -- it from the FIFO, when the current command is a raw data command. A + -- register value of 0 means shift 32 times. + RAW_N_SHIFTS : EXPAND_SHIFT_RAW_N_SHIFTS_Field := 16#1#; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- How many bits to right-rotate the shift register by each time data is + -- pushed to the output shifter, when the current command is an encoded + -- data command (e.g. TMDS). + ENC_SHIFT : EXPAND_SHIFT_ENC_SHIFT_Field := 16#0#; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Number of times to consume from the shift register before refilling + -- it from the FIFO, when the current command is an encoded data command + -- (e.g. TMDS). A register value of 0 means shift 32 times. + ENC_N_SHIFTS : EXPAND_SHIFT_ENC_N_SHIFTS_Field := 16#1#; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXPAND_SHIFT_Register use record + RAW_SHIFT at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + RAW_N_SHIFTS at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + ENC_SHIFT at 0 range 16 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + ENC_N_SHIFTS at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype EXPAND_TMDS_L0_ROT_Field is HAL.UInt5; + subtype EXPAND_TMDS_L0_NBITS_Field is HAL.UInt3; + subtype EXPAND_TMDS_L1_ROT_Field is HAL.UInt5; + subtype EXPAND_TMDS_L1_NBITS_Field is HAL.UInt3; + subtype EXPAND_TMDS_L2_ROT_Field is HAL.UInt5; + subtype EXPAND_TMDS_L2_NBITS_Field is HAL.UInt3; + + -- Configure the optional TMDS encoder inside the command expander + type EXPAND_TMDS_Register is record + -- Right-rotate applied to the current shifter data before the lane 0 + -- TMDS encoder. + L0_ROT : EXPAND_TMDS_L0_ROT_Field := 16#0#; + -- Number of valid data bits for the lane 0 TMDS encoder, starting from + -- bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 + -- -> 8 bits. + L0_NBITS : EXPAND_TMDS_L0_NBITS_Field := 16#0#; + -- Right-rotate applied to the current shifter data before the lane 1 + -- TMDS encoder. + L1_ROT : EXPAND_TMDS_L1_ROT_Field := 16#0#; + -- Number of valid data bits for the lane 1 TMDS encoder, starting from + -- bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 + -- -> 8 bits. + L1_NBITS : EXPAND_TMDS_L1_NBITS_Field := 16#0#; + -- Right-rotate applied to the current shifter data before the lane 2 + -- TMDS encoder. + L2_ROT : EXPAND_TMDS_L2_ROT_Field := 16#0#; + -- Number of valid data bits for the lane 2 TMDS encoder, starting from + -- bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 + -- -> 8 bits. + L2_NBITS : EXPAND_TMDS_L2_NBITS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXPAND_TMDS_Register use record + L0_ROT at 0 range 0 .. 4; + L0_NBITS at 0 range 5 .. 7; + L1_ROT at 0 range 8 .. 12; + L1_NBITS at 0 range 13 .. 15; + L2_ROT at 0 range 16 .. 20; + L2_NBITS at 0 range 21 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Control interface to HSTX. For FIFO write access and status, see the + -- HSTX_FIFO register block. + type HSTX_CTRL_Peripheral is record + CSR : aliased CSR_Register; + -- Data control register for output bit 0 + BIT0 : aliased BIT_Register; + -- Data control register for output bit 1 + BIT1 : aliased BIT_Register; + -- Data control register for output bit 2 + BIT2 : aliased BIT_Register; + -- Data control register for output bit 3 + BIT3 : aliased BIT_Register; + -- Data control register for output bit 4 + BIT4 : aliased BIT_Register; + -- Data control register for output bit 5 + BIT5 : aliased BIT_Register; + -- Data control register for output bit 6 + BIT6 : aliased BIT_Register; + -- Data control register for output bit 7 + BIT7 : aliased BIT_Register; + -- Configure the optional shifter inside the command expander + EXPAND_SHIFT : aliased EXPAND_SHIFT_Register; + -- Configure the optional TMDS encoder inside the command expander + EXPAND_TMDS : aliased EXPAND_TMDS_Register; + end record + with Volatile; + + for HSTX_CTRL_Peripheral use record + CSR at 16#0# range 0 .. 31; + BIT0 at 16#4# range 0 .. 31; + BIT1 at 16#8# range 0 .. 31; + BIT2 at 16#C# range 0 .. 31; + BIT3 at 16#10# range 0 .. 31; + BIT4 at 16#14# range 0 .. 31; + BIT5 at 16#18# range 0 .. 31; + BIT6 at 16#1C# range 0 .. 31; + BIT7 at 16#20# range 0 .. 31; + EXPAND_SHIFT at 16#24# range 0 .. 31; + EXPAND_TMDS at 16#28# range 0 .. 31; + end record; + + -- Control interface to HSTX. For FIFO write access and status, see the + -- HSTX_FIFO register block. + HSTX_CTRL_Periph : aliased HSTX_CTRL_Peripheral + with Import, Address => HSTX_CTRL_Base; + +end RP2350_SVD.HSTX_CTRL; diff --git a/src/svd/rp2350_svd-hstx_fifo.ads b/src/svd/rp2350_svd-hstx_fifo.ads new file mode 100644 index 0000000..89f63b3 --- /dev/null +++ b/src/svd/rp2350_svd-hstx_fifo.ads @@ -0,0 +1,69 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- FIFO status and write access for HSTX +package RP2350_SVD.HSTX_FIFO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype STAT_LEVEL_Field is HAL.UInt8; + + -- FIFO status + type STAT_Register is record + -- Read-only. + LEVEL : STAT_LEVEL_Field := 16#0#; + -- Read-only. + FULL : Boolean := False; + -- Read-only. + EMPTY : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. FIFO was written when full. Write 1 to clear. + WOF : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STAT_Register use record + LEVEL at 0 range 0 .. 7; + FULL at 0 range 8 .. 8; + EMPTY at 0 range 9 .. 9; + WOF at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- FIFO status and write access for HSTX + type HSTX_FIFO_Peripheral is record + -- FIFO status + STAT : aliased STAT_Register; + -- Write access to FIFO + FIFO : aliased HAL.UInt32; + end record + with Volatile; + + for HSTX_FIFO_Peripheral use record + STAT at 16#0# range 0 .. 31; + FIFO at 16#4# range 0 .. 31; + end record; + + -- FIFO status and write access for HSTX + HSTX_FIFO_Periph : aliased HSTX_FIFO_Peripheral + with Import, Address => HSTX_FIFO_Base; + +end RP2350_SVD.HSTX_FIFO; diff --git a/src/svd/rp2350_svd-interrupts.ads b/src/svd/rp2350_svd-interrupts.ads new file mode 100644 index 0000000..8300bc0 --- /dev/null +++ b/src/svd/rp2350_svd-interrupts.ads @@ -0,0 +1,61 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +-- Definition of the device's interrupts +package RP2350_SVD.Interrupts + with Preelaborate +is + + ---------------- + -- Interrupts -- + ---------------- + + TIMER0_IRQ_0_Interrupt : constant := 0; + TIMER0_IRQ_1_Interrupt : constant := 1; + TIMER0_IRQ_2_Interrupt : constant := 2; + TIMER0_IRQ_3_Interrupt : constant := 3; + TIMER1_IRQ_0_Interrupt : constant := 4; + TIMER1_IRQ_1_Interrupt : constant := 5; + TIMER1_IRQ_2_Interrupt : constant := 6; + TIMER1_IRQ_3_Interrupt : constant := 7; + PWM_IRQ_WRAP_0_Interrupt : constant := 8; + PWM_IRQ_WRAP_1_Interrupt : constant := 9; + DMA_IRQ_0_Interrupt : constant := 10; + DMA_IRQ_1_Interrupt : constant := 11; + DMA_IRQ_2_Interrupt : constant := 12; + DMA_IRQ_3_Interrupt : constant := 13; + USBCTRL_Interrupt : constant := 14; + PIO0_IRQ_0_Interrupt : constant := 15; + PIO0_IRQ_1_Interrupt : constant := 16; + PIO1_IRQ_0_Interrupt : constant := 17; + PIO1_IRQ_1_Interrupt : constant := 18; + PIO2_IRQ_0_Interrupt : constant := 19; + PIO2_IRQ_1_Interrupt : constant := 20; + IO_IRQ_BANK0_Interrupt : constant := 21; + IO_IRQ_BANK0_NS_Interrupt : constant := 22; + IO_IRQ_QSPI_Interrupt : constant := 23; + IO_IRQ_QSPI_NS_Interrupt : constant := 24; + SIO_IRQ_FIFO_Interrupt : constant := 25; + SIO_IRQ_BELL_Interrupt : constant := 26; + SIO_IRQ_FIFO_NS_Interrupt : constant := 27; + SIO_IRQ_BELL_NS_Interrupt : constant := 28; + SIO_IRQ_MTIMECMP_Interrupt : constant := 29; + CLOCKS_Interrupt : constant := 30; + SPI0_Interrupt : constant := 31; + SPI1_Interrupt : constant := 32; + UART0_Interrupt : constant := 33; + UART1_Interrupt : constant := 34; + ADC_IRQ_FIFO_Interrupt : constant := 35; + I2C0_Interrupt : constant := 36; + I2C1_Interrupt : constant := 37; + OTP_Interrupt : constant := 38; + TRNG_Interrupt : constant := 39; + PLL_SYS_Interrupt : constant := 42; + PLL_USB_Interrupt : constant := 43; + POWMAN_IRQ_POW_Interrupt : constant := 44; + POWMAN_IRQ_TIMER_Interrupt : constant := 45; + +end RP2350_SVD.Interrupts; diff --git a/src/svd/rp2350_svd-io_bank0.ads b/src/svd/rp2350_svd-io_bank0.ads new file mode 100644 index 0000000..5c8fcf4 --- /dev/null +++ b/src/svd/rp2350_svd-io_bank0.ads @@ -0,0 +1,13625 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.IO_BANK0 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type GPIO0_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO0_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO0_CTRL_FUNCSEL_Field is + (jtag_tck, + spi0_rx, + uart0_tx, + i2c0_sda, + pwm_a_0, + siob_proc_0, + pio0_0, + pio1_0, + pio2_0, + xip_ss_n_1, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO0_CTRL_FUNCSEL_Field use + (jtag_tck => 0, + spi0_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_0 => 4, + siob_proc_0 => 5, + pio0_0 => 6, + pio1_0 => 7, + pio2_0 => 8, + xip_ss_n_1 => 9, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO0_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO0_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO0_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO0_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO0_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO0_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO0_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO0_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO0_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO0_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO0_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO0_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO0_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO0_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO0_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO1_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO1_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO1_CTRL_FUNCSEL_Field is + (jtag_tms, + spi0_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_0, + siob_proc_1, + pio0_1, + pio1_1, + pio2_1, + coresight_traceclk, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO1_CTRL_FUNCSEL_Field use + (jtag_tms => 0, + spi0_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_0 => 4, + siob_proc_1 => 5, + pio0_1 => 6, + pio1_1 => 7, + pio2_1 => 8, + coresight_traceclk => 9, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO1_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO1_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO1_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO1_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO1_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO1_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO1_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO1_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO1_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO1_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO1_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO1_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO1_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO1_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO1_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO2_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO2_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO2_CTRL_FUNCSEL_Field is + (jtag_tdi, + spi0_sclk, + uart0_cts, + i2c1_sda, + pwm_a_1, + siob_proc_2, + pio0_2, + pio1_2, + pio2_2, + coresight_tracedata_0, + usb_muxing_vbus_en, + uart0_tx, + null_k) + with Size => 5; + for GPIO2_CTRL_FUNCSEL_Field use + (jtag_tdi => 0, + spi0_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_1 => 4, + siob_proc_2 => 5, + pio0_2 => 6, + pio1_2 => 7, + pio2_2 => 8, + coresight_tracedata_0 => 9, + usb_muxing_vbus_en => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO2_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO2_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO2_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO2_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO2_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO2_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO2_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO2_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO2_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO2_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO2_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO2_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO2_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO2_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO2_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO3_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO3_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO3_CTRL_FUNCSEL_Field is + (jtag_tdo, + spi0_tx, + uart0_rts, + i2c1_scl, + pwm_b_1, + siob_proc_3, + pio0_3, + pio1_3, + pio2_3, + coresight_tracedata_1, + usb_muxing_overcurr_detect, + uart0_rx, + null_k) + with Size => 5; + for GPIO3_CTRL_FUNCSEL_Field use + (jtag_tdo => 0, + spi0_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_1 => 4, + siob_proc_3 => 5, + pio0_3 => 6, + pio1_3 => 7, + pio2_3 => 8, + coresight_tracedata_1 => 9, + usb_muxing_overcurr_detect => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO3_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO3_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO3_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO3_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO3_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO3_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO3_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO3_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO3_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO3_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO3_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO3_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO3_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO3_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO3_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO4_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO4_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO4_CTRL_FUNCSEL_Field is + (spi0_rx, + uart1_tx, + i2c0_sda, + pwm_a_2, + siob_proc_4, + pio0_4, + pio1_4, + pio2_4, + coresight_tracedata_2, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO4_CTRL_FUNCSEL_Field use + (spi0_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_2 => 4, + siob_proc_4 => 5, + pio0_4 => 6, + pio1_4 => 7, + pio2_4 => 8, + coresight_tracedata_2 => 9, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO4_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO4_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO4_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO4_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO4_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO4_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO4_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO4_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO4_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO4_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO4_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO4_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO4_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO4_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO4_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO5_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO5_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO5_CTRL_FUNCSEL_Field is + (spi0_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_2, + siob_proc_5, + pio0_5, + pio1_5, + pio2_5, + coresight_tracedata_3, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO5_CTRL_FUNCSEL_Field use + (spi0_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_2 => 4, + siob_proc_5 => 5, + pio0_5 => 6, + pio1_5 => 7, + pio2_5 => 8, + coresight_tracedata_3 => 9, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO5_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO5_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO5_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO5_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO5_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO5_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO5_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO5_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO5_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO5_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO5_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO5_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO5_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO5_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO5_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO6_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO6_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO6_CTRL_FUNCSEL_Field is + (spi0_sclk, + uart1_cts, + i2c1_sda, + pwm_a_3, + siob_proc_6, + pio0_6, + pio1_6, + pio2_6, + usb_muxing_overcurr_detect, + uart1_tx, + null_k) + with Size => 5; + for GPIO6_CTRL_FUNCSEL_Field use + (spi0_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_3 => 4, + siob_proc_6 => 5, + pio0_6 => 6, + pio1_6 => 7, + pio2_6 => 8, + usb_muxing_overcurr_detect => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO6_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO6_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO6_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO6_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO6_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO6_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO6_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO6_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO6_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO6_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO6_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO6_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO6_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO6_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO6_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO7_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO7_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO7_CTRL_FUNCSEL_Field is + (spi0_tx, + uart1_rts, + i2c1_scl, + pwm_b_3, + siob_proc_7, + pio0_7, + pio1_7, + pio2_7, + usb_muxing_vbus_detect, + uart1_rx, + null_k) + with Size => 5; + for GPIO7_CTRL_FUNCSEL_Field use + (spi0_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_3 => 4, + siob_proc_7 => 5, + pio0_7 => 6, + pio1_7 => 7, + pio2_7 => 8, + usb_muxing_vbus_detect => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO7_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO7_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO7_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO7_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO7_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO7_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO7_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO7_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO7_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO7_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO7_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO7_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO7_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO7_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO7_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO8_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO8_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO8_CTRL_FUNCSEL_Field is + (spi1_rx, + uart1_tx, + i2c0_sda, + pwm_a_4, + siob_proc_8, + pio0_8, + pio1_8, + pio2_8, + xip_ss_n_1, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO8_CTRL_FUNCSEL_Field use + (spi1_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_4 => 4, + siob_proc_8 => 5, + pio0_8 => 6, + pio1_8 => 7, + pio2_8 => 8, + xip_ss_n_1 => 9, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO8_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO8_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO8_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO8_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO8_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO8_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO8_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO8_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO8_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO8_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO8_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO8_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO8_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO8_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO8_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO9_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO9_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO9_CTRL_FUNCSEL_Field is + (spi1_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_4, + siob_proc_9, + pio0_9, + pio1_9, + pio2_9, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO9_CTRL_FUNCSEL_Field use + (spi1_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_4 => 4, + siob_proc_9 => 5, + pio0_9 => 6, + pio1_9 => 7, + pio2_9 => 8, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO9_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO9_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO9_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO9_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO9_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO9_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO9_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO9_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO9_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO9_CTRL_FUNCSEL_Field := RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO9_CTRL_OUTOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO9_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO9_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO9_CTRL_IRQOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO9_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO10_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO10_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO10_CTRL_FUNCSEL_Field is + (spi1_sclk, + uart1_cts, + i2c1_sda, + pwm_a_5, + siob_proc_10, + pio0_10, + pio1_10, + pio2_10, + usb_muxing_vbus_detect, + uart1_tx, + null_k) + with Size => 5; + for GPIO10_CTRL_FUNCSEL_Field use + (spi1_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_5 => 4, + siob_proc_10 => 5, + pio0_10 => 6, + pio1_10 => 7, + pio2_10 => 8, + usb_muxing_vbus_detect => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO10_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO10_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO10_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO10_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO10_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO10_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO10_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO10_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO10_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO10_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO10_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO10_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO10_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO10_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO10_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO11_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO11_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO11_CTRL_FUNCSEL_Field is + (spi1_tx, + uart1_rts, + i2c1_scl, + pwm_b_5, + siob_proc_11, + pio0_11, + pio1_11, + pio2_11, + usb_muxing_vbus_en, + uart1_rx, + null_k) + with Size => 5; + for GPIO11_CTRL_FUNCSEL_Field use + (spi1_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_5 => 4, + siob_proc_11 => 5, + pio0_11 => 6, + pio1_11 => 7, + pio2_11 => 8, + usb_muxing_vbus_en => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO11_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO11_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO11_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO11_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO11_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO11_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO11_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO11_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO11_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO11_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO11_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO11_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO11_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO11_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO11_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO12_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO12_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO12_CTRL_FUNCSEL_Field is + (hstx_0, + spi1_rx, + uart0_tx, + i2c0_sda, + pwm_a_6, + siob_proc_12, + pio0_12, + pio1_12, + pio2_12, + clocks_gpin_0, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO12_CTRL_FUNCSEL_Field use + (hstx_0 => 0, + spi1_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_6 => 4, + siob_proc_12 => 5, + pio0_12 => 6, + pio1_12 => 7, + pio2_12 => 8, + clocks_gpin_0 => 9, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO12_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO12_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO12_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO12_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO12_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO12_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO12_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO12_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO12_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO12_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO12_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO12_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO12_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO12_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO12_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO13_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO13_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO13_CTRL_FUNCSEL_Field is + (hstx_1, + spi1_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_6, + siob_proc_13, + pio0_13, + pio1_13, + pio2_13, + clocks_gpout_0, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO13_CTRL_FUNCSEL_Field use + (hstx_1 => 0, + spi1_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_6 => 4, + siob_proc_13 => 5, + pio0_13 => 6, + pio1_13 => 7, + pio2_13 => 8, + clocks_gpout_0 => 9, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO13_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO13_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO13_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO13_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO13_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO13_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO13_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO13_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO13_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO13_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO13_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO13_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO13_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO13_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO13_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO14_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO14_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO14_CTRL_FUNCSEL_Field is + (hstx_2, + spi1_sclk, + uart0_cts, + i2c1_sda, + pwm_a_7, + siob_proc_14, + pio0_14, + pio1_14, + pio2_14, + clocks_gpin_1, + usb_muxing_vbus_en, + uart0_tx, + null_k) + with Size => 5; + for GPIO14_CTRL_FUNCSEL_Field use + (hstx_2 => 0, + spi1_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_7 => 4, + siob_proc_14 => 5, + pio0_14 => 6, + pio1_14 => 7, + pio2_14 => 8, + clocks_gpin_1 => 9, + usb_muxing_vbus_en => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO14_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO14_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO14_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO14_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO14_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO14_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO14_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO14_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO14_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO14_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO14_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO14_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO14_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO14_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO14_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO15_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO15_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO15_CTRL_FUNCSEL_Field is + (hstx_3, + spi1_tx, + uart0_rts, + i2c1_scl, + pwm_b_7, + siob_proc_15, + pio0_15, + pio1_15, + pio2_15, + clocks_gpout_1, + usb_muxing_overcurr_detect, + uart0_rx, + null_k) + with Size => 5; + for GPIO15_CTRL_FUNCSEL_Field use + (hstx_3 => 0, + spi1_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_7 => 4, + siob_proc_15 => 5, + pio0_15 => 6, + pio1_15 => 7, + pio2_15 => 8, + clocks_gpout_1 => 9, + usb_muxing_overcurr_detect => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO15_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO15_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO15_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO15_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO15_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO15_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO15_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO15_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO15_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO15_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO15_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO15_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO15_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO15_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO15_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO16_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO16_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO16_CTRL_FUNCSEL_Field is + (hstx_4, + spi0_rx, + uart0_tx, + i2c0_sda, + pwm_a_0, + siob_proc_16, + pio0_16, + pio1_16, + pio2_16, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO16_CTRL_FUNCSEL_Field use + (hstx_4 => 0, + spi0_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_0 => 4, + siob_proc_16 => 5, + pio0_16 => 6, + pio1_16 => 7, + pio2_16 => 8, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO16_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO16_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO16_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO16_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO16_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO16_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO16_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO16_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO16_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO16_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO16_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO16_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO16_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO16_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO16_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO17_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO17_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO17_CTRL_FUNCSEL_Field is + (hstx_5, + spi0_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_0, + siob_proc_17, + pio0_17, + pio1_17, + pio2_17, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO17_CTRL_FUNCSEL_Field use + (hstx_5 => 0, + spi0_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_0 => 4, + siob_proc_17 => 5, + pio0_17 => 6, + pio1_17 => 7, + pio2_17 => 8, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO17_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO17_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO17_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO17_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO17_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO17_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO17_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO17_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO17_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO17_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO17_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO17_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO17_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO17_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO17_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO18_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO18_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO18_CTRL_FUNCSEL_Field is + (hstx_6, + spi0_sclk, + uart0_cts, + i2c1_sda, + pwm_a_1, + siob_proc_18, + pio0_18, + pio1_18, + pio2_18, + usb_muxing_overcurr_detect, + uart0_tx, + null_k) + with Size => 5; + for GPIO18_CTRL_FUNCSEL_Field use + (hstx_6 => 0, + spi0_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_1 => 4, + siob_proc_18 => 5, + pio0_18 => 6, + pio1_18 => 7, + pio2_18 => 8, + usb_muxing_overcurr_detect => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO18_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO18_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO18_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO18_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO18_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO18_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO18_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO18_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO18_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO18_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO18_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO18_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO18_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO18_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO18_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO19_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO19_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO19_CTRL_FUNCSEL_Field is + (hstx_7, + spi0_tx, + uart0_rts, + i2c1_scl, + pwm_b_1, + siob_proc_19, + pio0_19, + pio1_19, + pio2_19, + xip_ss_n_1, + usb_muxing_vbus_detect, + uart0_rx, + null_k) + with Size => 5; + for GPIO19_CTRL_FUNCSEL_Field use + (hstx_7 => 0, + spi0_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_1 => 4, + siob_proc_19 => 5, + pio0_19 => 6, + pio1_19 => 7, + pio2_19 => 8, + xip_ss_n_1 => 9, + usb_muxing_vbus_detect => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO19_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO19_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO19_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO19_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO19_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO19_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO19_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO19_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO19_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO19_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO19_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO19_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO19_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO19_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO19_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO20_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO20_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO20_CTRL_FUNCSEL_Field is + (spi0_rx, + uart1_tx, + i2c0_sda, + pwm_a_2, + siob_proc_20, + pio0_20, + pio1_20, + pio2_20, + clocks_gpin_0, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO20_CTRL_FUNCSEL_Field use + (spi0_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_2 => 4, + siob_proc_20 => 5, + pio0_20 => 6, + pio1_20 => 7, + pio2_20 => 8, + clocks_gpin_0 => 9, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO20_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO20_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO20_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO20_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO20_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO20_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO20_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO20_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO20_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO20_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO20_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO20_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO20_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO20_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO20_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO21_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO21_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO21_CTRL_FUNCSEL_Field is + (spi0_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_2, + siob_proc_21, + pio0_21, + pio1_21, + pio2_21, + clocks_gpout_0, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO21_CTRL_FUNCSEL_Field use + (spi0_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_2 => 4, + siob_proc_21 => 5, + pio0_21 => 6, + pio1_21 => 7, + pio2_21 => 8, + clocks_gpout_0 => 9, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO21_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO21_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO21_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO21_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO21_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO21_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO21_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO21_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO21_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO21_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO21_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO21_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO21_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO21_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO21_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO22_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO22_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO22_CTRL_FUNCSEL_Field is + (spi0_sclk, + uart1_cts, + i2c1_sda, + pwm_a_3, + siob_proc_22, + pio0_22, + pio1_22, + pio2_22, + clocks_gpin_1, + usb_muxing_vbus_detect, + uart1_tx, + null_k) + with Size => 5; + for GPIO22_CTRL_FUNCSEL_Field use + (spi0_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_3 => 4, + siob_proc_22 => 5, + pio0_22 => 6, + pio1_22 => 7, + pio2_22 => 8, + clocks_gpin_1 => 9, + usb_muxing_vbus_detect => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO22_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO22_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO22_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO22_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO22_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO22_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO22_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO22_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO22_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO22_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO22_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO22_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO22_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO22_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO22_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO23_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO23_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO23_CTRL_FUNCSEL_Field is + (spi0_tx, + uart1_rts, + i2c1_scl, + pwm_b_3, + siob_proc_23, + pio0_23, + pio1_23, + pio2_23, + clocks_gpout_1, + usb_muxing_vbus_en, + uart1_rx, + null_k) + with Size => 5; + for GPIO23_CTRL_FUNCSEL_Field use + (spi0_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_3 => 4, + siob_proc_23 => 5, + pio0_23 => 6, + pio1_23 => 7, + pio2_23 => 8, + clocks_gpout_1 => 9, + usb_muxing_vbus_en => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO23_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO23_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO23_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO23_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO23_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO23_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO23_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO23_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO23_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO23_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO23_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO23_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO23_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO23_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO23_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO24_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO24_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO24_CTRL_FUNCSEL_Field is + (spi1_rx, + uart1_tx, + i2c0_sda, + pwm_a_4, + siob_proc_24, + pio0_24, + pio1_24, + pio2_24, + clocks_gpout_2, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO24_CTRL_FUNCSEL_Field use + (spi1_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_4 => 4, + siob_proc_24 => 5, + pio0_24 => 6, + pio1_24 => 7, + pio2_24 => 8, + clocks_gpout_2 => 9, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO24_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO24_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO24_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO24_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO24_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO24_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO24_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO24_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO24_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO24_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO24_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO24_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO24_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO24_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO24_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO25_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO25_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO25_CTRL_FUNCSEL_Field is + (spi1_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_4, + siob_proc_25, + pio0_25, + pio1_25, + pio2_25, + clocks_gpout_3, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO25_CTRL_FUNCSEL_Field use + (spi1_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_4 => 4, + siob_proc_25 => 5, + pio0_25 => 6, + pio1_25 => 7, + pio2_25 => 8, + clocks_gpout_3 => 9, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO25_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO25_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO25_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO25_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO25_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO25_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO25_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO25_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO25_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO25_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO25_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO25_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO25_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO25_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO25_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO26_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO26_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO26_CTRL_FUNCSEL_Field is + (spi1_sclk, + uart1_cts, + i2c1_sda, + pwm_a_5, + siob_proc_26, + pio0_26, + pio1_26, + pio2_26, + usb_muxing_vbus_en, + uart1_tx, + null_k) + with Size => 5; + for GPIO26_CTRL_FUNCSEL_Field use + (spi1_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_5 => 4, + siob_proc_26 => 5, + pio0_26 => 6, + pio1_26 => 7, + pio2_26 => 8, + usb_muxing_vbus_en => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO26_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO26_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO26_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO26_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO26_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO26_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO26_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO26_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO26_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO26_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO26_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO26_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO26_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO26_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO26_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO27_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO27_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO27_CTRL_FUNCSEL_Field is + (spi1_tx, + uart1_rts, + i2c1_scl, + pwm_b_5, + siob_proc_27, + pio0_27, + pio1_27, + pio2_27, + usb_muxing_overcurr_detect, + uart1_rx, + null_k) + with Size => 5; + for GPIO27_CTRL_FUNCSEL_Field use + (spi1_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_5 => 4, + siob_proc_27 => 5, + pio0_27 => 6, + pio1_27 => 7, + pio2_27 => 8, + usb_muxing_overcurr_detect => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO27_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO27_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO27_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO27_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO27_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO27_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO27_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO27_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO27_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO27_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO27_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO27_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO27_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO27_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO27_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO28_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO28_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO28_CTRL_FUNCSEL_Field is + (spi1_rx, + uart0_tx, + i2c0_sda, + pwm_a_6, + siob_proc_28, + pio0_28, + pio1_28, + pio2_28, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO28_CTRL_FUNCSEL_Field use + (spi1_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_6 => 4, + siob_proc_28 => 5, + pio0_28 => 6, + pio1_28 => 7, + pio2_28 => 8, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO28_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO28_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO28_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO28_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO28_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO28_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO28_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO28_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO28_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO28_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO28_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO28_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO28_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO28_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO28_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO29_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO29_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO29_CTRL_FUNCSEL_Field is + (spi1_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_6, + siob_proc_29, + pio0_29, + pio1_29, + pio2_29, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO29_CTRL_FUNCSEL_Field use + (spi1_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_6 => 4, + siob_proc_29 => 5, + pio0_29 => 6, + pio1_29 => 7, + pio2_29 => 8, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO29_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO29_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO29_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO29_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO29_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO29_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO29_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO29_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO29_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO29_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO29_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO29_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO29_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO29_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO29_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO30_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO30_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO30_CTRL_FUNCSEL_Field is + (spi1_sclk, + uart0_cts, + i2c1_sda, + pwm_a_7, + siob_proc_30, + pio0_30, + pio1_30, + pio2_30, + usb_muxing_overcurr_detect, + uart0_tx, + null_k) + with Size => 5; + for GPIO30_CTRL_FUNCSEL_Field use + (spi1_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_7 => 4, + siob_proc_30 => 5, + pio0_30 => 6, + pio1_30 => 7, + pio2_30 => 8, + usb_muxing_overcurr_detect => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO30_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO30_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO30_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO30_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO30_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO30_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO30_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO30_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO30_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO30_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO30_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO30_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO30_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO30_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO30_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO31_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO31_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO31_CTRL_FUNCSEL_Field is + (spi1_tx, + uart0_rts, + i2c1_scl, + pwm_b_7, + siob_proc_31, + pio0_31, + pio1_31, + pio2_31, + usb_muxing_vbus_detect, + uart0_rx, + null_k) + with Size => 5; + for GPIO31_CTRL_FUNCSEL_Field use + (spi1_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_7 => 4, + siob_proc_31 => 5, + pio0_31 => 6, + pio1_31 => 7, + pio2_31 => 8, + usb_muxing_vbus_detect => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO31_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO31_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO31_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO31_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO31_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO31_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO31_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO31_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO31_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO31_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO31_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO31_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO31_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO31_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO31_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO32_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO32_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO32_CTRL_FUNCSEL_Field is + (spi0_rx, + uart0_tx, + i2c0_sda, + pwm_a_8, + siob_proc_32, + pio0_32, + pio1_32, + pio2_32, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO32_CTRL_FUNCSEL_Field use + (spi0_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_8 => 4, + siob_proc_32 => 5, + pio0_32 => 6, + pio1_32 => 7, + pio2_32 => 8, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO32_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO32_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO32_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO32_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO32_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO32_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO32_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO32_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO32_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO32_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO32_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO32_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO32_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO32_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO32_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO33_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO33_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO33_CTRL_FUNCSEL_Field is + (spi0_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_8, + siob_proc_33, + pio0_33, + pio1_33, + pio2_33, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO33_CTRL_FUNCSEL_Field use + (spi0_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_8 => 4, + siob_proc_33 => 5, + pio0_33 => 6, + pio1_33 => 7, + pio2_33 => 8, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO33_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO33_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO33_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO33_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO33_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO33_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO33_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO33_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO33_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO33_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO33_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO33_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO33_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO33_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO33_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO34_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO34_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO34_CTRL_FUNCSEL_Field is + (spi0_sclk, + uart0_cts, + i2c1_sda, + pwm_a_9, + siob_proc_34, + pio0_34, + pio1_34, + pio2_34, + usb_muxing_vbus_detect, + uart0_tx, + null_k) + with Size => 5; + for GPIO34_CTRL_FUNCSEL_Field use + (spi0_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_9 => 4, + siob_proc_34 => 5, + pio0_34 => 6, + pio1_34 => 7, + pio2_34 => 8, + usb_muxing_vbus_detect => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO34_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO34_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO34_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO34_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO34_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO34_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO34_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO34_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO34_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO34_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO34_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO34_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO34_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO34_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO34_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO35_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO35_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO35_CTRL_FUNCSEL_Field is + (spi0_tx, + uart0_rts, + i2c1_scl, + pwm_b_9, + siob_proc_35, + pio0_35, + pio1_35, + pio2_35, + usb_muxing_vbus_en, + uart0_rx, + null_k) + with Size => 5; + for GPIO35_CTRL_FUNCSEL_Field use + (spi0_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_9 => 4, + siob_proc_35 => 5, + pio0_35 => 6, + pio1_35 => 7, + pio2_35 => 8, + usb_muxing_vbus_en => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO35_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO35_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO35_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO35_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO35_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO35_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO35_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO35_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO35_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO35_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO35_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO35_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO35_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO35_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO35_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO36_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO36_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO36_CTRL_FUNCSEL_Field is + (spi0_rx, + uart1_tx, + i2c0_sda, + pwm_a_10, + siob_proc_36, + pio0_36, + pio1_36, + pio2_36, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO36_CTRL_FUNCSEL_Field use + (spi0_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_10 => 4, + siob_proc_36 => 5, + pio0_36 => 6, + pio1_36 => 7, + pio2_36 => 8, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO36_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO36_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO36_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO36_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO36_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO36_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO36_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO36_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO36_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO36_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO36_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO36_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO36_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO36_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO36_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO37_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO37_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO37_CTRL_FUNCSEL_Field is + (spi0_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_10, + siob_proc_37, + pio0_37, + pio1_37, + pio2_37, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO37_CTRL_FUNCSEL_Field use + (spi0_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_10 => 4, + siob_proc_37 => 5, + pio0_37 => 6, + pio1_37 => 7, + pio2_37 => 8, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO37_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO37_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO37_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO37_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO37_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO37_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO37_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO37_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO37_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO37_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO37_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO37_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO37_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO37_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO37_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO38_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO38_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO38_CTRL_FUNCSEL_Field is + (spi0_sclk, + uart1_cts, + i2c1_sda, + pwm_a_11, + siob_proc_38, + pio0_38, + pio1_38, + pio2_38, + usb_muxing_vbus_en, + uart1_tx, + null_k) + with Size => 5; + for GPIO38_CTRL_FUNCSEL_Field use + (spi0_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_11 => 4, + siob_proc_38 => 5, + pio0_38 => 6, + pio1_38 => 7, + pio2_38 => 8, + usb_muxing_vbus_en => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO38_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO38_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO38_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO38_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO38_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO38_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO38_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO38_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO38_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO38_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO38_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO38_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO38_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO38_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO38_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO39_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO39_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO39_CTRL_FUNCSEL_Field is + (spi0_tx, + uart1_rts, + i2c1_scl, + pwm_b_11, + siob_proc_39, + pio0_39, + pio1_39, + pio2_39, + usb_muxing_overcurr_detect, + uart1_rx, + null_k) + with Size => 5; + for GPIO39_CTRL_FUNCSEL_Field use + (spi0_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_11 => 4, + siob_proc_39 => 5, + pio0_39 => 6, + pio1_39 => 7, + pio2_39 => 8, + usb_muxing_overcurr_detect => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO39_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO39_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO39_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO39_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO39_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO39_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO39_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO39_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO39_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO39_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO39_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO39_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO39_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO39_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO39_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO40_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO40_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO40_CTRL_FUNCSEL_Field is + (spi1_rx, + uart1_tx, + i2c0_sda, + pwm_a_8, + siob_proc_40, + pio0_40, + pio1_40, + pio2_40, + usb_muxing_vbus_detect, + null_k) + with Size => 5; + for GPIO40_CTRL_FUNCSEL_Field use + (spi1_rx => 1, + uart1_tx => 2, + i2c0_sda => 3, + pwm_a_8 => 4, + siob_proc_40 => 5, + pio0_40 => 6, + pio1_40 => 7, + pio2_40 => 8, + usb_muxing_vbus_detect => 10, + null_k => 31); + + type GPIO40_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO40_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO40_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO40_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO40_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO40_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO40_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO40_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO40_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO40_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO40_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO40_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO40_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO40_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO40_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO41_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO41_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO41_CTRL_FUNCSEL_Field is + (spi1_ss_n, + uart1_rx, + i2c0_scl, + pwm_b_8, + siob_proc_41, + pio0_41, + pio1_41, + pio2_41, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO41_CTRL_FUNCSEL_Field use + (spi1_ss_n => 1, + uart1_rx => 2, + i2c0_scl => 3, + pwm_b_8 => 4, + siob_proc_41 => 5, + pio0_41 => 6, + pio1_41 => 7, + pio2_41 => 8, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO41_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO41_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO41_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO41_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO41_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO41_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO41_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO41_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO41_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO41_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO41_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO41_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO41_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO41_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO41_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO42_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO42_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO42_CTRL_FUNCSEL_Field is + (spi1_sclk, + uart1_cts, + i2c1_sda, + pwm_a_9, + siob_proc_42, + pio0_42, + pio1_42, + pio2_42, + usb_muxing_overcurr_detect, + uart1_tx, + null_k) + with Size => 5; + for GPIO42_CTRL_FUNCSEL_Field use + (spi1_sclk => 1, + uart1_cts => 2, + i2c1_sda => 3, + pwm_a_9 => 4, + siob_proc_42 => 5, + pio0_42 => 6, + pio1_42 => 7, + pio2_42 => 8, + usb_muxing_overcurr_detect => 10, + uart1_tx => 11, + null_k => 31); + + type GPIO42_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO42_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO42_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO42_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO42_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO42_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO42_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO42_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO42_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO42_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO42_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO42_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO42_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO42_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO42_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO43_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO43_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO43_CTRL_FUNCSEL_Field is + (spi1_tx, + uart1_rts, + i2c1_scl, + pwm_b_9, + siob_proc_43, + pio0_43, + pio1_43, + pio2_43, + usb_muxing_vbus_detect, + uart1_rx, + null_k) + with Size => 5; + for GPIO43_CTRL_FUNCSEL_Field use + (spi1_tx => 1, + uart1_rts => 2, + i2c1_scl => 3, + pwm_b_9 => 4, + siob_proc_43 => 5, + pio0_43 => 6, + pio1_43 => 7, + pio2_43 => 8, + usb_muxing_vbus_detect => 10, + uart1_rx => 11, + null_k => 31); + + type GPIO43_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO43_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO43_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO43_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO43_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO43_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO43_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO43_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO43_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO43_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO43_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO43_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO43_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO43_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO43_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO44_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO44_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO44_CTRL_FUNCSEL_Field is + (spi1_rx, + uart0_tx, + i2c0_sda, + pwm_a_10, + siob_proc_44, + pio0_44, + pio1_44, + pio2_44, + usb_muxing_vbus_en, + null_k) + with Size => 5; + for GPIO44_CTRL_FUNCSEL_Field use + (spi1_rx => 1, + uart0_tx => 2, + i2c0_sda => 3, + pwm_a_10 => 4, + siob_proc_44 => 5, + pio0_44 => 6, + pio1_44 => 7, + pio2_44 => 8, + usb_muxing_vbus_en => 10, + null_k => 31); + + type GPIO44_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO44_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO44_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO44_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO44_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO44_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO44_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO44_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO44_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO44_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO44_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO44_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO44_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO44_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO44_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO45_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO45_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO45_CTRL_FUNCSEL_Field is + (spi1_ss_n, + uart0_rx, + i2c0_scl, + pwm_b_10, + siob_proc_45, + pio0_45, + pio1_45, + pio2_45, + usb_muxing_overcurr_detect, + null_k) + with Size => 5; + for GPIO45_CTRL_FUNCSEL_Field use + (spi1_ss_n => 1, + uart0_rx => 2, + i2c0_scl => 3, + pwm_b_10 => 4, + siob_proc_45 => 5, + pio0_45 => 6, + pio1_45 => 7, + pio2_45 => 8, + usb_muxing_overcurr_detect => 10, + null_k => 31); + + type GPIO45_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO45_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO45_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO45_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO45_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO45_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO45_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO45_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO45_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO45_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO45_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO45_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO45_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO45_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO45_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO46_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO46_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO46_CTRL_FUNCSEL_Field is + (spi1_sclk, + uart0_cts, + i2c1_sda, + pwm_a_11, + siob_proc_46, + pio0_46, + pio1_46, + pio2_46, + usb_muxing_vbus_detect, + uart0_tx, + null_k) + with Size => 5; + for GPIO46_CTRL_FUNCSEL_Field use + (spi1_sclk => 1, + uart0_cts => 2, + i2c1_sda => 3, + pwm_a_11 => 4, + siob_proc_46 => 5, + pio0_46 => 6, + pio1_46 => 7, + pio2_46 => 8, + usb_muxing_vbus_detect => 10, + uart0_tx => 11, + null_k => 31); + + type GPIO46_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO46_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO46_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO46_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO46_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO46_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO46_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO46_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO46_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO46_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO46_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO46_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO46_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO46_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO46_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO47_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO47_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO47_CTRL_FUNCSEL_Field is + (spi1_tx, + uart0_rts, + i2c1_scl, + pwm_b_11, + siob_proc_47, + pio0_47, + pio1_47, + pio2_47, + xip_ss_n_1, + usb_muxing_vbus_en, + uart0_rx, + null_k) + with Size => 5; + for GPIO47_CTRL_FUNCSEL_Field use + (spi1_tx => 1, + uart0_rts => 2, + i2c1_scl => 3, + pwm_b_11 => 4, + siob_proc_47 => 5, + pio0_47 => 6, + pio1_47 => 7, + pio2_47 => 8, + xip_ss_n_1 => 9, + usb_muxing_vbus_en => 10, + uart0_rx => 11, + null_k => 31); + + type GPIO47_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO47_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO47_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO47_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO47_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO47_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO47_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO47_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO47_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO47_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_BANK0.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO47_CTRL_OUTOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + OEOVER : GPIO47_CTRL_OEOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + INOVER : GPIO47_CTRL_INOVER_Field := RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO47_CTRL_IRQOVER_Field := + RP2350_SVD.IO_BANK0.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO47_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- IRQSUMMARY_PROC0_SECURE0_GPIO array + type IRQSUMMARY_PROC0_SECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_PROC0_SECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC0_SECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_SECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_PROC0_SECURE1_GPIO array + type IRQSUMMARY_PROC0_SECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_PROC0_SECURE1_GPIO + type IRQSUMMARY_PROC0_SECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC0_SECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_PROC0_SECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_PROC0_SECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_PROC0_SECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_SECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQSUMMARY_PROC0_NONSECURE0_GPIO array + type IRQSUMMARY_PROC0_NONSECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_PROC0_NONSECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC0_NONSECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_NONSECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_PROC0_NONSECURE1_GPIO array + type IRQSUMMARY_PROC0_NONSECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_PROC0_NONSECURE1_GPIO + type IRQSUMMARY_PROC0_NONSECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC0_NONSECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_PROC0_NONSECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_PROC0_NONSECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_PROC0_NONSECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_NONSECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQSUMMARY_PROC1_SECURE0_GPIO array + type IRQSUMMARY_PROC1_SECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_PROC1_SECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC1_SECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_SECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_PROC1_SECURE1_GPIO array + type IRQSUMMARY_PROC1_SECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_PROC1_SECURE1_GPIO + type IRQSUMMARY_PROC1_SECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC1_SECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_PROC1_SECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_PROC1_SECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_PROC1_SECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_SECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQSUMMARY_PROC1_NONSECURE0_GPIO array + type IRQSUMMARY_PROC1_NONSECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_PROC1_NONSECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC1_NONSECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_NONSECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_PROC1_NONSECURE1_GPIO array + type IRQSUMMARY_PROC1_NONSECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_PROC1_NONSECURE1_GPIO + type IRQSUMMARY_PROC1_NONSECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_PROC1_NONSECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_PROC1_NONSECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_PROC1_NONSECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_PROC1_NONSECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_NONSECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO array + type IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_DORMANT_WAKE_SECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_SECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO array + type IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO + type IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_DORMANT_WAKE_SECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_SECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO array + type IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO_Field_Array is array (0 .. 31) + of Boolean + with Component_Size => 1, Size => 32; + + type IRQSUMMARY_DORMANT_WAKE_NONSECURE0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt32; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_NONSECURE0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO array + type IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO_Field_Array is array (32 .. 47) + of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO + type IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO as a value + Val : HAL.UInt16; + when True => + -- GPIO as an array + Arr : IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + type IRQSUMMARY_DORMANT_WAKE_NONSECURE1_Register is record + -- Read-only. + GPIO : IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Raw Interrupts + type INTR0_Register is record + -- Read-only. + GPIO0_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO0_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO0_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO0_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO1_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO1_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO1_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO1_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO2_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO2_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO2_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO2_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO3_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO3_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO3_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO3_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO4_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO4_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO4_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO4_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO5_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO5_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO5_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO5_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO6_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO6_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO6_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO6_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO7_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO7_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO7_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR1_Register is record + -- Read-only. + GPIO8_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO8_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO8_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO8_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO9_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO9_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO9_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO9_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO10_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO10_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO10_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO10_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO11_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO11_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO11_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO11_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO12_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO12_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO12_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO12_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO13_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO13_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO13_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO13_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO14_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO14_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO14_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO14_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO15_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO15_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO15_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR2_Register is record + -- Read-only. + GPIO16_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO16_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO16_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO16_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO17_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO17_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO17_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO17_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO18_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO18_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO18_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO18_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO19_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO19_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO19_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO19_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO20_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO20_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO20_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO20_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO21_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO21_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO21_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO21_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO22_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO22_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO22_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO22_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO23_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO23_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO23_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR3_Register is record + -- Read-only. + GPIO24_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO24_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO24_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO24_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO25_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO25_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO25_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO25_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO26_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO26_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO26_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO26_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO27_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO27_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO27_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO27_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO28_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO28_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO28_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO28_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO29_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO29_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO29_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO29_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO30_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO30_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO30_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO30_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO31_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO31_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO31_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR4_Register is record + -- Read-only. + GPIO32_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO32_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO32_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO32_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO33_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO33_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO33_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO33_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO34_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO34_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO34_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO34_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO35_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO35_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO35_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO35_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO36_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO36_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO36_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO36_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO37_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO37_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO37_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO37_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO38_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO38_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO38_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO38_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO39_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO39_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO39_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Raw Interrupts + type INTR5_Register is record + -- Read-only. + GPIO40_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO40_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO40_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO40_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO41_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO41_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO41_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO41_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO42_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO42_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO42_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO42_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO43_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO43_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO43_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO43_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO44_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO44_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO44_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO44_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO45_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO45_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO45_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO45_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO46_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO46_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO46_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO46_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO47_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO47_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO47_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS0_Register is record + -- Read-only. + GPIO0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO0_EDGE_LOW : Boolean; + -- Read-only. + GPIO0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO1_EDGE_LOW : Boolean; + -- Read-only. + GPIO1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO2_EDGE_LOW : Boolean; + -- Read-only. + GPIO2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO3_EDGE_LOW : Boolean; + -- Read-only. + GPIO3_EDGE_HIGH : Boolean; + -- Read-only. + GPIO4_LEVEL_LOW : Boolean; + -- Read-only. + GPIO4_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO4_EDGE_LOW : Boolean; + -- Read-only. + GPIO4_EDGE_HIGH : Boolean; + -- Read-only. + GPIO5_LEVEL_LOW : Boolean; + -- Read-only. + GPIO5_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO5_EDGE_LOW : Boolean; + -- Read-only. + GPIO5_EDGE_HIGH : Boolean; + -- Read-only. + GPIO6_LEVEL_LOW : Boolean; + -- Read-only. + GPIO6_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO6_EDGE_LOW : Boolean; + -- Read-only. + GPIO6_EDGE_HIGH : Boolean; + -- Read-only. + GPIO7_LEVEL_LOW : Boolean; + -- Read-only. + GPIO7_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO7_EDGE_LOW : Boolean; + -- Read-only. + GPIO7_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS1_Register is record + -- Read-only. + GPIO8_LEVEL_LOW : Boolean; + -- Read-only. + GPIO8_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO8_EDGE_LOW : Boolean; + -- Read-only. + GPIO8_EDGE_HIGH : Boolean; + -- Read-only. + GPIO9_LEVEL_LOW : Boolean; + -- Read-only. + GPIO9_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO9_EDGE_LOW : Boolean; + -- Read-only. + GPIO9_EDGE_HIGH : Boolean; + -- Read-only. + GPIO10_LEVEL_LOW : Boolean; + -- Read-only. + GPIO10_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO10_EDGE_LOW : Boolean; + -- Read-only. + GPIO10_EDGE_HIGH : Boolean; + -- Read-only. + GPIO11_LEVEL_LOW : Boolean; + -- Read-only. + GPIO11_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO11_EDGE_LOW : Boolean; + -- Read-only. + GPIO11_EDGE_HIGH : Boolean; + -- Read-only. + GPIO12_LEVEL_LOW : Boolean; + -- Read-only. + GPIO12_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO12_EDGE_LOW : Boolean; + -- Read-only. + GPIO12_EDGE_HIGH : Boolean; + -- Read-only. + GPIO13_LEVEL_LOW : Boolean; + -- Read-only. + GPIO13_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO13_EDGE_LOW : Boolean; + -- Read-only. + GPIO13_EDGE_HIGH : Boolean; + -- Read-only. + GPIO14_LEVEL_LOW : Boolean; + -- Read-only. + GPIO14_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO14_EDGE_LOW : Boolean; + -- Read-only. + GPIO14_EDGE_HIGH : Boolean; + -- Read-only. + GPIO15_LEVEL_LOW : Boolean; + -- Read-only. + GPIO15_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO15_EDGE_LOW : Boolean; + -- Read-only. + GPIO15_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS2_Register is record + -- Read-only. + GPIO16_LEVEL_LOW : Boolean; + -- Read-only. + GPIO16_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO16_EDGE_LOW : Boolean; + -- Read-only. + GPIO16_EDGE_HIGH : Boolean; + -- Read-only. + GPIO17_LEVEL_LOW : Boolean; + -- Read-only. + GPIO17_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO17_EDGE_LOW : Boolean; + -- Read-only. + GPIO17_EDGE_HIGH : Boolean; + -- Read-only. + GPIO18_LEVEL_LOW : Boolean; + -- Read-only. + GPIO18_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO18_EDGE_LOW : Boolean; + -- Read-only. + GPIO18_EDGE_HIGH : Boolean; + -- Read-only. + GPIO19_LEVEL_LOW : Boolean; + -- Read-only. + GPIO19_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO19_EDGE_LOW : Boolean; + -- Read-only. + GPIO19_EDGE_HIGH : Boolean; + -- Read-only. + GPIO20_LEVEL_LOW : Boolean; + -- Read-only. + GPIO20_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO20_EDGE_LOW : Boolean; + -- Read-only. + GPIO20_EDGE_HIGH : Boolean; + -- Read-only. + GPIO21_LEVEL_LOW : Boolean; + -- Read-only. + GPIO21_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO21_EDGE_LOW : Boolean; + -- Read-only. + GPIO21_EDGE_HIGH : Boolean; + -- Read-only. + GPIO22_LEVEL_LOW : Boolean; + -- Read-only. + GPIO22_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO22_EDGE_LOW : Boolean; + -- Read-only. + GPIO22_EDGE_HIGH : Boolean; + -- Read-only. + GPIO23_LEVEL_LOW : Boolean; + -- Read-only. + GPIO23_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO23_EDGE_LOW : Boolean; + -- Read-only. + GPIO23_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS3_Register is record + -- Read-only. + GPIO24_LEVEL_LOW : Boolean; + -- Read-only. + GPIO24_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO24_EDGE_LOW : Boolean; + -- Read-only. + GPIO24_EDGE_HIGH : Boolean; + -- Read-only. + GPIO25_LEVEL_LOW : Boolean; + -- Read-only. + GPIO25_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO25_EDGE_LOW : Boolean; + -- Read-only. + GPIO25_EDGE_HIGH : Boolean; + -- Read-only. + GPIO26_LEVEL_LOW : Boolean; + -- Read-only. + GPIO26_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO26_EDGE_LOW : Boolean; + -- Read-only. + GPIO26_EDGE_HIGH : Boolean; + -- Read-only. + GPIO27_LEVEL_LOW : Boolean; + -- Read-only. + GPIO27_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO27_EDGE_LOW : Boolean; + -- Read-only. + GPIO27_EDGE_HIGH : Boolean; + -- Read-only. + GPIO28_LEVEL_LOW : Boolean; + -- Read-only. + GPIO28_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO28_EDGE_LOW : Boolean; + -- Read-only. + GPIO28_EDGE_HIGH : Boolean; + -- Read-only. + GPIO29_LEVEL_LOW : Boolean; + -- Read-only. + GPIO29_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO29_EDGE_LOW : Boolean; + -- Read-only. + GPIO29_EDGE_HIGH : Boolean; + -- Read-only. + GPIO30_LEVEL_LOW : Boolean; + -- Read-only. + GPIO30_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO30_EDGE_LOW : Boolean; + -- Read-only. + GPIO30_EDGE_HIGH : Boolean; + -- Read-only. + GPIO31_LEVEL_LOW : Boolean; + -- Read-only. + GPIO31_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO31_EDGE_LOW : Boolean; + -- Read-only. + GPIO31_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS4_Register is record + -- Read-only. + GPIO32_LEVEL_LOW : Boolean; + -- Read-only. + GPIO32_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO32_EDGE_LOW : Boolean; + -- Read-only. + GPIO32_EDGE_HIGH : Boolean; + -- Read-only. + GPIO33_LEVEL_LOW : Boolean; + -- Read-only. + GPIO33_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO33_EDGE_LOW : Boolean; + -- Read-only. + GPIO33_EDGE_HIGH : Boolean; + -- Read-only. + GPIO34_LEVEL_LOW : Boolean; + -- Read-only. + GPIO34_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO34_EDGE_LOW : Boolean; + -- Read-only. + GPIO34_EDGE_HIGH : Boolean; + -- Read-only. + GPIO35_LEVEL_LOW : Boolean; + -- Read-only. + GPIO35_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO35_EDGE_LOW : Boolean; + -- Read-only. + GPIO35_EDGE_HIGH : Boolean; + -- Read-only. + GPIO36_LEVEL_LOW : Boolean; + -- Read-only. + GPIO36_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO36_EDGE_LOW : Boolean; + -- Read-only. + GPIO36_EDGE_HIGH : Boolean; + -- Read-only. + GPIO37_LEVEL_LOW : Boolean; + -- Read-only. + GPIO37_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO37_EDGE_LOW : Boolean; + -- Read-only. + GPIO37_EDGE_HIGH : Boolean; + -- Read-only. + GPIO38_LEVEL_LOW : Boolean; + -- Read-only. + GPIO38_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO38_EDGE_LOW : Boolean; + -- Read-only. + GPIO38_EDGE_HIGH : Boolean; + -- Read-only. + GPIO39_LEVEL_LOW : Boolean; + -- Read-only. + GPIO39_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO39_EDGE_LOW : Boolean; + -- Read-only. + GPIO39_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS5_Register is record + -- Read-only. + GPIO40_LEVEL_LOW : Boolean; + -- Read-only. + GPIO40_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO40_EDGE_LOW : Boolean; + -- Read-only. + GPIO40_EDGE_HIGH : Boolean; + -- Read-only. + GPIO41_LEVEL_LOW : Boolean; + -- Read-only. + GPIO41_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO41_EDGE_LOW : Boolean; + -- Read-only. + GPIO41_EDGE_HIGH : Boolean; + -- Read-only. + GPIO42_LEVEL_LOW : Boolean; + -- Read-only. + GPIO42_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO42_EDGE_LOW : Boolean; + -- Read-only. + GPIO42_EDGE_HIGH : Boolean; + -- Read-only. + GPIO43_LEVEL_LOW : Boolean; + -- Read-only. + GPIO43_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO43_EDGE_LOW : Boolean; + -- Read-only. + GPIO43_EDGE_HIGH : Boolean; + -- Read-only. + GPIO44_LEVEL_LOW : Boolean; + -- Read-only. + GPIO44_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO44_EDGE_LOW : Boolean; + -- Read-only. + GPIO44_EDGE_HIGH : Boolean; + -- Read-only. + GPIO45_LEVEL_LOW : Boolean; + -- Read-only. + GPIO45_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO45_EDGE_LOW : Boolean; + -- Read-only. + GPIO45_EDGE_HIGH : Boolean; + -- Read-only. + GPIO46_LEVEL_LOW : Boolean; + -- Read-only. + GPIO46_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO46_EDGE_LOW : Boolean; + -- Read-only. + GPIO46_EDGE_HIGH : Boolean; + -- Read-only. + GPIO47_LEVEL_LOW : Boolean; + -- Read-only. + GPIO47_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO47_EDGE_LOW : Boolean; + -- Read-only. + GPIO47_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS0_Register is record + -- Read-only. + GPIO0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO0_EDGE_LOW : Boolean; + -- Read-only. + GPIO0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO1_EDGE_LOW : Boolean; + -- Read-only. + GPIO1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO2_EDGE_LOW : Boolean; + -- Read-only. + GPIO2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO3_EDGE_LOW : Boolean; + -- Read-only. + GPIO3_EDGE_HIGH : Boolean; + -- Read-only. + GPIO4_LEVEL_LOW : Boolean; + -- Read-only. + GPIO4_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO4_EDGE_LOW : Boolean; + -- Read-only. + GPIO4_EDGE_HIGH : Boolean; + -- Read-only. + GPIO5_LEVEL_LOW : Boolean; + -- Read-only. + GPIO5_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO5_EDGE_LOW : Boolean; + -- Read-only. + GPIO5_EDGE_HIGH : Boolean; + -- Read-only. + GPIO6_LEVEL_LOW : Boolean; + -- Read-only. + GPIO6_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO6_EDGE_LOW : Boolean; + -- Read-only. + GPIO6_EDGE_HIGH : Boolean; + -- Read-only. + GPIO7_LEVEL_LOW : Boolean; + -- Read-only. + GPIO7_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO7_EDGE_LOW : Boolean; + -- Read-only. + GPIO7_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS1_Register is record + -- Read-only. + GPIO8_LEVEL_LOW : Boolean; + -- Read-only. + GPIO8_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO8_EDGE_LOW : Boolean; + -- Read-only. + GPIO8_EDGE_HIGH : Boolean; + -- Read-only. + GPIO9_LEVEL_LOW : Boolean; + -- Read-only. + GPIO9_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO9_EDGE_LOW : Boolean; + -- Read-only. + GPIO9_EDGE_HIGH : Boolean; + -- Read-only. + GPIO10_LEVEL_LOW : Boolean; + -- Read-only. + GPIO10_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO10_EDGE_LOW : Boolean; + -- Read-only. + GPIO10_EDGE_HIGH : Boolean; + -- Read-only. + GPIO11_LEVEL_LOW : Boolean; + -- Read-only. + GPIO11_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO11_EDGE_LOW : Boolean; + -- Read-only. + GPIO11_EDGE_HIGH : Boolean; + -- Read-only. + GPIO12_LEVEL_LOW : Boolean; + -- Read-only. + GPIO12_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO12_EDGE_LOW : Boolean; + -- Read-only. + GPIO12_EDGE_HIGH : Boolean; + -- Read-only. + GPIO13_LEVEL_LOW : Boolean; + -- Read-only. + GPIO13_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO13_EDGE_LOW : Boolean; + -- Read-only. + GPIO13_EDGE_HIGH : Boolean; + -- Read-only. + GPIO14_LEVEL_LOW : Boolean; + -- Read-only. + GPIO14_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO14_EDGE_LOW : Boolean; + -- Read-only. + GPIO14_EDGE_HIGH : Boolean; + -- Read-only. + GPIO15_LEVEL_LOW : Boolean; + -- Read-only. + GPIO15_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO15_EDGE_LOW : Boolean; + -- Read-only. + GPIO15_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS2_Register is record + -- Read-only. + GPIO16_LEVEL_LOW : Boolean; + -- Read-only. + GPIO16_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO16_EDGE_LOW : Boolean; + -- Read-only. + GPIO16_EDGE_HIGH : Boolean; + -- Read-only. + GPIO17_LEVEL_LOW : Boolean; + -- Read-only. + GPIO17_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO17_EDGE_LOW : Boolean; + -- Read-only. + GPIO17_EDGE_HIGH : Boolean; + -- Read-only. + GPIO18_LEVEL_LOW : Boolean; + -- Read-only. + GPIO18_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO18_EDGE_LOW : Boolean; + -- Read-only. + GPIO18_EDGE_HIGH : Boolean; + -- Read-only. + GPIO19_LEVEL_LOW : Boolean; + -- Read-only. + GPIO19_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO19_EDGE_LOW : Boolean; + -- Read-only. + GPIO19_EDGE_HIGH : Boolean; + -- Read-only. + GPIO20_LEVEL_LOW : Boolean; + -- Read-only. + GPIO20_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO20_EDGE_LOW : Boolean; + -- Read-only. + GPIO20_EDGE_HIGH : Boolean; + -- Read-only. + GPIO21_LEVEL_LOW : Boolean; + -- Read-only. + GPIO21_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO21_EDGE_LOW : Boolean; + -- Read-only. + GPIO21_EDGE_HIGH : Boolean; + -- Read-only. + GPIO22_LEVEL_LOW : Boolean; + -- Read-only. + GPIO22_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO22_EDGE_LOW : Boolean; + -- Read-only. + GPIO22_EDGE_HIGH : Boolean; + -- Read-only. + GPIO23_LEVEL_LOW : Boolean; + -- Read-only. + GPIO23_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO23_EDGE_LOW : Boolean; + -- Read-only. + GPIO23_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS3_Register is record + -- Read-only. + GPIO24_LEVEL_LOW : Boolean; + -- Read-only. + GPIO24_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO24_EDGE_LOW : Boolean; + -- Read-only. + GPIO24_EDGE_HIGH : Boolean; + -- Read-only. + GPIO25_LEVEL_LOW : Boolean; + -- Read-only. + GPIO25_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO25_EDGE_LOW : Boolean; + -- Read-only. + GPIO25_EDGE_HIGH : Boolean; + -- Read-only. + GPIO26_LEVEL_LOW : Boolean; + -- Read-only. + GPIO26_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO26_EDGE_LOW : Boolean; + -- Read-only. + GPIO26_EDGE_HIGH : Boolean; + -- Read-only. + GPIO27_LEVEL_LOW : Boolean; + -- Read-only. + GPIO27_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO27_EDGE_LOW : Boolean; + -- Read-only. + GPIO27_EDGE_HIGH : Boolean; + -- Read-only. + GPIO28_LEVEL_LOW : Boolean; + -- Read-only. + GPIO28_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO28_EDGE_LOW : Boolean; + -- Read-only. + GPIO28_EDGE_HIGH : Boolean; + -- Read-only. + GPIO29_LEVEL_LOW : Boolean; + -- Read-only. + GPIO29_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO29_EDGE_LOW : Boolean; + -- Read-only. + GPIO29_EDGE_HIGH : Boolean; + -- Read-only. + GPIO30_LEVEL_LOW : Boolean; + -- Read-only. + GPIO30_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO30_EDGE_LOW : Boolean; + -- Read-only. + GPIO30_EDGE_HIGH : Boolean; + -- Read-only. + GPIO31_LEVEL_LOW : Boolean; + -- Read-only. + GPIO31_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO31_EDGE_LOW : Boolean; + -- Read-only. + GPIO31_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS4_Register is record + -- Read-only. + GPIO32_LEVEL_LOW : Boolean; + -- Read-only. + GPIO32_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO32_EDGE_LOW : Boolean; + -- Read-only. + GPIO32_EDGE_HIGH : Boolean; + -- Read-only. + GPIO33_LEVEL_LOW : Boolean; + -- Read-only. + GPIO33_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO33_EDGE_LOW : Boolean; + -- Read-only. + GPIO33_EDGE_HIGH : Boolean; + -- Read-only. + GPIO34_LEVEL_LOW : Boolean; + -- Read-only. + GPIO34_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO34_EDGE_LOW : Boolean; + -- Read-only. + GPIO34_EDGE_HIGH : Boolean; + -- Read-only. + GPIO35_LEVEL_LOW : Boolean; + -- Read-only. + GPIO35_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO35_EDGE_LOW : Boolean; + -- Read-only. + GPIO35_EDGE_HIGH : Boolean; + -- Read-only. + GPIO36_LEVEL_LOW : Boolean; + -- Read-only. + GPIO36_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO36_EDGE_LOW : Boolean; + -- Read-only. + GPIO36_EDGE_HIGH : Boolean; + -- Read-only. + GPIO37_LEVEL_LOW : Boolean; + -- Read-only. + GPIO37_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO37_EDGE_LOW : Boolean; + -- Read-only. + GPIO37_EDGE_HIGH : Boolean; + -- Read-only. + GPIO38_LEVEL_LOW : Boolean; + -- Read-only. + GPIO38_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO38_EDGE_LOW : Boolean; + -- Read-only. + GPIO38_EDGE_HIGH : Boolean; + -- Read-only. + GPIO39_LEVEL_LOW : Boolean; + -- Read-only. + GPIO39_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO39_EDGE_LOW : Boolean; + -- Read-only. + GPIO39_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS5_Register is record + -- Read-only. + GPIO40_LEVEL_LOW : Boolean; + -- Read-only. + GPIO40_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO40_EDGE_LOW : Boolean; + -- Read-only. + GPIO40_EDGE_HIGH : Boolean; + -- Read-only. + GPIO41_LEVEL_LOW : Boolean; + -- Read-only. + GPIO41_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO41_EDGE_LOW : Boolean; + -- Read-only. + GPIO41_EDGE_HIGH : Boolean; + -- Read-only. + GPIO42_LEVEL_LOW : Boolean; + -- Read-only. + GPIO42_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO42_EDGE_LOW : Boolean; + -- Read-only. + GPIO42_EDGE_HIGH : Boolean; + -- Read-only. + GPIO43_LEVEL_LOW : Boolean; + -- Read-only. + GPIO43_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO43_EDGE_LOW : Boolean; + -- Read-only. + GPIO43_EDGE_HIGH : Boolean; + -- Read-only. + GPIO44_LEVEL_LOW : Boolean; + -- Read-only. + GPIO44_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO44_EDGE_LOW : Boolean; + -- Read-only. + GPIO44_EDGE_HIGH : Boolean; + -- Read-only. + GPIO45_LEVEL_LOW : Boolean; + -- Read-only. + GPIO45_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO45_EDGE_LOW : Boolean; + -- Read-only. + GPIO45_EDGE_HIGH : Boolean; + -- Read-only. + GPIO46_LEVEL_LOW : Boolean; + -- Read-only. + GPIO46_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO46_EDGE_LOW : Boolean; + -- Read-only. + GPIO46_EDGE_HIGH : Boolean; + -- Read-only. + GPIO47_LEVEL_LOW : Boolean; + -- Read-only. + GPIO47_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO47_EDGE_LOW : Boolean; + -- Read-only. + GPIO47_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF0_Register is record + GPIO0_LEVEL_LOW : Boolean := False; + GPIO0_LEVEL_HIGH : Boolean := False; + GPIO0_EDGE_LOW : Boolean := False; + GPIO0_EDGE_HIGH : Boolean := False; + GPIO1_LEVEL_LOW : Boolean := False; + GPIO1_LEVEL_HIGH : Boolean := False; + GPIO1_EDGE_LOW : Boolean := False; + GPIO1_EDGE_HIGH : Boolean := False; + GPIO2_LEVEL_LOW : Boolean := False; + GPIO2_LEVEL_HIGH : Boolean := False; + GPIO2_EDGE_LOW : Boolean := False; + GPIO2_EDGE_HIGH : Boolean := False; + GPIO3_LEVEL_LOW : Boolean := False; + GPIO3_LEVEL_HIGH : Boolean := False; + GPIO3_EDGE_LOW : Boolean := False; + GPIO3_EDGE_HIGH : Boolean := False; + GPIO4_LEVEL_LOW : Boolean := False; + GPIO4_LEVEL_HIGH : Boolean := False; + GPIO4_EDGE_LOW : Boolean := False; + GPIO4_EDGE_HIGH : Boolean := False; + GPIO5_LEVEL_LOW : Boolean := False; + GPIO5_LEVEL_HIGH : Boolean := False; + GPIO5_EDGE_LOW : Boolean := False; + GPIO5_EDGE_HIGH : Boolean := False; + GPIO6_LEVEL_LOW : Boolean := False; + GPIO6_LEVEL_HIGH : Boolean := False; + GPIO6_EDGE_LOW : Boolean := False; + GPIO6_EDGE_HIGH : Boolean := False; + GPIO7_LEVEL_LOW : Boolean := False; + GPIO7_LEVEL_HIGH : Boolean := False; + GPIO7_EDGE_LOW : Boolean := False; + GPIO7_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF1_Register is record + GPIO8_LEVEL_LOW : Boolean := False; + GPIO8_LEVEL_HIGH : Boolean := False; + GPIO8_EDGE_LOW : Boolean := False; + GPIO8_EDGE_HIGH : Boolean := False; + GPIO9_LEVEL_LOW : Boolean := False; + GPIO9_LEVEL_HIGH : Boolean := False; + GPIO9_EDGE_LOW : Boolean := False; + GPIO9_EDGE_HIGH : Boolean := False; + GPIO10_LEVEL_LOW : Boolean := False; + GPIO10_LEVEL_HIGH : Boolean := False; + GPIO10_EDGE_LOW : Boolean := False; + GPIO10_EDGE_HIGH : Boolean := False; + GPIO11_LEVEL_LOW : Boolean := False; + GPIO11_LEVEL_HIGH : Boolean := False; + GPIO11_EDGE_LOW : Boolean := False; + GPIO11_EDGE_HIGH : Boolean := False; + GPIO12_LEVEL_LOW : Boolean := False; + GPIO12_LEVEL_HIGH : Boolean := False; + GPIO12_EDGE_LOW : Boolean := False; + GPIO12_EDGE_HIGH : Boolean := False; + GPIO13_LEVEL_LOW : Boolean := False; + GPIO13_LEVEL_HIGH : Boolean := False; + GPIO13_EDGE_LOW : Boolean := False; + GPIO13_EDGE_HIGH : Boolean := False; + GPIO14_LEVEL_LOW : Boolean := False; + GPIO14_LEVEL_HIGH : Boolean := False; + GPIO14_EDGE_LOW : Boolean := False; + GPIO14_EDGE_HIGH : Boolean := False; + GPIO15_LEVEL_LOW : Boolean := False; + GPIO15_LEVEL_HIGH : Boolean := False; + GPIO15_EDGE_LOW : Boolean := False; + GPIO15_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF2_Register is record + GPIO16_LEVEL_LOW : Boolean := False; + GPIO16_LEVEL_HIGH : Boolean := False; + GPIO16_EDGE_LOW : Boolean := False; + GPIO16_EDGE_HIGH : Boolean := False; + GPIO17_LEVEL_LOW : Boolean := False; + GPIO17_LEVEL_HIGH : Boolean := False; + GPIO17_EDGE_LOW : Boolean := False; + GPIO17_EDGE_HIGH : Boolean := False; + GPIO18_LEVEL_LOW : Boolean := False; + GPIO18_LEVEL_HIGH : Boolean := False; + GPIO18_EDGE_LOW : Boolean := False; + GPIO18_EDGE_HIGH : Boolean := False; + GPIO19_LEVEL_LOW : Boolean := False; + GPIO19_LEVEL_HIGH : Boolean := False; + GPIO19_EDGE_LOW : Boolean := False; + GPIO19_EDGE_HIGH : Boolean := False; + GPIO20_LEVEL_LOW : Boolean := False; + GPIO20_LEVEL_HIGH : Boolean := False; + GPIO20_EDGE_LOW : Boolean := False; + GPIO20_EDGE_HIGH : Boolean := False; + GPIO21_LEVEL_LOW : Boolean := False; + GPIO21_LEVEL_HIGH : Boolean := False; + GPIO21_EDGE_LOW : Boolean := False; + GPIO21_EDGE_HIGH : Boolean := False; + GPIO22_LEVEL_LOW : Boolean := False; + GPIO22_LEVEL_HIGH : Boolean := False; + GPIO22_EDGE_LOW : Boolean := False; + GPIO22_EDGE_HIGH : Boolean := False; + GPIO23_LEVEL_LOW : Boolean := False; + GPIO23_LEVEL_HIGH : Boolean := False; + GPIO23_EDGE_LOW : Boolean := False; + GPIO23_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF3_Register is record + GPIO24_LEVEL_LOW : Boolean := False; + GPIO24_LEVEL_HIGH : Boolean := False; + GPIO24_EDGE_LOW : Boolean := False; + GPIO24_EDGE_HIGH : Boolean := False; + GPIO25_LEVEL_LOW : Boolean := False; + GPIO25_LEVEL_HIGH : Boolean := False; + GPIO25_EDGE_LOW : Boolean := False; + GPIO25_EDGE_HIGH : Boolean := False; + GPIO26_LEVEL_LOW : Boolean := False; + GPIO26_LEVEL_HIGH : Boolean := False; + GPIO26_EDGE_LOW : Boolean := False; + GPIO26_EDGE_HIGH : Boolean := False; + GPIO27_LEVEL_LOW : Boolean := False; + GPIO27_LEVEL_HIGH : Boolean := False; + GPIO27_EDGE_LOW : Boolean := False; + GPIO27_EDGE_HIGH : Boolean := False; + GPIO28_LEVEL_LOW : Boolean := False; + GPIO28_LEVEL_HIGH : Boolean := False; + GPIO28_EDGE_LOW : Boolean := False; + GPIO28_EDGE_HIGH : Boolean := False; + GPIO29_LEVEL_LOW : Boolean := False; + GPIO29_LEVEL_HIGH : Boolean := False; + GPIO29_EDGE_LOW : Boolean := False; + GPIO29_EDGE_HIGH : Boolean := False; + GPIO30_LEVEL_LOW : Boolean := False; + GPIO30_LEVEL_HIGH : Boolean := False; + GPIO30_EDGE_LOW : Boolean := False; + GPIO30_EDGE_HIGH : Boolean := False; + GPIO31_LEVEL_LOW : Boolean := False; + GPIO31_LEVEL_HIGH : Boolean := False; + GPIO31_EDGE_LOW : Boolean := False; + GPIO31_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF4_Register is record + GPIO32_LEVEL_LOW : Boolean := False; + GPIO32_LEVEL_HIGH : Boolean := False; + GPIO32_EDGE_LOW : Boolean := False; + GPIO32_EDGE_HIGH : Boolean := False; + GPIO33_LEVEL_LOW : Boolean := False; + GPIO33_LEVEL_HIGH : Boolean := False; + GPIO33_EDGE_LOW : Boolean := False; + GPIO33_EDGE_HIGH : Boolean := False; + GPIO34_LEVEL_LOW : Boolean := False; + GPIO34_LEVEL_HIGH : Boolean := False; + GPIO34_EDGE_LOW : Boolean := False; + GPIO34_EDGE_HIGH : Boolean := False; + GPIO35_LEVEL_LOW : Boolean := False; + GPIO35_LEVEL_HIGH : Boolean := False; + GPIO35_EDGE_LOW : Boolean := False; + GPIO35_EDGE_HIGH : Boolean := False; + GPIO36_LEVEL_LOW : Boolean := False; + GPIO36_LEVEL_HIGH : Boolean := False; + GPIO36_EDGE_LOW : Boolean := False; + GPIO36_EDGE_HIGH : Boolean := False; + GPIO37_LEVEL_LOW : Boolean := False; + GPIO37_LEVEL_HIGH : Boolean := False; + GPIO37_EDGE_LOW : Boolean := False; + GPIO37_EDGE_HIGH : Boolean := False; + GPIO38_LEVEL_LOW : Boolean := False; + GPIO38_LEVEL_HIGH : Boolean := False; + GPIO38_EDGE_LOW : Boolean := False; + GPIO38_EDGE_HIGH : Boolean := False; + GPIO39_LEVEL_LOW : Boolean := False; + GPIO39_LEVEL_HIGH : Boolean := False; + GPIO39_EDGE_LOW : Boolean := False; + GPIO39_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF5_Register is record + GPIO40_LEVEL_LOW : Boolean := False; + GPIO40_LEVEL_HIGH : Boolean := False; + GPIO40_EDGE_LOW : Boolean := False; + GPIO40_EDGE_HIGH : Boolean := False; + GPIO41_LEVEL_LOW : Boolean := False; + GPIO41_LEVEL_HIGH : Boolean := False; + GPIO41_EDGE_LOW : Boolean := False; + GPIO41_EDGE_HIGH : Boolean := False; + GPIO42_LEVEL_LOW : Boolean := False; + GPIO42_LEVEL_HIGH : Boolean := False; + GPIO42_EDGE_LOW : Boolean := False; + GPIO42_EDGE_HIGH : Boolean := False; + GPIO43_LEVEL_LOW : Boolean := False; + GPIO43_LEVEL_HIGH : Boolean := False; + GPIO43_EDGE_LOW : Boolean := False; + GPIO43_EDGE_HIGH : Boolean := False; + GPIO44_LEVEL_LOW : Boolean := False; + GPIO44_LEVEL_HIGH : Boolean := False; + GPIO44_EDGE_LOW : Boolean := False; + GPIO44_EDGE_HIGH : Boolean := False; + GPIO45_LEVEL_LOW : Boolean := False; + GPIO45_LEVEL_HIGH : Boolean := False; + GPIO45_EDGE_LOW : Boolean := False; + GPIO45_EDGE_HIGH : Boolean := False; + GPIO46_LEVEL_LOW : Boolean := False; + GPIO46_LEVEL_HIGH : Boolean := False; + GPIO46_EDGE_LOW : Boolean := False; + GPIO46_EDGE_HIGH : Boolean := False; + GPIO47_LEVEL_LOW : Boolean := False; + GPIO47_LEVEL_HIGH : Boolean := False; + GPIO47_EDGE_LOW : Boolean := False; + GPIO47_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS0_Register is record + -- Read-only. + GPIO0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO0_EDGE_LOW : Boolean; + -- Read-only. + GPIO0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO1_EDGE_LOW : Boolean; + -- Read-only. + GPIO1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO2_EDGE_LOW : Boolean; + -- Read-only. + GPIO2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO3_EDGE_LOW : Boolean; + -- Read-only. + GPIO3_EDGE_HIGH : Boolean; + -- Read-only. + GPIO4_LEVEL_LOW : Boolean; + -- Read-only. + GPIO4_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO4_EDGE_LOW : Boolean; + -- Read-only. + GPIO4_EDGE_HIGH : Boolean; + -- Read-only. + GPIO5_LEVEL_LOW : Boolean; + -- Read-only. + GPIO5_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO5_EDGE_LOW : Boolean; + -- Read-only. + GPIO5_EDGE_HIGH : Boolean; + -- Read-only. + GPIO6_LEVEL_LOW : Boolean; + -- Read-only. + GPIO6_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO6_EDGE_LOW : Boolean; + -- Read-only. + GPIO6_EDGE_HIGH : Boolean; + -- Read-only. + GPIO7_LEVEL_LOW : Boolean; + -- Read-only. + GPIO7_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO7_EDGE_LOW : Boolean; + -- Read-only. + GPIO7_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS0_Register use record + GPIO0_LEVEL_LOW at 0 range 0 .. 0; + GPIO0_LEVEL_HIGH at 0 range 1 .. 1; + GPIO0_EDGE_LOW at 0 range 2 .. 2; + GPIO0_EDGE_HIGH at 0 range 3 .. 3; + GPIO1_LEVEL_LOW at 0 range 4 .. 4; + GPIO1_LEVEL_HIGH at 0 range 5 .. 5; + GPIO1_EDGE_LOW at 0 range 6 .. 6; + GPIO1_EDGE_HIGH at 0 range 7 .. 7; + GPIO2_LEVEL_LOW at 0 range 8 .. 8; + GPIO2_LEVEL_HIGH at 0 range 9 .. 9; + GPIO2_EDGE_LOW at 0 range 10 .. 10; + GPIO2_EDGE_HIGH at 0 range 11 .. 11; + GPIO3_LEVEL_LOW at 0 range 12 .. 12; + GPIO3_LEVEL_HIGH at 0 range 13 .. 13; + GPIO3_EDGE_LOW at 0 range 14 .. 14; + GPIO3_EDGE_HIGH at 0 range 15 .. 15; + GPIO4_LEVEL_LOW at 0 range 16 .. 16; + GPIO4_LEVEL_HIGH at 0 range 17 .. 17; + GPIO4_EDGE_LOW at 0 range 18 .. 18; + GPIO4_EDGE_HIGH at 0 range 19 .. 19; + GPIO5_LEVEL_LOW at 0 range 20 .. 20; + GPIO5_LEVEL_HIGH at 0 range 21 .. 21; + GPIO5_EDGE_LOW at 0 range 22 .. 22; + GPIO5_EDGE_HIGH at 0 range 23 .. 23; + GPIO6_LEVEL_LOW at 0 range 24 .. 24; + GPIO6_LEVEL_HIGH at 0 range 25 .. 25; + GPIO6_EDGE_LOW at 0 range 26 .. 26; + GPIO6_EDGE_HIGH at 0 range 27 .. 27; + GPIO7_LEVEL_LOW at 0 range 28 .. 28; + GPIO7_LEVEL_HIGH at 0 range 29 .. 29; + GPIO7_EDGE_LOW at 0 range 30 .. 30; + GPIO7_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS1_Register is record + -- Read-only. + GPIO8_LEVEL_LOW : Boolean; + -- Read-only. + GPIO8_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO8_EDGE_LOW : Boolean; + -- Read-only. + GPIO8_EDGE_HIGH : Boolean; + -- Read-only. + GPIO9_LEVEL_LOW : Boolean; + -- Read-only. + GPIO9_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO9_EDGE_LOW : Boolean; + -- Read-only. + GPIO9_EDGE_HIGH : Boolean; + -- Read-only. + GPIO10_LEVEL_LOW : Boolean; + -- Read-only. + GPIO10_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO10_EDGE_LOW : Boolean; + -- Read-only. + GPIO10_EDGE_HIGH : Boolean; + -- Read-only. + GPIO11_LEVEL_LOW : Boolean; + -- Read-only. + GPIO11_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO11_EDGE_LOW : Boolean; + -- Read-only. + GPIO11_EDGE_HIGH : Boolean; + -- Read-only. + GPIO12_LEVEL_LOW : Boolean; + -- Read-only. + GPIO12_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO12_EDGE_LOW : Boolean; + -- Read-only. + GPIO12_EDGE_HIGH : Boolean; + -- Read-only. + GPIO13_LEVEL_LOW : Boolean; + -- Read-only. + GPIO13_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO13_EDGE_LOW : Boolean; + -- Read-only. + GPIO13_EDGE_HIGH : Boolean; + -- Read-only. + GPIO14_LEVEL_LOW : Boolean; + -- Read-only. + GPIO14_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO14_EDGE_LOW : Boolean; + -- Read-only. + GPIO14_EDGE_HIGH : Boolean; + -- Read-only. + GPIO15_LEVEL_LOW : Boolean; + -- Read-only. + GPIO15_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO15_EDGE_LOW : Boolean; + -- Read-only. + GPIO15_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS1_Register use record + GPIO8_LEVEL_LOW at 0 range 0 .. 0; + GPIO8_LEVEL_HIGH at 0 range 1 .. 1; + GPIO8_EDGE_LOW at 0 range 2 .. 2; + GPIO8_EDGE_HIGH at 0 range 3 .. 3; + GPIO9_LEVEL_LOW at 0 range 4 .. 4; + GPIO9_LEVEL_HIGH at 0 range 5 .. 5; + GPIO9_EDGE_LOW at 0 range 6 .. 6; + GPIO9_EDGE_HIGH at 0 range 7 .. 7; + GPIO10_LEVEL_LOW at 0 range 8 .. 8; + GPIO10_LEVEL_HIGH at 0 range 9 .. 9; + GPIO10_EDGE_LOW at 0 range 10 .. 10; + GPIO10_EDGE_HIGH at 0 range 11 .. 11; + GPIO11_LEVEL_LOW at 0 range 12 .. 12; + GPIO11_LEVEL_HIGH at 0 range 13 .. 13; + GPIO11_EDGE_LOW at 0 range 14 .. 14; + GPIO11_EDGE_HIGH at 0 range 15 .. 15; + GPIO12_LEVEL_LOW at 0 range 16 .. 16; + GPIO12_LEVEL_HIGH at 0 range 17 .. 17; + GPIO12_EDGE_LOW at 0 range 18 .. 18; + GPIO12_EDGE_HIGH at 0 range 19 .. 19; + GPIO13_LEVEL_LOW at 0 range 20 .. 20; + GPIO13_LEVEL_HIGH at 0 range 21 .. 21; + GPIO13_EDGE_LOW at 0 range 22 .. 22; + GPIO13_EDGE_HIGH at 0 range 23 .. 23; + GPIO14_LEVEL_LOW at 0 range 24 .. 24; + GPIO14_LEVEL_HIGH at 0 range 25 .. 25; + GPIO14_EDGE_LOW at 0 range 26 .. 26; + GPIO14_EDGE_HIGH at 0 range 27 .. 27; + GPIO15_LEVEL_LOW at 0 range 28 .. 28; + GPIO15_LEVEL_HIGH at 0 range 29 .. 29; + GPIO15_EDGE_LOW at 0 range 30 .. 30; + GPIO15_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS2_Register is record + -- Read-only. + GPIO16_LEVEL_LOW : Boolean; + -- Read-only. + GPIO16_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO16_EDGE_LOW : Boolean; + -- Read-only. + GPIO16_EDGE_HIGH : Boolean; + -- Read-only. + GPIO17_LEVEL_LOW : Boolean; + -- Read-only. + GPIO17_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO17_EDGE_LOW : Boolean; + -- Read-only. + GPIO17_EDGE_HIGH : Boolean; + -- Read-only. + GPIO18_LEVEL_LOW : Boolean; + -- Read-only. + GPIO18_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO18_EDGE_LOW : Boolean; + -- Read-only. + GPIO18_EDGE_HIGH : Boolean; + -- Read-only. + GPIO19_LEVEL_LOW : Boolean; + -- Read-only. + GPIO19_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO19_EDGE_LOW : Boolean; + -- Read-only. + GPIO19_EDGE_HIGH : Boolean; + -- Read-only. + GPIO20_LEVEL_LOW : Boolean; + -- Read-only. + GPIO20_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO20_EDGE_LOW : Boolean; + -- Read-only. + GPIO20_EDGE_HIGH : Boolean; + -- Read-only. + GPIO21_LEVEL_LOW : Boolean; + -- Read-only. + GPIO21_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO21_EDGE_LOW : Boolean; + -- Read-only. + GPIO21_EDGE_HIGH : Boolean; + -- Read-only. + GPIO22_LEVEL_LOW : Boolean; + -- Read-only. + GPIO22_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO22_EDGE_LOW : Boolean; + -- Read-only. + GPIO22_EDGE_HIGH : Boolean; + -- Read-only. + GPIO23_LEVEL_LOW : Boolean; + -- Read-only. + GPIO23_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO23_EDGE_LOW : Boolean; + -- Read-only. + GPIO23_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS2_Register use record + GPIO16_LEVEL_LOW at 0 range 0 .. 0; + GPIO16_LEVEL_HIGH at 0 range 1 .. 1; + GPIO16_EDGE_LOW at 0 range 2 .. 2; + GPIO16_EDGE_HIGH at 0 range 3 .. 3; + GPIO17_LEVEL_LOW at 0 range 4 .. 4; + GPIO17_LEVEL_HIGH at 0 range 5 .. 5; + GPIO17_EDGE_LOW at 0 range 6 .. 6; + GPIO17_EDGE_HIGH at 0 range 7 .. 7; + GPIO18_LEVEL_LOW at 0 range 8 .. 8; + GPIO18_LEVEL_HIGH at 0 range 9 .. 9; + GPIO18_EDGE_LOW at 0 range 10 .. 10; + GPIO18_EDGE_HIGH at 0 range 11 .. 11; + GPIO19_LEVEL_LOW at 0 range 12 .. 12; + GPIO19_LEVEL_HIGH at 0 range 13 .. 13; + GPIO19_EDGE_LOW at 0 range 14 .. 14; + GPIO19_EDGE_HIGH at 0 range 15 .. 15; + GPIO20_LEVEL_LOW at 0 range 16 .. 16; + GPIO20_LEVEL_HIGH at 0 range 17 .. 17; + GPIO20_EDGE_LOW at 0 range 18 .. 18; + GPIO20_EDGE_HIGH at 0 range 19 .. 19; + GPIO21_LEVEL_LOW at 0 range 20 .. 20; + GPIO21_LEVEL_HIGH at 0 range 21 .. 21; + GPIO21_EDGE_LOW at 0 range 22 .. 22; + GPIO21_EDGE_HIGH at 0 range 23 .. 23; + GPIO22_LEVEL_LOW at 0 range 24 .. 24; + GPIO22_LEVEL_HIGH at 0 range 25 .. 25; + GPIO22_EDGE_LOW at 0 range 26 .. 26; + GPIO22_EDGE_HIGH at 0 range 27 .. 27; + GPIO23_LEVEL_LOW at 0 range 28 .. 28; + GPIO23_LEVEL_HIGH at 0 range 29 .. 29; + GPIO23_EDGE_LOW at 0 range 30 .. 30; + GPIO23_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS3_Register is record + -- Read-only. + GPIO24_LEVEL_LOW : Boolean; + -- Read-only. + GPIO24_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO24_EDGE_LOW : Boolean; + -- Read-only. + GPIO24_EDGE_HIGH : Boolean; + -- Read-only. + GPIO25_LEVEL_LOW : Boolean; + -- Read-only. + GPIO25_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO25_EDGE_LOW : Boolean; + -- Read-only. + GPIO25_EDGE_HIGH : Boolean; + -- Read-only. + GPIO26_LEVEL_LOW : Boolean; + -- Read-only. + GPIO26_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO26_EDGE_LOW : Boolean; + -- Read-only. + GPIO26_EDGE_HIGH : Boolean; + -- Read-only. + GPIO27_LEVEL_LOW : Boolean; + -- Read-only. + GPIO27_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO27_EDGE_LOW : Boolean; + -- Read-only. + GPIO27_EDGE_HIGH : Boolean; + -- Read-only. + GPIO28_LEVEL_LOW : Boolean; + -- Read-only. + GPIO28_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO28_EDGE_LOW : Boolean; + -- Read-only. + GPIO28_EDGE_HIGH : Boolean; + -- Read-only. + GPIO29_LEVEL_LOW : Boolean; + -- Read-only. + GPIO29_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO29_EDGE_LOW : Boolean; + -- Read-only. + GPIO29_EDGE_HIGH : Boolean; + -- Read-only. + GPIO30_LEVEL_LOW : Boolean; + -- Read-only. + GPIO30_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO30_EDGE_LOW : Boolean; + -- Read-only. + GPIO30_EDGE_HIGH : Boolean; + -- Read-only. + GPIO31_LEVEL_LOW : Boolean; + -- Read-only. + GPIO31_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO31_EDGE_LOW : Boolean; + -- Read-only. + GPIO31_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS3_Register use record + GPIO24_LEVEL_LOW at 0 range 0 .. 0; + GPIO24_LEVEL_HIGH at 0 range 1 .. 1; + GPIO24_EDGE_LOW at 0 range 2 .. 2; + GPIO24_EDGE_HIGH at 0 range 3 .. 3; + GPIO25_LEVEL_LOW at 0 range 4 .. 4; + GPIO25_LEVEL_HIGH at 0 range 5 .. 5; + GPIO25_EDGE_LOW at 0 range 6 .. 6; + GPIO25_EDGE_HIGH at 0 range 7 .. 7; + GPIO26_LEVEL_LOW at 0 range 8 .. 8; + GPIO26_LEVEL_HIGH at 0 range 9 .. 9; + GPIO26_EDGE_LOW at 0 range 10 .. 10; + GPIO26_EDGE_HIGH at 0 range 11 .. 11; + GPIO27_LEVEL_LOW at 0 range 12 .. 12; + GPIO27_LEVEL_HIGH at 0 range 13 .. 13; + GPIO27_EDGE_LOW at 0 range 14 .. 14; + GPIO27_EDGE_HIGH at 0 range 15 .. 15; + GPIO28_LEVEL_LOW at 0 range 16 .. 16; + GPIO28_LEVEL_HIGH at 0 range 17 .. 17; + GPIO28_EDGE_LOW at 0 range 18 .. 18; + GPIO28_EDGE_HIGH at 0 range 19 .. 19; + GPIO29_LEVEL_LOW at 0 range 20 .. 20; + GPIO29_LEVEL_HIGH at 0 range 21 .. 21; + GPIO29_EDGE_LOW at 0 range 22 .. 22; + GPIO29_EDGE_HIGH at 0 range 23 .. 23; + GPIO30_LEVEL_LOW at 0 range 24 .. 24; + GPIO30_LEVEL_HIGH at 0 range 25 .. 25; + GPIO30_EDGE_LOW at 0 range 26 .. 26; + GPIO30_EDGE_HIGH at 0 range 27 .. 27; + GPIO31_LEVEL_LOW at 0 range 28 .. 28; + GPIO31_LEVEL_HIGH at 0 range 29 .. 29; + GPIO31_EDGE_LOW at 0 range 30 .. 30; + GPIO31_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS4_Register is record + -- Read-only. + GPIO32_LEVEL_LOW : Boolean; + -- Read-only. + GPIO32_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO32_EDGE_LOW : Boolean; + -- Read-only. + GPIO32_EDGE_HIGH : Boolean; + -- Read-only. + GPIO33_LEVEL_LOW : Boolean; + -- Read-only. + GPIO33_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO33_EDGE_LOW : Boolean; + -- Read-only. + GPIO33_EDGE_HIGH : Boolean; + -- Read-only. + GPIO34_LEVEL_LOW : Boolean; + -- Read-only. + GPIO34_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO34_EDGE_LOW : Boolean; + -- Read-only. + GPIO34_EDGE_HIGH : Boolean; + -- Read-only. + GPIO35_LEVEL_LOW : Boolean; + -- Read-only. + GPIO35_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO35_EDGE_LOW : Boolean; + -- Read-only. + GPIO35_EDGE_HIGH : Boolean; + -- Read-only. + GPIO36_LEVEL_LOW : Boolean; + -- Read-only. + GPIO36_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO36_EDGE_LOW : Boolean; + -- Read-only. + GPIO36_EDGE_HIGH : Boolean; + -- Read-only. + GPIO37_LEVEL_LOW : Boolean; + -- Read-only. + GPIO37_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO37_EDGE_LOW : Boolean; + -- Read-only. + GPIO37_EDGE_HIGH : Boolean; + -- Read-only. + GPIO38_LEVEL_LOW : Boolean; + -- Read-only. + GPIO38_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO38_EDGE_LOW : Boolean; + -- Read-only. + GPIO38_EDGE_HIGH : Boolean; + -- Read-only. + GPIO39_LEVEL_LOW : Boolean; + -- Read-only. + GPIO39_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO39_EDGE_LOW : Boolean; + -- Read-only. + GPIO39_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS4_Register use record + GPIO32_LEVEL_LOW at 0 range 0 .. 0; + GPIO32_LEVEL_HIGH at 0 range 1 .. 1; + GPIO32_EDGE_LOW at 0 range 2 .. 2; + GPIO32_EDGE_HIGH at 0 range 3 .. 3; + GPIO33_LEVEL_LOW at 0 range 4 .. 4; + GPIO33_LEVEL_HIGH at 0 range 5 .. 5; + GPIO33_EDGE_LOW at 0 range 6 .. 6; + GPIO33_EDGE_HIGH at 0 range 7 .. 7; + GPIO34_LEVEL_LOW at 0 range 8 .. 8; + GPIO34_LEVEL_HIGH at 0 range 9 .. 9; + GPIO34_EDGE_LOW at 0 range 10 .. 10; + GPIO34_EDGE_HIGH at 0 range 11 .. 11; + GPIO35_LEVEL_LOW at 0 range 12 .. 12; + GPIO35_LEVEL_HIGH at 0 range 13 .. 13; + GPIO35_EDGE_LOW at 0 range 14 .. 14; + GPIO35_EDGE_HIGH at 0 range 15 .. 15; + GPIO36_LEVEL_LOW at 0 range 16 .. 16; + GPIO36_LEVEL_HIGH at 0 range 17 .. 17; + GPIO36_EDGE_LOW at 0 range 18 .. 18; + GPIO36_EDGE_HIGH at 0 range 19 .. 19; + GPIO37_LEVEL_LOW at 0 range 20 .. 20; + GPIO37_LEVEL_HIGH at 0 range 21 .. 21; + GPIO37_EDGE_LOW at 0 range 22 .. 22; + GPIO37_EDGE_HIGH at 0 range 23 .. 23; + GPIO38_LEVEL_LOW at 0 range 24 .. 24; + GPIO38_LEVEL_HIGH at 0 range 25 .. 25; + GPIO38_EDGE_LOW at 0 range 26 .. 26; + GPIO38_EDGE_HIGH at 0 range 27 .. 27; + GPIO39_LEVEL_LOW at 0 range 28 .. 28; + GPIO39_LEVEL_HIGH at 0 range 29 .. 29; + GPIO39_EDGE_LOW at 0 range 30 .. 30; + GPIO39_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS5_Register is record + -- Read-only. + GPIO40_LEVEL_LOW : Boolean; + -- Read-only. + GPIO40_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO40_EDGE_LOW : Boolean; + -- Read-only. + GPIO40_EDGE_HIGH : Boolean; + -- Read-only. + GPIO41_LEVEL_LOW : Boolean; + -- Read-only. + GPIO41_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO41_EDGE_LOW : Boolean; + -- Read-only. + GPIO41_EDGE_HIGH : Boolean; + -- Read-only. + GPIO42_LEVEL_LOW : Boolean; + -- Read-only. + GPIO42_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO42_EDGE_LOW : Boolean; + -- Read-only. + GPIO42_EDGE_HIGH : Boolean; + -- Read-only. + GPIO43_LEVEL_LOW : Boolean; + -- Read-only. + GPIO43_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO43_EDGE_LOW : Boolean; + -- Read-only. + GPIO43_EDGE_HIGH : Boolean; + -- Read-only. + GPIO44_LEVEL_LOW : Boolean; + -- Read-only. + GPIO44_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO44_EDGE_LOW : Boolean; + -- Read-only. + GPIO44_EDGE_HIGH : Boolean; + -- Read-only. + GPIO45_LEVEL_LOW : Boolean; + -- Read-only. + GPIO45_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO45_EDGE_LOW : Boolean; + -- Read-only. + GPIO45_EDGE_HIGH : Boolean; + -- Read-only. + GPIO46_LEVEL_LOW : Boolean; + -- Read-only. + GPIO46_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO46_EDGE_LOW : Boolean; + -- Read-only. + GPIO46_EDGE_HIGH : Boolean; + -- Read-only. + GPIO47_LEVEL_LOW : Boolean; + -- Read-only. + GPIO47_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO47_EDGE_LOW : Boolean; + -- Read-only. + GPIO47_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS5_Register use record + GPIO40_LEVEL_LOW at 0 range 0 .. 0; + GPIO40_LEVEL_HIGH at 0 range 1 .. 1; + GPIO40_EDGE_LOW at 0 range 2 .. 2; + GPIO40_EDGE_HIGH at 0 range 3 .. 3; + GPIO41_LEVEL_LOW at 0 range 4 .. 4; + GPIO41_LEVEL_HIGH at 0 range 5 .. 5; + GPIO41_EDGE_LOW at 0 range 6 .. 6; + GPIO41_EDGE_HIGH at 0 range 7 .. 7; + GPIO42_LEVEL_LOW at 0 range 8 .. 8; + GPIO42_LEVEL_HIGH at 0 range 9 .. 9; + GPIO42_EDGE_LOW at 0 range 10 .. 10; + GPIO42_EDGE_HIGH at 0 range 11 .. 11; + GPIO43_LEVEL_LOW at 0 range 12 .. 12; + GPIO43_LEVEL_HIGH at 0 range 13 .. 13; + GPIO43_EDGE_LOW at 0 range 14 .. 14; + GPIO43_EDGE_HIGH at 0 range 15 .. 15; + GPIO44_LEVEL_LOW at 0 range 16 .. 16; + GPIO44_LEVEL_HIGH at 0 range 17 .. 17; + GPIO44_EDGE_LOW at 0 range 18 .. 18; + GPIO44_EDGE_HIGH at 0 range 19 .. 19; + GPIO45_LEVEL_LOW at 0 range 20 .. 20; + GPIO45_LEVEL_HIGH at 0 range 21 .. 21; + GPIO45_EDGE_LOW at 0 range 22 .. 22; + GPIO45_EDGE_HIGH at 0 range 23 .. 23; + GPIO46_LEVEL_LOW at 0 range 24 .. 24; + GPIO46_LEVEL_HIGH at 0 range 25 .. 25; + GPIO46_EDGE_LOW at 0 range 26 .. 26; + GPIO46_EDGE_HIGH at 0 range 27 .. 27; + GPIO47_LEVEL_LOW at 0 range 28 .. 28; + GPIO47_LEVEL_HIGH at 0 range 29 .. 29; + GPIO47_EDGE_LOW at 0 range 30 .. 30; + GPIO47_EDGE_HIGH at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type IO_BANK0_Peripheral is record + GPIO0_STATUS : aliased GPIO0_STATUS_Register; + GPIO0_CTRL : aliased GPIO0_CTRL_Register; + GPIO1_STATUS : aliased GPIO1_STATUS_Register; + GPIO1_CTRL : aliased GPIO1_CTRL_Register; + GPIO2_STATUS : aliased GPIO2_STATUS_Register; + GPIO2_CTRL : aliased GPIO2_CTRL_Register; + GPIO3_STATUS : aliased GPIO3_STATUS_Register; + GPIO3_CTRL : aliased GPIO3_CTRL_Register; + GPIO4_STATUS : aliased GPIO4_STATUS_Register; + GPIO4_CTRL : aliased GPIO4_CTRL_Register; + GPIO5_STATUS : aliased GPIO5_STATUS_Register; + GPIO5_CTRL : aliased GPIO5_CTRL_Register; + GPIO6_STATUS : aliased GPIO6_STATUS_Register; + GPIO6_CTRL : aliased GPIO6_CTRL_Register; + GPIO7_STATUS : aliased GPIO7_STATUS_Register; + GPIO7_CTRL : aliased GPIO7_CTRL_Register; + GPIO8_STATUS : aliased GPIO8_STATUS_Register; + GPIO8_CTRL : aliased GPIO8_CTRL_Register; + GPIO9_STATUS : aliased GPIO9_STATUS_Register; + GPIO9_CTRL : aliased GPIO9_CTRL_Register; + GPIO10_STATUS : aliased GPIO10_STATUS_Register; + GPIO10_CTRL : aliased GPIO10_CTRL_Register; + GPIO11_STATUS : aliased GPIO11_STATUS_Register; + GPIO11_CTRL : aliased GPIO11_CTRL_Register; + GPIO12_STATUS : aliased GPIO12_STATUS_Register; + GPIO12_CTRL : aliased GPIO12_CTRL_Register; + GPIO13_STATUS : aliased GPIO13_STATUS_Register; + GPIO13_CTRL : aliased GPIO13_CTRL_Register; + GPIO14_STATUS : aliased GPIO14_STATUS_Register; + GPIO14_CTRL : aliased GPIO14_CTRL_Register; + GPIO15_STATUS : aliased GPIO15_STATUS_Register; + GPIO15_CTRL : aliased GPIO15_CTRL_Register; + GPIO16_STATUS : aliased GPIO16_STATUS_Register; + GPIO16_CTRL : aliased GPIO16_CTRL_Register; + GPIO17_STATUS : aliased GPIO17_STATUS_Register; + GPIO17_CTRL : aliased GPIO17_CTRL_Register; + GPIO18_STATUS : aliased GPIO18_STATUS_Register; + GPIO18_CTRL : aliased GPIO18_CTRL_Register; + GPIO19_STATUS : aliased GPIO19_STATUS_Register; + GPIO19_CTRL : aliased GPIO19_CTRL_Register; + GPIO20_STATUS : aliased GPIO20_STATUS_Register; + GPIO20_CTRL : aliased GPIO20_CTRL_Register; + GPIO21_STATUS : aliased GPIO21_STATUS_Register; + GPIO21_CTRL : aliased GPIO21_CTRL_Register; + GPIO22_STATUS : aliased GPIO22_STATUS_Register; + GPIO22_CTRL : aliased GPIO22_CTRL_Register; + GPIO23_STATUS : aliased GPIO23_STATUS_Register; + GPIO23_CTRL : aliased GPIO23_CTRL_Register; + GPIO24_STATUS : aliased GPIO24_STATUS_Register; + GPIO24_CTRL : aliased GPIO24_CTRL_Register; + GPIO25_STATUS : aliased GPIO25_STATUS_Register; + GPIO25_CTRL : aliased GPIO25_CTRL_Register; + GPIO26_STATUS : aliased GPIO26_STATUS_Register; + GPIO26_CTRL : aliased GPIO26_CTRL_Register; + GPIO27_STATUS : aliased GPIO27_STATUS_Register; + GPIO27_CTRL : aliased GPIO27_CTRL_Register; + GPIO28_STATUS : aliased GPIO28_STATUS_Register; + GPIO28_CTRL : aliased GPIO28_CTRL_Register; + GPIO29_STATUS : aliased GPIO29_STATUS_Register; + GPIO29_CTRL : aliased GPIO29_CTRL_Register; + GPIO30_STATUS : aliased GPIO30_STATUS_Register; + GPIO30_CTRL : aliased GPIO30_CTRL_Register; + GPIO31_STATUS : aliased GPIO31_STATUS_Register; + GPIO31_CTRL : aliased GPIO31_CTRL_Register; + GPIO32_STATUS : aliased GPIO32_STATUS_Register; + GPIO32_CTRL : aliased GPIO32_CTRL_Register; + GPIO33_STATUS : aliased GPIO33_STATUS_Register; + GPIO33_CTRL : aliased GPIO33_CTRL_Register; + GPIO34_STATUS : aliased GPIO34_STATUS_Register; + GPIO34_CTRL : aliased GPIO34_CTRL_Register; + GPIO35_STATUS : aliased GPIO35_STATUS_Register; + GPIO35_CTRL : aliased GPIO35_CTRL_Register; + GPIO36_STATUS : aliased GPIO36_STATUS_Register; + GPIO36_CTRL : aliased GPIO36_CTRL_Register; + GPIO37_STATUS : aliased GPIO37_STATUS_Register; + GPIO37_CTRL : aliased GPIO37_CTRL_Register; + GPIO38_STATUS : aliased GPIO38_STATUS_Register; + GPIO38_CTRL : aliased GPIO38_CTRL_Register; + GPIO39_STATUS : aliased GPIO39_STATUS_Register; + GPIO39_CTRL : aliased GPIO39_CTRL_Register; + GPIO40_STATUS : aliased GPIO40_STATUS_Register; + GPIO40_CTRL : aliased GPIO40_CTRL_Register; + GPIO41_STATUS : aliased GPIO41_STATUS_Register; + GPIO41_CTRL : aliased GPIO41_CTRL_Register; + GPIO42_STATUS : aliased GPIO42_STATUS_Register; + GPIO42_CTRL : aliased GPIO42_CTRL_Register; + GPIO43_STATUS : aliased GPIO43_STATUS_Register; + GPIO43_CTRL : aliased GPIO43_CTRL_Register; + GPIO44_STATUS : aliased GPIO44_STATUS_Register; + GPIO44_CTRL : aliased GPIO44_CTRL_Register; + GPIO45_STATUS : aliased GPIO45_STATUS_Register; + GPIO45_CTRL : aliased GPIO45_CTRL_Register; + GPIO46_STATUS : aliased GPIO46_STATUS_Register; + GPIO46_CTRL : aliased GPIO46_CTRL_Register; + GPIO47_STATUS : aliased GPIO47_STATUS_Register; + GPIO47_CTRL : aliased GPIO47_CTRL_Register; + IRQSUMMARY_PROC0_SECURE0 : aliased IRQSUMMARY_PROC0_SECURE0_Register; + IRQSUMMARY_PROC0_SECURE1 : aliased IRQSUMMARY_PROC0_SECURE1_Register; + IRQSUMMARY_PROC0_NONSECURE0 : aliased IRQSUMMARY_PROC0_NONSECURE0_Register; + IRQSUMMARY_PROC0_NONSECURE1 : aliased IRQSUMMARY_PROC0_NONSECURE1_Register; + IRQSUMMARY_PROC1_SECURE0 : aliased IRQSUMMARY_PROC1_SECURE0_Register; + IRQSUMMARY_PROC1_SECURE1 : aliased IRQSUMMARY_PROC1_SECURE1_Register; + IRQSUMMARY_PROC1_NONSECURE0 : aliased IRQSUMMARY_PROC1_NONSECURE0_Register; + IRQSUMMARY_PROC1_NONSECURE1 : aliased IRQSUMMARY_PROC1_NONSECURE1_Register; + IRQSUMMARY_DORMANT_WAKE_SECURE0 : aliased IRQSUMMARY_DORMANT_WAKE_SECURE0_Register; + IRQSUMMARY_DORMANT_WAKE_SECURE1 : aliased IRQSUMMARY_DORMANT_WAKE_SECURE1_Register; + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 : aliased IRQSUMMARY_DORMANT_WAKE_NONSECURE0_Register; + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 : aliased IRQSUMMARY_DORMANT_WAKE_NONSECURE1_Register; + -- Raw Interrupts + INTR0 : aliased INTR0_Register; + -- Raw Interrupts + INTR1 : aliased INTR1_Register; + -- Raw Interrupts + INTR2 : aliased INTR2_Register; + -- Raw Interrupts + INTR3 : aliased INTR3_Register; + -- Raw Interrupts + INTR4 : aliased INTR4_Register; + -- Raw Interrupts + INTR5 : aliased INTR5_Register; + -- Interrupt Enable for proc0 + PROC0_INTE0 : aliased PROC0_INTE0_Register; + -- Interrupt Enable for proc0 + PROC0_INTE1 : aliased PROC0_INTE1_Register; + -- Interrupt Enable for proc0 + PROC0_INTE2 : aliased PROC0_INTE2_Register; + -- Interrupt Enable for proc0 + PROC0_INTE3 : aliased PROC0_INTE3_Register; + -- Interrupt Enable for proc0 + PROC0_INTE4 : aliased PROC0_INTE4_Register; + -- Interrupt Enable for proc0 + PROC0_INTE5 : aliased PROC0_INTE5_Register; + -- Interrupt Force for proc0 + PROC0_INTF0 : aliased PROC0_INTF0_Register; + -- Interrupt Force for proc0 + PROC0_INTF1 : aliased PROC0_INTF1_Register; + -- Interrupt Force for proc0 + PROC0_INTF2 : aliased PROC0_INTF2_Register; + -- Interrupt Force for proc0 + PROC0_INTF3 : aliased PROC0_INTF3_Register; + -- Interrupt Force for proc0 + PROC0_INTF4 : aliased PROC0_INTF4_Register; + -- Interrupt Force for proc0 + PROC0_INTF5 : aliased PROC0_INTF5_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS0 : aliased PROC0_INTS0_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS1 : aliased PROC0_INTS1_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS2 : aliased PROC0_INTS2_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS3 : aliased PROC0_INTS3_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS4 : aliased PROC0_INTS4_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS5 : aliased PROC0_INTS5_Register; + -- Interrupt Enable for proc1 + PROC1_INTE0 : aliased PROC1_INTE0_Register; + -- Interrupt Enable for proc1 + PROC1_INTE1 : aliased PROC1_INTE1_Register; + -- Interrupt Enable for proc1 + PROC1_INTE2 : aliased PROC1_INTE2_Register; + -- Interrupt Enable for proc1 + PROC1_INTE3 : aliased PROC1_INTE3_Register; + -- Interrupt Enable for proc1 + PROC1_INTE4 : aliased PROC1_INTE4_Register; + -- Interrupt Enable for proc1 + PROC1_INTE5 : aliased PROC1_INTE5_Register; + -- Interrupt Force for proc1 + PROC1_INTF0 : aliased PROC1_INTF0_Register; + -- Interrupt Force for proc1 + PROC1_INTF1 : aliased PROC1_INTF1_Register; + -- Interrupt Force for proc1 + PROC1_INTF2 : aliased PROC1_INTF2_Register; + -- Interrupt Force for proc1 + PROC1_INTF3 : aliased PROC1_INTF3_Register; + -- Interrupt Force for proc1 + PROC1_INTF4 : aliased PROC1_INTF4_Register; + -- Interrupt Force for proc1 + PROC1_INTF5 : aliased PROC1_INTF5_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS0 : aliased PROC1_INTS0_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS1 : aliased PROC1_INTS1_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS2 : aliased PROC1_INTS2_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS3 : aliased PROC1_INTS3_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS4 : aliased PROC1_INTS4_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS5 : aliased PROC1_INTS5_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE0 : aliased DORMANT_WAKE_INTE0_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE1 : aliased DORMANT_WAKE_INTE1_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE2 : aliased DORMANT_WAKE_INTE2_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE3 : aliased DORMANT_WAKE_INTE3_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE4 : aliased DORMANT_WAKE_INTE4_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE5 : aliased DORMANT_WAKE_INTE5_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF0 : aliased DORMANT_WAKE_INTF0_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF1 : aliased DORMANT_WAKE_INTF1_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF2 : aliased DORMANT_WAKE_INTF2_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF3 : aliased DORMANT_WAKE_INTF3_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF4 : aliased DORMANT_WAKE_INTF4_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF5 : aliased DORMANT_WAKE_INTF5_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS0 : aliased DORMANT_WAKE_INTS0_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS1 : aliased DORMANT_WAKE_INTS1_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS2 : aliased DORMANT_WAKE_INTS2_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS3 : aliased DORMANT_WAKE_INTS3_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS4 : aliased DORMANT_WAKE_INTS4_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS5 : aliased DORMANT_WAKE_INTS5_Register; + end record + with Volatile; + + for IO_BANK0_Peripheral use record + GPIO0_STATUS at 16#0# range 0 .. 31; + GPIO0_CTRL at 16#4# range 0 .. 31; + GPIO1_STATUS at 16#8# range 0 .. 31; + GPIO1_CTRL at 16#C# range 0 .. 31; + GPIO2_STATUS at 16#10# range 0 .. 31; + GPIO2_CTRL at 16#14# range 0 .. 31; + GPIO3_STATUS at 16#18# range 0 .. 31; + GPIO3_CTRL at 16#1C# range 0 .. 31; + GPIO4_STATUS at 16#20# range 0 .. 31; + GPIO4_CTRL at 16#24# range 0 .. 31; + GPIO5_STATUS at 16#28# range 0 .. 31; + GPIO5_CTRL at 16#2C# range 0 .. 31; + GPIO6_STATUS at 16#30# range 0 .. 31; + GPIO6_CTRL at 16#34# range 0 .. 31; + GPIO7_STATUS at 16#38# range 0 .. 31; + GPIO7_CTRL at 16#3C# range 0 .. 31; + GPIO8_STATUS at 16#40# range 0 .. 31; + GPIO8_CTRL at 16#44# range 0 .. 31; + GPIO9_STATUS at 16#48# range 0 .. 31; + GPIO9_CTRL at 16#4C# range 0 .. 31; + GPIO10_STATUS at 16#50# range 0 .. 31; + GPIO10_CTRL at 16#54# range 0 .. 31; + GPIO11_STATUS at 16#58# range 0 .. 31; + GPIO11_CTRL at 16#5C# range 0 .. 31; + GPIO12_STATUS at 16#60# range 0 .. 31; + GPIO12_CTRL at 16#64# range 0 .. 31; + GPIO13_STATUS at 16#68# range 0 .. 31; + GPIO13_CTRL at 16#6C# range 0 .. 31; + GPIO14_STATUS at 16#70# range 0 .. 31; + GPIO14_CTRL at 16#74# range 0 .. 31; + GPIO15_STATUS at 16#78# range 0 .. 31; + GPIO15_CTRL at 16#7C# range 0 .. 31; + GPIO16_STATUS at 16#80# range 0 .. 31; + GPIO16_CTRL at 16#84# range 0 .. 31; + GPIO17_STATUS at 16#88# range 0 .. 31; + GPIO17_CTRL at 16#8C# range 0 .. 31; + GPIO18_STATUS at 16#90# range 0 .. 31; + GPIO18_CTRL at 16#94# range 0 .. 31; + GPIO19_STATUS at 16#98# range 0 .. 31; + GPIO19_CTRL at 16#9C# range 0 .. 31; + GPIO20_STATUS at 16#A0# range 0 .. 31; + GPIO20_CTRL at 16#A4# range 0 .. 31; + GPIO21_STATUS at 16#A8# range 0 .. 31; + GPIO21_CTRL at 16#AC# range 0 .. 31; + GPIO22_STATUS at 16#B0# range 0 .. 31; + GPIO22_CTRL at 16#B4# range 0 .. 31; + GPIO23_STATUS at 16#B8# range 0 .. 31; + GPIO23_CTRL at 16#BC# range 0 .. 31; + GPIO24_STATUS at 16#C0# range 0 .. 31; + GPIO24_CTRL at 16#C4# range 0 .. 31; + GPIO25_STATUS at 16#C8# range 0 .. 31; + GPIO25_CTRL at 16#CC# range 0 .. 31; + GPIO26_STATUS at 16#D0# range 0 .. 31; + GPIO26_CTRL at 16#D4# range 0 .. 31; + GPIO27_STATUS at 16#D8# range 0 .. 31; + GPIO27_CTRL at 16#DC# range 0 .. 31; + GPIO28_STATUS at 16#E0# range 0 .. 31; + GPIO28_CTRL at 16#E4# range 0 .. 31; + GPIO29_STATUS at 16#E8# range 0 .. 31; + GPIO29_CTRL at 16#EC# range 0 .. 31; + GPIO30_STATUS at 16#F0# range 0 .. 31; + GPIO30_CTRL at 16#F4# range 0 .. 31; + GPIO31_STATUS at 16#F8# range 0 .. 31; + GPIO31_CTRL at 16#FC# range 0 .. 31; + GPIO32_STATUS at 16#100# range 0 .. 31; + GPIO32_CTRL at 16#104# range 0 .. 31; + GPIO33_STATUS at 16#108# range 0 .. 31; + GPIO33_CTRL at 16#10C# range 0 .. 31; + GPIO34_STATUS at 16#110# range 0 .. 31; + GPIO34_CTRL at 16#114# range 0 .. 31; + GPIO35_STATUS at 16#118# range 0 .. 31; + GPIO35_CTRL at 16#11C# range 0 .. 31; + GPIO36_STATUS at 16#120# range 0 .. 31; + GPIO36_CTRL at 16#124# range 0 .. 31; + GPIO37_STATUS at 16#128# range 0 .. 31; + GPIO37_CTRL at 16#12C# range 0 .. 31; + GPIO38_STATUS at 16#130# range 0 .. 31; + GPIO38_CTRL at 16#134# range 0 .. 31; + GPIO39_STATUS at 16#138# range 0 .. 31; + GPIO39_CTRL at 16#13C# range 0 .. 31; + GPIO40_STATUS at 16#140# range 0 .. 31; + GPIO40_CTRL at 16#144# range 0 .. 31; + GPIO41_STATUS at 16#148# range 0 .. 31; + GPIO41_CTRL at 16#14C# range 0 .. 31; + GPIO42_STATUS at 16#150# range 0 .. 31; + GPIO42_CTRL at 16#154# range 0 .. 31; + GPIO43_STATUS at 16#158# range 0 .. 31; + GPIO43_CTRL at 16#15C# range 0 .. 31; + GPIO44_STATUS at 16#160# range 0 .. 31; + GPIO44_CTRL at 16#164# range 0 .. 31; + GPIO45_STATUS at 16#168# range 0 .. 31; + GPIO45_CTRL at 16#16C# range 0 .. 31; + GPIO46_STATUS at 16#170# range 0 .. 31; + GPIO46_CTRL at 16#174# range 0 .. 31; + GPIO47_STATUS at 16#178# range 0 .. 31; + GPIO47_CTRL at 16#17C# range 0 .. 31; + IRQSUMMARY_PROC0_SECURE0 at 16#200# range 0 .. 31; + IRQSUMMARY_PROC0_SECURE1 at 16#204# range 0 .. 31; + IRQSUMMARY_PROC0_NONSECURE0 at 16#208# range 0 .. 31; + IRQSUMMARY_PROC0_NONSECURE1 at 16#20C# range 0 .. 31; + IRQSUMMARY_PROC1_SECURE0 at 16#210# range 0 .. 31; + IRQSUMMARY_PROC1_SECURE1 at 16#214# range 0 .. 31; + IRQSUMMARY_PROC1_NONSECURE0 at 16#218# range 0 .. 31; + IRQSUMMARY_PROC1_NONSECURE1 at 16#21C# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_SECURE0 at 16#220# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_SECURE1 at 16#224# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 at 16#228# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 at 16#22C# range 0 .. 31; + INTR0 at 16#230# range 0 .. 31; + INTR1 at 16#234# range 0 .. 31; + INTR2 at 16#238# range 0 .. 31; + INTR3 at 16#23C# range 0 .. 31; + INTR4 at 16#240# range 0 .. 31; + INTR5 at 16#244# range 0 .. 31; + PROC0_INTE0 at 16#248# range 0 .. 31; + PROC0_INTE1 at 16#24C# range 0 .. 31; + PROC0_INTE2 at 16#250# range 0 .. 31; + PROC0_INTE3 at 16#254# range 0 .. 31; + PROC0_INTE4 at 16#258# range 0 .. 31; + PROC0_INTE5 at 16#25C# range 0 .. 31; + PROC0_INTF0 at 16#260# range 0 .. 31; + PROC0_INTF1 at 16#264# range 0 .. 31; + PROC0_INTF2 at 16#268# range 0 .. 31; + PROC0_INTF3 at 16#26C# range 0 .. 31; + PROC0_INTF4 at 16#270# range 0 .. 31; + PROC0_INTF5 at 16#274# range 0 .. 31; + PROC0_INTS0 at 16#278# range 0 .. 31; + PROC0_INTS1 at 16#27C# range 0 .. 31; + PROC0_INTS2 at 16#280# range 0 .. 31; + PROC0_INTS3 at 16#284# range 0 .. 31; + PROC0_INTS4 at 16#288# range 0 .. 31; + PROC0_INTS5 at 16#28C# range 0 .. 31; + PROC1_INTE0 at 16#290# range 0 .. 31; + PROC1_INTE1 at 16#294# range 0 .. 31; + PROC1_INTE2 at 16#298# range 0 .. 31; + PROC1_INTE3 at 16#29C# range 0 .. 31; + PROC1_INTE4 at 16#2A0# range 0 .. 31; + PROC1_INTE5 at 16#2A4# range 0 .. 31; + PROC1_INTF0 at 16#2A8# range 0 .. 31; + PROC1_INTF1 at 16#2AC# range 0 .. 31; + PROC1_INTF2 at 16#2B0# range 0 .. 31; + PROC1_INTF3 at 16#2B4# range 0 .. 31; + PROC1_INTF4 at 16#2B8# range 0 .. 31; + PROC1_INTF5 at 16#2BC# range 0 .. 31; + PROC1_INTS0 at 16#2C0# range 0 .. 31; + PROC1_INTS1 at 16#2C4# range 0 .. 31; + PROC1_INTS2 at 16#2C8# range 0 .. 31; + PROC1_INTS3 at 16#2CC# range 0 .. 31; + PROC1_INTS4 at 16#2D0# range 0 .. 31; + PROC1_INTS5 at 16#2D4# range 0 .. 31; + DORMANT_WAKE_INTE0 at 16#2D8# range 0 .. 31; + DORMANT_WAKE_INTE1 at 16#2DC# range 0 .. 31; + DORMANT_WAKE_INTE2 at 16#2E0# range 0 .. 31; + DORMANT_WAKE_INTE3 at 16#2E4# range 0 .. 31; + DORMANT_WAKE_INTE4 at 16#2E8# range 0 .. 31; + DORMANT_WAKE_INTE5 at 16#2EC# range 0 .. 31; + DORMANT_WAKE_INTF0 at 16#2F0# range 0 .. 31; + DORMANT_WAKE_INTF1 at 16#2F4# range 0 .. 31; + DORMANT_WAKE_INTF2 at 16#2F8# range 0 .. 31; + DORMANT_WAKE_INTF3 at 16#2FC# range 0 .. 31; + DORMANT_WAKE_INTF4 at 16#300# range 0 .. 31; + DORMANT_WAKE_INTF5 at 16#304# range 0 .. 31; + DORMANT_WAKE_INTS0 at 16#308# range 0 .. 31; + DORMANT_WAKE_INTS1 at 16#30C# range 0 .. 31; + DORMANT_WAKE_INTS2 at 16#310# range 0 .. 31; + DORMANT_WAKE_INTS3 at 16#314# range 0 .. 31; + DORMANT_WAKE_INTS4 at 16#318# range 0 .. 31; + DORMANT_WAKE_INTS5 at 16#31C# range 0 .. 31; + end record; + + IO_BANK0_Periph : aliased IO_BANK0_Peripheral + with Import, Address => IO_BANK0_Base; + +end RP2350_SVD.IO_BANK0; diff --git a/src/svd/rp2350_svd-io_qspi.ads b/src/svd/rp2350_svd-io_qspi.ads new file mode 100644 index 0000000..c8e9d6e --- /dev/null +++ b/src/svd/rp2350_svd-io_qspi.ads @@ -0,0 +1,2475 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.IO_QSPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type USBPHY_DP_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DP_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type USBPHY_DP_CTRL_FUNCSEL_Field is + (uart1_tx, + i2c0_sda, + siob_proc_56, + null_k) + with Size => 5; + for USBPHY_DP_CTRL_FUNCSEL_Field use + (uart1_tx => 2, + i2c0_sda => 3, + siob_proc_56 => 5, + null_k => 31); + + type USBPHY_DP_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for USBPHY_DP_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DP_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for USBPHY_DP_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type USBPHY_DP_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for USBPHY_DP_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DP_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for USBPHY_DP_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DP_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : USBPHY_DP_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : USBPHY_DP_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : USBPHY_DP_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : USBPHY_DP_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : USBPHY_DP_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DP_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type USBPHY_DM_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DM_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type USBPHY_DM_CTRL_FUNCSEL_Field is + (uart1_rx, + i2c0_scl, + siob_proc_57, + null_k) + with Size => 5; + for USBPHY_DM_CTRL_FUNCSEL_Field use + (uart1_rx => 2, + i2c0_scl => 3, + siob_proc_57 => 5, + null_k => 31); + + type USBPHY_DM_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for USBPHY_DM_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DM_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for USBPHY_DM_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type USBPHY_DM_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for USBPHY_DM_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DM_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for USBPHY_DM_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type USBPHY_DM_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : USBPHY_DM_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : USBPHY_DM_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : USBPHY_DM_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : USBPHY_DM_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : USBPHY_DM_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DM_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SCLK_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SCLK_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SCLK_CTRL_FUNCSEL_Field is + (xip_sclk, + uart1_cts, + i2c1_sda, + siob_proc_58, + uart1_tx, + null_k) + with Size => 5; + for GPIO_QSPI_SCLK_CTRL_FUNCSEL_Field use + (xip_sclk => 0, + uart1_cts => 2, + i2c1_sda => 3, + siob_proc_58 => 5, + uart1_tx => 11, + null_k => 31); + + type GPIO_QSPI_SCLK_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SCLK_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SCLK_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SCLK_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SCLK_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SCLK_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SCLK_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SCLK_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SCLK_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SCLK_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SCLK_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SCLK_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SCLK_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SCLK_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SCLK_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SS_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SS_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SS_CTRL_FUNCSEL_Field is + (xip_ss_n_0, + uart1_rts, + i2c1_scl, + siob_proc_59, + uart1_rx, + null_k) + with Size => 5; + for GPIO_QSPI_SS_CTRL_FUNCSEL_Field use + (xip_ss_n_0 => 0, + uart1_rts => 2, + i2c1_scl => 3, + siob_proc_59 => 5, + uart1_rx => 11, + null_k => 31); + + type GPIO_QSPI_SS_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SS_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SS_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SS_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SS_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SS_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SS_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SS_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SS_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SS_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SS_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SS_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SS_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SS_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SS_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SD0_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD0_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SD0_CTRL_FUNCSEL_Field is + (xip_sd0, + uart0_tx, + i2c0_sda, + siob_proc_60, + null_k) + with Size => 5; + for GPIO_QSPI_SD0_CTRL_FUNCSEL_Field use + (xip_sd0 => 0, + uart0_tx => 2, + i2c0_sda => 3, + siob_proc_60 => 5, + null_k => 31); + + type GPIO_QSPI_SD0_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SD0_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD0_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SD0_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SD0_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SD0_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD0_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SD0_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD0_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SD0_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SD0_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SD0_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SD0_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SD0_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD0_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SD1_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD1_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SD1_CTRL_FUNCSEL_Field is + (xip_sd1, + uart0_rx, + i2c0_scl, + siob_proc_61, + null_k) + with Size => 5; + for GPIO_QSPI_SD1_CTRL_FUNCSEL_Field use + (xip_sd1 => 0, + uart0_rx => 2, + i2c0_scl => 3, + siob_proc_61 => 5, + null_k => 31); + + type GPIO_QSPI_SD1_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SD1_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD1_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SD1_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SD1_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SD1_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD1_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SD1_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD1_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SD1_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SD1_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SD1_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SD1_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SD1_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD1_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SD2_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD2_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SD2_CTRL_FUNCSEL_Field is + (xip_sd2, + uart0_cts, + i2c1_sda, + siob_proc_62, + uart0_tx, + null_k) + with Size => 5; + for GPIO_QSPI_SD2_CTRL_FUNCSEL_Field use + (xip_sd2 => 0, + uart0_cts => 2, + i2c1_sda => 3, + siob_proc_62 => 5, + uart0_tx => 11, + null_k => 31); + + type GPIO_QSPI_SD2_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SD2_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD2_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SD2_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SD2_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SD2_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD2_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SD2_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD2_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SD2_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SD2_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SD2_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SD2_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SD2_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD2_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + type GPIO_QSPI_SD3_STATUS_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9; + -- Read-only. output signal to pad after register override is applied + OUTTOPAD : Boolean; + -- unspecified + Reserved_10_12 : HAL.UInt3; + -- Read-only. output enable to pad after register override is applied + OETOPAD : Boolean; + -- unspecified + Reserved_14_16 : HAL.UInt3; + -- Read-only. input signal from pad, before filtering and override are + -- applied + INFROMPAD : Boolean; + -- unspecified + Reserved_18_25 : HAL.UInt8; + -- Read-only. interrupt to processors, after override is applied + IRQTOPROC : Boolean; + -- unspecified + Reserved_27_31 : HAL.UInt5; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD3_STATUS_Register use record + Reserved_0_8 at 0 range 0 .. 8; + OUTTOPAD at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + OETOPAD at 0 range 13 .. 13; + Reserved_14_16 at 0 range 14 .. 16; + INFROMPAD at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + IRQTOPROC at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + type GPIO_QSPI_SD3_CTRL_FUNCSEL_Field is + (xip_sd3, + uart0_rts, + i2c1_scl, + siob_proc_63, + uart0_rx, + null_k) + with Size => 5; + for GPIO_QSPI_SD3_CTRL_FUNCSEL_Field use + (xip_sd3 => 0, + uart0_rts => 2, + i2c1_scl => 3, + siob_proc_63 => 5, + uart0_rx => 11, + null_k => 31); + + type GPIO_QSPI_SD3_CTRL_OUTOVER_Field is + (-- drive output from peripheral signal selected by funcsel + NORMAL, + -- drive output from inverse of peripheral signal selected by funcsel + INVERT, + -- drive output low + LOW, + -- drive output high + HIGH) + with Size => 2; + for GPIO_QSPI_SD3_CTRL_OUTOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD3_CTRL_OEOVER_Field is + (-- drive output enable from peripheral signal selected by funcsel + NORMAL, + -- drive output enable from inverse of peripheral signal selected by funcsel + INVERT, + -- disable output + DISABLE, + -- enable output + ENABLE) + with Size => 2; + for GPIO_QSPI_SD3_CTRL_OEOVER_Field use + (NORMAL => 0, + INVERT => 1, + DISABLE => 2, + ENABLE => 3); + + type GPIO_QSPI_SD3_CTRL_INOVER_Field is + (-- don't invert the peri input + NORMAL, + -- invert the peri input + INVERT, + -- drive peri input low + LOW, + -- drive peri input high + HIGH) + with Size => 2; + for GPIO_QSPI_SD3_CTRL_INOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD3_CTRL_IRQOVER_Field is + (-- don't invert the interrupt + NORMAL, + -- invert the interrupt + INVERT, + -- drive interrupt low + LOW, + -- drive interrupt high + HIGH) + with Size => 2; + for GPIO_QSPI_SD3_CTRL_IRQOVER_Field use + (NORMAL => 0, + INVERT => 1, + LOW => 2, + HIGH => 3); + + type GPIO_QSPI_SD3_CTRL_Register is record + -- 0-31 -> selects pin function according to the gpio table 31 == NULL + FUNCSEL : GPIO_QSPI_SD3_CTRL_FUNCSEL_Field := + RP2350_SVD.IO_QSPI.null_k; + -- unspecified + Reserved_5_11 : HAL.UInt7 := 16#0#; + OUTOVER : GPIO_QSPI_SD3_CTRL_OUTOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + OEOVER : GPIO_QSPI_SD3_CTRL_OEOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + INOVER : GPIO_QSPI_SD3_CTRL_INOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_18_27 : HAL.UInt10 := 16#0#; + IRQOVER : GPIO_QSPI_SD3_CTRL_IRQOVER_Field := + RP2350_SVD.IO_QSPI.NORMAL; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD3_CTRL_Register use record + FUNCSEL at 0 range 0 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + OUTOVER at 0 range 12 .. 13; + OEOVER at 0 range 14 .. 15; + INOVER at 0 range 16 .. 17; + Reserved_18_27 at 0 range 18 .. 27; + IRQOVER at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD array + type IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD + type IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_PROC0_SECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_SECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD array + type IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD + type IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_PROC0_NONSECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC0_NONSECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD array + type IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD + type IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_PROC1_SECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_SECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD array + type IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD + type IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_PROC1_NONSECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_PROC1_NONSECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD array + type IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD + type IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_DORMANT_WAKE_SECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_SECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD array + type IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD_Field_Array is array (0 .. 3) + of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD + type IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GPIO_QSPI_SD as a value + Val : HAL.UInt4; + when True => + -- GPIO_QSPI_SD as an array + Arr : IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + type IRQSUMMARY_DORMANT_WAKE_NONSECURE_Register is record + -- Read-only. + USBPHY_DP : Boolean; + -- Read-only. + USBPHY_DM : Boolean; + -- Read-only. + GPIO_QSPI_SCLK : Boolean; + -- Read-only. + GPIO_QSPI_SS : Boolean; + -- Read-only. + GPIO_QSPI_SD : IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQSUMMARY_DORMANT_WAKE_NONSECURE_Register use record + USBPHY_DP at 0 range 0 .. 0; + USBPHY_DM at 0 range 1 .. 1; + GPIO_QSPI_SCLK at 0 range 2 .. 2; + GPIO_QSPI_SS at 0 range 3 .. 3; + GPIO_QSPI_SD at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + USBPHY_DP_LEVEL_LOW : Boolean := False; + -- Read-only. + USBPHY_DP_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + USBPHY_DP_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + USBPHY_DP_EDGE_HIGH : Boolean := False; + -- Read-only. + USBPHY_DM_LEVEL_LOW : Boolean := False; + -- Read-only. + USBPHY_DM_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + USBPHY_DM_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + USBPHY_DM_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc0 + type PROC0_INTE_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTE_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc0 + type PROC0_INTF_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTF_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc0 + type PROC0_INTS_Register is record + -- Read-only. + USBPHY_DP_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DP_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DP_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DP_EDGE_HIGH : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DM_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DM_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_INTS_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for proc1 + type PROC1_INTE_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTE_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for proc1 + type PROC1_INTF_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTF_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for proc1 + type PROC1_INTS_Register is record + -- Read-only. + USBPHY_DP_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DP_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DP_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DP_EDGE_HIGH : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DM_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DM_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_INTS_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Enable for dormant_wake + type DORMANT_WAKE_INTE_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTE_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt Force for dormant_wake + type DORMANT_WAKE_INTF_Register is record + USBPHY_DP_LEVEL_LOW : Boolean := False; + USBPHY_DP_LEVEL_HIGH : Boolean := False; + USBPHY_DP_EDGE_LOW : Boolean := False; + USBPHY_DP_EDGE_HIGH : Boolean := False; + USBPHY_DM_LEVEL_LOW : Boolean := False; + USBPHY_DM_LEVEL_HIGH : Boolean := False; + USBPHY_DM_EDGE_LOW : Boolean := False; + USBPHY_DM_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SCLK_EDGE_LOW : Boolean := False; + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SS_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SS_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SS_EDGE_LOW : Boolean := False; + GPIO_QSPI_SS_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD0_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD0_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD0_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD1_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD1_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD1_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD2_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD2_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD2_EDGE_HIGH : Boolean := False; + GPIO_QSPI_SD3_LEVEL_LOW : Boolean := False; + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean := False; + GPIO_QSPI_SD3_EDGE_LOW : Boolean := False; + GPIO_QSPI_SD3_EDGE_HIGH : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTF_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + -- Interrupt status after masking & forcing for dormant_wake + type DORMANT_WAKE_INTS_Register is record + -- Read-only. + USBPHY_DP_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DP_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DP_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DP_EDGE_HIGH : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_LOW : Boolean; + -- Read-only. + USBPHY_DM_LEVEL_HIGH : Boolean; + -- Read-only. + USBPHY_DM_EDGE_LOW : Boolean; + -- Read-only. + USBPHY_DM_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SCLK_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SS_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD0_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD1_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD2_EDGE_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_LEVEL_HIGH : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_LOW : Boolean; + -- Read-only. + GPIO_QSPI_SD3_EDGE_HIGH : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DORMANT_WAKE_INTS_Register use record + USBPHY_DP_LEVEL_LOW at 0 range 0 .. 0; + USBPHY_DP_LEVEL_HIGH at 0 range 1 .. 1; + USBPHY_DP_EDGE_LOW at 0 range 2 .. 2; + USBPHY_DP_EDGE_HIGH at 0 range 3 .. 3; + USBPHY_DM_LEVEL_LOW at 0 range 4 .. 4; + USBPHY_DM_LEVEL_HIGH at 0 range 5 .. 5; + USBPHY_DM_EDGE_LOW at 0 range 6 .. 6; + USBPHY_DM_EDGE_HIGH at 0 range 7 .. 7; + GPIO_QSPI_SCLK_LEVEL_LOW at 0 range 8 .. 8; + GPIO_QSPI_SCLK_LEVEL_HIGH at 0 range 9 .. 9; + GPIO_QSPI_SCLK_EDGE_LOW at 0 range 10 .. 10; + GPIO_QSPI_SCLK_EDGE_HIGH at 0 range 11 .. 11; + GPIO_QSPI_SS_LEVEL_LOW at 0 range 12 .. 12; + GPIO_QSPI_SS_LEVEL_HIGH at 0 range 13 .. 13; + GPIO_QSPI_SS_EDGE_LOW at 0 range 14 .. 14; + GPIO_QSPI_SS_EDGE_HIGH at 0 range 15 .. 15; + GPIO_QSPI_SD0_LEVEL_LOW at 0 range 16 .. 16; + GPIO_QSPI_SD0_LEVEL_HIGH at 0 range 17 .. 17; + GPIO_QSPI_SD0_EDGE_LOW at 0 range 18 .. 18; + GPIO_QSPI_SD0_EDGE_HIGH at 0 range 19 .. 19; + GPIO_QSPI_SD1_LEVEL_LOW at 0 range 20 .. 20; + GPIO_QSPI_SD1_LEVEL_HIGH at 0 range 21 .. 21; + GPIO_QSPI_SD1_EDGE_LOW at 0 range 22 .. 22; + GPIO_QSPI_SD1_EDGE_HIGH at 0 range 23 .. 23; + GPIO_QSPI_SD2_LEVEL_LOW at 0 range 24 .. 24; + GPIO_QSPI_SD2_LEVEL_HIGH at 0 range 25 .. 25; + GPIO_QSPI_SD2_EDGE_LOW at 0 range 26 .. 26; + GPIO_QSPI_SD2_EDGE_HIGH at 0 range 27 .. 27; + GPIO_QSPI_SD3_LEVEL_LOW at 0 range 28 .. 28; + GPIO_QSPI_SD3_LEVEL_HIGH at 0 range 29 .. 29; + GPIO_QSPI_SD3_EDGE_LOW at 0 range 30 .. 30; + GPIO_QSPI_SD3_EDGE_HIGH at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type IO_QSPI_Peripheral is record + USBPHY_DP_STATUS : aliased USBPHY_DP_STATUS_Register; + USBPHY_DP_CTRL : aliased USBPHY_DP_CTRL_Register; + USBPHY_DM_STATUS : aliased USBPHY_DM_STATUS_Register; + USBPHY_DM_CTRL : aliased USBPHY_DM_CTRL_Register; + GPIO_QSPI_SCLK_STATUS : aliased GPIO_QSPI_SCLK_STATUS_Register; + GPIO_QSPI_SCLK_CTRL : aliased GPIO_QSPI_SCLK_CTRL_Register; + GPIO_QSPI_SS_STATUS : aliased GPIO_QSPI_SS_STATUS_Register; + GPIO_QSPI_SS_CTRL : aliased GPIO_QSPI_SS_CTRL_Register; + GPIO_QSPI_SD0_STATUS : aliased GPIO_QSPI_SD0_STATUS_Register; + GPIO_QSPI_SD0_CTRL : aliased GPIO_QSPI_SD0_CTRL_Register; + GPIO_QSPI_SD1_STATUS : aliased GPIO_QSPI_SD1_STATUS_Register; + GPIO_QSPI_SD1_CTRL : aliased GPIO_QSPI_SD1_CTRL_Register; + GPIO_QSPI_SD2_STATUS : aliased GPIO_QSPI_SD2_STATUS_Register; + GPIO_QSPI_SD2_CTRL : aliased GPIO_QSPI_SD2_CTRL_Register; + GPIO_QSPI_SD3_STATUS : aliased GPIO_QSPI_SD3_STATUS_Register; + GPIO_QSPI_SD3_CTRL : aliased GPIO_QSPI_SD3_CTRL_Register; + IRQSUMMARY_PROC0_SECURE : aliased IRQSUMMARY_PROC0_SECURE_Register; + IRQSUMMARY_PROC0_NONSECURE : aliased IRQSUMMARY_PROC0_NONSECURE_Register; + IRQSUMMARY_PROC1_SECURE : aliased IRQSUMMARY_PROC1_SECURE_Register; + IRQSUMMARY_PROC1_NONSECURE : aliased IRQSUMMARY_PROC1_NONSECURE_Register; + IRQSUMMARY_DORMANT_WAKE_SECURE : aliased IRQSUMMARY_DORMANT_WAKE_SECURE_Register; + IRQSUMMARY_DORMANT_WAKE_NONSECURE : aliased IRQSUMMARY_DORMANT_WAKE_NONSECURE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable for proc0 + PROC0_INTE : aliased PROC0_INTE_Register; + -- Interrupt Force for proc0 + PROC0_INTF : aliased PROC0_INTF_Register; + -- Interrupt status after masking & forcing for proc0 + PROC0_INTS : aliased PROC0_INTS_Register; + -- Interrupt Enable for proc1 + PROC1_INTE : aliased PROC1_INTE_Register; + -- Interrupt Force for proc1 + PROC1_INTF : aliased PROC1_INTF_Register; + -- Interrupt status after masking & forcing for proc1 + PROC1_INTS : aliased PROC1_INTS_Register; + -- Interrupt Enable for dormant_wake + DORMANT_WAKE_INTE : aliased DORMANT_WAKE_INTE_Register; + -- Interrupt Force for dormant_wake + DORMANT_WAKE_INTF : aliased DORMANT_WAKE_INTF_Register; + -- Interrupt status after masking & forcing for dormant_wake + DORMANT_WAKE_INTS : aliased DORMANT_WAKE_INTS_Register; + end record + with Volatile; + + for IO_QSPI_Peripheral use record + USBPHY_DP_STATUS at 16#0# range 0 .. 31; + USBPHY_DP_CTRL at 16#4# range 0 .. 31; + USBPHY_DM_STATUS at 16#8# range 0 .. 31; + USBPHY_DM_CTRL at 16#C# range 0 .. 31; + GPIO_QSPI_SCLK_STATUS at 16#10# range 0 .. 31; + GPIO_QSPI_SCLK_CTRL at 16#14# range 0 .. 31; + GPIO_QSPI_SS_STATUS at 16#18# range 0 .. 31; + GPIO_QSPI_SS_CTRL at 16#1C# range 0 .. 31; + GPIO_QSPI_SD0_STATUS at 16#20# range 0 .. 31; + GPIO_QSPI_SD0_CTRL at 16#24# range 0 .. 31; + GPIO_QSPI_SD1_STATUS at 16#28# range 0 .. 31; + GPIO_QSPI_SD1_CTRL at 16#2C# range 0 .. 31; + GPIO_QSPI_SD2_STATUS at 16#30# range 0 .. 31; + GPIO_QSPI_SD2_CTRL at 16#34# range 0 .. 31; + GPIO_QSPI_SD3_STATUS at 16#38# range 0 .. 31; + GPIO_QSPI_SD3_CTRL at 16#3C# range 0 .. 31; + IRQSUMMARY_PROC0_SECURE at 16#200# range 0 .. 31; + IRQSUMMARY_PROC0_NONSECURE at 16#204# range 0 .. 31; + IRQSUMMARY_PROC1_SECURE at 16#208# range 0 .. 31; + IRQSUMMARY_PROC1_NONSECURE at 16#20C# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_SECURE at 16#210# range 0 .. 31; + IRQSUMMARY_DORMANT_WAKE_NONSECURE at 16#214# range 0 .. 31; + INTR at 16#218# range 0 .. 31; + PROC0_INTE at 16#21C# range 0 .. 31; + PROC0_INTF at 16#220# range 0 .. 31; + PROC0_INTS at 16#224# range 0 .. 31; + PROC1_INTE at 16#228# range 0 .. 31; + PROC1_INTF at 16#22C# range 0 .. 31; + PROC1_INTS at 16#230# range 0 .. 31; + DORMANT_WAKE_INTE at 16#234# range 0 .. 31; + DORMANT_WAKE_INTF at 16#238# range 0 .. 31; + DORMANT_WAKE_INTS at 16#23C# range 0 .. 31; + end record; + + IO_QSPI_Periph : aliased IO_QSPI_Peripheral + with Import, Address => IO_QSPI_Base; + +end RP2350_SVD.IO_QSPI; diff --git a/src/svd/rp2350_svd-otp.ads b/src/svd/rp2350_svd-otp.ads new file mode 100644 index 0000000..0460f3d --- /dev/null +++ b/src/svd/rp2350_svd-otp.ads @@ -0,0 +1,1177 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- SNPS OTP control IF (SBPI and RPi wrapper control) +package RP2350_SVD.OTP is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Secure lock status. Writes are OR'd with the current value. This field + -- is read-only to Non-secure code. + type SW_LOCK0_SEC_Field is + (read_write, + read_only, + inaccessible) + with Size => 2; + for SW_LOCK0_SEC_Field use + (read_write => 0, + read_only => 1, + inaccessible => 3); + + -- Non-secure lock status. Writes are OR'd with the current value. + type SW_LOCK0_NSEC_Field is + (read_write, + read_only, + inaccessible) + with Size => 2; + for SW_LOCK0_NSEC_Field use + (read_write => 0, + read_only => 1, + inaccessible => 3); + + -- Software lock register for page 0. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance the + -- lock state of each page (until next reset), and read to check the + -- current lock state of a page. + type SW_LOCK_Register is record + -- Secure lock status. Writes are OR'd with the current value. This + -- field is read-only to Non-secure code. + SEC : SW_LOCK0_SEC_Field := RP2350_SVD.OTP.read_write; + -- Non-secure lock status. Writes are OR'd with the current value. + NSEC : SW_LOCK0_NSEC_Field := RP2350_SVD.OTP.read_write; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SW_LOCK_Register use record + SEC at 0 range 0 .. 1; + NSEC at 0 range 2 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype SBPI_INSTR_SHORT_WDATA_Field is HAL.UInt8; + subtype SBPI_INSTR_CMD_Field is HAL.UInt8; + subtype SBPI_INSTR_TARGET_Field is HAL.UInt8; + subtype SBPI_INSTR_PAYLOAD_SIZE_M1_Field is HAL.UInt4; + + -- Dispatch instructions to the SBPI interface, used for programming the + -- OTP fuses. + type SBPI_INSTR_Register is record + -- wdata to be used only when payload_size_m1=0 + SHORT_WDATA : SBPI_INSTR_SHORT_WDATA_Field := 16#0#; + CMD : SBPI_INSTR_CMD_Field := 16#0#; + -- Instruction target, it can be PMC (0x3a) or DAP (0x02) + TARGET : SBPI_INSTR_TARGET_Field := 16#0#; + -- Instruction payload size in bytes minus 1 + PAYLOAD_SIZE_M1 : SBPI_INSTR_PAYLOAD_SIZE_M1_Field := 16#0#; + -- Instruction has payload (data to be written or to be read) + HAS_PAYLOAD : Boolean := False; + -- Payload type is write + IS_WR : Boolean := False; + -- Write-only. Execute instruction + EXEC : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SBPI_INSTR_Register use record + SHORT_WDATA at 0 range 0 .. 7; + CMD at 0 range 8 .. 15; + TARGET at 0 range 16 .. 23; + PAYLOAD_SIZE_M1 at 0 range 24 .. 27; + HAS_PAYLOAD at 0 range 28 .. 28; + IS_WR at 0 range 29 .. 29; + EXEC at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype SBPI_STATUS_MISO_Field is HAL.UInt8; + + type SBPI_STATUS_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Read command has returned data + RDATA_VLD : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Last instruction done + INSTR_DONE : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Last instruction missed (dropped), as the previous has + -- not finished running + INSTR_MISS : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Read-only. SBPI flag + FLAG : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Read-only. SBPI MISO (master in - slave out): response from SBPI + MISO : SBPI_STATUS_MISO_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SBPI_STATUS_Register use record + RDATA_VLD at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + INSTR_DONE at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + INSTR_MISS at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + FLAG at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + MISO at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Controls for APB data read interface (USER interface) + type USR_Register is record + -- 1 enables USER interface; 0 disables USER interface (enables SBPI). + -- This bit must be cleared before performing any SBPI access, such as + -- when programming the OTP. The APB data read interface (USER + -- interface) will be inaccessible during this time, and will return a + -- bus error if any read is attempted. + DCTRL : Boolean := True; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Power-down; 1 disables current reference. Must be 0 to read data from + -- the OTP. + PD : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USR_Register use record + DCTRL at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + PD at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype DBG_PSM_STATE_Field is HAL.UInt4; + + -- Debug for OTP power-on state machine + type DBG_Register is record + -- Read-only. PSM done status flag + PSM_DONE : Boolean := False; + -- Read-only. PSM boot done status flag + BOOT_DONE : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Ring oscillator was seen up and running + ROSC_UP_SEEN : Boolean := False; + -- Read-only. Ring oscillator is up and running + ROSC_UP : Boolean := False; + -- Read-only. Monitor the PSM FSM's state + PSM_STATE : DBG_PSM_STATE_Field := 16#0#; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Read-only. The chip is in RMA mode + CUSTOMER_RMA_FLAG : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBG_Register use record + PSM_DONE at 0 range 0 .. 0; + BOOT_DONE at 0 range 1 .. 1; + ROSC_UP_SEEN at 0 range 2 .. 2; + ROSC_UP at 0 range 3 .. 3; + PSM_STATE at 0 range 4 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + CUSTOMER_RMA_FLAG at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype BIST_CNT_Field is HAL.UInt13; + subtype BIST_CNT_MAX_Field is HAL.UInt12; + + -- During BIST, count address locations that have at least one leaky bit + type BIST_Register is record + -- Read-only. Number of locations that have at least one leaky bit. + -- Note: This count is true only if the BIST was initiated without the + -- fix option. + CNT : BIST_CNT_Field := 16#0#; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- The cnt_fail flag will be set if the number of leaky locations + -- exceeds this number + CNT_MAX : BIST_CNT_MAX_Field := 16#FFF#; + -- Enable the counter before the BIST function is initiated + CNT_ENA : Boolean := False; + -- Write-only. Clear counter before use + CNT_CLR : Boolean := False; + -- Read-only. Flag if the count of address locations with at least one + -- leaky bit exceeds cnt_max + CNT_FAIL : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BIST_Register use record + CNT at 0 range 0 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + CNT_MAX at 0 range 16 .. 27; + CNT_ENA at 0 range 28 .. 28; + CNT_CLR at 0 range 29 .. 29; + CNT_FAIL at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype CRITICAL_GLITCH_DETECTOR_SENS_Field is HAL.UInt2; + + -- Quickly check values of critical flags read during boot up + type CRITICAL_Register is record + -- Read-only. + SECURE_BOOT_ENABLE : Boolean; + -- Read-only. + SECURE_DEBUG_DISABLE : Boolean; + -- Read-only. + DEBUG_DISABLE : Boolean; + -- Read-only. + DEFAULT_ARCHSEL : Boolean; + -- Read-only. + GLITCH_DETECTOR_ENABLE : Boolean; + -- Read-only. + GLITCH_DETECTOR_SENS : CRITICAL_GLITCH_DETECTOR_SENS_Field; + -- unspecified + Reserved_7_15 : HAL.UInt9; + -- Read-only. + ARM_DISABLE : Boolean; + -- Read-only. + RISCV_DISABLE : Boolean; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRITICAL_Register use record + SECURE_BOOT_ENABLE at 0 range 0 .. 0; + SECURE_DEBUG_DISABLE at 0 range 1 .. 1; + DEBUG_DISABLE at 0 range 2 .. 2; + DEFAULT_ARCHSEL at 0 range 3 .. 3; + GLITCH_DETECTOR_ENABLE at 0 range 4 .. 4; + GLITCH_DETECTOR_SENS at 0 range 5 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + ARM_DISABLE at 0 range 16 .. 16; + RISCV_DISABLE at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype KEY_VALID_KEY_VALID_Field is HAL.UInt8; + + -- Which keys were valid (enrolled) at boot time + type KEY_VALID_Register is record + -- Read-only. + KEY_VALID : KEY_VALID_KEY_VALID_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY_VALID_Register use record + KEY_VALID at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Enable a debug feature that has been disabled. Debug features are + -- disabled if one of the relevant critical boot flags is set in OTP + -- (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked + -- valid in OTP, and the matching key value has not been supplied over SWD. + -- Specifically: - The DEBUG_DISABLE flag disables all debug features. This + -- can be fully overridden by setting all bits of this register. - The + -- SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be + -- fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of + -- this register. - If a single debug key has been registered, and no + -- matching key value has been supplied over SWD, then all debug features + -- are disabled. This can be fully overridden by setting all bits of this + -- register. - If both debug keys have been registered, and the Non-secure + -- key's value (key 6) has been supplied over SWD, secure processor debug + -- is disabled. This can be fully overridden by setting the PROC0_SECURE + -- and PROC1_SECURE bits of this register. - If both debug keys have been + -- registered, and the Secure key's value (key 5) has been supplied over + -- SWD, then no debug features are disabled by the key mechanism. However, + -- note that in this case debug features may still be disabled by the + -- critical boot flags. + type DEBUGEN_Register is record + -- Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is + -- disabled by default if either of the debug disable critical flags is + -- set, or if at least one debug key has been enrolled and the least + -- secure of these enrolled key values has not been provided over SWD. + -- Note also that core Mem-APs are unconditionally disabled when a core + -- is switched to RISC-V mode (by setting the ARCHSEL bit and performing + -- a warm reset of the core). + PROC0 : Boolean := False; + -- Permit core 0's Mem-AP to generate Secure accesses, assuming it is + -- enabled at all. Also enable secure debug of core 0 (SPIDEN and + -- SPNIDEN). Secure debug of core 0 is disabled by default if the secure + -- debug disable critical flag is set, or if at least one debug key has + -- been enrolled and the most secure of these enrolled key values not + -- yet provided over SWD. Note also that core Mem-APs are + -- unconditionally disabled when a core is switched to RISC-V mode (by + -- setting the ARCHSEL bit and performing a warm reset of the core). + PROC0_SECURE : Boolean := False; + -- Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is + -- disabled by default if either of the debug disable critical flags is + -- set, or if at least one debug key has been enrolled and the least + -- secure of these enrolled key values has not been provided over SWD. + PROC1 : Boolean := False; + -- Permit core 1's Mem-AP to generate Secure accesses, assuming it is + -- enabled at all. Also enable secure debug of core 1 (SPIDEN and + -- SPNIDEN). Secure debug of core 1 is disabled by default if the secure + -- debug disable critical flag is set, or if at least one debug key has + -- been enrolled and the most secure of these enrolled key values not + -- yet provided over SWD. + PROC1_SECURE : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Enable other debug components. Specifically, the CTI, and the APB-AP + -- used to access the RISC-V Debug Module. These components are disabled + -- by default if either of the debug disable critical flags is set, or + -- if at least one debug key has been enrolled and the least secure of + -- these enrolled key values has not been provided over SWD. + MISC : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEBUGEN_Register use record + PROC0 at 0 range 0 .. 0; + PROC0_SECURE at 0 range 1 .. 1; + PROC1 at 0 range 2 .. 2; + PROC1_SECURE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + MISC at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Write 1s to lock corresponding bits in DEBUGEN. This register is reset + -- by the processor cold reset. + type DEBUGEN_LOCK_Register is record + -- Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + PROC0 : Boolean := False; + -- Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared + -- once set. + PROC0_SECURE : Boolean := False; + -- Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + PROC1 : Boolean := False; + -- Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared + -- once set. + PROC1_SECURE : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + MISC : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEBUGEN_LOCK_Register use record + PROC0 at 0 range 0 .. 0; + PROC0_SECURE at 0 range 1 .. 1; + PROC1 at 0 range 2 .. 2; + PROC1_SECURE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + MISC at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Select architecture for core 0. + type ARCHSEL_CORE0_Field is + (-- Switch core 0 to Arm (Cortex-M33) + arm, + -- Switch core 0 to RISC-V (Hazard3) + riscv) + with Size => 1; + for ARCHSEL_CORE0_Field use + (arm => 0, + riscv => 1); + + -- Select architecture for core 1. + type ARCHSEL_CORE1_Field is + (-- Switch core 1 to Arm (Cortex-M33) + arm, + -- Switch core 1 to RISC-V (Hazard3) + riscv) + with Size => 1; + for ARCHSEL_CORE1_Field use + (arm => 0, + riscv => 1); + + -- Architecture select (Arm/RISC-V). The default and allowable values of + -- this register are constrained by the critical boot flags. This register + -- is reset by the earliest reset in the switched core power domain (before + -- a processor cold reset). Cores sample their architecture select signal + -- on a warm reset. The source of the warm reset could be the system + -- power-up state machine, the watchdog timer, Arm SYSRESETREQ or from + -- RISC-V hartresetreq. Note that when an Arm core is deselected, its cold + -- reset domain is also held in reset, since in particular the SYSRESETREQ + -- bit becomes inaccessible once the core is deselected. Note also the + -- RISC-V cores do not have a cold reset domain, since their corresponding + -- controls are located in the Debug Module. + type ARCHSEL_Register is record + -- Select architecture for core 0. + CORE0 : ARCHSEL_CORE0_Field := RP2350_SVD.OTP.arm; + -- Select architecture for core 1. + CORE1 : ARCHSEL_CORE1_Field := RP2350_SVD.OTP.arm; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARCHSEL_Register use record + CORE0 at 0 range 0 .. 0; + CORE1 at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Current architecture for core 0. Updated on processor warm reset. + type ARCHSEL_STATUS_CORE0_Field is + (-- Core 0 is currently Arm (Cortex-M33) + arm, + -- Core 0 is currently RISC-V (Hazard3) + riscv) + with Size => 1; + for ARCHSEL_STATUS_CORE0_Field use + (arm => 0, + riscv => 1); + + -- Current architecture for core 0. Updated on processor warm reset. + type ARCHSEL_STATUS_CORE1_Field is + (-- Core 1 is currently Arm (Cortex-M33) + arm, + -- Core 1 is currently RISC-V (Hazard3) + riscv) + with Size => 1; + for ARCHSEL_STATUS_CORE1_Field use + (arm => 0, + riscv => 1); + + -- Get the current architecture select state of each core. Cores sample the + -- current value of the ARCHSEL register when their warm reset is released, + -- at which point the corresponding bit in this register will also update. + type ARCHSEL_STATUS_Register is record + -- Read-only. Current architecture for core 0. Updated on processor warm + -- reset. + CORE0 : ARCHSEL_STATUS_CORE0_Field; + -- Read-only. Current architecture for core 0. Updated on processor warm + -- reset. + CORE1 : ARCHSEL_STATUS_CORE1_Field; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARCHSEL_STATUS_Register use record + CORE0 at 0 range 0 .. 0; + CORE1 at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Tell the bootrom to ignore scratch register boot vectors (both power + -- manager and watchdog) on the next power up. If an early boot stage has + -- soft-locked some OTP pages in order to protect their contents from later + -- stages, there is a risk that Secure code running at a later stage can + -- unlock the pages by performing a watchdog reset that resets the OTP. + -- This register can be used to ensure that the bootloader runs as normal + -- on the next power up, preventing Secure code at a later stage from + -- accessing OTP in its unlocked state. Should be used in conjunction with + -- the power manager BOOTDIS register. + type BOOTDIS_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. When the core is powered down, the current value of + -- BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + -- The bootrom checks this flag before reading the boot scratch + -- registers. If it is set, the bootrom clears it, and ignores the BOOT + -- registers. This prevents Secure software from diverting the boot path + -- before a bootloader has had the chance to soft lock OTP pages + -- containing sensitive data. + NOW : Boolean := False; + -- This flag always ORs writes into its current contents. It can be set + -- but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the + -- BOOTDIS_NOW bit when the core is powered down. Simultaneously, the + -- BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot + -- scratch registers will be ignored following the next core power down. + -- This flag should be set by an early boot stage that has soft-locked + -- OTP pages, to prevent later stages from unlocking it via watchdog + -- reset. + NEXT : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTDIS_Register use record + NOW at 0 range 0 .. 0; + NEXT at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + SBPI_FLAG_N : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + SBPI_WR_FAIL : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + APB_DCTRL_FAIL : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + APB_RD_SEC_FAIL : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + APB_RD_NSEC_FAIL : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + SBPI_FLAG_N at 0 range 0 .. 0; + SBPI_WR_FAIL at 0 range 1 .. 1; + APB_DCTRL_FAIL at 0 range 2 .. 2; + APB_RD_SEC_FAIL at 0 range 3 .. 3; + APB_RD_NSEC_FAIL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + SBPI_FLAG_N : Boolean := False; + SBPI_WR_FAIL : Boolean := False; + APB_DCTRL_FAIL : Boolean := False; + APB_RD_SEC_FAIL : Boolean := False; + APB_RD_NSEC_FAIL : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + SBPI_FLAG_N at 0 range 0 .. 0; + SBPI_WR_FAIL at 0 range 1 .. 1; + APB_DCTRL_FAIL at 0 range 2 .. 2; + APB_RD_SEC_FAIL at 0 range 3 .. 3; + APB_RD_NSEC_FAIL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + SBPI_FLAG_N : Boolean := False; + SBPI_WR_FAIL : Boolean := False; + APB_DCTRL_FAIL : Boolean := False; + APB_RD_SEC_FAIL : Boolean := False; + APB_RD_NSEC_FAIL : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + SBPI_FLAG_N at 0 range 0 .. 0; + SBPI_WR_FAIL at 0 range 1 .. 1; + APB_DCTRL_FAIL at 0 range 2 .. 2; + APB_RD_SEC_FAIL at 0 range 3 .. 3; + APB_RD_NSEC_FAIL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + SBPI_FLAG_N : Boolean; + -- Read-only. + SBPI_WR_FAIL : Boolean; + -- Read-only. + APB_DCTRL_FAIL : Boolean; + -- Read-only. + APB_RD_SEC_FAIL : Boolean; + -- Read-only. + APB_RD_NSEC_FAIL : Boolean; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + SBPI_FLAG_N at 0 range 0 .. 0; + SBPI_WR_FAIL at 0 range 1 .. 1; + APB_DCTRL_FAIL at 0 range 2 .. 2; + APB_RD_SEC_FAIL at 0 range 3 .. 3; + APB_RD_NSEC_FAIL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- SNPS OTP control IF (SBPI and RPi wrapper control) + type OTP_Peripheral is record + -- Software lock register for page 0. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK0 : aliased SW_LOCK_Register; + -- Software lock register for page 1. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK1 : aliased SW_LOCK_Register; + -- Software lock register for page 2. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK2 : aliased SW_LOCK_Register; + -- Software lock register for page 3. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK3 : aliased SW_LOCK_Register; + -- Software lock register for page 4. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK4 : aliased SW_LOCK_Register; + -- Software lock register for page 5. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK5 : aliased SW_LOCK_Register; + -- Software lock register for page 6. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK6 : aliased SW_LOCK_Register; + -- Software lock register for page 7. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK7 : aliased SW_LOCK_Register; + -- Software lock register for page 8. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK8 : aliased SW_LOCK_Register; + -- Software lock register for page 9. Locks are initialised from the OTP + -- lock pages at reset. This register can be written to further advance + -- the lock state of each page (until next reset), and read to check the + -- current lock state of a page. + SW_LOCK9 : aliased SW_LOCK_Register; + -- Software lock register for page 10. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK10 : aliased SW_LOCK_Register; + -- Software lock register for page 11. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK11 : aliased SW_LOCK_Register; + -- Software lock register for page 12. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK12 : aliased SW_LOCK_Register; + -- Software lock register for page 13. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK13 : aliased SW_LOCK_Register; + -- Software lock register for page 14. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK14 : aliased SW_LOCK_Register; + -- Software lock register for page 15. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK15 : aliased SW_LOCK_Register; + -- Software lock register for page 16. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK16 : aliased SW_LOCK_Register; + -- Software lock register for page 17. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK17 : aliased SW_LOCK_Register; + -- Software lock register for page 18. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK18 : aliased SW_LOCK_Register; + -- Software lock register for page 19. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK19 : aliased SW_LOCK_Register; + -- Software lock register for page 20. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK20 : aliased SW_LOCK_Register; + -- Software lock register for page 21. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK21 : aliased SW_LOCK_Register; + -- Software lock register for page 22. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK22 : aliased SW_LOCK_Register; + -- Software lock register for page 23. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK23 : aliased SW_LOCK_Register; + -- Software lock register for page 24. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK24 : aliased SW_LOCK_Register; + -- Software lock register for page 25. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK25 : aliased SW_LOCK_Register; + -- Software lock register for page 26. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK26 : aliased SW_LOCK_Register; + -- Software lock register for page 27. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK27 : aliased SW_LOCK_Register; + -- Software lock register for page 28. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK28 : aliased SW_LOCK_Register; + -- Software lock register for page 29. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK29 : aliased SW_LOCK_Register; + -- Software lock register for page 30. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK30 : aliased SW_LOCK_Register; + -- Software lock register for page 31. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK31 : aliased SW_LOCK_Register; + -- Software lock register for page 32. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK32 : aliased SW_LOCK_Register; + -- Software lock register for page 33. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK33 : aliased SW_LOCK_Register; + -- Software lock register for page 34. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK34 : aliased SW_LOCK_Register; + -- Software lock register for page 35. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK35 : aliased SW_LOCK_Register; + -- Software lock register for page 36. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK36 : aliased SW_LOCK_Register; + -- Software lock register for page 37. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK37 : aliased SW_LOCK_Register; + -- Software lock register for page 38. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK38 : aliased SW_LOCK_Register; + -- Software lock register for page 39. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK39 : aliased SW_LOCK_Register; + -- Software lock register for page 40. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK40 : aliased SW_LOCK_Register; + -- Software lock register for page 41. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK41 : aliased SW_LOCK_Register; + -- Software lock register for page 42. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK42 : aliased SW_LOCK_Register; + -- Software lock register for page 43. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK43 : aliased SW_LOCK_Register; + -- Software lock register for page 44. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK44 : aliased SW_LOCK_Register; + -- Software lock register for page 45. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK45 : aliased SW_LOCK_Register; + -- Software lock register for page 46. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK46 : aliased SW_LOCK_Register; + -- Software lock register for page 47. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK47 : aliased SW_LOCK_Register; + -- Software lock register for page 48. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK48 : aliased SW_LOCK_Register; + -- Software lock register for page 49. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK49 : aliased SW_LOCK_Register; + -- Software lock register for page 50. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK50 : aliased SW_LOCK_Register; + -- Software lock register for page 51. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK51 : aliased SW_LOCK_Register; + -- Software lock register for page 52. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK52 : aliased SW_LOCK_Register; + -- Software lock register for page 53. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK53 : aliased SW_LOCK_Register; + -- Software lock register for page 54. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK54 : aliased SW_LOCK_Register; + -- Software lock register for page 55. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK55 : aliased SW_LOCK_Register; + -- Software lock register for page 56. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK56 : aliased SW_LOCK_Register; + -- Software lock register for page 57. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK57 : aliased SW_LOCK_Register; + -- Software lock register for page 58. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK58 : aliased SW_LOCK_Register; + -- Software lock register for page 59. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK59 : aliased SW_LOCK_Register; + -- Software lock register for page 60. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK60 : aliased SW_LOCK_Register; + -- Software lock register for page 61. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK61 : aliased SW_LOCK_Register; + -- Software lock register for page 62. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK62 : aliased SW_LOCK_Register; + -- Software lock register for page 63. Locks are initialised from the + -- OTP lock pages at reset. This register can be written to further + -- advance the lock state of each page (until next reset), and read to + -- check the current lock state of a page. + SW_LOCK63 : aliased SW_LOCK_Register; + -- Dispatch instructions to the SBPI interface, used for programming the + -- OTP fuses. + SBPI_INSTR : aliased SBPI_INSTR_Register; + -- SBPI write payload bytes 3..0 + SBPI_WDATA_0 : aliased HAL.UInt32; + -- SBPI write payload bytes 7..4 + SBPI_WDATA_1 : aliased HAL.UInt32; + -- SBPI write payload bytes 11..8 + SBPI_WDATA_2 : aliased HAL.UInt32; + -- SBPI write payload bytes 15..12 + SBPI_WDATA_3 : aliased HAL.UInt32; + -- Read payload bytes 3..0. Once read, the data in the register will + -- automatically clear to 0. + SBPI_RDATA_0 : aliased HAL.UInt32; + -- Read payload bytes 7..4. Once read, the data in the register will + -- automatically clear to 0. + SBPI_RDATA_1 : aliased HAL.UInt32; + -- Read payload bytes 11..8. Once read, the data in the register will + -- automatically clear to 0. + SBPI_RDATA_2 : aliased HAL.UInt32; + -- Read payload bytes 15..12. Once read, the data in the register will + -- automatically clear to 0. + SBPI_RDATA_3 : aliased HAL.UInt32; + SBPI_STATUS : aliased SBPI_STATUS_Register; + -- Controls for APB data read interface (USER interface) + USR : aliased USR_Register; + -- Debug for OTP power-on state machine + DBG : aliased DBG_Register; + -- During BIST, count address locations that have at least one leaky bit + BIST : aliased BIST_Register; + -- Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + CRT_KEY_W0 : aliased HAL.UInt32; + -- Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + CRT_KEY_W1 : aliased HAL.UInt32; + -- Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + CRT_KEY_W2 : aliased HAL.UInt32; + -- Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + CRT_KEY_W3 : aliased HAL.UInt32; + -- Quickly check values of critical flags read during boot up + CRITICAL : aliased CRITICAL_Register; + -- Which keys were valid (enrolled) at boot time + KEY_VALID : aliased KEY_VALID_Register; + -- Enable a debug feature that has been disabled. Debug features are + -- disabled if one of the relevant critical boot flags is set in OTP + -- (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked + -- valid in OTP, and the matching key value has not been supplied over + -- SWD. Specifically: - The DEBUG_DISABLE flag disables all debug + -- features. This can be fully overridden by setting all bits of this + -- register. - The SECURE_DEBUG_DISABLE flag disables secure processor + -- debug. This can be fully overridden by setting the PROC0_SECURE and + -- PROC1_SECURE bits of this register. - If a single debug key has been + -- registered, and no matching key value has been supplied over SWD, + -- then all debug features are disabled. This can be fully overridden by + -- setting all bits of this register. - If both debug keys have been + -- registered, and the Non-secure key's value (key 6) has been supplied + -- over SWD, secure processor debug is disabled. This can be fully + -- overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this + -- register. - If both debug keys have been registered, and the Secure + -- key's value (key 5) has been supplied over SWD, then no debug + -- features are disabled by the key mechanism. However, note that in + -- this case debug features may still be disabled by the critical boot + -- flags. + DEBUGEN : aliased DEBUGEN_Register; + -- Write 1s to lock corresponding bits in DEBUGEN. This register is + -- reset by the processor cold reset. + DEBUGEN_LOCK : aliased DEBUGEN_LOCK_Register; + -- Architecture select (Arm/RISC-V). The default and allowable values of + -- this register are constrained by the critical boot flags. This + -- register is reset by the earliest reset in the switched core power + -- domain (before a processor cold reset). Cores sample their + -- architecture select signal on a warm reset. The source of the warm + -- reset could be the system power-up state machine, the watchdog timer, + -- Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm + -- core is deselected, its cold reset domain is also held in reset, + -- since in particular the SYSRESETREQ bit becomes inaccessible once the + -- core is deselected. Note also the RISC-V cores do not have a cold + -- reset domain, since their corresponding controls are located in the + -- Debug Module. + ARCHSEL : aliased ARCHSEL_Register; + -- Get the current architecture select state of each core. Cores sample + -- the current value of the ARCHSEL register when their warm reset is + -- released, at which point the corresponding bit in this register will + -- also update. + ARCHSEL_STATUS : aliased ARCHSEL_STATUS_Register; + -- Tell the bootrom to ignore scratch register boot vectors (both power + -- manager and watchdog) on the next power up. If an early boot stage + -- has soft-locked some OTP pages in order to protect their contents + -- from later stages, there is a risk that Secure code running at a + -- later stage can unlock the pages by performing a watchdog reset that + -- resets the OTP. This register can be used to ensure that the + -- bootloader runs as normal on the next power up, preventing Secure + -- code at a later stage from accessing OTP in its unlocked state. + -- Should be used in conjunction with the power manager BOOTDIS + -- register. + BOOTDIS : aliased BOOTDIS_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for OTP_Peripheral use record + SW_LOCK0 at 16#0# range 0 .. 31; + SW_LOCK1 at 16#4# range 0 .. 31; + SW_LOCK2 at 16#8# range 0 .. 31; + SW_LOCK3 at 16#C# range 0 .. 31; + SW_LOCK4 at 16#10# range 0 .. 31; + SW_LOCK5 at 16#14# range 0 .. 31; + SW_LOCK6 at 16#18# range 0 .. 31; + SW_LOCK7 at 16#1C# range 0 .. 31; + SW_LOCK8 at 16#20# range 0 .. 31; + SW_LOCK9 at 16#24# range 0 .. 31; + SW_LOCK10 at 16#28# range 0 .. 31; + SW_LOCK11 at 16#2C# range 0 .. 31; + SW_LOCK12 at 16#30# range 0 .. 31; + SW_LOCK13 at 16#34# range 0 .. 31; + SW_LOCK14 at 16#38# range 0 .. 31; + SW_LOCK15 at 16#3C# range 0 .. 31; + SW_LOCK16 at 16#40# range 0 .. 31; + SW_LOCK17 at 16#44# range 0 .. 31; + SW_LOCK18 at 16#48# range 0 .. 31; + SW_LOCK19 at 16#4C# range 0 .. 31; + SW_LOCK20 at 16#50# range 0 .. 31; + SW_LOCK21 at 16#54# range 0 .. 31; + SW_LOCK22 at 16#58# range 0 .. 31; + SW_LOCK23 at 16#5C# range 0 .. 31; + SW_LOCK24 at 16#60# range 0 .. 31; + SW_LOCK25 at 16#64# range 0 .. 31; + SW_LOCK26 at 16#68# range 0 .. 31; + SW_LOCK27 at 16#6C# range 0 .. 31; + SW_LOCK28 at 16#70# range 0 .. 31; + SW_LOCK29 at 16#74# range 0 .. 31; + SW_LOCK30 at 16#78# range 0 .. 31; + SW_LOCK31 at 16#7C# range 0 .. 31; + SW_LOCK32 at 16#80# range 0 .. 31; + SW_LOCK33 at 16#84# range 0 .. 31; + SW_LOCK34 at 16#88# range 0 .. 31; + SW_LOCK35 at 16#8C# range 0 .. 31; + SW_LOCK36 at 16#90# range 0 .. 31; + SW_LOCK37 at 16#94# range 0 .. 31; + SW_LOCK38 at 16#98# range 0 .. 31; + SW_LOCK39 at 16#9C# range 0 .. 31; + SW_LOCK40 at 16#A0# range 0 .. 31; + SW_LOCK41 at 16#A4# range 0 .. 31; + SW_LOCK42 at 16#A8# range 0 .. 31; + SW_LOCK43 at 16#AC# range 0 .. 31; + SW_LOCK44 at 16#B0# range 0 .. 31; + SW_LOCK45 at 16#B4# range 0 .. 31; + SW_LOCK46 at 16#B8# range 0 .. 31; + SW_LOCK47 at 16#BC# range 0 .. 31; + SW_LOCK48 at 16#C0# range 0 .. 31; + SW_LOCK49 at 16#C4# range 0 .. 31; + SW_LOCK50 at 16#C8# range 0 .. 31; + SW_LOCK51 at 16#CC# range 0 .. 31; + SW_LOCK52 at 16#D0# range 0 .. 31; + SW_LOCK53 at 16#D4# range 0 .. 31; + SW_LOCK54 at 16#D8# range 0 .. 31; + SW_LOCK55 at 16#DC# range 0 .. 31; + SW_LOCK56 at 16#E0# range 0 .. 31; + SW_LOCK57 at 16#E4# range 0 .. 31; + SW_LOCK58 at 16#E8# range 0 .. 31; + SW_LOCK59 at 16#EC# range 0 .. 31; + SW_LOCK60 at 16#F0# range 0 .. 31; + SW_LOCK61 at 16#F4# range 0 .. 31; + SW_LOCK62 at 16#F8# range 0 .. 31; + SW_LOCK63 at 16#FC# range 0 .. 31; + SBPI_INSTR at 16#100# range 0 .. 31; + SBPI_WDATA_0 at 16#104# range 0 .. 31; + SBPI_WDATA_1 at 16#108# range 0 .. 31; + SBPI_WDATA_2 at 16#10C# range 0 .. 31; + SBPI_WDATA_3 at 16#110# range 0 .. 31; + SBPI_RDATA_0 at 16#114# range 0 .. 31; + SBPI_RDATA_1 at 16#118# range 0 .. 31; + SBPI_RDATA_2 at 16#11C# range 0 .. 31; + SBPI_RDATA_3 at 16#120# range 0 .. 31; + SBPI_STATUS at 16#124# range 0 .. 31; + USR at 16#128# range 0 .. 31; + DBG at 16#12C# range 0 .. 31; + BIST at 16#134# range 0 .. 31; + CRT_KEY_W0 at 16#138# range 0 .. 31; + CRT_KEY_W1 at 16#13C# range 0 .. 31; + CRT_KEY_W2 at 16#140# range 0 .. 31; + CRT_KEY_W3 at 16#144# range 0 .. 31; + CRITICAL at 16#148# range 0 .. 31; + KEY_VALID at 16#14C# range 0 .. 31; + DEBUGEN at 16#150# range 0 .. 31; + DEBUGEN_LOCK at 16#154# range 0 .. 31; + ARCHSEL at 16#158# range 0 .. 31; + ARCHSEL_STATUS at 16#15C# range 0 .. 31; + BOOTDIS at 16#160# range 0 .. 31; + INTR at 16#164# range 0 .. 31; + INTE at 16#168# range 0 .. 31; + INTF at 16#16C# range 0 .. 31; + INTS at 16#170# range 0 .. 31; + end record; + + -- SNPS OTP control IF (SBPI and RPi wrapper control) + OTP_Periph : aliased OTP_Peripheral + with Import, Address => OTP_Base; + +end RP2350_SVD.OTP; diff --git a/src/svd/rp2350_svd-otp_data.ads b/src/svd/rp2350_svd-otp_data.ads new file mode 100644 index 0000000..d8b6e3c --- /dev/null +++ b/src/svd/rp2350_svd-otp_data.ads @@ -0,0 +1,794 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Predefined OTP data layout for RP2350 +package RP2350_SVD.OTP_DATA is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype NUM_GPIOS_NUM_GPIOS_Field is HAL.UInt8; + + -- The number of main user GPIOs (bank 0). Should read 48 in the QFN80 + -- package, and 30 in the QFN60 package. (ECC) + type NUM_GPIOS_Register is record + -- Read-only. + NUM_GPIOS : NUM_GPIOS_NUM_GPIOS_Field; + -- unspecified + Reserved_8_15 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 16, + Bit_Order => System.Low_Order_First; + + for NUM_GPIOS_Register use record + NUM_GPIOS at 0 range 0 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + end record; + + subtype FLASH_DEVINFO_CS1_GPIO_Field is HAL.UInt6; + + -- The size of the flash/PSRAM device on chip select 0 (addressable at + -- 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of + -- zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For + -- example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 + -- megabytes is encoded with a CS0_SIZE value of 12. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is + -- used. + type FLASH_DEVINFO_CS0_SIZE_Field is + (NONE, + Val_8K, + Val_16K, + Val_32K, + Val_64k, + Val_128K, + Val_256K, + Val_512K, + Val_1M, + Val_2M, + Val_4M, + Val_8M, + Val_16M) + with Size => 4; + for FLASH_DEVINFO_CS0_SIZE_Field use + (NONE => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64k => 4, + Val_128K => 5, + Val_256K => 6, + Val_512K => 7, + Val_1M => 8, + Val_2M => 9, + Val_4M => 10, + Val_8M => 11, + Val_16M => 12); + + -- The size of the flash/PSRAM device on chip select 1 (addressable at + -- 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of + -- zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For + -- example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 + -- megabytes is encoded with a CS1_SIZE value of 12. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + type FLASH_DEVINFO_CS1_SIZE_Field is + (NONE, + Val_8K, + Val_16K, + Val_32K, + Val_64k, + Val_128K, + Val_256K, + Val_512K, + Val_1M, + Val_2M, + Val_4M, + Val_8M, + Val_16M) + with Size => 4; + for FLASH_DEVINFO_CS1_SIZE_Field use + (NONE => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64k => 4, + Val_128K => 5, + Val_256K => 6, + Val_512K => 7, + Val_1M => 8, + Val_2M => 9, + Val_4M => 10, + Val_8M => 11, + Val_16M => 12); + + -- Stores information about external flash device(s). (ECC) Assumed to be + -- valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + type FLASH_DEVINFO_Register is record + -- Read-only. Indicate a GPIO number to be used for the secondary flash + -- chip select (CS1), which selects the external QSPI device mapped at + -- system addresses 0x11000000 through 0x11ffffff. There is no such + -- configuration for CS0, as the primary chip select has a dedicated + -- pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + -- Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will + -- automatically configure this GPIO as a second chip select upon + -- entering the flash boot path, or entering any other path that may use + -- the QSPI flash interface, such as BOOTSEL mode (nsboot). + CS1_GPIO : FLASH_DEVINFO_CS1_GPIO_Field; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. If true, all attached devices are assumed to support (or + -- ignore, in the case of PSRAM) a block erase command with a command + -- prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost + -- all 25-series flash devices support this command. If set, the bootrom + -- will use the D8h erase command where it is able, to accelerate bulk + -- erase operations. This makes flash programming faster. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to + -- false. + D8H_ERASE_SUPPORTED : Boolean; + -- Read-only. The size of the flash/PSRAM device on chip select 0 + -- (addressable at 0x10000000 through 0x10ffffff). A value of zero is + -- decoded as a size of zero (no device). Nonzero values are decoded as + -- 4kiB << CS0_SIZE. For example, four megabytes is encoded with a + -- CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE + -- value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a + -- default of 12 (16 MiB) is used. + CS0_SIZE : FLASH_DEVINFO_CS0_SIZE_Field; + -- Read-only. The size of the flash/PSRAM device on chip select 1 + -- (addressable at 0x11000000 through 0x11ffffff). A value of zero is + -- decoded as a size of zero (no device). Nonzero values are decoded as + -- 4kiB << CS1_SIZE. For example, four megabytes is encoded with a + -- CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE + -- value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a + -- default of zero is used. + CS1_SIZE : FLASH_DEVINFO_CS1_SIZE_Field; + end record + with Volatile_Full_Access, Object_Size => 16, + Bit_Order => System.Low_Order_First; + + for FLASH_DEVINFO_Register use record + CS1_GPIO at 0 range 0 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + D8H_ERASE_SUPPORTED at 0 range 7 .. 7; + CS0_SIZE at 0 range 8 .. 11; + CS1_SIZE at 0 range 12 .. 15; + end record; + + subtype BOOTSEL_LED_CFG_PIN_Field is HAL.UInt6; + + -- Pin configuration for LED status, used by USB bootloader. (ECC) Must be + -- valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + type BOOTSEL_LED_CFG_Register is record + -- Read-only. GPIO index to use for bootloader activity LED. + PIN : BOOTSEL_LED_CFG_PIN_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. LED is active-low. (Default: active-high.) + ACTIVELOW : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + end record + with Volatile_Full_Access, Object_Size => 16, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_LED_CFG_Register use record + PIN at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ACTIVELOW at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + end record; + + subtype BOOTSEL_PLL_CFG_FBDIV_Field is HAL.UInt9; + -- BOOTSEL_PLL_CFG_POSTDIV array element + subtype BOOTSEL_PLL_CFG_POSTDIV_Element is HAL.UInt3; + + -- BOOTSEL_PLL_CFG_POSTDIV array + type BOOTSEL_PLL_CFG_POSTDIV_Field_Array is array (1 .. 2) + of BOOTSEL_PLL_CFG_POSTDIV_Element + with Component_Size => 3, Size => 6; + + -- Type definition for BOOTSEL_PLL_CFG_POSTDIV + type BOOTSEL_PLL_CFG_POSTDIV_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- POSTDIV as a value + Val : HAL.UInt6; + when True => + -- POSTDIV as an array + Arr : BOOTSEL_PLL_CFG_POSTDIV_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for BOOTSEL_PLL_CFG_POSTDIV_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- Optional PLL configuration for BOOTSEL mode. (ECC) This should be + -- configured to produce an exact 48 MHz based on the crystal oscillator + -- frequency. User mode software may also use this value to calculate the + -- expected crystal frequency based on an assumed 48 MHz PLL output. If no + -- configuration is given, the crystal is assumed to be 12 MHz. The PLL + -- frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + -- x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be + -- calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x + -- POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in + -- this OTP location is the actual divisor value minus one.) Used if and + -- only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + -- That bit should be set only after this row and BOOTSEL_XOSC_CFG are both + -- correctly programmed. + type BOOTSEL_PLL_CFG_Register is record + -- Read-only. PLL feedback divisor, in the range 16..320 inclusive. + FBDIV : BOOTSEL_PLL_CFG_FBDIV_Field; + -- Read-only. PLL post-divide 1 divisor, in the range 1..7 inclusive. + POSTDIV : BOOTSEL_PLL_CFG_POSTDIV_Field; + -- Read-only. PLL reference divisor, minus one. Programming a value of 0 + -- means a reference divisor of 1. Programming a value of 1 means a + -- reference divisor of 2 (for exceptionally fast XIN inputs) + REFDIV : Boolean; + end record + with Volatile_Full_Access, Object_Size => 16, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_PLL_CFG_Register use record + FBDIV at 0 range 0 .. 8; + POSTDIV at 0 range 9 .. 14; + REFDIV at 0 range 15 .. 15; + end record; + + subtype BOOTSEL_XOSC_CFG_STARTUP_Field is HAL.UInt14; + + -- Value of the XOSC_CTRL_FREQ_RANGE register. + type BOOTSEL_XOSC_CFG_RANGE_Field is + (Val_1_15MHZ, + Val_10_30MHZ, + Val_25_60MHZ, + Val_40_100MHZ) + with Size => 2; + for BOOTSEL_XOSC_CFG_RANGE_Field use + (Val_1_15MHZ => 0, + Val_10_30MHZ => 1, + Val_25_60MHZ => 2, + Val_40_100MHZ => 3); + + -- Non-default crystal oscillator configuration for the USB bootloader. + -- (ECC) These values may also be used by user code configuring the crystal + -- oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + -- is set in BOOT_FLAGS0. That bit should be set only after this row and + -- BOOTSEL_PLL_CFG are both correctly programmed. + type BOOTSEL_XOSC_CFG_Register is record + -- Read-only. Value of the XOSC_STARTUP register + STARTUP : BOOTSEL_XOSC_CFG_STARTUP_Field; + -- Read-only. Value of the XOSC_CTRL_FREQ_RANGE register. + RANGE_k : BOOTSEL_XOSC_CFG_RANGE_Field; + end record + with Volatile_Full_Access, Object_Size => 16, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_XOSC_CFG_Register use record + STARTUP at 0 range 0 .. 13; + RANGE_k at 0 range 14 .. 15; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Predefined OTP data layout for RP2350 + type OTP_DATA_Peripheral is record + -- Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a + -- 64-bit random identifier for this chip, which can be read from the + -- USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + -- The number of random bits makes the occurrence of twins exceedingly + -- unlikely: for example, a fleet of a hundred million devices has a + -- 99.97% probability of no twinned IDs. This is estimated to be lower + -- than the occurrence of process errors in the assignment of sequential + -- random IDs, and for practical purposes CHIPID may be treated as + -- unique. + CHIPID0 : aliased HAL.UInt16; + -- Bits 31:16 of public device ID (ECC) + CHIPID1 : aliased HAL.UInt16; + -- Bits 47:32 of public device ID (ECC) + CHIPID2 : aliased HAL.UInt16; + -- Bits 63:48 of public device ID (ECC) + CHIPID3 : aliased HAL.UInt16; + -- Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + -- rows form a 128-bit random number generated during device test. This + -- ID is not exposed through the USB PICOBOOT GET_INFO command or the + -- ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP + -- access point can read the entirety of page 0, so this value is not + -- meaningfully private unless the USB PICOBOOT interface is disabled + -- via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + RANDID0 : aliased HAL.UInt16; + -- Bits 31:16 of private per-device random number (ECC) + RANDID1 : aliased HAL.UInt16; + -- Bits 47:32 of private per-device random number (ECC) + RANDID2 : aliased HAL.UInt16; + -- Bits 63:48 of private per-device random number (ECC) + RANDID3 : aliased HAL.UInt16; + -- Bits 79:64 of private per-device random number (ECC) + RANDID4 : aliased HAL.UInt16; + -- Bits 95:80 of private per-device random number (ECC) + RANDID5 : aliased HAL.UInt16; + -- Bits 111:96 of private per-device random number (ECC) + RANDID6 : aliased HAL.UInt16; + -- Bits 127:112 of private per-device random number (ECC) + RANDID7 : aliased HAL.UInt16; + -- Ring oscillator frequency in kHz, measured during manufacturing (ECC) + -- This is measured at 1.1 V, at room temperature, with the ROSC + -- configuration registers in their reset state. + ROSC_CALIB : aliased HAL.UInt16; + -- Low-power oscillator frequency in Hz, measured during manufacturing + -- (ECC) This is measured at 1.1V, at room temperature, with the LPOSC + -- trim register in its reset state. + LPOSC_CALIB : aliased HAL.UInt16; + -- The number of main user GPIOs (bank 0). Should read 48 in the QFN80 + -- package, and 30 in the QFN60 package. (ECC) + NUM_GPIOS : aliased NUM_GPIOS_Register; + -- Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + -- 0x4c11db7, input reflected, output reflected, seed all-ones, final + -- XOR all-ones) (ECC) + INFO_CRC0 : aliased HAL.UInt16; + -- Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + INFO_CRC1 : aliased HAL.UInt16; + -- Stores information about external flash device(s). (ECC) Assumed to + -- be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + FLASH_DEVINFO : aliased FLASH_DEVINFO_Register; + -- Gap between partition table slot 0 and slot 1 at the start of flash + -- (the default size is 4096 bytes) (ECC) Enabled by the + -- OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is + -- 4096 * (value + 1) + FLASH_PARTITION_SLOT_SIZE : aliased HAL.UInt16; + -- Pin configuration for LED status, used by USB bootloader. (ECC) Must + -- be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + BOOTSEL_LED_CFG : aliased BOOTSEL_LED_CFG_Register; + -- Optional PLL configuration for BOOTSEL mode. (ECC) This should be + -- configured to produce an exact 48 MHz based on the crystal oscillator + -- frequency. User mode software may also use this value to calculate + -- the expected crystal frequency based on an assumed 48 MHz PLL output. + -- If no configuration is given, the crystal is assumed to be 12 MHz. + -- The PLL frequency can be calculated as: PLL out = (XOSC frequency / + -- (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + -- frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) + -- x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the + -- value stored in this OTP location is the actual divisor value minus + -- one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is + -- set in BOOT_FLAGS0. That bit should be set only after this row and + -- BOOTSEL_XOSC_CFG are both correctly programmed. + BOOTSEL_PLL_CFG : aliased BOOTSEL_PLL_CFG_Register; + -- Non-default crystal oscillator configuration for the USB bootloader. + -- (ECC) These values may also be used by user code configuring the + -- crystal oscillator. Used if and only if + -- ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That + -- bit should be set only after this row and BOOTSEL_PLL_CFG are both + -- correctly programmed. + BOOTSEL_XOSC_CFG : aliased BOOTSEL_XOSC_CFG_Register; + -- Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table + -- has 16 rows, each of which are also ECC and marked valid by the + -- corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are + -- either _VALUEs where the 16 bit value is used as is, or _STRDEFs + -- which acts as a pointers to a string value. The value stored in a + -- _STRDEF is two separate bytes: The low seven bits of the first (LSB) + -- byte indicates the number of characters in the string, and the top + -- bit of the first (LSB) byte if set to indicate that each character in + -- the string is two bytes (Unicode) versus one byte if unset. The + -- second (MSB) byte represents the location of the string data, and is + -- encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. + -- the row of the start of the string is USB_WHITE_LABEL_ADDR value + + -- msb_byte. In each case, the corresponding valid bit enables replacing + -- the default value for the corresponding item provided by the boot + -- rom. Note that Unicode _STRDEFs are only supported for + -- USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and + -- USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if + -- specified for other fields, and non-unicode values for these three + -- items will be converted to Unicode characters by setting the upper 8 + -- bits to zero. Note that if the USB_WHITE_LABEL structure or the + -- corresponding strings are not readable by BOOTSEL mode based on OTP + -- permissions, or if alignment requirements are not met, then the + -- corresponding default values are used. The index values indicate + -- where each field is located (row USB_WHITE_LABEL_ADDR value + index): + USB_WHITE_LABEL_ADDR : aliased HAL.UInt16; + -- OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + -- the bootrom will load from this location into SRAM and then directly + -- enter the loaded image. Note that the image must be signed if + -- SECURE_BOOT_ENABLE is set. The image itself is assumed to be + -- ECC-protected. This must be an even number. Equivalently, the OTP + -- boot image must start at a word-aligned location in the ECC read data + -- address window. + OTPBOOT_SRC : aliased HAL.UInt16; + -- Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. + -- The total image size must be a multiple of 4 bytes (32 bits). + OTPBOOT_LEN : aliased HAL.UInt16; + -- Bits 15:0 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + OTPBOOT_DST0 : aliased HAL.UInt16; + -- Bits 31:16 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + OTPBOOT_DST1 : aliased HAL.UInt16; + -- Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_0 : aliased HAL.UInt16; + -- Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_1 : aliased HAL.UInt16; + -- Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_2 : aliased HAL.UInt16; + -- Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_3 : aliased HAL.UInt16; + -- Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_4 : aliased HAL.UInt16; + -- Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_5 : aliased HAL.UInt16; + -- Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_6 : aliased HAL.UInt16; + -- Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_7 : aliased HAL.UInt16; + -- Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_8 : aliased HAL.UInt16; + -- Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_9 : aliased HAL.UInt16; + -- Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_10 : aliased HAL.UInt16; + -- Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_11 : aliased HAL.UInt16; + -- Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_12 : aliased HAL.UInt16; + -- Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_13 : aliased HAL.UInt16; + -- Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_14 : aliased HAL.UInt16; + -- Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_15 : aliased HAL.UInt16; + -- Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_0 : aliased HAL.UInt16; + -- Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_1 : aliased HAL.UInt16; + -- Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_2 : aliased HAL.UInt16; + -- Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_3 : aliased HAL.UInt16; + -- Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_4 : aliased HAL.UInt16; + -- Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_5 : aliased HAL.UInt16; + -- Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_6 : aliased HAL.UInt16; + -- Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_7 : aliased HAL.UInt16; + -- Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_8 : aliased HAL.UInt16; + -- Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_9 : aliased HAL.UInt16; + -- Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_10 : aliased HAL.UInt16; + -- Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_11 : aliased HAL.UInt16; + -- Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_12 : aliased HAL.UInt16; + -- Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_13 : aliased HAL.UInt16; + -- Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_14 : aliased HAL.UInt16; + -- Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_15 : aliased HAL.UInt16; + -- Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_0 : aliased HAL.UInt16; + -- Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_1 : aliased HAL.UInt16; + -- Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_2 : aliased HAL.UInt16; + -- Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_3 : aliased HAL.UInt16; + -- Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_4 : aliased HAL.UInt16; + -- Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_5 : aliased HAL.UInt16; + -- Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_6 : aliased HAL.UInt16; + -- Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_7 : aliased HAL.UInt16; + -- Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_8 : aliased HAL.UInt16; + -- Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_9 : aliased HAL.UInt16; + -- Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_10 : aliased HAL.UInt16; + -- Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_11 : aliased HAL.UInt16; + -- Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_12 : aliased HAL.UInt16; + -- Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_13 : aliased HAL.UInt16; + -- Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_14 : aliased HAL.UInt16; + -- Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_15 : aliased HAL.UInt16; + -- Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_0 : aliased HAL.UInt16; + -- Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_1 : aliased HAL.UInt16; + -- Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_2 : aliased HAL.UInt16; + -- Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_3 : aliased HAL.UInt16; + -- Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_4 : aliased HAL.UInt16; + -- Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_5 : aliased HAL.UInt16; + -- Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_6 : aliased HAL.UInt16; + -- Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_7 : aliased HAL.UInt16; + -- Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_8 : aliased HAL.UInt16; + -- Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_9 : aliased HAL.UInt16; + -- Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_10 : aliased HAL.UInt16; + -- Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_11 : aliased HAL.UInt16; + -- Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_12 : aliased HAL.UInt16; + -- Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_13 : aliased HAL.UInt16; + -- Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_14 : aliased HAL.UInt16; + -- Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_15 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 1 (ECC) + KEY1_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 1 (ECC) + KEY1_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 1 (ECC) + KEY1_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 1 (ECC) + KEY1_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 1 (ECC) + KEY1_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 1 (ECC) + KEY1_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 1 (ECC) + KEY1_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 1 (ECC) + KEY1_7 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 2 (ECC) + KEY2_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 2 (ECC) + KEY2_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 2 (ECC) + KEY2_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 2 (ECC) + KEY2_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 2 (ECC) + KEY2_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 2 (ECC) + KEY2_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 2 (ECC) + KEY2_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 2 (ECC) + KEY2_7 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 3 (ECC) + KEY3_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 3 (ECC) + KEY3_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 3 (ECC) + KEY3_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 3 (ECC) + KEY3_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 3 (ECC) + KEY3_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 3 (ECC) + KEY3_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 3 (ECC) + KEY3_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 3 (ECC) + KEY3_7 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 4 (ECC) + KEY4_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 4 (ECC) + KEY4_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 4 (ECC) + KEY4_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 4 (ECC) + KEY4_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 4 (ECC) + KEY4_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 4 (ECC) + KEY4_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 4 (ECC) + KEY4_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 4 (ECC) + KEY4_7 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 5 (ECC) + KEY5_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 5 (ECC) + KEY5_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 5 (ECC) + KEY5_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 5 (ECC) + KEY5_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 5 (ECC) + KEY5_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 5 (ECC) + KEY5_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 5 (ECC) + KEY5_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 5 (ECC) + KEY5_7 : aliased HAL.UInt16; + -- Bits 15:0 of OTP access key 6 (ECC) + KEY6_0 : aliased HAL.UInt16; + -- Bits 31:16 of OTP access key 6 (ECC) + KEY6_1 : aliased HAL.UInt16; + -- Bits 47:32 of OTP access key 6 (ECC) + KEY6_2 : aliased HAL.UInt16; + -- Bits 63:48 of OTP access key 6 (ECC) + KEY6_3 : aliased HAL.UInt16; + -- Bits 79:64 of OTP access key 6 (ECC) + KEY6_4 : aliased HAL.UInt16; + -- Bits 95:80 of OTP access key 6 (ECC) + KEY6_5 : aliased HAL.UInt16; + -- Bits 111:96 of OTP access key 6 (ECC) + KEY6_6 : aliased HAL.UInt16; + -- Bits 127:112 of OTP access key 6 (ECC) + KEY6_7 : aliased HAL.UInt16; + end record + with Volatile; + + for OTP_DATA_Peripheral use record + CHIPID0 at 16#0# range 0 .. 15; + CHIPID1 at 16#2# range 0 .. 15; + CHIPID2 at 16#4# range 0 .. 15; + CHIPID3 at 16#6# range 0 .. 15; + RANDID0 at 16#8# range 0 .. 15; + RANDID1 at 16#A# range 0 .. 15; + RANDID2 at 16#C# range 0 .. 15; + RANDID3 at 16#E# range 0 .. 15; + RANDID4 at 16#10# range 0 .. 15; + RANDID5 at 16#12# range 0 .. 15; + RANDID6 at 16#14# range 0 .. 15; + RANDID7 at 16#16# range 0 .. 15; + ROSC_CALIB at 16#20# range 0 .. 15; + LPOSC_CALIB at 16#22# range 0 .. 15; + NUM_GPIOS at 16#30# range 0 .. 15; + INFO_CRC0 at 16#6C# range 0 .. 15; + INFO_CRC1 at 16#6E# range 0 .. 15; + FLASH_DEVINFO at 16#A8# range 0 .. 15; + FLASH_PARTITION_SLOT_SIZE at 16#AA# range 0 .. 15; + BOOTSEL_LED_CFG at 16#AC# range 0 .. 15; + BOOTSEL_PLL_CFG at 16#AE# range 0 .. 15; + BOOTSEL_XOSC_CFG at 16#B0# range 0 .. 15; + USB_WHITE_LABEL_ADDR at 16#B8# range 0 .. 15; + OTPBOOT_SRC at 16#BC# range 0 .. 15; + OTPBOOT_LEN at 16#BE# range 0 .. 15; + OTPBOOT_DST0 at 16#C0# range 0 .. 15; + OTPBOOT_DST1 at 16#C2# range 0 .. 15; + BOOTKEY0_0 at 16#100# range 0 .. 15; + BOOTKEY0_1 at 16#102# range 0 .. 15; + BOOTKEY0_2 at 16#104# range 0 .. 15; + BOOTKEY0_3 at 16#106# range 0 .. 15; + BOOTKEY0_4 at 16#108# range 0 .. 15; + BOOTKEY0_5 at 16#10A# range 0 .. 15; + BOOTKEY0_6 at 16#10C# range 0 .. 15; + BOOTKEY0_7 at 16#10E# range 0 .. 15; + BOOTKEY0_8 at 16#110# range 0 .. 15; + BOOTKEY0_9 at 16#112# range 0 .. 15; + BOOTKEY0_10 at 16#114# range 0 .. 15; + BOOTKEY0_11 at 16#116# range 0 .. 15; + BOOTKEY0_12 at 16#118# range 0 .. 15; + BOOTKEY0_13 at 16#11A# range 0 .. 15; + BOOTKEY0_14 at 16#11C# range 0 .. 15; + BOOTKEY0_15 at 16#11E# range 0 .. 15; + BOOTKEY1_0 at 16#120# range 0 .. 15; + BOOTKEY1_1 at 16#122# range 0 .. 15; + BOOTKEY1_2 at 16#124# range 0 .. 15; + BOOTKEY1_3 at 16#126# range 0 .. 15; + BOOTKEY1_4 at 16#128# range 0 .. 15; + BOOTKEY1_5 at 16#12A# range 0 .. 15; + BOOTKEY1_6 at 16#12C# range 0 .. 15; + BOOTKEY1_7 at 16#12E# range 0 .. 15; + BOOTKEY1_8 at 16#130# range 0 .. 15; + BOOTKEY1_9 at 16#132# range 0 .. 15; + BOOTKEY1_10 at 16#134# range 0 .. 15; + BOOTKEY1_11 at 16#136# range 0 .. 15; + BOOTKEY1_12 at 16#138# range 0 .. 15; + BOOTKEY1_13 at 16#13A# range 0 .. 15; + BOOTKEY1_14 at 16#13C# range 0 .. 15; + BOOTKEY1_15 at 16#13E# range 0 .. 15; + BOOTKEY2_0 at 16#140# range 0 .. 15; + BOOTKEY2_1 at 16#142# range 0 .. 15; + BOOTKEY2_2 at 16#144# range 0 .. 15; + BOOTKEY2_3 at 16#146# range 0 .. 15; + BOOTKEY2_4 at 16#148# range 0 .. 15; + BOOTKEY2_5 at 16#14A# range 0 .. 15; + BOOTKEY2_6 at 16#14C# range 0 .. 15; + BOOTKEY2_7 at 16#14E# range 0 .. 15; + BOOTKEY2_8 at 16#150# range 0 .. 15; + BOOTKEY2_9 at 16#152# range 0 .. 15; + BOOTKEY2_10 at 16#154# range 0 .. 15; + BOOTKEY2_11 at 16#156# range 0 .. 15; + BOOTKEY2_12 at 16#158# range 0 .. 15; + BOOTKEY2_13 at 16#15A# range 0 .. 15; + BOOTKEY2_14 at 16#15C# range 0 .. 15; + BOOTKEY2_15 at 16#15E# range 0 .. 15; + BOOTKEY3_0 at 16#160# range 0 .. 15; + BOOTKEY3_1 at 16#162# range 0 .. 15; + BOOTKEY3_2 at 16#164# range 0 .. 15; + BOOTKEY3_3 at 16#166# range 0 .. 15; + BOOTKEY3_4 at 16#168# range 0 .. 15; + BOOTKEY3_5 at 16#16A# range 0 .. 15; + BOOTKEY3_6 at 16#16C# range 0 .. 15; + BOOTKEY3_7 at 16#16E# range 0 .. 15; + BOOTKEY3_8 at 16#170# range 0 .. 15; + BOOTKEY3_9 at 16#172# range 0 .. 15; + BOOTKEY3_10 at 16#174# range 0 .. 15; + BOOTKEY3_11 at 16#176# range 0 .. 15; + BOOTKEY3_12 at 16#178# range 0 .. 15; + BOOTKEY3_13 at 16#17A# range 0 .. 15; + BOOTKEY3_14 at 16#17C# range 0 .. 15; + BOOTKEY3_15 at 16#17E# range 0 .. 15; + KEY1_0 at 16#1E90# range 0 .. 15; + KEY1_1 at 16#1E92# range 0 .. 15; + KEY1_2 at 16#1E94# range 0 .. 15; + KEY1_3 at 16#1E96# range 0 .. 15; + KEY1_4 at 16#1E98# range 0 .. 15; + KEY1_5 at 16#1E9A# range 0 .. 15; + KEY1_6 at 16#1E9C# range 0 .. 15; + KEY1_7 at 16#1E9E# range 0 .. 15; + KEY2_0 at 16#1EA0# range 0 .. 15; + KEY2_1 at 16#1EA2# range 0 .. 15; + KEY2_2 at 16#1EA4# range 0 .. 15; + KEY2_3 at 16#1EA6# range 0 .. 15; + KEY2_4 at 16#1EA8# range 0 .. 15; + KEY2_5 at 16#1EAA# range 0 .. 15; + KEY2_6 at 16#1EAC# range 0 .. 15; + KEY2_7 at 16#1EAE# range 0 .. 15; + KEY3_0 at 16#1EB0# range 0 .. 15; + KEY3_1 at 16#1EB2# range 0 .. 15; + KEY3_2 at 16#1EB4# range 0 .. 15; + KEY3_3 at 16#1EB6# range 0 .. 15; + KEY3_4 at 16#1EB8# range 0 .. 15; + KEY3_5 at 16#1EBA# range 0 .. 15; + KEY3_6 at 16#1EBC# range 0 .. 15; + KEY3_7 at 16#1EBE# range 0 .. 15; + KEY4_0 at 16#1EC0# range 0 .. 15; + KEY4_1 at 16#1EC2# range 0 .. 15; + KEY4_2 at 16#1EC4# range 0 .. 15; + KEY4_3 at 16#1EC6# range 0 .. 15; + KEY4_4 at 16#1EC8# range 0 .. 15; + KEY4_5 at 16#1ECA# range 0 .. 15; + KEY4_6 at 16#1ECC# range 0 .. 15; + KEY4_7 at 16#1ECE# range 0 .. 15; + KEY5_0 at 16#1ED0# range 0 .. 15; + KEY5_1 at 16#1ED2# range 0 .. 15; + KEY5_2 at 16#1ED4# range 0 .. 15; + KEY5_3 at 16#1ED6# range 0 .. 15; + KEY5_4 at 16#1ED8# range 0 .. 15; + KEY5_5 at 16#1EDA# range 0 .. 15; + KEY5_6 at 16#1EDC# range 0 .. 15; + KEY5_7 at 16#1EDE# range 0 .. 15; + KEY6_0 at 16#1EE0# range 0 .. 15; + KEY6_1 at 16#1EE2# range 0 .. 15; + KEY6_2 at 16#1EE4# range 0 .. 15; + KEY6_3 at 16#1EE6# range 0 .. 15; + KEY6_4 at 16#1EE8# range 0 .. 15; + KEY6_5 at 16#1EEA# range 0 .. 15; + KEY6_6 at 16#1EEC# range 0 .. 15; + KEY6_7 at 16#1EEE# range 0 .. 15; + end record; + + -- Predefined OTP data layout for RP2350 + OTP_DATA_Periph : aliased OTP_DATA_Peripheral + with Import, Address => OTP_DATA_Base; + +end RP2350_SVD.OTP_DATA; diff --git a/src/svd/rp2350_svd-otp_data_raw.ads b/src/svd/rp2350_svd-otp_data_raw.ads new file mode 100644 index 0000000..4ae1421 --- /dev/null +++ b/src/svd/rp2350_svd-otp_data_raw.ads @@ -0,0 +1,18426 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Predefined OTP data layout for RP2350 +package RP2350_SVD.OTP_DATA_RAW is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CHIPID0_CHIPID0_Field is HAL.UInt16; + + -- Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a + -- 64-bit random identifier for this chip, which can be read from the USB + -- bootloader PICOBOOT interface or from the get_sys_info ROM API. The + -- number of random bits makes the occurrence of twins exceedingly + -- unlikely: for example, a fleet of a hundred million devices has a 99.97% + -- probability of no twinned IDs. This is estimated to be lower than the + -- occurrence of process errors in the assignment of sequential random IDs, + -- and for practical purposes CHIPID may be treated as unique. + type CHIPID0_Register is record + -- Read-only. + CHIPID0 : CHIPID0_CHIPID0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIPID0_Register use record + CHIPID0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CHIPID1_CHIPID1_Field is HAL.UInt16; + + -- Bits 31:16 of public device ID (ECC) + type CHIPID1_Register is record + -- Read-only. + CHIPID1 : CHIPID1_CHIPID1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIPID1_Register use record + CHIPID1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CHIPID2_CHIPID2_Field is HAL.UInt16; + + -- Bits 47:32 of public device ID (ECC) + type CHIPID2_Register is record + -- Read-only. + CHIPID2 : CHIPID2_CHIPID2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIPID2_Register use record + CHIPID2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CHIPID3_CHIPID3_Field is HAL.UInt16; + + -- Bits 63:48 of public device ID (ECC) + type CHIPID3_Register is record + -- Read-only. + CHIPID3 : CHIPID3_CHIPID3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIPID3_Register use record + CHIPID3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID0_RANDID0_Field is HAL.UInt16; + + -- Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows + -- form a 128-bit random number generated during device test. This ID is + -- not exposed through the USB PICOBOOT GET_INFO command or the ROM + -- `get_sys_info()` API. However note that the USB PICOBOOT OTP access + -- point can read the entirety of page 0, so this value is not meaningfully + -- private unless the USB PICOBOOT interface is disabled via the + -- DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + type RANDID0_Register is record + -- Read-only. + RANDID0 : RANDID0_RANDID0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID0_Register use record + RANDID0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID1_RANDID1_Field is HAL.UInt16; + + -- Bits 31:16 of private per-device random number (ECC) + type RANDID1_Register is record + -- Read-only. + RANDID1 : RANDID1_RANDID1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID1_Register use record + RANDID1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID2_RANDID2_Field is HAL.UInt16; + + -- Bits 47:32 of private per-device random number (ECC) + type RANDID2_Register is record + -- Read-only. + RANDID2 : RANDID2_RANDID2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID2_Register use record + RANDID2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID3_RANDID3_Field is HAL.UInt16; + + -- Bits 63:48 of private per-device random number (ECC) + type RANDID3_Register is record + -- Read-only. + RANDID3 : RANDID3_RANDID3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID3_Register use record + RANDID3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID4_RANDID4_Field is HAL.UInt16; + + -- Bits 79:64 of private per-device random number (ECC) + type RANDID4_Register is record + -- Read-only. + RANDID4 : RANDID4_RANDID4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID4_Register use record + RANDID4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID5_RANDID5_Field is HAL.UInt16; + + -- Bits 95:80 of private per-device random number (ECC) + type RANDID5_Register is record + -- Read-only. + RANDID5 : RANDID5_RANDID5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID5_Register use record + RANDID5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID6_RANDID6_Field is HAL.UInt16; + + -- Bits 111:96 of private per-device random number (ECC) + type RANDID6_Register is record + -- Read-only. + RANDID6 : RANDID6_RANDID6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID6_Register use record + RANDID6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype RANDID7_RANDID7_Field is HAL.UInt16; + + -- Bits 127:112 of private per-device random number (ECC) + type RANDID7_Register is record + -- Read-only. + RANDID7 : RANDID7_RANDID7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDID7_Register use record + RANDID7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ROSC_CALIB_ROSC_CALIB_Field is HAL.UInt16; + + -- Ring oscillator frequency in kHz, measured during manufacturing (ECC) + -- This is measured at 1.1 V, at room temperature, with the ROSC + -- configuration registers in their reset state. + type ROSC_CALIB_Register is record + -- Read-only. + ROSC_CALIB : ROSC_CALIB_ROSC_CALIB_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ROSC_CALIB_Register use record + ROSC_CALIB at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype LPOSC_CALIB_LPOSC_CALIB_Field is HAL.UInt16; + + -- Low-power oscillator frequency in Hz, measured during manufacturing + -- (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim + -- register in its reset state. + type LPOSC_CALIB_Register is record + -- Read-only. + LPOSC_CALIB : LPOSC_CALIB_LPOSC_CALIB_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LPOSC_CALIB_Register use record + LPOSC_CALIB at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype NUM_GPIOS_NUM_GPIOS_Field is HAL.UInt8; + + -- The number of main user GPIOs (bank 0). Should read 48 in the QFN80 + -- package, and 30 in the QFN60 package. (ECC) + type NUM_GPIOS_Register is record + -- Read-only. + NUM_GPIOS : NUM_GPIOS_NUM_GPIOS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NUM_GPIOS_Register use record + NUM_GPIOS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype INFO_CRC0_INFO_CRC0_Field is HAL.UInt16; + + -- Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + -- 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR + -- all-ones) (ECC) + type INFO_CRC0_Register is record + -- Read-only. + INFO_CRC0 : INFO_CRC0_INFO_CRC0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INFO_CRC0_Register use record + INFO_CRC0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INFO_CRC1_INFO_CRC1_Field is HAL.UInt16; + + -- Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + type INFO_CRC1_Register is record + -- Read-only. + INFO_CRC1 : INFO_CRC1_INFO_CRC1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INFO_CRC1_Register use record + INFO_CRC1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Page 0 critical boot flags (RBIT-8) + type CRIT0_Register is record + -- Read-only. Permanently disable ARM processors (Cortex-M33) + ARM_DISABLE : Boolean; + -- Read-only. Permanently disable RISC-V processors (Hazard3) + RISCV_DISABLE : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_Register use record + ARM_DISABLE at 0 range 0 .. 0; + RISCV_DISABLE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype CRIT0_R1_CRIT0_R1_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R1_Register is record + -- Read-only. + CRIT0_R1 : CRIT0_R1_CRIT0_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R1_Register use record + CRIT0_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R2_CRIT0_R2_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R2_Register is record + -- Read-only. + CRIT0_R2 : CRIT0_R2_CRIT0_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R2_Register use record + CRIT0_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R3_CRIT0_R3_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R3_Register is record + -- Read-only. + CRIT0_R3 : CRIT0_R3_CRIT0_R3_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R3_Register use record + CRIT0_R3 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R4_CRIT0_R4_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R4_Register is record + -- Read-only. + CRIT0_R4 : CRIT0_R4_CRIT0_R4_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R4_Register use record + CRIT0_R4 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R5_CRIT0_R5_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R5_Register is record + -- Read-only. + CRIT0_R5 : CRIT0_R5_CRIT0_R5_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R5_Register use record + CRIT0_R5 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R6_CRIT0_R6_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R6_Register is record + -- Read-only. + CRIT0_R6 : CRIT0_R6_CRIT0_R6_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R6_Register use record + CRIT0_R6 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT0_R7_CRIT0_R7_Field is HAL.UInt24; + + -- Redundant copy of CRIT0 + type CRIT0_R7_Register is record + -- Read-only. + CRIT0_R7 : CRIT0_R7_CRIT0_R7_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT0_R7_Register use record + CRIT0_R7 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_GLITCH_DETECTOR_SENS_Field is HAL.UInt2; + + -- Page 1 critical boot flags (RBIT-8) + type CRIT1_Register is record + -- Read-only. Enable boot signature enforcement, and permanently disable + -- the RISC-V cores. + SECURE_BOOT_ENABLE : Boolean; + -- Read-only. Disable Secure debug access + SECURE_DEBUG_DISABLE : Boolean; + -- Read-only. Disable all debug access + DEBUG_DISABLE : Boolean; + -- Read-only. Set the default boot architecture, 0=ARM 1=RISC-V. Ignored + -- if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + BOOT_ARCH : Boolean; + -- Read-only. Arm the glitch detectors to reset the system if an + -- abnormal clock/power event is observed. + GLITCH_DETECTOR_ENABLE : Boolean; + -- Read-only. Increase the sensitivity of the glitch detectors from + -- their default. + GLITCH_DETECTOR_SENS : CRIT1_GLITCH_DETECTOR_SENS_Field; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_Register use record + SECURE_BOOT_ENABLE at 0 range 0 .. 0; + SECURE_DEBUG_DISABLE at 0 range 1 .. 1; + DEBUG_DISABLE at 0 range 2 .. 2; + BOOT_ARCH at 0 range 3 .. 3; + GLITCH_DETECTOR_ENABLE at 0 range 4 .. 4; + GLITCH_DETECTOR_SENS at 0 range 5 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype CRIT1_R1_CRIT1_R1_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R1_Register is record + -- Read-only. + CRIT1_R1 : CRIT1_R1_CRIT1_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R1_Register use record + CRIT1_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R2_CRIT1_R2_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R2_Register is record + -- Read-only. + CRIT1_R2 : CRIT1_R2_CRIT1_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R2_Register use record + CRIT1_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R3_CRIT1_R3_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R3_Register is record + -- Read-only. + CRIT1_R3 : CRIT1_R3_CRIT1_R3_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R3_Register use record + CRIT1_R3 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R4_CRIT1_R4_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R4_Register is record + -- Read-only. + CRIT1_R4 : CRIT1_R4_CRIT1_R4_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R4_Register use record + CRIT1_R4 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R5_CRIT1_R5_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R5_Register is record + -- Read-only. + CRIT1_R5 : CRIT1_R5_CRIT1_R5_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R5_Register use record + CRIT1_R5 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R6_CRIT1_R6_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R6_Register is record + -- Read-only. + CRIT1_R6 : CRIT1_R6_CRIT1_R6_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R6_Register use record + CRIT1_R6 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype CRIT1_R7_CRIT1_R7_Field is HAL.UInt24; + + -- Redundant copy of CRIT1 + type CRIT1_R7_Register is record + -- Read-only. + CRIT1_R7 : CRIT1_R7_CRIT1_R7_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CRIT1_R7_Register use record + CRIT1_R7 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + -- always supersede enables. Enables are provided where there are other + -- configurations in OTP that must be valid. (RBIT-3) + type BOOT_FLAGS0_Register is record + -- Read-only. + DISABLE_BOOTSEL_EXEC2 : Boolean; + -- Read-only. Enable bootloader activity LED. If set, bootsel_led_cfg is + -- assumed to be valid + ENABLE_BOOTSEL_LED : Boolean; + -- Read-only. Enable loading of the non-default XOSC and PLL + -- configuration before entering BOOTSEL mode. Ensure that + -- BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before + -- setting this bit. If this bit is set, user software may use the + -- contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency + -- based on the fixed USB boot frequency of 48 MHz. + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG : Boolean; + -- Read-only. If 1, configure the QSPI pads for 1.8 V operation when + -- accessing flash for the first time from the bootrom, using the + -- VOLTAGE_SELECT register for the QSPI pads bank. This slightly + -- improves the input timing of the pads at low voltages, but does not + -- affect their output characteristics. If 0, leave VOLTAGE_SELECT in + -- its reset state (suitable for operation at and above 2.5 V) + FLASH_IO_VOLTAGE_1V8 : Boolean; + -- Read-only. Enable quartering of ROSC divisor during signature check, + -- to reduce secure boot time + FAST_SIGCHECK_ROSC_DIV : Boolean; + -- Read-only. Mark FLASH_DEVINFO as containing valid, ECC'd data which + -- describes external flash devices. + FLASH_DEVINFO_ENABLE : Boolean; + -- Read-only. Override the limit for default flash metadata scanning. + -- The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure + -- FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + OVERRIDE_FLASH_PARTITION_SLOT_SIZE : Boolean; + -- Read-only. Restrict flash boot path to use of a single binary at the + -- start of flash + SINGLE_FLASH_BINARY : Boolean; + -- Read-only. Disable auto-switch of CPU architecture on boot when the + -- (only) binary to be booted is for the other Arm/RISC-V architecture + -- and both architectures are enabled + DISABLE_AUTO_SWITCH_ARCH : Boolean; + -- Read-only. Require a partition table to be signed + SECURE_PARTITION_TABLE : Boolean; + -- Read-only. Require a partition table to be hashed (if not signed) + HASHED_PARTITION_TABLE : Boolean; + -- Read-only. Require binaries to have a rollback version. Set + -- automatically the first time a binary with a rollback version is + -- booted. + ROLLBACK_REQUIRED : Boolean; + -- Read-only. + DISABLE_FLASH_BOOT : Boolean; + -- Read-only. Takes precedence over ENABLE_OTP_BOOT. + DISABLE_OTP_BOOT : Boolean; + -- Read-only. Enable OTP boot. A number of OTP rows specified by + -- OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM + -- location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded + -- program image is stored with ECC, 16 bits per row, and must contain a + -- valid IMAGE_DEF. Do not set this bit without first programming an + -- image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 + -- and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even + -- numbers of OTP rows. Equivalently, the image must be a multiple of 32 + -- bits in size, and must start at a 32-bit-aligned address in the ECC + -- read data address window. + ENABLE_OTP_BOOT : Boolean; + -- Read-only. + DISABLE_POWER_SCRATCH : Boolean; + -- Read-only. + DISABLE_WATCHDOG_SCRATCH : Boolean; + -- Read-only. + DISABLE_BOOTSEL_USB_MSD_IFC : Boolean; + -- Read-only. + DISABLE_BOOTSEL_USB_PICOBOOT_IFC : Boolean; + -- Read-only. + DISABLE_BOOTSEL_UART_BOOT : Boolean; + -- Read-only. Disable all access to XIP after entering an SRAM binary. + -- Note that this will cause bootrom APIs that access XIP to fail, + -- including APIs that interact with the partition table. + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY : Boolean; + -- Read-only. + DISABLE_SRAM_WINDOW_BOOT : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS0_Register use record + DISABLE_BOOTSEL_EXEC2 at 0 range 0 .. 0; + ENABLE_BOOTSEL_LED at 0 range 1 .. 1; + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG at 0 range 2 .. 2; + FLASH_IO_VOLTAGE_1V8 at 0 range 3 .. 3; + FAST_SIGCHECK_ROSC_DIV at 0 range 4 .. 4; + FLASH_DEVINFO_ENABLE at 0 range 5 .. 5; + OVERRIDE_FLASH_PARTITION_SLOT_SIZE at 0 range 6 .. 6; + SINGLE_FLASH_BINARY at 0 range 7 .. 7; + DISABLE_AUTO_SWITCH_ARCH at 0 range 8 .. 8; + SECURE_PARTITION_TABLE at 0 range 9 .. 9; + HASHED_PARTITION_TABLE at 0 range 10 .. 10; + ROLLBACK_REQUIRED at 0 range 11 .. 11; + DISABLE_FLASH_BOOT at 0 range 12 .. 12; + DISABLE_OTP_BOOT at 0 range 13 .. 13; + ENABLE_OTP_BOOT at 0 range 14 .. 14; + DISABLE_POWER_SCRATCH at 0 range 15 .. 15; + DISABLE_WATCHDOG_SCRATCH at 0 range 16 .. 16; + DISABLE_BOOTSEL_USB_MSD_IFC at 0 range 17 .. 17; + DISABLE_BOOTSEL_USB_PICOBOOT_IFC at 0 range 18 .. 18; + DISABLE_BOOTSEL_UART_BOOT at 0 range 19 .. 19; + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY at 0 range 20 .. 20; + DISABLE_SRAM_WINDOW_BOOT at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype BOOT_FLAGS0_R1_BOOT_FLAGS0_R1_Field is HAL.UInt24; + + -- Redundant copy of BOOT_FLAGS0 + type BOOT_FLAGS0_R1_Register is record + -- Read-only. + BOOT_FLAGS0_R1 : BOOT_FLAGS0_R1_BOOT_FLAGS0_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS0_R1_Register use record + BOOT_FLAGS0_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype BOOT_FLAGS0_R2_BOOT_FLAGS0_R2_Field is HAL.UInt24; + + -- Redundant copy of BOOT_FLAGS0 + type BOOT_FLAGS0_R2_Register is record + -- Read-only. + BOOT_FLAGS0_R2 : BOOT_FLAGS0_R2_BOOT_FLAGS0_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS0_R2_Register use record + BOOT_FLAGS0_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype BOOT_FLAGS1_KEY_VALID_Field is HAL.UInt4; + subtype BOOT_FLAGS1_KEY_INVALID_Field is HAL.UInt4; + subtype BOOT_FLAGS1_DOUBLE_TAP_DELAY_Field is HAL.UInt3; + + -- Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + -- always supersede enables. Enables are provided where there are other + -- configurations in OTP that must be valid. (RBIT-3) + type BOOT_FLAGS1_Register is record + -- Read-only. Mark each of the possible boot keys as valid. The bootrom + -- will check signatures against all valid boot keys, and ignore invalid + -- boot keys. Each bit in this field corresponds to one of the four + -- 256-bit boot key hashes that may be stored in page 2 of the OTP. A + -- KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. + -- Boot keys are considered valid only when KEY_VALID is set and + -- KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does + -- not contain a valid SHA-256 hash of your secp256k1 public key. Verify + -- keys after programming, before setting the KEY_VALID bits -- a boot + -- key with uncorrectable ECC faults will render your device unbootable + -- if secure boot is enabled. Do not enable secure boot without first + -- installing a valid key. This will render your device unbootable. + KEY_VALID : BOOT_FLAGS1_KEY_VALID_Field; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Mark a boot key as invalid, or prevent it from ever + -- becoming valid. The bootrom will ignore any boot key marked as + -- invalid during secure boot signature checks. Each bit in this field + -- corresponds to one of the four 256-bit boot key hashes that may be + -- stored in page 2 of the OTP. When provisioning boot keys, it's + -- recommended to mark any boot key slots you don't intend to use as + -- KEY_INVALID, so that spurious keys can not be installed at a later + -- time. + KEY_INVALID : BOOT_FLAGS1_KEY_INVALID_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Adjust how long to wait for a second reset when double tap + -- BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 + -- milliseconds, and each unit of this field adds an additional 50 + -- milliseconds. For example, settings this field to its maximum value + -- of 7 will cause the chip to wait for 400 milliseconds at boot to + -- check for a second reset which requests entry to BOOTSEL mode. 200 + -- milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + DOUBLE_TAP_DELAY : BOOT_FLAGS1_DOUBLE_TAP_DELAY_Field; + -- Read-only. Enable entering BOOTSEL mode via double-tap of the + -- RUN/RSTn pin. Adds a significant delay to boot time, as configured by + -- DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. + -- following a reset) to see if a second reset is applied soon + -- afterward. The second reset is detected by the bootrom with help of + -- the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the + -- external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to + -- await further instruction over USB or UART. + DOUBLE_TAP : Boolean; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS1_Register use record + KEY_VALID at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + KEY_INVALID at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + DOUBLE_TAP_DELAY at 0 range 16 .. 18; + DOUBLE_TAP at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype BOOT_FLAGS1_R1_BOOT_FLAGS1_R1_Field is HAL.UInt24; + + -- Redundant copy of BOOT_FLAGS1 + type BOOT_FLAGS1_R1_Register is record + -- Read-only. + BOOT_FLAGS1_R1 : BOOT_FLAGS1_R1_BOOT_FLAGS1_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS1_R1_Register use record + BOOT_FLAGS1_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype BOOT_FLAGS1_R2_BOOT_FLAGS1_R2_Field is HAL.UInt24; + + -- Redundant copy of BOOT_FLAGS1 + type BOOT_FLAGS1_R2_Register is record + -- Read-only. + BOOT_FLAGS1_R2 : BOOT_FLAGS1_R2_BOOT_FLAGS1_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOT_FLAGS1_R2_Register use record + BOOT_FLAGS1_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION0_DEFAULT_BOOT_VERSION0_Field is HAL.UInt24; + + -- Default boot version thermometer counter, bits 23:0 (RBIT-3) + type DEFAULT_BOOT_VERSION0_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION0 : DEFAULT_BOOT_VERSION0_DEFAULT_BOOT_VERSION0_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION0_Register use record + DEFAULT_BOOT_VERSION0 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION0_R1_DEFAULT_BOOT_VERSION0_R1_Field is + HAL.UInt24; + + -- Redundant copy of DEFAULT_BOOT_VERSION0 + type DEFAULT_BOOT_VERSION0_R1_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION0_R1 : DEFAULT_BOOT_VERSION0_R1_DEFAULT_BOOT_VERSION0_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION0_R1_Register use record + DEFAULT_BOOT_VERSION0_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION0_R2_DEFAULT_BOOT_VERSION0_R2_Field is + HAL.UInt24; + + -- Redundant copy of DEFAULT_BOOT_VERSION0 + type DEFAULT_BOOT_VERSION0_R2_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION0_R2 : DEFAULT_BOOT_VERSION0_R2_DEFAULT_BOOT_VERSION0_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION0_R2_Register use record + DEFAULT_BOOT_VERSION0_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION1_DEFAULT_BOOT_VERSION1_Field is HAL.UInt24; + + -- Default boot version thermometer counter, bits 47:24 (RBIT-3) + type DEFAULT_BOOT_VERSION1_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION1 : DEFAULT_BOOT_VERSION1_DEFAULT_BOOT_VERSION1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION1_Register use record + DEFAULT_BOOT_VERSION1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION1_R1_DEFAULT_BOOT_VERSION1_R1_Field is + HAL.UInt24; + + -- Redundant copy of DEFAULT_BOOT_VERSION1 + type DEFAULT_BOOT_VERSION1_R1_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION1_R1 : DEFAULT_BOOT_VERSION1_R1_DEFAULT_BOOT_VERSION1_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION1_R1_Register use record + DEFAULT_BOOT_VERSION1_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DEFAULT_BOOT_VERSION1_R2_DEFAULT_BOOT_VERSION1_R2_Field is + HAL.UInt24; + + -- Redundant copy of DEFAULT_BOOT_VERSION1 + type DEFAULT_BOOT_VERSION1_R2_Register is record + -- Read-only. + DEFAULT_BOOT_VERSION1_R2 : DEFAULT_BOOT_VERSION1_R2_DEFAULT_BOOT_VERSION1_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEFAULT_BOOT_VERSION1_R2_Register use record + DEFAULT_BOOT_VERSION1_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype FLASH_DEVINFO_CS1_GPIO_Field is HAL.UInt6; + + -- The size of the flash/PSRAM device on chip select 0 (addressable at + -- 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of + -- zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For + -- example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 + -- megabytes is encoded with a CS0_SIZE value of 12. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is + -- used. + type FLASH_DEVINFO_CS0_SIZE_Field is + (NONE, + Val_8K, + Val_16K, + Val_32K, + Val_64k, + Val_128K, + Val_256K, + Val_512K, + Val_1M, + Val_2M, + Val_4M, + Val_8M, + Val_16M) + with Size => 4; + for FLASH_DEVINFO_CS0_SIZE_Field use + (NONE => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64k => 4, + Val_128K => 5, + Val_256K => 6, + Val_512K => 7, + Val_1M => 8, + Val_2M => 9, + Val_4M => 10, + Val_8M => 11, + Val_16M => 12); + + -- The size of the flash/PSRAM device on chip select 1 (addressable at + -- 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of + -- zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For + -- example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 + -- megabytes is encoded with a CS1_SIZE value of 12. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + type FLASH_DEVINFO_CS1_SIZE_Field is + (NONE, + Val_8K, + Val_16K, + Val_32K, + Val_64k, + Val_128K, + Val_256K, + Val_512K, + Val_1M, + Val_2M, + Val_4M, + Val_8M, + Val_16M) + with Size => 4; + for FLASH_DEVINFO_CS1_SIZE_Field use + (NONE => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64k => 4, + Val_128K => 5, + Val_256K => 6, + Val_512K => 7, + Val_1M => 8, + Val_2M => 9, + Val_4M => 10, + Val_8M => 11, + Val_16M => 12); + + -- Stores information about external flash device(s). (ECC) Assumed to be + -- valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + type FLASH_DEVINFO_Register is record + -- Read-only. Indicate a GPIO number to be used for the secondary flash + -- chip select (CS1), which selects the external QSPI device mapped at + -- system addresses 0x11000000 through 0x11ffffff. There is no such + -- configuration for CS0, as the primary chip select has a dedicated + -- pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + -- Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will + -- automatically configure this GPIO as a second chip select upon + -- entering the flash boot path, or entering any other path that may use + -- the QSPI flash interface, such as BOOTSEL mode (nsboot). + CS1_GPIO : FLASH_DEVINFO_CS1_GPIO_Field; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. If true, all attached devices are assumed to support (or + -- ignore, in the case of PSRAM) a block erase command with a command + -- prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost + -- all 25-series flash devices support this command. If set, the bootrom + -- will use the D8h erase command where it is able, to accelerate bulk + -- erase operations. This makes flash programming faster. When + -- BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to + -- false. + D8H_ERASE_SUPPORTED : Boolean; + -- Read-only. The size of the flash/PSRAM device on chip select 0 + -- (addressable at 0x10000000 through 0x10ffffff). A value of zero is + -- decoded as a size of zero (no device). Nonzero values are decoded as + -- 4kiB << CS0_SIZE. For example, four megabytes is encoded with a + -- CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE + -- value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a + -- default of 12 (16 MiB) is used. + CS0_SIZE : FLASH_DEVINFO_CS0_SIZE_Field; + -- Read-only. The size of the flash/PSRAM device on chip select 1 + -- (addressable at 0x11000000 through 0x11ffffff). A value of zero is + -- decoded as a size of zero (no device). Nonzero values are decoded as + -- 4kiB << CS1_SIZE. For example, four megabytes is encoded with a + -- CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE + -- value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a + -- default of zero is used. + CS1_SIZE : FLASH_DEVINFO_CS1_SIZE_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FLASH_DEVINFO_Register use record + CS1_GPIO at 0 range 0 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + D8H_ERASE_SUPPORTED at 0 range 7 .. 7; + CS0_SIZE at 0 range 8 .. 11; + CS1_SIZE at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Field is + HAL.UInt16; + + -- Gap between partition table slot 0 and slot 1 at the start of flash (the + -- default size is 4096 bytes) (ECC) Enabled by the + -- OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * + -- (value + 1) + type FLASH_PARTITION_SLOT_SIZE_Register is record + -- Read-only. + FLASH_PARTITION_SLOT_SIZE : FLASH_PARTITION_SLOT_SIZE_FLASH_PARTITION_SLOT_SIZE_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FLASH_PARTITION_SLOT_SIZE_Register use record + FLASH_PARTITION_SLOT_SIZE at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTSEL_LED_CFG_PIN_Field is HAL.UInt6; + + -- Pin configuration for LED status, used by USB bootloader. (ECC) Must be + -- valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + type BOOTSEL_LED_CFG_Register is record + -- Read-only. GPIO index to use for bootloader activity LED. + PIN : BOOTSEL_LED_CFG_PIN_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. LED is active-low. (Default: active-high.) + ACTIVELOW : Boolean; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_LED_CFG_Register use record + PIN at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + ACTIVELOW at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype BOOTSEL_PLL_CFG_FBDIV_Field is HAL.UInt9; + -- BOOTSEL_PLL_CFG_POSTDIV array element + subtype BOOTSEL_PLL_CFG_POSTDIV_Element is HAL.UInt3; + + -- BOOTSEL_PLL_CFG_POSTDIV array + type BOOTSEL_PLL_CFG_POSTDIV_Field_Array is array (1 .. 2) + of BOOTSEL_PLL_CFG_POSTDIV_Element + with Component_Size => 3, Size => 6; + + -- Type definition for BOOTSEL_PLL_CFG_POSTDIV + type BOOTSEL_PLL_CFG_POSTDIV_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- POSTDIV as a value + Val : HAL.UInt6; + when True => + -- POSTDIV as an array + Arr : BOOTSEL_PLL_CFG_POSTDIV_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for BOOTSEL_PLL_CFG_POSTDIV_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- Optional PLL configuration for BOOTSEL mode. (ECC) This should be + -- configured to produce an exact 48 MHz based on the crystal oscillator + -- frequency. User mode software may also use this value to calculate the + -- expected crystal frequency based on an assumed 48 MHz PLL output. If no + -- configuration is given, the crystal is assumed to be 12 MHz. The PLL + -- frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + -- x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be + -- calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x + -- POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in + -- this OTP location is the actual divisor value minus one.) Used if and + -- only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + -- That bit should be set only after this row and BOOTSEL_XOSC_CFG are both + -- correctly programmed. + type BOOTSEL_PLL_CFG_Register is record + -- Read-only. PLL feedback divisor, in the range 16..320 inclusive. + FBDIV : BOOTSEL_PLL_CFG_FBDIV_Field; + -- Read-only. PLL post-divide 1 divisor, in the range 1..7 inclusive. + POSTDIV : BOOTSEL_PLL_CFG_POSTDIV_Field; + -- Read-only. PLL reference divisor, minus one. Programming a value of 0 + -- means a reference divisor of 1. Programming a value of 1 means a + -- reference divisor of 2 (for exceptionally fast XIN inputs) + REFDIV : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_PLL_CFG_Register use record + FBDIV at 0 range 0 .. 8; + POSTDIV at 0 range 9 .. 14; + REFDIV at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTSEL_XOSC_CFG_STARTUP_Field is HAL.UInt14; + + -- Value of the XOSC_CTRL_FREQ_RANGE register. + type BOOTSEL_XOSC_CFG_RANGE_Field is + (Val_1_15MHZ, + Val_10_30MHZ, + Val_25_60MHZ, + Val_40_100MHZ) + with Size => 2; + for BOOTSEL_XOSC_CFG_RANGE_Field use + (Val_1_15MHZ => 0, + Val_10_30MHZ => 1, + Val_25_60MHZ => 2, + Val_40_100MHZ => 3); + + -- Non-default crystal oscillator configuration for the USB bootloader. + -- (ECC) These values may also be used by user code configuring the crystal + -- oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + -- is set in BOOT_FLAGS0. That bit should be set only after this row and + -- BOOTSEL_PLL_CFG are both correctly programmed. + type BOOTSEL_XOSC_CFG_Register is record + -- Read-only. Value of the XOSC_STARTUP register + STARTUP : BOOTSEL_XOSC_CFG_STARTUP_Field; + -- Read-only. Value of the XOSC_CTRL_FREQ_RANGE register. + RANGE_k : BOOTSEL_XOSC_CFG_RANGE_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTSEL_XOSC_CFG_Register use record + STARTUP at 0 range 0 .. 13; + RANGE_k at 0 range 14 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- USB boot specific feature flags (RBIT-3) + type USB_BOOT_FLAGS_Register is record + -- Read-only. valid flag for USB_DEVICE_VID_VALUE entry of the + -- USB_WHITE_LABEL struct (index 0) + WL_USB_DEVICE_VID_VALUE_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_PID_VALUE entry of the + -- USB_WHITE_LABEL struct (index 1) + WL_USB_DEVICE_PID_VALUE_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the + -- USB_WHITE_LABEL struct (index 2) + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_LANG_ID_VALUE entry of the + -- USB_WHITE_LABEL struct (index 3) + WL_USB_DEVICE_LANG_ID_VALUE_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 4) + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 5) + WL_USB_DEVICE_PRODUCT_STRDEF_VALID : Boolean; + -- Read-only. valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of + -- the USB_WHITE_LABEL struct (index 6) + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID : Boolean; + -- Read-only. valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + -- entry of the USB_WHITE_LABEL struct (index 7) + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID : Boolean; + -- Read-only. valid flag for VOLUME_LABEL_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 8) + WL_VOLUME_LABEL_STRDEF_VALID : Boolean; + -- Read-only. valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 9) + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID : Boolean; + -- Read-only. valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 10) + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID : Boolean; + -- Read-only. valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 11) + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID : Boolean; + -- Read-only. valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 12) + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID : Boolean; + -- Read-only. valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 13) + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID : Boolean; + -- Read-only. valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 14) + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID : Boolean; + -- Read-only. valid flag for the USB_WHITE_LABEL_ADDR field + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID : Boolean; + -- unspecified + Reserved_16_21 : HAL.UInt6; + -- Read-only. valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the + -- USB_WHITE_LABEL struct (index 15) + WHITE_LABEL_ADDR_VALID : Boolean; + -- Read-only. Swap DM/DP during USB boot, to support board layouts with + -- mirrored USB routing (deliberate or accidental). + DP_DM_SWAP : Boolean; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_BOOT_FLAGS_Register use record + WL_USB_DEVICE_VID_VALUE_VALID at 0 range 0 .. 0; + WL_USB_DEVICE_PID_VALUE_VALID at 0 range 1 .. 1; + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID at 0 range 2 .. 2; + WL_USB_DEVICE_LANG_ID_VALUE_VALID at 0 range 3 .. 3; + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID at 0 range 4 .. 4; + WL_USB_DEVICE_PRODUCT_STRDEF_VALID at 0 range 5 .. 5; + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID at 0 range 6 .. 6; + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID at 0 range 7 .. 7; + WL_VOLUME_LABEL_STRDEF_VALID at 0 range 8 .. 8; + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID at 0 range 9 .. 9; + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID at 0 range 10 .. 10; + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID at 0 range 11 .. 11; + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID at 0 range 12 .. 12; + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID at 0 range 13 .. 13; + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID at 0 range 14 .. 14; + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID at 0 range 15 .. 15; + Reserved_16_21 at 0 range 16 .. 21; + WHITE_LABEL_ADDR_VALID at 0 range 22 .. 22; + DP_DM_SWAP at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USB_BOOT_FLAGS_R1_USB_BOOT_FLAGS_R1_Field is HAL.UInt24; + + -- Redundant copy of USB_BOOT_FLAGS + type USB_BOOT_FLAGS_R1_Register is record + -- Read-only. + USB_BOOT_FLAGS_R1 : USB_BOOT_FLAGS_R1_USB_BOOT_FLAGS_R1_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_BOOT_FLAGS_R1_Register use record + USB_BOOT_FLAGS_R1 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USB_BOOT_FLAGS_R2_USB_BOOT_FLAGS_R2_Field is HAL.UInt24; + + -- Redundant copy of USB_BOOT_FLAGS + type USB_BOOT_FLAGS_R2_Register is record + -- Read-only. + USB_BOOT_FLAGS_R2 : USB_BOOT_FLAGS_R2_USB_BOOT_FLAGS_R2_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_BOOT_FLAGS_R2_Register use record + USB_BOOT_FLAGS_R2 at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + type USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Field is + (INDEX_USB_DEVICE_VID_VALUE, + INDEX_USB_DEVICE_PID_VALUE, + INDEX_USB_DEVICE_BCD_DEVICE_VALUE, + INDEX_USB_DEVICE_LANG_ID_VALUE, + INDEX_USB_DEVICE_MANUFACTURER_STRDEF, + INDEX_USB_DEVICE_PRODUCT_STRDEF, + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF, + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES, + INDEX_VOLUME_LABEL_STRDEF, + INDEX_SCSI_INQUIRY_VENDOR_STRDEF, + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF, + INDEX_SCSI_INQUIRY_VERSION_STRDEF, + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF, + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF, + INDEX_INFO_UF2_TXT_MODEL_STRDEF, + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF) + with Size => 16; + for USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Field use + (INDEX_USB_DEVICE_VID_VALUE => 0, + INDEX_USB_DEVICE_PID_VALUE => 1, + INDEX_USB_DEVICE_BCD_DEVICE_VALUE => 2, + INDEX_USB_DEVICE_LANG_ID_VALUE => 3, + INDEX_USB_DEVICE_MANUFACTURER_STRDEF => 4, + INDEX_USB_DEVICE_PRODUCT_STRDEF => 5, + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF => 6, + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES => 7, + INDEX_VOLUME_LABEL_STRDEF => 8, + INDEX_SCSI_INQUIRY_VENDOR_STRDEF => 9, + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF => 10, + INDEX_SCSI_INQUIRY_VERSION_STRDEF => 11, + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF => 12, + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF => 13, + INDEX_INFO_UF2_TXT_MODEL_STRDEF => 14, + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF => 15); + + -- Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table + -- has 16 rows, each of which are also ECC and marked valid by the + -- corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either + -- _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as + -- a pointers to a string value. The value stored in a _STRDEF is two + -- separate bytes: The low seven bits of the first (LSB) byte indicates the + -- number of characters in the string, and the top bit of the first (LSB) + -- byte if set to indicate that each character in the string is two bytes + -- (Unicode) versus one byte if unset. The second (MSB) byte represents the + -- location of the string data, and is encoded as the number of rows from + -- this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is + -- USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding + -- valid bit enables replacing the default value for the corresponding item + -- provided by the boot rom. Note that Unicode _STRDEFs are only supported + -- for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and + -- USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if + -- specified for other fields, and non-unicode values for these three items + -- will be converted to Unicode characters by setting the upper 8 bits to + -- zero. Note that if the USB_WHITE_LABEL structure or the corresponding + -- strings are not readable by BOOTSEL mode based on OTP permissions, or if + -- alignment requirements are not met, then the corresponding default + -- values are used. The index values indicate where each field is located + -- (row USB_WHITE_LABEL_ADDR value + index): + type USB_WHITE_LABEL_ADDR_Register is record + -- Read-only. + USB_WHITE_LABEL_ADDR : USB_WHITE_LABEL_ADDR_USB_WHITE_LABEL_ADDR_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_WHITE_LABEL_ADDR_Register use record + USB_WHITE_LABEL_ADDR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype OTPBOOT_SRC_OTPBOOT_SRC_Field is HAL.UInt16; + + -- OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the + -- bootrom will load from this location into SRAM and then directly enter + -- the loaded image. Note that the image must be signed if + -- SECURE_BOOT_ENABLE is set. The image itself is assumed to be + -- ECC-protected. This must be an even number. Equivalently, the OTP boot + -- image must start at a word-aligned location in the ECC read data address + -- window. + type OTPBOOT_SRC_Register is record + -- Read-only. + OTPBOOT_SRC : OTPBOOT_SRC_OTPBOOT_SRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTPBOOT_SRC_Register use record + OTPBOOT_SRC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype OTPBOOT_LEN_OTPBOOT_LEN_Field is HAL.UInt16; + + -- Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. + -- The total image size must be a multiple of 4 bytes (32 bits). + type OTPBOOT_LEN_Register is record + -- Read-only. + OTPBOOT_LEN : OTPBOOT_LEN_OTPBOOT_LEN_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTPBOOT_LEN_Register use record + OTPBOOT_LEN at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype OTPBOOT_DST0_OTPBOOT_DST0_Field is HAL.UInt16; + + -- Bits 15:0 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + type OTPBOOT_DST0_Register is record + -- Read-only. + OTPBOOT_DST0 : OTPBOOT_DST0_OTPBOOT_DST0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTPBOOT_DST0_Register use record + OTPBOOT_DST0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype OTPBOOT_DST1_OTPBOOT_DST1_Field is HAL.UInt16; + + -- Bits 31:16 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + type OTPBOOT_DST1_Register is record + -- Read-only. + OTPBOOT_DST1 : OTPBOOT_DST1_OTPBOOT_DST1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for OTPBOOT_DST1_Register use record + OTPBOOT_DST1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_0_BOOTKEY0_0_Field is HAL.UInt16; + + -- Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_0_Register is record + -- Read-only. + BOOTKEY0_0 : BOOTKEY0_0_BOOTKEY0_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_0_Register use record + BOOTKEY0_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_1_BOOTKEY0_1_Field is HAL.UInt16; + + -- Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_1_Register is record + -- Read-only. + BOOTKEY0_1 : BOOTKEY0_1_BOOTKEY0_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_1_Register use record + BOOTKEY0_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_2_BOOTKEY0_2_Field is HAL.UInt16; + + -- Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_2_Register is record + -- Read-only. + BOOTKEY0_2 : BOOTKEY0_2_BOOTKEY0_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_2_Register use record + BOOTKEY0_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_3_BOOTKEY0_3_Field is HAL.UInt16; + + -- Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_3_Register is record + -- Read-only. + BOOTKEY0_3 : BOOTKEY0_3_BOOTKEY0_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_3_Register use record + BOOTKEY0_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_4_BOOTKEY0_4_Field is HAL.UInt16; + + -- Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_4_Register is record + -- Read-only. + BOOTKEY0_4 : BOOTKEY0_4_BOOTKEY0_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_4_Register use record + BOOTKEY0_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_5_BOOTKEY0_5_Field is HAL.UInt16; + + -- Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_5_Register is record + -- Read-only. + BOOTKEY0_5 : BOOTKEY0_5_BOOTKEY0_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_5_Register use record + BOOTKEY0_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_6_BOOTKEY0_6_Field is HAL.UInt16; + + -- Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_6_Register is record + -- Read-only. + BOOTKEY0_6 : BOOTKEY0_6_BOOTKEY0_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_6_Register use record + BOOTKEY0_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_7_BOOTKEY0_7_Field is HAL.UInt16; + + -- Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_7_Register is record + -- Read-only. + BOOTKEY0_7 : BOOTKEY0_7_BOOTKEY0_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_7_Register use record + BOOTKEY0_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_8_BOOTKEY0_8_Field is HAL.UInt16; + + -- Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_8_Register is record + -- Read-only. + BOOTKEY0_8 : BOOTKEY0_8_BOOTKEY0_8_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_8_Register use record + BOOTKEY0_8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_9_BOOTKEY0_9_Field is HAL.UInt16; + + -- Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_9_Register is record + -- Read-only. + BOOTKEY0_9 : BOOTKEY0_9_BOOTKEY0_9_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_9_Register use record + BOOTKEY0_9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_10_BOOTKEY0_10_Field is HAL.UInt16; + + -- Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_10_Register is record + -- Read-only. + BOOTKEY0_10 : BOOTKEY0_10_BOOTKEY0_10_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_10_Register use record + BOOTKEY0_10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_11_BOOTKEY0_11_Field is HAL.UInt16; + + -- Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_11_Register is record + -- Read-only. + BOOTKEY0_11 : BOOTKEY0_11_BOOTKEY0_11_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_11_Register use record + BOOTKEY0_11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_12_BOOTKEY0_12_Field is HAL.UInt16; + + -- Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_12_Register is record + -- Read-only. + BOOTKEY0_12 : BOOTKEY0_12_BOOTKEY0_12_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_12_Register use record + BOOTKEY0_12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_13_BOOTKEY0_13_Field is HAL.UInt16; + + -- Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_13_Register is record + -- Read-only. + BOOTKEY0_13 : BOOTKEY0_13_BOOTKEY0_13_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_13_Register use record + BOOTKEY0_13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_14_BOOTKEY0_14_Field is HAL.UInt16; + + -- Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_14_Register is record + -- Read-only. + BOOTKEY0_14 : BOOTKEY0_14_BOOTKEY0_14_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_14_Register use record + BOOTKEY0_14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY0_15_BOOTKEY0_15_Field is HAL.UInt16; + + -- Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + type BOOTKEY0_15_Register is record + -- Read-only. + BOOTKEY0_15 : BOOTKEY0_15_BOOTKEY0_15_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY0_15_Register use record + BOOTKEY0_15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_0_BOOTKEY1_0_Field is HAL.UInt16; + + -- Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_0_Register is record + -- Read-only. + BOOTKEY1_0 : BOOTKEY1_0_BOOTKEY1_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_0_Register use record + BOOTKEY1_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_1_BOOTKEY1_1_Field is HAL.UInt16; + + -- Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_1_Register is record + -- Read-only. + BOOTKEY1_1 : BOOTKEY1_1_BOOTKEY1_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_1_Register use record + BOOTKEY1_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_2_BOOTKEY1_2_Field is HAL.UInt16; + + -- Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_2_Register is record + -- Read-only. + BOOTKEY1_2 : BOOTKEY1_2_BOOTKEY1_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_2_Register use record + BOOTKEY1_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_3_BOOTKEY1_3_Field is HAL.UInt16; + + -- Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_3_Register is record + -- Read-only. + BOOTKEY1_3 : BOOTKEY1_3_BOOTKEY1_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_3_Register use record + BOOTKEY1_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_4_BOOTKEY1_4_Field is HAL.UInt16; + + -- Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_4_Register is record + -- Read-only. + BOOTKEY1_4 : BOOTKEY1_4_BOOTKEY1_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_4_Register use record + BOOTKEY1_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_5_BOOTKEY1_5_Field is HAL.UInt16; + + -- Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_5_Register is record + -- Read-only. + BOOTKEY1_5 : BOOTKEY1_5_BOOTKEY1_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_5_Register use record + BOOTKEY1_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_6_BOOTKEY1_6_Field is HAL.UInt16; + + -- Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_6_Register is record + -- Read-only. + BOOTKEY1_6 : BOOTKEY1_6_BOOTKEY1_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_6_Register use record + BOOTKEY1_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_7_BOOTKEY1_7_Field is HAL.UInt16; + + -- Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_7_Register is record + -- Read-only. + BOOTKEY1_7 : BOOTKEY1_7_BOOTKEY1_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_7_Register use record + BOOTKEY1_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_8_BOOTKEY1_8_Field is HAL.UInt16; + + -- Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_8_Register is record + -- Read-only. + BOOTKEY1_8 : BOOTKEY1_8_BOOTKEY1_8_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_8_Register use record + BOOTKEY1_8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_9_BOOTKEY1_9_Field is HAL.UInt16; + + -- Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_9_Register is record + -- Read-only. + BOOTKEY1_9 : BOOTKEY1_9_BOOTKEY1_9_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_9_Register use record + BOOTKEY1_9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_10_BOOTKEY1_10_Field is HAL.UInt16; + + -- Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_10_Register is record + -- Read-only. + BOOTKEY1_10 : BOOTKEY1_10_BOOTKEY1_10_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_10_Register use record + BOOTKEY1_10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_11_BOOTKEY1_11_Field is HAL.UInt16; + + -- Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_11_Register is record + -- Read-only. + BOOTKEY1_11 : BOOTKEY1_11_BOOTKEY1_11_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_11_Register use record + BOOTKEY1_11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_12_BOOTKEY1_12_Field is HAL.UInt16; + + -- Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_12_Register is record + -- Read-only. + BOOTKEY1_12 : BOOTKEY1_12_BOOTKEY1_12_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_12_Register use record + BOOTKEY1_12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_13_BOOTKEY1_13_Field is HAL.UInt16; + + -- Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_13_Register is record + -- Read-only. + BOOTKEY1_13 : BOOTKEY1_13_BOOTKEY1_13_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_13_Register use record + BOOTKEY1_13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_14_BOOTKEY1_14_Field is HAL.UInt16; + + -- Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_14_Register is record + -- Read-only. + BOOTKEY1_14 : BOOTKEY1_14_BOOTKEY1_14_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_14_Register use record + BOOTKEY1_14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY1_15_BOOTKEY1_15_Field is HAL.UInt16; + + -- Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + type BOOTKEY1_15_Register is record + -- Read-only. + BOOTKEY1_15 : BOOTKEY1_15_BOOTKEY1_15_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY1_15_Register use record + BOOTKEY1_15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_0_BOOTKEY2_0_Field is HAL.UInt16; + + -- Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_0_Register is record + -- Read-only. + BOOTKEY2_0 : BOOTKEY2_0_BOOTKEY2_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_0_Register use record + BOOTKEY2_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_1_BOOTKEY2_1_Field is HAL.UInt16; + + -- Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_1_Register is record + -- Read-only. + BOOTKEY2_1 : BOOTKEY2_1_BOOTKEY2_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_1_Register use record + BOOTKEY2_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_2_BOOTKEY2_2_Field is HAL.UInt16; + + -- Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_2_Register is record + -- Read-only. + BOOTKEY2_2 : BOOTKEY2_2_BOOTKEY2_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_2_Register use record + BOOTKEY2_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_3_BOOTKEY2_3_Field is HAL.UInt16; + + -- Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_3_Register is record + -- Read-only. + BOOTKEY2_3 : BOOTKEY2_3_BOOTKEY2_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_3_Register use record + BOOTKEY2_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_4_BOOTKEY2_4_Field is HAL.UInt16; + + -- Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_4_Register is record + -- Read-only. + BOOTKEY2_4 : BOOTKEY2_4_BOOTKEY2_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_4_Register use record + BOOTKEY2_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_5_BOOTKEY2_5_Field is HAL.UInt16; + + -- Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_5_Register is record + -- Read-only. + BOOTKEY2_5 : BOOTKEY2_5_BOOTKEY2_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_5_Register use record + BOOTKEY2_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_6_BOOTKEY2_6_Field is HAL.UInt16; + + -- Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_6_Register is record + -- Read-only. + BOOTKEY2_6 : BOOTKEY2_6_BOOTKEY2_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_6_Register use record + BOOTKEY2_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_7_BOOTKEY2_7_Field is HAL.UInt16; + + -- Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_7_Register is record + -- Read-only. + BOOTKEY2_7 : BOOTKEY2_7_BOOTKEY2_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_7_Register use record + BOOTKEY2_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_8_BOOTKEY2_8_Field is HAL.UInt16; + + -- Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_8_Register is record + -- Read-only. + BOOTKEY2_8 : BOOTKEY2_8_BOOTKEY2_8_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_8_Register use record + BOOTKEY2_8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_9_BOOTKEY2_9_Field is HAL.UInt16; + + -- Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_9_Register is record + -- Read-only. + BOOTKEY2_9 : BOOTKEY2_9_BOOTKEY2_9_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_9_Register use record + BOOTKEY2_9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_10_BOOTKEY2_10_Field is HAL.UInt16; + + -- Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_10_Register is record + -- Read-only. + BOOTKEY2_10 : BOOTKEY2_10_BOOTKEY2_10_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_10_Register use record + BOOTKEY2_10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_11_BOOTKEY2_11_Field is HAL.UInt16; + + -- Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_11_Register is record + -- Read-only. + BOOTKEY2_11 : BOOTKEY2_11_BOOTKEY2_11_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_11_Register use record + BOOTKEY2_11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_12_BOOTKEY2_12_Field is HAL.UInt16; + + -- Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_12_Register is record + -- Read-only. + BOOTKEY2_12 : BOOTKEY2_12_BOOTKEY2_12_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_12_Register use record + BOOTKEY2_12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_13_BOOTKEY2_13_Field is HAL.UInt16; + + -- Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_13_Register is record + -- Read-only. + BOOTKEY2_13 : BOOTKEY2_13_BOOTKEY2_13_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_13_Register use record + BOOTKEY2_13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_14_BOOTKEY2_14_Field is HAL.UInt16; + + -- Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_14_Register is record + -- Read-only. + BOOTKEY2_14 : BOOTKEY2_14_BOOTKEY2_14_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_14_Register use record + BOOTKEY2_14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY2_15_BOOTKEY2_15_Field is HAL.UInt16; + + -- Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + type BOOTKEY2_15_Register is record + -- Read-only. + BOOTKEY2_15 : BOOTKEY2_15_BOOTKEY2_15_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY2_15_Register use record + BOOTKEY2_15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_0_BOOTKEY3_0_Field is HAL.UInt16; + + -- Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_0_Register is record + -- Read-only. + BOOTKEY3_0 : BOOTKEY3_0_BOOTKEY3_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_0_Register use record + BOOTKEY3_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_1_BOOTKEY3_1_Field is HAL.UInt16; + + -- Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_1_Register is record + -- Read-only. + BOOTKEY3_1 : BOOTKEY3_1_BOOTKEY3_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_1_Register use record + BOOTKEY3_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_2_BOOTKEY3_2_Field is HAL.UInt16; + + -- Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_2_Register is record + -- Read-only. + BOOTKEY3_2 : BOOTKEY3_2_BOOTKEY3_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_2_Register use record + BOOTKEY3_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_3_BOOTKEY3_3_Field is HAL.UInt16; + + -- Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_3_Register is record + -- Read-only. + BOOTKEY3_3 : BOOTKEY3_3_BOOTKEY3_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_3_Register use record + BOOTKEY3_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_4_BOOTKEY3_4_Field is HAL.UInt16; + + -- Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_4_Register is record + -- Read-only. + BOOTKEY3_4 : BOOTKEY3_4_BOOTKEY3_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_4_Register use record + BOOTKEY3_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_5_BOOTKEY3_5_Field is HAL.UInt16; + + -- Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_5_Register is record + -- Read-only. + BOOTKEY3_5 : BOOTKEY3_5_BOOTKEY3_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_5_Register use record + BOOTKEY3_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_6_BOOTKEY3_6_Field is HAL.UInt16; + + -- Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_6_Register is record + -- Read-only. + BOOTKEY3_6 : BOOTKEY3_6_BOOTKEY3_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_6_Register use record + BOOTKEY3_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_7_BOOTKEY3_7_Field is HAL.UInt16; + + -- Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_7_Register is record + -- Read-only. + BOOTKEY3_7 : BOOTKEY3_7_BOOTKEY3_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_7_Register use record + BOOTKEY3_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_8_BOOTKEY3_8_Field is HAL.UInt16; + + -- Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_8_Register is record + -- Read-only. + BOOTKEY3_8 : BOOTKEY3_8_BOOTKEY3_8_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_8_Register use record + BOOTKEY3_8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_9_BOOTKEY3_9_Field is HAL.UInt16; + + -- Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_9_Register is record + -- Read-only. + BOOTKEY3_9 : BOOTKEY3_9_BOOTKEY3_9_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_9_Register use record + BOOTKEY3_9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_10_BOOTKEY3_10_Field is HAL.UInt16; + + -- Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_10_Register is record + -- Read-only. + BOOTKEY3_10 : BOOTKEY3_10_BOOTKEY3_10_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_10_Register use record + BOOTKEY3_10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_11_BOOTKEY3_11_Field is HAL.UInt16; + + -- Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_11_Register is record + -- Read-only. + BOOTKEY3_11 : BOOTKEY3_11_BOOTKEY3_11_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_11_Register use record + BOOTKEY3_11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_12_BOOTKEY3_12_Field is HAL.UInt16; + + -- Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_12_Register is record + -- Read-only. + BOOTKEY3_12 : BOOTKEY3_12_BOOTKEY3_12_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_12_Register use record + BOOTKEY3_12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_13_BOOTKEY3_13_Field is HAL.UInt16; + + -- Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_13_Register is record + -- Read-only. + BOOTKEY3_13 : BOOTKEY3_13_BOOTKEY3_13_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_13_Register use record + BOOTKEY3_13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_14_BOOTKEY3_14_Field is HAL.UInt16; + + -- Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_14_Register is record + -- Read-only. + BOOTKEY3_14 : BOOTKEY3_14_BOOTKEY3_14_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_14_Register use record + BOOTKEY3_14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype BOOTKEY3_15_BOOTKEY3_15_Field is HAL.UInt16; + + -- Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + type BOOTKEY3_15_Register is record + -- Read-only. + BOOTKEY3_15 : BOOTKEY3_15_BOOTKEY3_15_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTKEY3_15_Register use record + BOOTKEY3_15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_0_KEY1_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 1 (ECC) + type KEY1_0_Register is record + -- Read-only. + KEY1_0 : KEY1_0_KEY1_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_0_Register use record + KEY1_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_1_KEY1_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 1 (ECC) + type KEY1_1_Register is record + -- Read-only. + KEY1_1 : KEY1_1_KEY1_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_1_Register use record + KEY1_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_2_KEY1_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 1 (ECC) + type KEY1_2_Register is record + -- Read-only. + KEY1_2 : KEY1_2_KEY1_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_2_Register use record + KEY1_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_3_KEY1_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 1 (ECC) + type KEY1_3_Register is record + -- Read-only. + KEY1_3 : KEY1_3_KEY1_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_3_Register use record + KEY1_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_4_KEY1_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 1 (ECC) + type KEY1_4_Register is record + -- Read-only. + KEY1_4 : KEY1_4_KEY1_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_4_Register use record + KEY1_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_5_KEY1_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 1 (ECC) + type KEY1_5_Register is record + -- Read-only. + KEY1_5 : KEY1_5_KEY1_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_5_Register use record + KEY1_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_6_KEY1_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 1 (ECC) + type KEY1_6_Register is record + -- Read-only. + KEY1_6 : KEY1_6_KEY1_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_6_Register use record + KEY1_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY1_7_KEY1_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 1 (ECC) + type KEY1_7_Register is record + -- Read-only. + KEY1_7 : KEY1_7_KEY1_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_7_Register use record + KEY1_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_0_KEY2_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 2 (ECC) + type KEY2_0_Register is record + -- Read-only. + KEY2_0 : KEY2_0_KEY2_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_0_Register use record + KEY2_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_1_KEY2_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 2 (ECC) + type KEY2_1_Register is record + -- Read-only. + KEY2_1 : KEY2_1_KEY2_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_1_Register use record + KEY2_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_2_KEY2_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 2 (ECC) + type KEY2_2_Register is record + -- Read-only. + KEY2_2 : KEY2_2_KEY2_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_2_Register use record + KEY2_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_3_KEY2_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 2 (ECC) + type KEY2_3_Register is record + -- Read-only. + KEY2_3 : KEY2_3_KEY2_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_3_Register use record + KEY2_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_4_KEY2_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 2 (ECC) + type KEY2_4_Register is record + -- Read-only. + KEY2_4 : KEY2_4_KEY2_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_4_Register use record + KEY2_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_5_KEY2_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 2 (ECC) + type KEY2_5_Register is record + -- Read-only. + KEY2_5 : KEY2_5_KEY2_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_5_Register use record + KEY2_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_6_KEY2_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 2 (ECC) + type KEY2_6_Register is record + -- Read-only. + KEY2_6 : KEY2_6_KEY2_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_6_Register use record + KEY2_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY2_7_KEY2_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 2 (ECC) + type KEY2_7_Register is record + -- Read-only. + KEY2_7 : KEY2_7_KEY2_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_7_Register use record + KEY2_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_0_KEY3_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 3 (ECC) + type KEY3_0_Register is record + -- Read-only. + KEY3_0 : KEY3_0_KEY3_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_0_Register use record + KEY3_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_1_KEY3_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 3 (ECC) + type KEY3_1_Register is record + -- Read-only. + KEY3_1 : KEY3_1_KEY3_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_1_Register use record + KEY3_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_2_KEY3_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 3 (ECC) + type KEY3_2_Register is record + -- Read-only. + KEY3_2 : KEY3_2_KEY3_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_2_Register use record + KEY3_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_3_KEY3_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 3 (ECC) + type KEY3_3_Register is record + -- Read-only. + KEY3_3 : KEY3_3_KEY3_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_3_Register use record + KEY3_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_4_KEY3_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 3 (ECC) + type KEY3_4_Register is record + -- Read-only. + KEY3_4 : KEY3_4_KEY3_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_4_Register use record + KEY3_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_5_KEY3_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 3 (ECC) + type KEY3_5_Register is record + -- Read-only. + KEY3_5 : KEY3_5_KEY3_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_5_Register use record + KEY3_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_6_KEY3_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 3 (ECC) + type KEY3_6_Register is record + -- Read-only. + KEY3_6 : KEY3_6_KEY3_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_6_Register use record + KEY3_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY3_7_KEY3_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 3 (ECC) + type KEY3_7_Register is record + -- Read-only. + KEY3_7 : KEY3_7_KEY3_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_7_Register use record + KEY3_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_0_KEY4_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 4 (ECC) + type KEY4_0_Register is record + -- Read-only. + KEY4_0 : KEY4_0_KEY4_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_0_Register use record + KEY4_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_1_KEY4_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 4 (ECC) + type KEY4_1_Register is record + -- Read-only. + KEY4_1 : KEY4_1_KEY4_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_1_Register use record + KEY4_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_2_KEY4_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 4 (ECC) + type KEY4_2_Register is record + -- Read-only. + KEY4_2 : KEY4_2_KEY4_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_2_Register use record + KEY4_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_3_KEY4_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 4 (ECC) + type KEY4_3_Register is record + -- Read-only. + KEY4_3 : KEY4_3_KEY4_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_3_Register use record + KEY4_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_4_KEY4_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 4 (ECC) + type KEY4_4_Register is record + -- Read-only. + KEY4_4 : KEY4_4_KEY4_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_4_Register use record + KEY4_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_5_KEY4_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 4 (ECC) + type KEY4_5_Register is record + -- Read-only. + KEY4_5 : KEY4_5_KEY4_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_5_Register use record + KEY4_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_6_KEY4_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 4 (ECC) + type KEY4_6_Register is record + -- Read-only. + KEY4_6 : KEY4_6_KEY4_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_6_Register use record + KEY4_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY4_7_KEY4_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 4 (ECC) + type KEY4_7_Register is record + -- Read-only. + KEY4_7 : KEY4_7_KEY4_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_7_Register use record + KEY4_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_0_KEY5_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 5 (ECC) + type KEY5_0_Register is record + -- Read-only. + KEY5_0 : KEY5_0_KEY5_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_0_Register use record + KEY5_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_1_KEY5_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 5 (ECC) + type KEY5_1_Register is record + -- Read-only. + KEY5_1 : KEY5_1_KEY5_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_1_Register use record + KEY5_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_2_KEY5_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 5 (ECC) + type KEY5_2_Register is record + -- Read-only. + KEY5_2 : KEY5_2_KEY5_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_2_Register use record + KEY5_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_3_KEY5_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 5 (ECC) + type KEY5_3_Register is record + -- Read-only. + KEY5_3 : KEY5_3_KEY5_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_3_Register use record + KEY5_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_4_KEY5_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 5 (ECC) + type KEY5_4_Register is record + -- Read-only. + KEY5_4 : KEY5_4_KEY5_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_4_Register use record + KEY5_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_5_KEY5_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 5 (ECC) + type KEY5_5_Register is record + -- Read-only. + KEY5_5 : KEY5_5_KEY5_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_5_Register use record + KEY5_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_6_KEY5_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 5 (ECC) + type KEY5_6_Register is record + -- Read-only. + KEY5_6 : KEY5_6_KEY5_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_6_Register use record + KEY5_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY5_7_KEY5_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 5 (ECC) + type KEY5_7_Register is record + -- Read-only. + KEY5_7 : KEY5_7_KEY5_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_7_Register use record + KEY5_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_0_KEY6_0_Field is HAL.UInt16; + + -- Bits 15:0 of OTP access key 6 (ECC) + type KEY6_0_Register is record + -- Read-only. + KEY6_0 : KEY6_0_KEY6_0_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_0_Register use record + KEY6_0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_1_KEY6_1_Field is HAL.UInt16; + + -- Bits 31:16 of OTP access key 6 (ECC) + type KEY6_1_Register is record + -- Read-only. + KEY6_1 : KEY6_1_KEY6_1_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_1_Register use record + KEY6_1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_2_KEY6_2_Field is HAL.UInt16; + + -- Bits 47:32 of OTP access key 6 (ECC) + type KEY6_2_Register is record + -- Read-only. + KEY6_2 : KEY6_2_KEY6_2_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_2_Register use record + KEY6_2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_3_KEY6_3_Field is HAL.UInt16; + + -- Bits 63:48 of OTP access key 6 (ECC) + type KEY6_3_Register is record + -- Read-only. + KEY6_3 : KEY6_3_KEY6_3_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_3_Register use record + KEY6_3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_4_KEY6_4_Field is HAL.UInt16; + + -- Bits 79:64 of OTP access key 6 (ECC) + type KEY6_4_Register is record + -- Read-only. + KEY6_4 : KEY6_4_KEY6_4_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_4_Register use record + KEY6_4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_5_KEY6_5_Field is HAL.UInt16; + + -- Bits 95:80 of OTP access key 6 (ECC) + type KEY6_5_Register is record + -- Read-only. + KEY6_5 : KEY6_5_KEY6_5_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_5_Register use record + KEY6_5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_6_KEY6_6_Field is HAL.UInt16; + + -- Bits 111:96 of OTP access key 6 (ECC) + type KEY6_6_Register is record + -- Read-only. + KEY6_6 : KEY6_6_KEY6_6_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_6_Register use record + KEY6_6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype KEY6_7_KEY6_7_Field is HAL.UInt16; + + -- Bits 127:112 of OTP access key 6 (ECC) + type KEY6_7_Register is record + -- Read-only. + KEY6_7 : KEY6_7_KEY6_7_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_7_Register use record + KEY6_7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Valid flag for key 1. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY1_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY1_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Valid flag for key 2. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY2_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY2_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Valid flag for key 3. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY3_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY3_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Valid flag for key 4. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY4_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY4_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Valid flag for key 5. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY5_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY5_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Valid flag for key 6. Once the valid flag is set, the key can no longer + -- be read or written, and becomes a valid fixed key for protecting OTP + -- pages. + type KEY6_VALID_Register is record + -- Read-only. + VALID : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R1 : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. Redundant copy of VALID, with 3-way majority vote + VALID_R2 : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for KEY6_VALID_Register use record + VALID at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + VALID_R1 at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + VALID_R2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype PAGE0_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE0_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE0_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE0_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE0_LOCK0_R array element + subtype PAGE0_LOCK0_R_Element is HAL.UInt8; + + -- PAGE0_LOCK0_R array + type PAGE0_LOCK0_R_Field_Array is array (1 .. 2) of PAGE0_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE0_LOCK0_R + type PAGE0_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE0_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE0_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE0_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE0_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE0_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE0_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE0_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE0_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE0_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE0_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE0_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE0_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE0_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE0_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE0_LOCK1_R array element + subtype PAGE0_LOCK1_R_Element is HAL.UInt8; + + -- PAGE0_LOCK1_R array + type PAGE0_LOCK1_R_Field_Array is array (1 .. 2) of PAGE0_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE0_LOCK1_R + type PAGE0_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE0_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE0_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE0_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE0_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE0_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE0_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE0_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE0_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE1_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE1_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE1_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE1_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE1_LOCK0_R array element + subtype PAGE1_LOCK0_R_Element is HAL.UInt8; + + -- PAGE1_LOCK0_R array + type PAGE1_LOCK0_R_Field_Array is array (1 .. 2) of PAGE1_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE1_LOCK0_R + type PAGE1_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE1_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE1_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE1_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE1_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE1_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE1_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE1_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE1_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE1_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE1_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE1_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE1_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE1_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE1_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE1_LOCK1_R array element + subtype PAGE1_LOCK1_R_Element is HAL.UInt8; + + -- PAGE1_LOCK1_R array + type PAGE1_LOCK1_R_Field_Array is array (1 .. 2) of PAGE1_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE1_LOCK1_R + type PAGE1_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE1_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE1_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE1_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE1_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE1_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE1_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE1_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE1_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE2_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE2_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE2_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE2_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE2_LOCK0_R array element + subtype PAGE2_LOCK0_R_Element is HAL.UInt8; + + -- PAGE2_LOCK0_R array + type PAGE2_LOCK0_R_Field_Array is array (1 .. 2) of PAGE2_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE2_LOCK0_R + type PAGE2_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE2_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE2_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE2_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE2_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE2_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE2_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE2_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE2_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE2_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE2_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE2_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE2_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE2_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE2_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE2_LOCK1_R array element + subtype PAGE2_LOCK1_R_Element is HAL.UInt8; + + -- PAGE2_LOCK1_R array + type PAGE2_LOCK1_R_Field_Array is array (1 .. 2) of PAGE2_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE2_LOCK1_R + type PAGE2_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE2_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE2_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE2_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE2_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE2_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE2_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE2_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE2_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE3_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE3_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE3_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE3_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE3_LOCK0_R array element + subtype PAGE3_LOCK0_R_Element is HAL.UInt8; + + -- PAGE3_LOCK0_R array + type PAGE3_LOCK0_R_Field_Array is array (1 .. 2) of PAGE3_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE3_LOCK0_R + type PAGE3_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE3_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE3_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE3_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE3_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE3_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE3_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE3_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE3_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE3_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE3_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE3_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE3_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE3_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE3_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE3_LOCK1_R array element + subtype PAGE3_LOCK1_R_Element is HAL.UInt8; + + -- PAGE3_LOCK1_R array + type PAGE3_LOCK1_R_Field_Array is array (1 .. 2) of PAGE3_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE3_LOCK1_R + type PAGE3_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE3_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE3_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE3_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE3_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE3_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE3_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE3_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE3_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE4_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE4_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE4_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE4_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE4_LOCK0_R array element + subtype PAGE4_LOCK0_R_Element is HAL.UInt8; + + -- PAGE4_LOCK0_R array + type PAGE4_LOCK0_R_Field_Array is array (1 .. 2) of PAGE4_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE4_LOCK0_R + type PAGE4_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE4_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE4_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE4_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE4_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE4_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE4_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE4_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE4_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE4_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE4_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE4_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE4_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE4_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE4_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE4_LOCK1_R array element + subtype PAGE4_LOCK1_R_Element is HAL.UInt8; + + -- PAGE4_LOCK1_R array + type PAGE4_LOCK1_R_Field_Array is array (1 .. 2) of PAGE4_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE4_LOCK1_R + type PAGE4_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE4_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE4_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE4_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE4_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE4_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE4_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE4_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE4_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE5_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE5_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE5_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE5_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE5_LOCK0_R array element + subtype PAGE5_LOCK0_R_Element is HAL.UInt8; + + -- PAGE5_LOCK0_R array + type PAGE5_LOCK0_R_Field_Array is array (1 .. 2) of PAGE5_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE5_LOCK0_R + type PAGE5_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE5_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE5_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE5_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE5_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE5_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE5_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE5_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE5_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE5_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE5_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE5_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE5_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE5_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE5_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE5_LOCK1_R array element + subtype PAGE5_LOCK1_R_Element is HAL.UInt8; + + -- PAGE5_LOCK1_R array + type PAGE5_LOCK1_R_Field_Array is array (1 .. 2) of PAGE5_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE5_LOCK1_R + type PAGE5_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE5_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE5_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE5_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE5_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE5_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE5_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE5_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE5_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE6_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE6_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE6_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE6_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE6_LOCK0_R array element + subtype PAGE6_LOCK0_R_Element is HAL.UInt8; + + -- PAGE6_LOCK0_R array + type PAGE6_LOCK0_R_Field_Array is array (1 .. 2) of PAGE6_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE6_LOCK0_R + type PAGE6_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE6_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE6_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE6_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE6_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE6_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE6_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE6_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE6_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE6_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE6_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE6_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE6_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE6_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE6_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE6_LOCK1_R array element + subtype PAGE6_LOCK1_R_Element is HAL.UInt8; + + -- PAGE6_LOCK1_R array + type PAGE6_LOCK1_R_Field_Array is array (1 .. 2) of PAGE6_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE6_LOCK1_R + type PAGE6_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE6_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE6_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE6_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE6_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE6_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE6_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE6_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE6_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE7_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE7_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE7_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE7_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE7_LOCK0_R array element + subtype PAGE7_LOCK0_R_Element is HAL.UInt8; + + -- PAGE7_LOCK0_R array + type PAGE7_LOCK0_R_Field_Array is array (1 .. 2) of PAGE7_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE7_LOCK0_R + type PAGE7_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE7_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE7_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE7_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE7_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE7_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE7_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE7_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE7_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE7_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE7_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE7_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE7_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE7_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE7_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE7_LOCK1_R array element + subtype PAGE7_LOCK1_R_Element is HAL.UInt8; + + -- PAGE7_LOCK1_R array + type PAGE7_LOCK1_R_Field_Array is array (1 .. 2) of PAGE7_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE7_LOCK1_R + type PAGE7_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE7_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE7_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE7_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE7_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE7_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE7_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE7_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE7_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE8_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE8_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE8_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE8_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE8_LOCK0_R array element + subtype PAGE8_LOCK0_R_Element is HAL.UInt8; + + -- PAGE8_LOCK0_R array + type PAGE8_LOCK0_R_Field_Array is array (1 .. 2) of PAGE8_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE8_LOCK0_R + type PAGE8_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE8_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE8_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE8_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE8_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE8_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE8_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE8_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE8_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE8_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE8_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE8_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE8_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE8_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE8_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE8_LOCK1_R array element + subtype PAGE8_LOCK1_R_Element is HAL.UInt8; + + -- PAGE8_LOCK1_R array + type PAGE8_LOCK1_R_Field_Array is array (1 .. 2) of PAGE8_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE8_LOCK1_R + type PAGE8_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE8_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE8_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE8_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE8_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE8_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE8_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE8_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE8_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE9_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE9_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE9_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE9_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE9_LOCK0_R array element + subtype PAGE9_LOCK0_R_Element is HAL.UInt8; + + -- PAGE9_LOCK0_R array + type PAGE9_LOCK0_R_Field_Array is array (1 .. 2) of PAGE9_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE9_LOCK0_R + type PAGE9_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE9_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE9_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE9_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE9_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE9_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE9_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE9_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE9_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE9_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE9_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE9_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE9_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE9_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE9_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE9_LOCK1_R array element + subtype PAGE9_LOCK1_R_Element is HAL.UInt8; + + -- PAGE9_LOCK1_R array + type PAGE9_LOCK1_R_Field_Array is array (1 .. 2) of PAGE9_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE9_LOCK1_R + type PAGE9_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE9_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE9_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE9_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE9_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE9_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE9_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE9_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE9_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE10_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE10_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE10_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE10_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE10_LOCK0_R array element + subtype PAGE10_LOCK0_R_Element is HAL.UInt8; + + -- PAGE10_LOCK0_R array + type PAGE10_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE10_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE10_LOCK0_R + type PAGE10_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE10_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE10_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE10_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE10_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE10_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE10_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE10_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE10_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE10_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE10_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE10_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE10_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE10_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE10_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE10_LOCK1_R array element + subtype PAGE10_LOCK1_R_Element is HAL.UInt8; + + -- PAGE10_LOCK1_R array + type PAGE10_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE10_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE10_LOCK1_R + type PAGE10_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE10_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE10_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE10_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE10_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE10_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE10_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE10_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE10_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE11_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE11_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE11_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE11_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE11_LOCK0_R array element + subtype PAGE11_LOCK0_R_Element is HAL.UInt8; + + -- PAGE11_LOCK0_R array + type PAGE11_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE11_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE11_LOCK0_R + type PAGE11_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE11_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE11_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE11_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE11_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE11_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE11_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE11_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE11_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE11_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE11_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE11_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE11_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE11_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE11_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE11_LOCK1_R array element + subtype PAGE11_LOCK1_R_Element is HAL.UInt8; + + -- PAGE11_LOCK1_R array + type PAGE11_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE11_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE11_LOCK1_R + type PAGE11_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE11_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE11_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE11_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE11_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE11_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE11_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE11_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE11_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE12_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE12_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE12_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE12_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE12_LOCK0_R array element + subtype PAGE12_LOCK0_R_Element is HAL.UInt8; + + -- PAGE12_LOCK0_R array + type PAGE12_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE12_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE12_LOCK0_R + type PAGE12_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE12_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE12_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE12_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE12_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE12_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE12_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE12_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE12_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE12_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE12_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE12_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE12_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE12_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE12_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE12_LOCK1_R array element + subtype PAGE12_LOCK1_R_Element is HAL.UInt8; + + -- PAGE12_LOCK1_R array + type PAGE12_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE12_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE12_LOCK1_R + type PAGE12_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE12_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE12_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE12_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE12_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE12_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE12_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE12_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE12_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE13_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE13_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE13_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE13_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE13_LOCK0_R array element + subtype PAGE13_LOCK0_R_Element is HAL.UInt8; + + -- PAGE13_LOCK0_R array + type PAGE13_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE13_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE13_LOCK0_R + type PAGE13_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE13_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE13_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE13_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE13_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE13_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE13_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE13_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE13_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE13_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE13_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE13_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE13_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE13_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE13_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE13_LOCK1_R array element + subtype PAGE13_LOCK1_R_Element is HAL.UInt8; + + -- PAGE13_LOCK1_R array + type PAGE13_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE13_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE13_LOCK1_R + type PAGE13_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE13_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE13_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE13_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE13_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE13_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE13_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE13_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE13_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE14_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE14_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE14_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE14_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE14_LOCK0_R array element + subtype PAGE14_LOCK0_R_Element is HAL.UInt8; + + -- PAGE14_LOCK0_R array + type PAGE14_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE14_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE14_LOCK0_R + type PAGE14_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE14_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE14_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE14_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE14_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE14_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE14_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE14_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE14_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE14_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE14_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE14_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE14_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE14_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE14_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE14_LOCK1_R array element + subtype PAGE14_LOCK1_R_Element is HAL.UInt8; + + -- PAGE14_LOCK1_R array + type PAGE14_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE14_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE14_LOCK1_R + type PAGE14_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE14_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE14_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE14_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE14_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE14_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE14_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE14_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE14_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE15_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE15_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE15_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE15_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE15_LOCK0_R array element + subtype PAGE15_LOCK0_R_Element is HAL.UInt8; + + -- PAGE15_LOCK0_R array + type PAGE15_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE15_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE15_LOCK0_R + type PAGE15_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE15_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE15_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE15_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE15_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE15_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE15_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE15_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE15_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE15_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE15_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE15_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE15_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE15_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE15_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE15_LOCK1_R array element + subtype PAGE15_LOCK1_R_Element is HAL.UInt8; + + -- PAGE15_LOCK1_R array + type PAGE15_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE15_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE15_LOCK1_R + type PAGE15_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE15_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE15_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE15_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE15_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE15_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE15_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE15_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE15_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE16_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE16_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE16_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE16_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE16_LOCK0_R array element + subtype PAGE16_LOCK0_R_Element is HAL.UInt8; + + -- PAGE16_LOCK0_R array + type PAGE16_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE16_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE16_LOCK0_R + type PAGE16_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE16_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE16_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE16_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE16_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE16_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE16_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE16_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE16_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE16_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE16_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE16_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE16_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE16_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE16_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE16_LOCK1_R array element + subtype PAGE16_LOCK1_R_Element is HAL.UInt8; + + -- PAGE16_LOCK1_R array + type PAGE16_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE16_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE16_LOCK1_R + type PAGE16_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE16_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE16_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE16_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE16_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE16_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE16_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE16_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE16_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE17_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE17_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE17_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE17_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE17_LOCK0_R array element + subtype PAGE17_LOCK0_R_Element is HAL.UInt8; + + -- PAGE17_LOCK0_R array + type PAGE17_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE17_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE17_LOCK0_R + type PAGE17_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE17_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE17_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE17_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE17_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE17_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE17_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE17_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE17_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE17_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE17_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE17_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE17_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE17_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE17_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE17_LOCK1_R array element + subtype PAGE17_LOCK1_R_Element is HAL.UInt8; + + -- PAGE17_LOCK1_R array + type PAGE17_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE17_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE17_LOCK1_R + type PAGE17_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE17_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE17_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE17_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE17_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE17_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE17_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE17_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE17_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE18_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE18_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE18_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE18_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE18_LOCK0_R array element + subtype PAGE18_LOCK0_R_Element is HAL.UInt8; + + -- PAGE18_LOCK0_R array + type PAGE18_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE18_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE18_LOCK0_R + type PAGE18_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE18_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE18_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE18_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE18_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE18_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE18_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE18_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE18_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE18_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE18_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE18_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE18_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE18_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE18_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE18_LOCK1_R array element + subtype PAGE18_LOCK1_R_Element is HAL.UInt8; + + -- PAGE18_LOCK1_R array + type PAGE18_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE18_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE18_LOCK1_R + type PAGE18_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE18_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE18_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE18_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE18_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE18_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE18_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE18_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE18_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE19_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE19_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE19_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE19_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE19_LOCK0_R array element + subtype PAGE19_LOCK0_R_Element is HAL.UInt8; + + -- PAGE19_LOCK0_R array + type PAGE19_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE19_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE19_LOCK0_R + type PAGE19_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE19_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE19_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE19_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE19_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE19_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE19_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE19_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE19_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE19_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE19_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE19_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE19_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE19_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE19_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE19_LOCK1_R array element + subtype PAGE19_LOCK1_R_Element is HAL.UInt8; + + -- PAGE19_LOCK1_R array + type PAGE19_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE19_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE19_LOCK1_R + type PAGE19_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE19_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE19_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE19_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE19_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE19_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE19_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE19_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE19_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE20_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE20_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE20_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE20_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE20_LOCK0_R array element + subtype PAGE20_LOCK0_R_Element is HAL.UInt8; + + -- PAGE20_LOCK0_R array + type PAGE20_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE20_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE20_LOCK0_R + type PAGE20_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE20_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE20_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE20_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE20_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE20_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE20_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE20_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE20_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE20_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE20_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE20_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE20_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE20_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE20_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE20_LOCK1_R array element + subtype PAGE20_LOCK1_R_Element is HAL.UInt8; + + -- PAGE20_LOCK1_R array + type PAGE20_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE20_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE20_LOCK1_R + type PAGE20_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE20_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE20_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE20_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE20_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE20_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE20_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE20_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE20_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE21_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE21_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE21_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE21_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE21_LOCK0_R array element + subtype PAGE21_LOCK0_R_Element is HAL.UInt8; + + -- PAGE21_LOCK0_R array + type PAGE21_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE21_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE21_LOCK0_R + type PAGE21_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE21_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE21_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE21_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE21_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE21_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE21_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE21_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE21_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE21_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE21_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE21_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE21_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE21_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE21_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE21_LOCK1_R array element + subtype PAGE21_LOCK1_R_Element is HAL.UInt8; + + -- PAGE21_LOCK1_R array + type PAGE21_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE21_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE21_LOCK1_R + type PAGE21_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE21_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE21_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE21_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE21_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE21_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE21_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE21_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE21_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE22_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE22_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE22_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE22_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE22_LOCK0_R array element + subtype PAGE22_LOCK0_R_Element is HAL.UInt8; + + -- PAGE22_LOCK0_R array + type PAGE22_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE22_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE22_LOCK0_R + type PAGE22_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE22_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE22_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE22_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE22_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE22_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE22_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE22_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE22_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE22_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE22_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE22_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE22_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE22_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE22_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE22_LOCK1_R array element + subtype PAGE22_LOCK1_R_Element is HAL.UInt8; + + -- PAGE22_LOCK1_R array + type PAGE22_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE22_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE22_LOCK1_R + type PAGE22_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE22_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE22_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE22_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE22_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE22_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE22_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE22_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE22_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE23_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE23_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE23_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE23_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE23_LOCK0_R array element + subtype PAGE23_LOCK0_R_Element is HAL.UInt8; + + -- PAGE23_LOCK0_R array + type PAGE23_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE23_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE23_LOCK0_R + type PAGE23_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE23_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE23_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE23_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE23_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE23_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE23_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE23_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE23_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE23_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE23_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE23_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE23_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE23_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE23_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE23_LOCK1_R array element + subtype PAGE23_LOCK1_R_Element is HAL.UInt8; + + -- PAGE23_LOCK1_R array + type PAGE23_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE23_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE23_LOCK1_R + type PAGE23_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE23_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE23_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE23_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE23_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE23_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE23_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE23_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE23_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE24_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE24_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE24_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE24_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE24_LOCK0_R array element + subtype PAGE24_LOCK0_R_Element is HAL.UInt8; + + -- PAGE24_LOCK0_R array + type PAGE24_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE24_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE24_LOCK0_R + type PAGE24_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE24_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE24_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE24_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE24_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE24_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE24_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE24_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE24_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE24_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE24_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE24_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE24_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE24_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE24_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE24_LOCK1_R array element + subtype PAGE24_LOCK1_R_Element is HAL.UInt8; + + -- PAGE24_LOCK1_R array + type PAGE24_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE24_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE24_LOCK1_R + type PAGE24_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE24_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE24_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE24_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE24_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE24_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE24_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE24_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE24_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE25_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE25_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE25_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE25_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE25_LOCK0_R array element + subtype PAGE25_LOCK0_R_Element is HAL.UInt8; + + -- PAGE25_LOCK0_R array + type PAGE25_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE25_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE25_LOCK0_R + type PAGE25_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE25_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE25_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE25_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE25_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE25_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE25_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE25_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE25_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE25_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE25_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE25_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE25_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE25_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE25_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE25_LOCK1_R array element + subtype PAGE25_LOCK1_R_Element is HAL.UInt8; + + -- PAGE25_LOCK1_R array + type PAGE25_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE25_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE25_LOCK1_R + type PAGE25_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE25_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE25_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE25_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE25_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE25_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE25_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE25_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE25_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE26_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE26_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE26_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE26_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE26_LOCK0_R array element + subtype PAGE26_LOCK0_R_Element is HAL.UInt8; + + -- PAGE26_LOCK0_R array + type PAGE26_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE26_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE26_LOCK0_R + type PAGE26_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE26_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE26_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE26_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE26_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE26_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE26_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE26_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE26_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE26_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE26_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE26_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE26_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE26_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE26_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE26_LOCK1_R array element + subtype PAGE26_LOCK1_R_Element is HAL.UInt8; + + -- PAGE26_LOCK1_R array + type PAGE26_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE26_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE26_LOCK1_R + type PAGE26_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE26_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE26_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE26_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE26_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE26_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE26_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE26_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE26_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE27_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE27_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE27_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE27_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE27_LOCK0_R array element + subtype PAGE27_LOCK0_R_Element is HAL.UInt8; + + -- PAGE27_LOCK0_R array + type PAGE27_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE27_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE27_LOCK0_R + type PAGE27_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE27_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE27_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE27_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE27_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE27_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE27_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE27_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE27_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE27_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE27_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE27_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE27_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE27_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE27_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE27_LOCK1_R array element + subtype PAGE27_LOCK1_R_Element is HAL.UInt8; + + -- PAGE27_LOCK1_R array + type PAGE27_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE27_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE27_LOCK1_R + type PAGE27_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE27_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE27_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE27_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE27_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE27_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE27_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE27_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE27_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE28_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE28_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE28_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE28_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE28_LOCK0_R array element + subtype PAGE28_LOCK0_R_Element is HAL.UInt8; + + -- PAGE28_LOCK0_R array + type PAGE28_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE28_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE28_LOCK0_R + type PAGE28_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE28_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE28_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE28_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE28_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE28_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE28_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE28_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE28_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE28_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE28_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE28_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE28_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE28_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE28_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE28_LOCK1_R array element + subtype PAGE28_LOCK1_R_Element is HAL.UInt8; + + -- PAGE28_LOCK1_R array + type PAGE28_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE28_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE28_LOCK1_R + type PAGE28_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE28_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE28_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE28_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE28_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE28_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE28_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE28_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE28_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE29_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE29_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE29_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE29_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE29_LOCK0_R array element + subtype PAGE29_LOCK0_R_Element is HAL.UInt8; + + -- PAGE29_LOCK0_R array + type PAGE29_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE29_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE29_LOCK0_R + type PAGE29_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE29_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE29_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE29_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE29_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE29_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE29_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE29_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE29_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE29_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE29_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE29_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE29_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE29_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE29_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE29_LOCK1_R array element + subtype PAGE29_LOCK1_R_Element is HAL.UInt8; + + -- PAGE29_LOCK1_R array + type PAGE29_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE29_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE29_LOCK1_R + type PAGE29_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE29_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE29_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE29_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE29_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE29_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE29_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE29_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE29_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE30_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE30_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE30_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE30_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE30_LOCK0_R array element + subtype PAGE30_LOCK0_R_Element is HAL.UInt8; + + -- PAGE30_LOCK0_R array + type PAGE30_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE30_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE30_LOCK0_R + type PAGE30_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE30_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE30_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE30_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE30_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE30_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE30_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE30_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE30_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE30_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE30_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE30_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE30_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE30_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE30_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE30_LOCK1_R array element + subtype PAGE30_LOCK1_R_Element is HAL.UInt8; + + -- PAGE30_LOCK1_R array + type PAGE30_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE30_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE30_LOCK1_R + type PAGE30_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE30_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE30_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE30_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE30_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE30_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE30_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE30_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE30_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE31_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE31_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE31_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE31_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE31_LOCK0_R array element + subtype PAGE31_LOCK0_R_Element is HAL.UInt8; + + -- PAGE31_LOCK0_R array + type PAGE31_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE31_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE31_LOCK0_R + type PAGE31_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE31_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE31_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE31_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE31_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE31_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE31_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE31_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE31_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE31_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE31_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE31_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE31_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE31_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE31_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE31_LOCK1_R array element + subtype PAGE31_LOCK1_R_Element is HAL.UInt8; + + -- PAGE31_LOCK1_R array + type PAGE31_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE31_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE31_LOCK1_R + type PAGE31_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE31_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE31_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE31_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE31_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE31_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE31_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE31_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE31_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE32_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE32_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE32_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE32_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE32_LOCK0_R array element + subtype PAGE32_LOCK0_R_Element is HAL.UInt8; + + -- PAGE32_LOCK0_R array + type PAGE32_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE32_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE32_LOCK0_R + type PAGE32_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE32_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE32_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE32_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE32_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE32_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE32_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE32_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE32_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE32_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE32_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE32_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE32_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE32_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE32_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE32_LOCK1_R array element + subtype PAGE32_LOCK1_R_Element is HAL.UInt8; + + -- PAGE32_LOCK1_R array + type PAGE32_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE32_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE32_LOCK1_R + type PAGE32_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE32_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE32_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE32_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE32_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE32_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE32_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE32_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE32_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE33_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE33_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE33_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE33_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE33_LOCK0_R array element + subtype PAGE33_LOCK0_R_Element is HAL.UInt8; + + -- PAGE33_LOCK0_R array + type PAGE33_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE33_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE33_LOCK0_R + type PAGE33_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE33_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE33_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE33_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE33_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE33_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE33_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE33_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE33_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE33_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE33_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE33_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE33_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE33_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE33_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE33_LOCK1_R array element + subtype PAGE33_LOCK1_R_Element is HAL.UInt8; + + -- PAGE33_LOCK1_R array + type PAGE33_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE33_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE33_LOCK1_R + type PAGE33_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE33_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE33_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE33_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE33_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE33_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE33_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE33_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE33_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE34_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE34_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE34_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE34_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE34_LOCK0_R array element + subtype PAGE34_LOCK0_R_Element is HAL.UInt8; + + -- PAGE34_LOCK0_R array + type PAGE34_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE34_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE34_LOCK0_R + type PAGE34_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE34_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE34_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE34_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE34_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE34_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE34_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE34_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE34_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE34_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE34_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE34_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE34_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE34_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE34_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE34_LOCK1_R array element + subtype PAGE34_LOCK1_R_Element is HAL.UInt8; + + -- PAGE34_LOCK1_R array + type PAGE34_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE34_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE34_LOCK1_R + type PAGE34_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE34_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE34_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE34_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE34_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE34_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE34_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE34_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE34_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE35_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE35_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE35_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE35_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE35_LOCK0_R array element + subtype PAGE35_LOCK0_R_Element is HAL.UInt8; + + -- PAGE35_LOCK0_R array + type PAGE35_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE35_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE35_LOCK0_R + type PAGE35_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE35_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE35_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE35_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE35_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE35_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE35_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE35_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE35_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE35_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE35_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE35_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE35_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE35_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE35_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE35_LOCK1_R array element + subtype PAGE35_LOCK1_R_Element is HAL.UInt8; + + -- PAGE35_LOCK1_R array + type PAGE35_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE35_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE35_LOCK1_R + type PAGE35_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE35_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE35_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE35_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE35_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE35_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE35_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE35_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE35_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE36_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE36_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE36_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE36_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE36_LOCK0_R array element + subtype PAGE36_LOCK0_R_Element is HAL.UInt8; + + -- PAGE36_LOCK0_R array + type PAGE36_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE36_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE36_LOCK0_R + type PAGE36_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE36_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE36_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE36_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE36_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE36_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE36_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE36_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE36_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE36_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE36_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE36_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE36_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE36_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE36_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE36_LOCK1_R array element + subtype PAGE36_LOCK1_R_Element is HAL.UInt8; + + -- PAGE36_LOCK1_R array + type PAGE36_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE36_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE36_LOCK1_R + type PAGE36_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE36_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE36_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE36_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE36_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE36_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE36_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE36_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE36_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE37_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE37_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE37_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE37_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE37_LOCK0_R array element + subtype PAGE37_LOCK0_R_Element is HAL.UInt8; + + -- PAGE37_LOCK0_R array + type PAGE37_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE37_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE37_LOCK0_R + type PAGE37_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE37_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE37_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE37_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE37_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE37_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE37_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE37_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE37_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE37_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE37_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE37_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE37_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE37_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE37_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE37_LOCK1_R array element + subtype PAGE37_LOCK1_R_Element is HAL.UInt8; + + -- PAGE37_LOCK1_R array + type PAGE37_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE37_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE37_LOCK1_R + type PAGE37_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE37_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE37_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE37_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE37_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE37_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE37_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE37_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE37_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE38_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE38_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE38_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE38_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE38_LOCK0_R array element + subtype PAGE38_LOCK0_R_Element is HAL.UInt8; + + -- PAGE38_LOCK0_R array + type PAGE38_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE38_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE38_LOCK0_R + type PAGE38_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE38_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE38_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE38_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE38_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE38_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE38_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE38_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE38_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE38_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE38_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE38_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE38_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE38_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE38_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE38_LOCK1_R array element + subtype PAGE38_LOCK1_R_Element is HAL.UInt8; + + -- PAGE38_LOCK1_R array + type PAGE38_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE38_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE38_LOCK1_R + type PAGE38_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE38_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE38_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE38_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE38_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE38_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE38_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE38_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE38_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE39_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE39_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE39_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE39_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE39_LOCK0_R array element + subtype PAGE39_LOCK0_R_Element is HAL.UInt8; + + -- PAGE39_LOCK0_R array + type PAGE39_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE39_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE39_LOCK0_R + type PAGE39_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE39_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE39_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE39_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE39_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE39_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE39_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE39_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE39_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE39_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE39_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE39_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE39_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE39_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE39_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE39_LOCK1_R array element + subtype PAGE39_LOCK1_R_Element is HAL.UInt8; + + -- PAGE39_LOCK1_R array + type PAGE39_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE39_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE39_LOCK1_R + type PAGE39_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE39_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE39_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE39_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE39_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE39_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE39_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE39_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE39_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE40_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE40_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE40_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE40_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE40_LOCK0_R array element + subtype PAGE40_LOCK0_R_Element is HAL.UInt8; + + -- PAGE40_LOCK0_R array + type PAGE40_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE40_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE40_LOCK0_R + type PAGE40_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE40_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE40_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE40_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE40_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE40_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE40_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE40_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE40_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE40_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE40_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE40_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE40_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE40_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE40_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE40_LOCK1_R array element + subtype PAGE40_LOCK1_R_Element is HAL.UInt8; + + -- PAGE40_LOCK1_R array + type PAGE40_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE40_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE40_LOCK1_R + type PAGE40_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE40_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE40_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE40_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE40_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE40_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE40_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE40_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE40_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE41_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE41_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE41_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE41_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE41_LOCK0_R array element + subtype PAGE41_LOCK0_R_Element is HAL.UInt8; + + -- PAGE41_LOCK0_R array + type PAGE41_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE41_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE41_LOCK0_R + type PAGE41_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE41_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE41_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE41_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE41_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE41_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE41_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE41_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE41_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE41_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE41_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE41_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE41_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE41_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE41_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE41_LOCK1_R array element + subtype PAGE41_LOCK1_R_Element is HAL.UInt8; + + -- PAGE41_LOCK1_R array + type PAGE41_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE41_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE41_LOCK1_R + type PAGE41_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE41_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE41_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE41_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE41_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE41_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE41_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE41_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE41_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE42_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE42_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE42_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE42_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE42_LOCK0_R array element + subtype PAGE42_LOCK0_R_Element is HAL.UInt8; + + -- PAGE42_LOCK0_R array + type PAGE42_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE42_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE42_LOCK0_R + type PAGE42_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE42_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE42_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE42_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE42_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE42_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE42_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE42_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE42_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE42_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE42_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE42_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE42_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE42_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE42_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE42_LOCK1_R array element + subtype PAGE42_LOCK1_R_Element is HAL.UInt8; + + -- PAGE42_LOCK1_R array + type PAGE42_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE42_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE42_LOCK1_R + type PAGE42_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE42_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE42_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE42_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE42_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE42_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE42_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE42_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE42_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE43_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE43_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE43_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE43_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE43_LOCK0_R array element + subtype PAGE43_LOCK0_R_Element is HAL.UInt8; + + -- PAGE43_LOCK0_R array + type PAGE43_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE43_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE43_LOCK0_R + type PAGE43_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE43_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE43_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE43_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE43_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE43_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE43_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE43_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE43_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE43_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE43_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE43_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE43_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE43_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE43_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE43_LOCK1_R array element + subtype PAGE43_LOCK1_R_Element is HAL.UInt8; + + -- PAGE43_LOCK1_R array + type PAGE43_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE43_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE43_LOCK1_R + type PAGE43_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE43_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE43_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE43_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE43_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE43_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE43_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE43_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE43_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE44_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE44_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE44_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE44_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE44_LOCK0_R array element + subtype PAGE44_LOCK0_R_Element is HAL.UInt8; + + -- PAGE44_LOCK0_R array + type PAGE44_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE44_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE44_LOCK0_R + type PAGE44_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE44_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE44_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE44_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE44_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE44_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE44_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE44_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE44_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE44_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE44_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE44_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE44_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE44_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE44_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE44_LOCK1_R array element + subtype PAGE44_LOCK1_R_Element is HAL.UInt8; + + -- PAGE44_LOCK1_R array + type PAGE44_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE44_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE44_LOCK1_R + type PAGE44_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE44_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE44_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE44_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE44_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE44_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE44_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE44_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE44_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE45_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE45_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE45_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE45_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE45_LOCK0_R array element + subtype PAGE45_LOCK0_R_Element is HAL.UInt8; + + -- PAGE45_LOCK0_R array + type PAGE45_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE45_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE45_LOCK0_R + type PAGE45_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE45_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE45_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE45_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE45_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE45_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE45_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE45_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE45_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE45_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE45_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE45_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE45_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE45_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE45_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE45_LOCK1_R array element + subtype PAGE45_LOCK1_R_Element is HAL.UInt8; + + -- PAGE45_LOCK1_R array + type PAGE45_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE45_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE45_LOCK1_R + type PAGE45_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE45_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE45_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE45_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE45_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE45_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE45_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE45_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE45_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE46_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE46_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE46_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE46_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE46_LOCK0_R array element + subtype PAGE46_LOCK0_R_Element is HAL.UInt8; + + -- PAGE46_LOCK0_R array + type PAGE46_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE46_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE46_LOCK0_R + type PAGE46_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE46_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE46_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE46_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE46_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE46_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE46_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE46_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE46_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE46_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE46_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE46_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE46_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE46_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE46_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE46_LOCK1_R array element + subtype PAGE46_LOCK1_R_Element is HAL.UInt8; + + -- PAGE46_LOCK1_R array + type PAGE46_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE46_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE46_LOCK1_R + type PAGE46_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE46_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE46_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE46_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE46_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE46_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE46_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE46_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE46_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE47_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE47_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE47_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE47_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE47_LOCK0_R array element + subtype PAGE47_LOCK0_R_Element is HAL.UInt8; + + -- PAGE47_LOCK0_R array + type PAGE47_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE47_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE47_LOCK0_R + type PAGE47_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE47_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE47_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE47_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE47_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE47_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE47_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE47_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE47_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE47_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE47_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE47_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE47_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE47_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE47_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE47_LOCK1_R array element + subtype PAGE47_LOCK1_R_Element is HAL.UInt8; + + -- PAGE47_LOCK1_R array + type PAGE47_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE47_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE47_LOCK1_R + type PAGE47_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE47_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE47_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE47_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE47_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE47_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE47_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE47_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE47_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE48_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE48_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE48_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE48_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE48_LOCK0_R array element + subtype PAGE48_LOCK0_R_Element is HAL.UInt8; + + -- PAGE48_LOCK0_R array + type PAGE48_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE48_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE48_LOCK0_R + type PAGE48_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE48_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE48_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE48_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE48_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE48_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE48_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE48_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE48_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE48_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE48_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE48_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE48_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE48_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE48_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE48_LOCK1_R array element + subtype PAGE48_LOCK1_R_Element is HAL.UInt8; + + -- PAGE48_LOCK1_R array + type PAGE48_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE48_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE48_LOCK1_R + type PAGE48_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE48_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE48_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE48_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE48_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE48_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE48_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE48_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE48_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE49_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE49_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE49_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE49_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE49_LOCK0_R array element + subtype PAGE49_LOCK0_R_Element is HAL.UInt8; + + -- PAGE49_LOCK0_R array + type PAGE49_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE49_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE49_LOCK0_R + type PAGE49_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE49_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE49_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE49_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE49_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE49_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE49_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE49_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE49_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE49_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE49_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE49_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE49_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE49_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE49_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE49_LOCK1_R array element + subtype PAGE49_LOCK1_R_Element is HAL.UInt8; + + -- PAGE49_LOCK1_R array + type PAGE49_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE49_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE49_LOCK1_R + type PAGE49_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE49_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE49_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE49_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE49_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE49_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE49_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE49_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE49_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE50_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE50_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE50_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE50_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE50_LOCK0_R array element + subtype PAGE50_LOCK0_R_Element is HAL.UInt8; + + -- PAGE50_LOCK0_R array + type PAGE50_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE50_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE50_LOCK0_R + type PAGE50_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE50_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE50_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE50_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE50_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE50_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE50_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE50_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE50_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE50_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE50_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE50_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE50_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE50_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE50_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE50_LOCK1_R array element + subtype PAGE50_LOCK1_R_Element is HAL.UInt8; + + -- PAGE50_LOCK1_R array + type PAGE50_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE50_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE50_LOCK1_R + type PAGE50_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE50_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE50_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE50_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE50_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE50_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE50_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE50_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE50_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE51_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE51_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE51_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE51_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE51_LOCK0_R array element + subtype PAGE51_LOCK0_R_Element is HAL.UInt8; + + -- PAGE51_LOCK0_R array + type PAGE51_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE51_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE51_LOCK0_R + type PAGE51_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE51_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE51_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE51_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE51_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE51_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE51_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE51_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE51_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE51_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE51_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE51_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE51_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE51_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE51_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE51_LOCK1_R array element + subtype PAGE51_LOCK1_R_Element is HAL.UInt8; + + -- PAGE51_LOCK1_R array + type PAGE51_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE51_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE51_LOCK1_R + type PAGE51_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE51_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE51_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE51_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE51_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE51_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE51_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE51_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE51_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE52_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE52_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE52_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE52_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE52_LOCK0_R array element + subtype PAGE52_LOCK0_R_Element is HAL.UInt8; + + -- PAGE52_LOCK0_R array + type PAGE52_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE52_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE52_LOCK0_R + type PAGE52_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE52_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE52_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE52_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE52_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE52_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE52_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE52_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE52_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE52_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE52_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE52_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE52_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE52_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE52_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE52_LOCK1_R array element + subtype PAGE52_LOCK1_R_Element is HAL.UInt8; + + -- PAGE52_LOCK1_R array + type PAGE52_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE52_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE52_LOCK1_R + type PAGE52_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE52_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE52_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE52_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE52_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE52_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE52_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE52_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE52_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE53_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE53_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE53_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE53_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE53_LOCK0_R array element + subtype PAGE53_LOCK0_R_Element is HAL.UInt8; + + -- PAGE53_LOCK0_R array + type PAGE53_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE53_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE53_LOCK0_R + type PAGE53_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE53_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE53_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE53_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE53_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE53_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE53_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE53_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE53_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE53_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE53_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE53_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE53_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE53_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE53_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE53_LOCK1_R array element + subtype PAGE53_LOCK1_R_Element is HAL.UInt8; + + -- PAGE53_LOCK1_R array + type PAGE53_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE53_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE53_LOCK1_R + type PAGE53_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE53_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE53_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE53_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE53_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE53_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE53_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE53_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE53_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE54_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE54_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE54_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE54_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE54_LOCK0_R array element + subtype PAGE54_LOCK0_R_Element is HAL.UInt8; + + -- PAGE54_LOCK0_R array + type PAGE54_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE54_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE54_LOCK0_R + type PAGE54_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE54_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE54_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE54_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE54_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE54_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE54_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE54_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE54_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE54_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE54_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE54_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE54_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE54_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE54_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE54_LOCK1_R array element + subtype PAGE54_LOCK1_R_Element is HAL.UInt8; + + -- PAGE54_LOCK1_R array + type PAGE54_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE54_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE54_LOCK1_R + type PAGE54_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE54_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE54_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE54_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE54_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE54_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE54_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE54_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE54_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE55_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE55_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE55_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE55_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE55_LOCK0_R array element + subtype PAGE55_LOCK0_R_Element is HAL.UInt8; + + -- PAGE55_LOCK0_R array + type PAGE55_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE55_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE55_LOCK0_R + type PAGE55_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE55_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE55_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE55_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE55_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE55_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE55_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE55_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE55_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE55_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE55_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE55_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE55_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE55_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE55_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE55_LOCK1_R array element + subtype PAGE55_LOCK1_R_Element is HAL.UInt8; + + -- PAGE55_LOCK1_R array + type PAGE55_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE55_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE55_LOCK1_R + type PAGE55_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE55_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE55_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE55_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE55_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE55_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE55_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE55_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE55_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE56_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE56_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE56_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE56_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE56_LOCK0_R array element + subtype PAGE56_LOCK0_R_Element is HAL.UInt8; + + -- PAGE56_LOCK0_R array + type PAGE56_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE56_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE56_LOCK0_R + type PAGE56_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE56_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE56_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE56_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE56_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE56_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE56_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE56_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE56_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE56_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE56_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE56_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE56_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE56_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE56_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE56_LOCK1_R array element + subtype PAGE56_LOCK1_R_Element is HAL.UInt8; + + -- PAGE56_LOCK1_R array + type PAGE56_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE56_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE56_LOCK1_R + type PAGE56_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE56_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE56_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE56_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE56_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE56_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE56_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE56_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE56_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE57_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE57_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE57_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE57_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE57_LOCK0_R array element + subtype PAGE57_LOCK0_R_Element is HAL.UInt8; + + -- PAGE57_LOCK0_R array + type PAGE57_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE57_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE57_LOCK0_R + type PAGE57_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE57_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE57_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE57_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE57_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE57_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE57_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE57_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE57_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE57_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE57_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE57_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE57_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE57_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE57_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE57_LOCK1_R array element + subtype PAGE57_LOCK1_R_Element is HAL.UInt8; + + -- PAGE57_LOCK1_R array + type PAGE57_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE57_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE57_LOCK1_R + type PAGE57_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE57_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE57_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE57_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE57_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE57_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE57_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE57_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE57_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE58_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE58_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE58_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE58_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE58_LOCK0_R array element + subtype PAGE58_LOCK0_R_Element is HAL.UInt8; + + -- PAGE58_LOCK0_R array + type PAGE58_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE58_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE58_LOCK0_R + type PAGE58_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE58_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE58_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE58_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE58_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE58_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE58_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE58_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE58_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE58_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE58_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE58_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE58_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE58_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE58_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE58_LOCK1_R array element + subtype PAGE58_LOCK1_R_Element is HAL.UInt8; + + -- PAGE58_LOCK1_R array + type PAGE58_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE58_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE58_LOCK1_R + type PAGE58_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE58_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE58_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE58_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE58_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE58_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE58_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE58_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE58_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE59_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE59_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE59_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE59_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE59_LOCK0_R array element + subtype PAGE59_LOCK0_R_Element is HAL.UInt8; + + -- PAGE59_LOCK0_R array + type PAGE59_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE59_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE59_LOCK0_R + type PAGE59_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE59_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE59_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE59_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE59_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE59_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE59_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE59_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE59_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE59_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE59_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE59_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE59_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE59_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE59_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE59_LOCK1_R array element + subtype PAGE59_LOCK1_R_Element is HAL.UInt8; + + -- PAGE59_LOCK1_R array + type PAGE59_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE59_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE59_LOCK1_R + type PAGE59_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE59_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE59_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE59_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE59_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE59_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE59_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE59_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE59_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE60_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE60_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE60_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE60_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE60_LOCK0_R array element + subtype PAGE60_LOCK0_R_Element is HAL.UInt8; + + -- PAGE60_LOCK0_R array + type PAGE60_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE60_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE60_LOCK0_R + type PAGE60_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE60_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE60_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE60_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE60_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE60_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE60_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE60_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE60_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE60_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE60_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE60_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE60_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE60_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE60_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE60_LOCK1_R array element + subtype PAGE60_LOCK1_R_Element is HAL.UInt8; + + -- PAGE60_LOCK1_R array + type PAGE60_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE60_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE60_LOCK1_R + type PAGE60_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE60_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE60_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE60_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE60_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE60_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE60_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE60_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE60_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE61_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE61_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE61_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE61_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE61_LOCK0_R array element + subtype PAGE61_LOCK0_R_Element is HAL.UInt8; + + -- PAGE61_LOCK0_R array + type PAGE61_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE61_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE61_LOCK0_R + type PAGE61_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE61_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE61_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE61_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE61_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE61_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE61_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE61_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE61_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE61_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE61_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE61_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE61_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE61_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE61_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE61_LOCK1_R array element + subtype PAGE61_LOCK1_R_Element is HAL.UInt8; + + -- PAGE61_LOCK1_R array + type PAGE61_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE61_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE61_LOCK1_R + type PAGE61_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE61_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE61_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE61_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE61_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE61_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE61_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE61_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE61_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE62_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE62_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE62_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE62_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE62_LOCK0_R array element + subtype PAGE62_LOCK0_R_Element is HAL.UInt8; + + -- PAGE62_LOCK0_R array + type PAGE62_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE62_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE62_LOCK0_R + type PAGE62_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE62_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE62_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE62_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE62_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE62_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE62_LOCK0_NO_KEY_STATE_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE62_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE62_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE62_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE62_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE62_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE62_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE62_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE62_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE62_LOCK1_R array element + subtype PAGE62_LOCK1_R_Element is HAL.UInt8; + + -- PAGE62_LOCK1_R array + type PAGE62_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE62_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE62_LOCK1_R + type PAGE62_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE62_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE62_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE62_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE62_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE62_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE62_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE62_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE62_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PAGE63_LOCK0_KEY_W_Field is HAL.UInt3; + subtype PAGE63_LOCK0_KEY_R_Field is HAL.UInt3; + + -- State when at least one key is registered for this page and no matching + -- key has been entered. + type PAGE63_LOCK0_NO_KEY_STATE_Field is + (read_only, + inaccessible) + with Size => 1; + for PAGE63_LOCK0_NO_KEY_STATE_Field use + (read_only => 0, + inaccessible => 1); + + -- PAGE63_LOCK0_R array element + subtype PAGE63_LOCK0_R_Element is HAL.UInt8; + + -- PAGE63_LOCK0_R array + type PAGE63_LOCK0_R_Field_Array is array (1 .. 2) + of PAGE63_LOCK0_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE63_LOCK0_R + type PAGE63_LOCK0_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE63_LOCK0_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE63_LOCK0_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE63_LOCK0_Register is record + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- write access, or 0 if no such key is required. + KEY_W : PAGE63_LOCK0_KEY_W_Field; + -- Read-only. Index 1-6 of a hardware key which must be entered to grant + -- read access, or 0 if no such key is required. + KEY_R : PAGE63_LOCK0_KEY_R_Field; + -- Read-only. State when at least one key is registered for this page + -- and no matching key has been entered. + NO_KEY_STATE : PAGE63_LOCK0_NO_KEY_STATE_Field; + -- Read-only. Decommission for RMA of a suspected faulty device. This + -- re-enables the factory test JTAG interface, and makes pages 3 through + -- 61 of the OTP permanently inaccessible. + RMA : Boolean; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE63_LOCK0_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE63_LOCK0_Register use record + KEY_W at 0 range 0 .. 2; + KEY_R at 0 range 3 .. 5; + NO_KEY_STATE at 0 range 6 .. 6; + RMA at 0 range 7 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Lock state for Secure accesses to this page. Thermometer-coded, so lock + -- state can be advanced permanently from any state to any less-permissive + -- state by programming OTP. Software can also advance the lock state + -- temporarily (until next OTP reset) using the SW_LOCKx registers. + type PAGE63_LOCK1_LOCK_S_Field is + (-- Page is fully accessible by Secure software. + read_write, + -- Page can be read by Secure software, but can not be written. + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Secure software. + inaccessible) + with Size => 2; + for PAGE63_LOCK1_LOCK_S_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Lock state for Non-secure accesses to this page. Thermometer-coded, so + -- lock state can be advanced permanently from any state to any + -- less-permissive state by programming OTP. Software can also advance the + -- lock state temporarily (until next OTP reset) using the SW_LOCKx + -- registers. Note that READ_WRITE and READ_ONLY are equivalent in + -- hardware, as the SBPI programming interface is not accessible to + -- Non-secure software. However, Secure software may check these bits to + -- apply write permissions to a Non-secure OTP programming API. + type PAGE63_LOCK1_LOCK_NS_Field is + (-- Page can be read by Non-secure software, and Secure software may permit +-- Non-secure writes. + read_write, + -- Page can be read by Non-secure software + read_only, + -- Do not use. Behaves the same as INACCESSIBLE. + reserved, + -- Page can not be accessed by Non-secure software. + inaccessible) + with Size => 2; + for PAGE63_LOCK1_LOCK_NS_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- Dummy lock bits reserved for bootloaders (including the RP2350 USB + -- bootloader) to store their own OTP access permissions. No hardware + -- effect, and no corresponding SW_LOCKx registers. + type PAGE63_LOCK1_LOCK_BL_Field is + (-- Bootloader permits user reads and writes to this page + read_write, + -- Bootloader permits user reads of this page + read_only, + -- Do not use. Behaves the same as INACCESSIBLE + reserved, + -- Bootloader does not permit user access to this page + inaccessible) + with Size => 2; + for PAGE63_LOCK1_LOCK_BL_Field use + (read_write => 0, + read_only => 1, + reserved => 2, + inaccessible => 3); + + -- PAGE63_LOCK1_R array element + subtype PAGE63_LOCK1_R_Element is HAL.UInt8; + + -- PAGE63_LOCK1_R array + type PAGE63_LOCK1_R_Field_Array is array (1 .. 2) + of PAGE63_LOCK1_R_Element + with Component_Size => 8, Size => 16; + + -- Type definition for PAGE63_LOCK1_R + type PAGE63_LOCK1_R_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- R as a value + Val : HAL.UInt16; + when True => + -- R as an array + Arr : PAGE63_LOCK1_R_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PAGE63_LOCK1_R_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + type PAGE63_LOCK1_Register is record + -- Read-only. Lock state for Secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. + LOCK_S : PAGE63_LOCK1_LOCK_S_Field; + -- Read-only. Lock state for Non-secure accesses to this page. + -- Thermometer-coded, so lock state can be advanced permanently from any + -- state to any less-permissive state by programming OTP. Software can + -- also advance the lock state temporarily (until next OTP reset) using + -- the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are + -- equivalent in hardware, as the SBPI programming interface is not + -- accessible to Non-secure software. However, Secure software may check + -- these bits to apply write permissions to a Non-secure OTP programming + -- API. + LOCK_NS : PAGE63_LOCK1_LOCK_NS_Field; + -- Read-only. Dummy lock bits reserved for bootloaders (including the + -- RP2350 USB bootloader) to store their own OTP access permissions. No + -- hardware effect, and no corresponding SW_LOCKx registers. + LOCK_BL : PAGE63_LOCK1_LOCK_BL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Redundant copy of bits 7:0 + R : PAGE63_LOCK1_R_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAGE63_LOCK1_Register use record + LOCK_S at 0 range 0 .. 1; + LOCK_NS at 0 range 2 .. 3; + LOCK_BL at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + R at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Predefined OTP data layout for RP2350 + type OTP_DATA_RAW_Peripheral is record + -- Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a + -- 64-bit random identifier for this chip, which can be read from the + -- USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + -- The number of random bits makes the occurrence of twins exceedingly + -- unlikely: for example, a fleet of a hundred million devices has a + -- 99.97% probability of no twinned IDs. This is estimated to be lower + -- than the occurrence of process errors in the assignment of sequential + -- random IDs, and for practical purposes CHIPID may be treated as + -- unique. + CHIPID0 : aliased CHIPID0_Register; + -- Bits 31:16 of public device ID (ECC) + CHIPID1 : aliased CHIPID1_Register; + -- Bits 47:32 of public device ID (ECC) + CHIPID2 : aliased CHIPID2_Register; + -- Bits 63:48 of public device ID (ECC) + CHIPID3 : aliased CHIPID3_Register; + -- Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + -- rows form a 128-bit random number generated during device test. This + -- ID is not exposed through the USB PICOBOOT GET_INFO command or the + -- ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP + -- access point can read the entirety of page 0, so this value is not + -- meaningfully private unless the USB PICOBOOT interface is disabled + -- via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + RANDID0 : aliased RANDID0_Register; + -- Bits 31:16 of private per-device random number (ECC) + RANDID1 : aliased RANDID1_Register; + -- Bits 47:32 of private per-device random number (ECC) + RANDID2 : aliased RANDID2_Register; + -- Bits 63:48 of private per-device random number (ECC) + RANDID3 : aliased RANDID3_Register; + -- Bits 79:64 of private per-device random number (ECC) + RANDID4 : aliased RANDID4_Register; + -- Bits 95:80 of private per-device random number (ECC) + RANDID5 : aliased RANDID5_Register; + -- Bits 111:96 of private per-device random number (ECC) + RANDID6 : aliased RANDID6_Register; + -- Bits 127:112 of private per-device random number (ECC) + RANDID7 : aliased RANDID7_Register; + -- Ring oscillator frequency in kHz, measured during manufacturing (ECC) + -- This is measured at 1.1 V, at room temperature, with the ROSC + -- configuration registers in their reset state. + ROSC_CALIB : aliased ROSC_CALIB_Register; + -- Low-power oscillator frequency in Hz, measured during manufacturing + -- (ECC) This is measured at 1.1V, at room temperature, with the LPOSC + -- trim register in its reset state. + LPOSC_CALIB : aliased LPOSC_CALIB_Register; + -- The number of main user GPIOs (bank 0). Should read 48 in the QFN80 + -- package, and 30 in the QFN60 package. (ECC) + NUM_GPIOS : aliased NUM_GPIOS_Register; + -- Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + -- 0x4c11db7, input reflected, output reflected, seed all-ones, final + -- XOR all-ones) (ECC) + INFO_CRC0 : aliased INFO_CRC0_Register; + -- Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + INFO_CRC1 : aliased INFO_CRC1_Register; + -- Page 0 critical boot flags (RBIT-8) + CRIT0 : aliased CRIT0_Register; + -- Redundant copy of CRIT0 + CRIT0_R1 : aliased CRIT0_R1_Register; + -- Redundant copy of CRIT0 + CRIT0_R2 : aliased CRIT0_R2_Register; + -- Redundant copy of CRIT0 + CRIT0_R3 : aliased CRIT0_R3_Register; + -- Redundant copy of CRIT0 + CRIT0_R4 : aliased CRIT0_R4_Register; + -- Redundant copy of CRIT0 + CRIT0_R5 : aliased CRIT0_R5_Register; + -- Redundant copy of CRIT0 + CRIT0_R6 : aliased CRIT0_R6_Register; + -- Redundant copy of CRIT0 + CRIT0_R7 : aliased CRIT0_R7_Register; + -- Page 1 critical boot flags (RBIT-8) + CRIT1 : aliased CRIT1_Register; + -- Redundant copy of CRIT1 + CRIT1_R1 : aliased CRIT1_R1_Register; + -- Redundant copy of CRIT1 + CRIT1_R2 : aliased CRIT1_R2_Register; + -- Redundant copy of CRIT1 + CRIT1_R3 : aliased CRIT1_R3_Register; + -- Redundant copy of CRIT1 + CRIT1_R4 : aliased CRIT1_R4_Register; + -- Redundant copy of CRIT1 + CRIT1_R5 : aliased CRIT1_R5_Register; + -- Redundant copy of CRIT1 + CRIT1_R6 : aliased CRIT1_R6_Register; + -- Redundant copy of CRIT1 + CRIT1_R7 : aliased CRIT1_R7_Register; + -- Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + -- always supersede enables. Enables are provided where there are other + -- configurations in OTP that must be valid. (RBIT-3) + BOOT_FLAGS0 : aliased BOOT_FLAGS0_Register; + -- Redundant copy of BOOT_FLAGS0 + BOOT_FLAGS0_R1 : aliased BOOT_FLAGS0_R1_Register; + -- Redundant copy of BOOT_FLAGS0 + BOOT_FLAGS0_R2 : aliased BOOT_FLAGS0_R2_Register; + -- Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + -- always supersede enables. Enables are provided where there are other + -- configurations in OTP that must be valid. (RBIT-3) + BOOT_FLAGS1 : aliased BOOT_FLAGS1_Register; + -- Redundant copy of BOOT_FLAGS1 + BOOT_FLAGS1_R1 : aliased BOOT_FLAGS1_R1_Register; + -- Redundant copy of BOOT_FLAGS1 + BOOT_FLAGS1_R2 : aliased BOOT_FLAGS1_R2_Register; + -- Default boot version thermometer counter, bits 23:0 (RBIT-3) + DEFAULT_BOOT_VERSION0 : aliased DEFAULT_BOOT_VERSION0_Register; + -- Redundant copy of DEFAULT_BOOT_VERSION0 + DEFAULT_BOOT_VERSION0_R1 : aliased DEFAULT_BOOT_VERSION0_R1_Register; + -- Redundant copy of DEFAULT_BOOT_VERSION0 + DEFAULT_BOOT_VERSION0_R2 : aliased DEFAULT_BOOT_VERSION0_R2_Register; + -- Default boot version thermometer counter, bits 47:24 (RBIT-3) + DEFAULT_BOOT_VERSION1 : aliased DEFAULT_BOOT_VERSION1_Register; + -- Redundant copy of DEFAULT_BOOT_VERSION1 + DEFAULT_BOOT_VERSION1_R1 : aliased DEFAULT_BOOT_VERSION1_R1_Register; + -- Redundant copy of DEFAULT_BOOT_VERSION1 + DEFAULT_BOOT_VERSION1_R2 : aliased DEFAULT_BOOT_VERSION1_R2_Register; + -- Stores information about external flash device(s). (ECC) Assumed to + -- be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + FLASH_DEVINFO : aliased FLASH_DEVINFO_Register; + -- Gap between partition table slot 0 and slot 1 at the start of flash + -- (the default size is 4096 bytes) (ECC) Enabled by the + -- OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is + -- 4096 * (value + 1) + FLASH_PARTITION_SLOT_SIZE : aliased FLASH_PARTITION_SLOT_SIZE_Register; + -- Pin configuration for LED status, used by USB bootloader. (ECC) Must + -- be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + BOOTSEL_LED_CFG : aliased BOOTSEL_LED_CFG_Register; + -- Optional PLL configuration for BOOTSEL mode. (ECC) This should be + -- configured to produce an exact 48 MHz based on the crystal oscillator + -- frequency. User mode software may also use this value to calculate + -- the expected crystal frequency based on an assumed 48 MHz PLL output. + -- If no configuration is given, the crystal is assumed to be 12 MHz. + -- The PLL frequency can be calculated as: PLL out = (XOSC frequency / + -- (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + -- frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) + -- x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the + -- value stored in this OTP location is the actual divisor value minus + -- one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is + -- set in BOOT_FLAGS0. That bit should be set only after this row and + -- BOOTSEL_XOSC_CFG are both correctly programmed. + BOOTSEL_PLL_CFG : aliased BOOTSEL_PLL_CFG_Register; + -- Non-default crystal oscillator configuration for the USB bootloader. + -- (ECC) These values may also be used by user code configuring the + -- crystal oscillator. Used if and only if + -- ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That + -- bit should be set only after this row and BOOTSEL_PLL_CFG are both + -- correctly programmed. + BOOTSEL_XOSC_CFG : aliased BOOTSEL_XOSC_CFG_Register; + -- USB boot specific feature flags (RBIT-3) + USB_BOOT_FLAGS : aliased USB_BOOT_FLAGS_Register; + -- Redundant copy of USB_BOOT_FLAGS + USB_BOOT_FLAGS_R1 : aliased USB_BOOT_FLAGS_R1_Register; + -- Redundant copy of USB_BOOT_FLAGS + USB_BOOT_FLAGS_R2 : aliased USB_BOOT_FLAGS_R2_Register; + -- Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table + -- has 16 rows, each of which are also ECC and marked valid by the + -- corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are + -- either _VALUEs where the 16 bit value is used as is, or _STRDEFs + -- which acts as a pointers to a string value. The value stored in a + -- _STRDEF is two separate bytes: The low seven bits of the first (LSB) + -- byte indicates the number of characters in the string, and the top + -- bit of the first (LSB) byte if set to indicate that each character in + -- the string is two bytes (Unicode) versus one byte if unset. The + -- second (MSB) byte represents the location of the string data, and is + -- encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. + -- the row of the start of the string is USB_WHITE_LABEL_ADDR value + + -- msb_byte. In each case, the corresponding valid bit enables replacing + -- the default value for the corresponding item provided by the boot + -- rom. Note that Unicode _STRDEFs are only supported for + -- USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and + -- USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if + -- specified for other fields, and non-unicode values for these three + -- items will be converted to Unicode characters by setting the upper 8 + -- bits to zero. Note that if the USB_WHITE_LABEL structure or the + -- corresponding strings are not readable by BOOTSEL mode based on OTP + -- permissions, or if alignment requirements are not met, then the + -- corresponding default values are used. The index values indicate + -- where each field is located (row USB_WHITE_LABEL_ADDR value + index): + USB_WHITE_LABEL_ADDR : aliased USB_WHITE_LABEL_ADDR_Register; + -- OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + -- the bootrom will load from this location into SRAM and then directly + -- enter the loaded image. Note that the image must be signed if + -- SECURE_BOOT_ENABLE is set. The image itself is assumed to be + -- ECC-protected. This must be an even number. Equivalently, the OTP + -- boot image must start at a word-aligned location in the ECC read data + -- address window. + OTPBOOT_SRC : aliased OTPBOOT_SRC_Register; + -- Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. + -- The total image size must be a multiple of 4 bytes (32 bits). + OTPBOOT_LEN : aliased OTPBOOT_LEN_Register; + -- Bits 15:0 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + OTPBOOT_DST0 : aliased OTPBOOT_DST0_Register; + -- Bits 31:16 of the OTP boot image load destination (and entry point). + -- (ECC) This must be a location in main SRAM (main SRAM is addresses + -- 0x20000000 through 0x20082000) and must be word-aligned. + OTPBOOT_DST1 : aliased OTPBOOT_DST1_Register; + -- Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_0 : aliased BOOTKEY0_0_Register; + -- Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_1 : aliased BOOTKEY0_1_Register; + -- Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_2 : aliased BOOTKEY0_2_Register; + -- Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_3 : aliased BOOTKEY0_3_Register; + -- Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_4 : aliased BOOTKEY0_4_Register; + -- Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_5 : aliased BOOTKEY0_5_Register; + -- Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_6 : aliased BOOTKEY0_6_Register; + -- Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_7 : aliased BOOTKEY0_7_Register; + -- Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_8 : aliased BOOTKEY0_8_Register; + -- Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_9 : aliased BOOTKEY0_9_Register; + -- Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_10 : aliased BOOTKEY0_10_Register; + -- Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_11 : aliased BOOTKEY0_11_Register; + -- Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_12 : aliased BOOTKEY0_12_Register; + -- Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_13 : aliased BOOTKEY0_13_Register; + -- Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_14 : aliased BOOTKEY0_14_Register; + -- Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + BOOTKEY0_15 : aliased BOOTKEY0_15_Register; + -- Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_0 : aliased BOOTKEY1_0_Register; + -- Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_1 : aliased BOOTKEY1_1_Register; + -- Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_2 : aliased BOOTKEY1_2_Register; + -- Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_3 : aliased BOOTKEY1_3_Register; + -- Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_4 : aliased BOOTKEY1_4_Register; + -- Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_5 : aliased BOOTKEY1_5_Register; + -- Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_6 : aliased BOOTKEY1_6_Register; + -- Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_7 : aliased BOOTKEY1_7_Register; + -- Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_8 : aliased BOOTKEY1_8_Register; + -- Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_9 : aliased BOOTKEY1_9_Register; + -- Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_10 : aliased BOOTKEY1_10_Register; + -- Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_11 : aliased BOOTKEY1_11_Register; + -- Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_12 : aliased BOOTKEY1_12_Register; + -- Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_13 : aliased BOOTKEY1_13_Register; + -- Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_14 : aliased BOOTKEY1_14_Register; + -- Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + BOOTKEY1_15 : aliased BOOTKEY1_15_Register; + -- Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_0 : aliased BOOTKEY2_0_Register; + -- Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_1 : aliased BOOTKEY2_1_Register; + -- Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_2 : aliased BOOTKEY2_2_Register; + -- Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_3 : aliased BOOTKEY2_3_Register; + -- Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_4 : aliased BOOTKEY2_4_Register; + -- Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_5 : aliased BOOTKEY2_5_Register; + -- Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_6 : aliased BOOTKEY2_6_Register; + -- Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_7 : aliased BOOTKEY2_7_Register; + -- Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_8 : aliased BOOTKEY2_8_Register; + -- Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_9 : aliased BOOTKEY2_9_Register; + -- Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_10 : aliased BOOTKEY2_10_Register; + -- Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_11 : aliased BOOTKEY2_11_Register; + -- Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_12 : aliased BOOTKEY2_12_Register; + -- Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_13 : aliased BOOTKEY2_13_Register; + -- Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_14 : aliased BOOTKEY2_14_Register; + -- Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + BOOTKEY2_15 : aliased BOOTKEY2_15_Register; + -- Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_0 : aliased BOOTKEY3_0_Register; + -- Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_1 : aliased BOOTKEY3_1_Register; + -- Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_2 : aliased BOOTKEY3_2_Register; + -- Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_3 : aliased BOOTKEY3_3_Register; + -- Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_4 : aliased BOOTKEY3_4_Register; + -- Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_5 : aliased BOOTKEY3_5_Register; + -- Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_6 : aliased BOOTKEY3_6_Register; + -- Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_7 : aliased BOOTKEY3_7_Register; + -- Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_8 : aliased BOOTKEY3_8_Register; + -- Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_9 : aliased BOOTKEY3_9_Register; + -- Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_10 : aliased BOOTKEY3_10_Register; + -- Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_11 : aliased BOOTKEY3_11_Register; + -- Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_12 : aliased BOOTKEY3_12_Register; + -- Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_13 : aliased BOOTKEY3_13_Register; + -- Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_14 : aliased BOOTKEY3_14_Register; + -- Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + BOOTKEY3_15 : aliased BOOTKEY3_15_Register; + -- Bits 15:0 of OTP access key 1 (ECC) + KEY1_0 : aliased KEY1_0_Register; + -- Bits 31:16 of OTP access key 1 (ECC) + KEY1_1 : aliased KEY1_1_Register; + -- Bits 47:32 of OTP access key 1 (ECC) + KEY1_2 : aliased KEY1_2_Register; + -- Bits 63:48 of OTP access key 1 (ECC) + KEY1_3 : aliased KEY1_3_Register; + -- Bits 79:64 of OTP access key 1 (ECC) + KEY1_4 : aliased KEY1_4_Register; + -- Bits 95:80 of OTP access key 1 (ECC) + KEY1_5 : aliased KEY1_5_Register; + -- Bits 111:96 of OTP access key 1 (ECC) + KEY1_6 : aliased KEY1_6_Register; + -- Bits 127:112 of OTP access key 1 (ECC) + KEY1_7 : aliased KEY1_7_Register; + -- Bits 15:0 of OTP access key 2 (ECC) + KEY2_0 : aliased KEY2_0_Register; + -- Bits 31:16 of OTP access key 2 (ECC) + KEY2_1 : aliased KEY2_1_Register; + -- Bits 47:32 of OTP access key 2 (ECC) + KEY2_2 : aliased KEY2_2_Register; + -- Bits 63:48 of OTP access key 2 (ECC) + KEY2_3 : aliased KEY2_3_Register; + -- Bits 79:64 of OTP access key 2 (ECC) + KEY2_4 : aliased KEY2_4_Register; + -- Bits 95:80 of OTP access key 2 (ECC) + KEY2_5 : aliased KEY2_5_Register; + -- Bits 111:96 of OTP access key 2 (ECC) + KEY2_6 : aliased KEY2_6_Register; + -- Bits 127:112 of OTP access key 2 (ECC) + KEY2_7 : aliased KEY2_7_Register; + -- Bits 15:0 of OTP access key 3 (ECC) + KEY3_0 : aliased KEY3_0_Register; + -- Bits 31:16 of OTP access key 3 (ECC) + KEY3_1 : aliased KEY3_1_Register; + -- Bits 47:32 of OTP access key 3 (ECC) + KEY3_2 : aliased KEY3_2_Register; + -- Bits 63:48 of OTP access key 3 (ECC) + KEY3_3 : aliased KEY3_3_Register; + -- Bits 79:64 of OTP access key 3 (ECC) + KEY3_4 : aliased KEY3_4_Register; + -- Bits 95:80 of OTP access key 3 (ECC) + KEY3_5 : aliased KEY3_5_Register; + -- Bits 111:96 of OTP access key 3 (ECC) + KEY3_6 : aliased KEY3_6_Register; + -- Bits 127:112 of OTP access key 3 (ECC) + KEY3_7 : aliased KEY3_7_Register; + -- Bits 15:0 of OTP access key 4 (ECC) + KEY4_0 : aliased KEY4_0_Register; + -- Bits 31:16 of OTP access key 4 (ECC) + KEY4_1 : aliased KEY4_1_Register; + -- Bits 47:32 of OTP access key 4 (ECC) + KEY4_2 : aliased KEY4_2_Register; + -- Bits 63:48 of OTP access key 4 (ECC) + KEY4_3 : aliased KEY4_3_Register; + -- Bits 79:64 of OTP access key 4 (ECC) + KEY4_4 : aliased KEY4_4_Register; + -- Bits 95:80 of OTP access key 4 (ECC) + KEY4_5 : aliased KEY4_5_Register; + -- Bits 111:96 of OTP access key 4 (ECC) + KEY4_6 : aliased KEY4_6_Register; + -- Bits 127:112 of OTP access key 4 (ECC) + KEY4_7 : aliased KEY4_7_Register; + -- Bits 15:0 of OTP access key 5 (ECC) + KEY5_0 : aliased KEY5_0_Register; + -- Bits 31:16 of OTP access key 5 (ECC) + KEY5_1 : aliased KEY5_1_Register; + -- Bits 47:32 of OTP access key 5 (ECC) + KEY5_2 : aliased KEY5_2_Register; + -- Bits 63:48 of OTP access key 5 (ECC) + KEY5_3 : aliased KEY5_3_Register; + -- Bits 79:64 of OTP access key 5 (ECC) + KEY5_4 : aliased KEY5_4_Register; + -- Bits 95:80 of OTP access key 5 (ECC) + KEY5_5 : aliased KEY5_5_Register; + -- Bits 111:96 of OTP access key 5 (ECC) + KEY5_6 : aliased KEY5_6_Register; + -- Bits 127:112 of OTP access key 5 (ECC) + KEY5_7 : aliased KEY5_7_Register; + -- Bits 15:0 of OTP access key 6 (ECC) + KEY6_0 : aliased KEY6_0_Register; + -- Bits 31:16 of OTP access key 6 (ECC) + KEY6_1 : aliased KEY6_1_Register; + -- Bits 47:32 of OTP access key 6 (ECC) + KEY6_2 : aliased KEY6_2_Register; + -- Bits 63:48 of OTP access key 6 (ECC) + KEY6_3 : aliased KEY6_3_Register; + -- Bits 79:64 of OTP access key 6 (ECC) + KEY6_4 : aliased KEY6_4_Register; + -- Bits 95:80 of OTP access key 6 (ECC) + KEY6_5 : aliased KEY6_5_Register; + -- Bits 111:96 of OTP access key 6 (ECC) + KEY6_6 : aliased KEY6_6_Register; + -- Bits 127:112 of OTP access key 6 (ECC) + KEY6_7 : aliased KEY6_7_Register; + -- Valid flag for key 1. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY1_VALID : aliased KEY1_VALID_Register; + -- Valid flag for key 2. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY2_VALID : aliased KEY2_VALID_Register; + -- Valid flag for key 3. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY3_VALID : aliased KEY3_VALID_Register; + -- Valid flag for key 4. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY4_VALID : aliased KEY4_VALID_Register; + -- Valid flag for key 5. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY5_VALID : aliased KEY5_VALID_Register; + -- Valid flag for key 6. Once the valid flag is set, the key can no + -- longer be read or written, and becomes a valid fixed key for + -- protecting OTP pages. + KEY6_VALID : aliased KEY6_VALID_Register; + -- Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE0_LOCK0 : aliased PAGE0_LOCK0_Register; + -- Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are + -- stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE0_LOCK1 : aliased PAGE0_LOCK1_Register; + -- Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE1_LOCK0 : aliased PAGE1_LOCK0_Register; + -- Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE1_LOCK1 : aliased PAGE1_LOCK1_Register; + -- Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE2_LOCK0 : aliased PAGE2_LOCK0_Register; + -- Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE2_LOCK1 : aliased PAGE2_LOCK1_Register; + -- Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE3_LOCK0 : aliased PAGE3_LOCK0_Register; + -- Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE3_LOCK1 : aliased PAGE3_LOCK1_Register; + -- Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE4_LOCK0 : aliased PAGE4_LOCK0_Register; + -- Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE4_LOCK1 : aliased PAGE4_LOCK1_Register; + -- Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE5_LOCK0 : aliased PAGE5_LOCK0_Register; + -- Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE5_LOCK1 : aliased PAGE5_LOCK1_Register; + -- Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE6_LOCK0 : aliased PAGE6_LOCK0_Register; + -- Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE6_LOCK1 : aliased PAGE6_LOCK1_Register; + -- Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE7_LOCK0 : aliased PAGE7_LOCK0_Register; + -- Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE7_LOCK1 : aliased PAGE7_LOCK1_Register; + -- Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE8_LOCK0 : aliased PAGE8_LOCK0_Register; + -- Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE8_LOCK1 : aliased PAGE8_LOCK1_Register; + -- Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE9_LOCK0 : aliased PAGE9_LOCK0_Register; + -- Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE9_LOCK1 : aliased PAGE9_LOCK1_Register; + -- Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE10_LOCK0 : aliased PAGE10_LOCK0_Register; + -- Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE10_LOCK1 : aliased PAGE10_LOCK1_Register; + -- Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE11_LOCK0 : aliased PAGE11_LOCK0_Register; + -- Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE11_LOCK1 : aliased PAGE11_LOCK1_Register; + -- Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE12_LOCK0 : aliased PAGE12_LOCK0_Register; + -- Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE12_LOCK1 : aliased PAGE12_LOCK1_Register; + -- Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE13_LOCK0 : aliased PAGE13_LOCK0_Register; + -- Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE13_LOCK1 : aliased PAGE13_LOCK1_Register; + -- Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE14_LOCK0 : aliased PAGE14_LOCK0_Register; + -- Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE14_LOCK1 : aliased PAGE14_LOCK1_Register; + -- Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE15_LOCK0 : aliased PAGE15_LOCK0_Register; + -- Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE15_LOCK1 : aliased PAGE15_LOCK1_Register; + -- Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE16_LOCK0 : aliased PAGE16_LOCK0_Register; + -- Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE16_LOCK1 : aliased PAGE16_LOCK1_Register; + -- Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE17_LOCK0 : aliased PAGE17_LOCK0_Register; + -- Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE17_LOCK1 : aliased PAGE17_LOCK1_Register; + -- Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE18_LOCK0 : aliased PAGE18_LOCK0_Register; + -- Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE18_LOCK1 : aliased PAGE18_LOCK1_Register; + -- Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE19_LOCK0 : aliased PAGE19_LOCK0_Register; + -- Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE19_LOCK1 : aliased PAGE19_LOCK1_Register; + -- Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE20_LOCK0 : aliased PAGE20_LOCK0_Register; + -- Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE20_LOCK1 : aliased PAGE20_LOCK1_Register; + -- Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE21_LOCK0 : aliased PAGE21_LOCK0_Register; + -- Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE21_LOCK1 : aliased PAGE21_LOCK1_Register; + -- Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE22_LOCK0 : aliased PAGE22_LOCK0_Register; + -- Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE22_LOCK1 : aliased PAGE22_LOCK1_Register; + -- Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE23_LOCK0 : aliased PAGE23_LOCK0_Register; + -- Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE23_LOCK1 : aliased PAGE23_LOCK1_Register; + -- Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE24_LOCK0 : aliased PAGE24_LOCK0_Register; + -- Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE24_LOCK1 : aliased PAGE24_LOCK1_Register; + -- Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE25_LOCK0 : aliased PAGE25_LOCK0_Register; + -- Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE25_LOCK1 : aliased PAGE25_LOCK1_Register; + -- Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE26_LOCK0 : aliased PAGE26_LOCK0_Register; + -- Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE26_LOCK1 : aliased PAGE26_LOCK1_Register; + -- Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE27_LOCK0 : aliased PAGE27_LOCK0_Register; + -- Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE27_LOCK1 : aliased PAGE27_LOCK1_Register; + -- Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE28_LOCK0 : aliased PAGE28_LOCK0_Register; + -- Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE28_LOCK1 : aliased PAGE28_LOCK1_Register; + -- Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE29_LOCK0 : aliased PAGE29_LOCK0_Register; + -- Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE29_LOCK1 : aliased PAGE29_LOCK1_Register; + -- Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE30_LOCK0 : aliased PAGE30_LOCK0_Register; + -- Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE30_LOCK1 : aliased PAGE30_LOCK1_Register; + -- Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE31_LOCK0 : aliased PAGE31_LOCK0_Register; + -- Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE31_LOCK1 : aliased PAGE31_LOCK1_Register; + -- Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE32_LOCK0 : aliased PAGE32_LOCK0_Register; + -- Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE32_LOCK1 : aliased PAGE32_LOCK1_Register; + -- Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE33_LOCK0 : aliased PAGE33_LOCK0_Register; + -- Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE33_LOCK1 : aliased PAGE33_LOCK1_Register; + -- Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE34_LOCK0 : aliased PAGE34_LOCK0_Register; + -- Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE34_LOCK1 : aliased PAGE34_LOCK1_Register; + -- Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE35_LOCK0 : aliased PAGE35_LOCK0_Register; + -- Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE35_LOCK1 : aliased PAGE35_LOCK1_Register; + -- Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE36_LOCK0 : aliased PAGE36_LOCK0_Register; + -- Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE36_LOCK1 : aliased PAGE36_LOCK1_Register; + -- Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE37_LOCK0 : aliased PAGE37_LOCK0_Register; + -- Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE37_LOCK1 : aliased PAGE37_LOCK1_Register; + -- Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE38_LOCK0 : aliased PAGE38_LOCK0_Register; + -- Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE38_LOCK1 : aliased PAGE38_LOCK1_Register; + -- Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE39_LOCK0 : aliased PAGE39_LOCK0_Register; + -- Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE39_LOCK1 : aliased PAGE39_LOCK1_Register; + -- Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE40_LOCK0 : aliased PAGE40_LOCK0_Register; + -- Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE40_LOCK1 : aliased PAGE40_LOCK1_Register; + -- Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE41_LOCK0 : aliased PAGE41_LOCK0_Register; + -- Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE41_LOCK1 : aliased PAGE41_LOCK1_Register; + -- Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE42_LOCK0 : aliased PAGE42_LOCK0_Register; + -- Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE42_LOCK1 : aliased PAGE42_LOCK1_Register; + -- Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE43_LOCK0 : aliased PAGE43_LOCK0_Register; + -- Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE43_LOCK1 : aliased PAGE43_LOCK1_Register; + -- Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE44_LOCK0 : aliased PAGE44_LOCK0_Register; + -- Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE44_LOCK1 : aliased PAGE44_LOCK1_Register; + -- Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE45_LOCK0 : aliased PAGE45_LOCK0_Register; + -- Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE45_LOCK1 : aliased PAGE45_LOCK1_Register; + -- Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE46_LOCK0 : aliased PAGE46_LOCK0_Register; + -- Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE46_LOCK1 : aliased PAGE46_LOCK1_Register; + -- Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE47_LOCK0 : aliased PAGE47_LOCK0_Register; + -- Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE47_LOCK1 : aliased PAGE47_LOCK1_Register; + -- Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE48_LOCK0 : aliased PAGE48_LOCK0_Register; + -- Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE48_LOCK1 : aliased PAGE48_LOCK1_Register; + -- Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE49_LOCK0 : aliased PAGE49_LOCK0_Register; + -- Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE49_LOCK1 : aliased PAGE49_LOCK1_Register; + -- Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE50_LOCK0 : aliased PAGE50_LOCK0_Register; + -- Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE50_LOCK1 : aliased PAGE50_LOCK1_Register; + -- Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE51_LOCK0 : aliased PAGE51_LOCK0_Register; + -- Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE51_LOCK1 : aliased PAGE51_LOCK1_Register; + -- Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE52_LOCK0 : aliased PAGE52_LOCK0_Register; + -- Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE52_LOCK1 : aliased PAGE52_LOCK1_Register; + -- Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE53_LOCK0 : aliased PAGE53_LOCK0_Register; + -- Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE53_LOCK1 : aliased PAGE53_LOCK1_Register; + -- Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE54_LOCK0 : aliased PAGE54_LOCK0_Register; + -- Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE54_LOCK1 : aliased PAGE54_LOCK1_Register; + -- Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE55_LOCK0 : aliased PAGE55_LOCK0_Register; + -- Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE55_LOCK1 : aliased PAGE55_LOCK1_Register; + -- Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE56_LOCK0 : aliased PAGE56_LOCK0_Register; + -- Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE56_LOCK1 : aliased PAGE56_LOCK1_Register; + -- Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE57_LOCK0 : aliased PAGE57_LOCK0_Register; + -- Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE57_LOCK1 : aliased PAGE57_LOCK1_Register; + -- Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE58_LOCK0 : aliased PAGE58_LOCK0_Register; + -- Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE58_LOCK1 : aliased PAGE58_LOCK1_Register; + -- Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE59_LOCK0 : aliased PAGE59_LOCK0_Register; + -- Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE59_LOCK1 : aliased PAGE59_LOCK1_Register; + -- Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE60_LOCK0 : aliased PAGE60_LOCK0_Register; + -- Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE60_LOCK1 : aliased PAGE60_LOCK1_Register; + -- Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE61_LOCK0 : aliased PAGE61_LOCK0_Register; + -- Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE61_LOCK1 : aliased PAGE61_LOCK1_Register; + -- Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE62_LOCK0 : aliased PAGE62_LOCK0_Register; + -- Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE62_LOCK1 : aliased PAGE62_LOCK1_Register; + -- Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE63_LOCK0 : aliased PAGE63_LOCK0_Register; + -- Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks + -- are stored with 3-way majority vote encoding, so that bits can be set + -- independently. This OTP location is always readable, and is + -- write-protected by its own permissions. + PAGE63_LOCK1 : aliased PAGE63_LOCK1_Register; + end record + with Volatile; + + for OTP_DATA_RAW_Peripheral use record + CHIPID0 at 16#0# range 0 .. 31; + CHIPID1 at 16#4# range 0 .. 31; + CHIPID2 at 16#8# range 0 .. 31; + CHIPID3 at 16#C# range 0 .. 31; + RANDID0 at 16#10# range 0 .. 31; + RANDID1 at 16#14# range 0 .. 31; + RANDID2 at 16#18# range 0 .. 31; + RANDID3 at 16#1C# range 0 .. 31; + RANDID4 at 16#20# range 0 .. 31; + RANDID5 at 16#24# range 0 .. 31; + RANDID6 at 16#28# range 0 .. 31; + RANDID7 at 16#2C# range 0 .. 31; + ROSC_CALIB at 16#40# range 0 .. 31; + LPOSC_CALIB at 16#44# range 0 .. 31; + NUM_GPIOS at 16#60# range 0 .. 31; + INFO_CRC0 at 16#D8# range 0 .. 31; + INFO_CRC1 at 16#DC# range 0 .. 31; + CRIT0 at 16#E0# range 0 .. 31; + CRIT0_R1 at 16#E4# range 0 .. 31; + CRIT0_R2 at 16#E8# range 0 .. 31; + CRIT0_R3 at 16#EC# range 0 .. 31; + CRIT0_R4 at 16#F0# range 0 .. 31; + CRIT0_R5 at 16#F4# range 0 .. 31; + CRIT0_R6 at 16#F8# range 0 .. 31; + CRIT0_R7 at 16#FC# range 0 .. 31; + CRIT1 at 16#100# range 0 .. 31; + CRIT1_R1 at 16#104# range 0 .. 31; + CRIT1_R2 at 16#108# range 0 .. 31; + CRIT1_R3 at 16#10C# range 0 .. 31; + CRIT1_R4 at 16#110# range 0 .. 31; + CRIT1_R5 at 16#114# range 0 .. 31; + CRIT1_R6 at 16#118# range 0 .. 31; + CRIT1_R7 at 16#11C# range 0 .. 31; + BOOT_FLAGS0 at 16#120# range 0 .. 31; + BOOT_FLAGS0_R1 at 16#124# range 0 .. 31; + BOOT_FLAGS0_R2 at 16#128# range 0 .. 31; + BOOT_FLAGS1 at 16#12C# range 0 .. 31; + BOOT_FLAGS1_R1 at 16#130# range 0 .. 31; + BOOT_FLAGS1_R2 at 16#134# range 0 .. 31; + DEFAULT_BOOT_VERSION0 at 16#138# range 0 .. 31; + DEFAULT_BOOT_VERSION0_R1 at 16#13C# range 0 .. 31; + DEFAULT_BOOT_VERSION0_R2 at 16#140# range 0 .. 31; + DEFAULT_BOOT_VERSION1 at 16#144# range 0 .. 31; + DEFAULT_BOOT_VERSION1_R1 at 16#148# range 0 .. 31; + DEFAULT_BOOT_VERSION1_R2 at 16#14C# range 0 .. 31; + FLASH_DEVINFO at 16#150# range 0 .. 31; + FLASH_PARTITION_SLOT_SIZE at 16#154# range 0 .. 31; + BOOTSEL_LED_CFG at 16#158# range 0 .. 31; + BOOTSEL_PLL_CFG at 16#15C# range 0 .. 31; + BOOTSEL_XOSC_CFG at 16#160# range 0 .. 31; + USB_BOOT_FLAGS at 16#164# range 0 .. 31; + USB_BOOT_FLAGS_R1 at 16#168# range 0 .. 31; + USB_BOOT_FLAGS_R2 at 16#16C# range 0 .. 31; + USB_WHITE_LABEL_ADDR at 16#170# range 0 .. 31; + OTPBOOT_SRC at 16#178# range 0 .. 31; + OTPBOOT_LEN at 16#17C# range 0 .. 31; + OTPBOOT_DST0 at 16#180# range 0 .. 31; + OTPBOOT_DST1 at 16#184# range 0 .. 31; + BOOTKEY0_0 at 16#200# range 0 .. 31; + BOOTKEY0_1 at 16#204# range 0 .. 31; + BOOTKEY0_2 at 16#208# range 0 .. 31; + BOOTKEY0_3 at 16#20C# range 0 .. 31; + BOOTKEY0_4 at 16#210# range 0 .. 31; + BOOTKEY0_5 at 16#214# range 0 .. 31; + BOOTKEY0_6 at 16#218# range 0 .. 31; + BOOTKEY0_7 at 16#21C# range 0 .. 31; + BOOTKEY0_8 at 16#220# range 0 .. 31; + BOOTKEY0_9 at 16#224# range 0 .. 31; + BOOTKEY0_10 at 16#228# range 0 .. 31; + BOOTKEY0_11 at 16#22C# range 0 .. 31; + BOOTKEY0_12 at 16#230# range 0 .. 31; + BOOTKEY0_13 at 16#234# range 0 .. 31; + BOOTKEY0_14 at 16#238# range 0 .. 31; + BOOTKEY0_15 at 16#23C# range 0 .. 31; + BOOTKEY1_0 at 16#240# range 0 .. 31; + BOOTKEY1_1 at 16#244# range 0 .. 31; + BOOTKEY1_2 at 16#248# range 0 .. 31; + BOOTKEY1_3 at 16#24C# range 0 .. 31; + BOOTKEY1_4 at 16#250# range 0 .. 31; + BOOTKEY1_5 at 16#254# range 0 .. 31; + BOOTKEY1_6 at 16#258# range 0 .. 31; + BOOTKEY1_7 at 16#25C# range 0 .. 31; + BOOTKEY1_8 at 16#260# range 0 .. 31; + BOOTKEY1_9 at 16#264# range 0 .. 31; + BOOTKEY1_10 at 16#268# range 0 .. 31; + BOOTKEY1_11 at 16#26C# range 0 .. 31; + BOOTKEY1_12 at 16#270# range 0 .. 31; + BOOTKEY1_13 at 16#274# range 0 .. 31; + BOOTKEY1_14 at 16#278# range 0 .. 31; + BOOTKEY1_15 at 16#27C# range 0 .. 31; + BOOTKEY2_0 at 16#280# range 0 .. 31; + BOOTKEY2_1 at 16#284# range 0 .. 31; + BOOTKEY2_2 at 16#288# range 0 .. 31; + BOOTKEY2_3 at 16#28C# range 0 .. 31; + BOOTKEY2_4 at 16#290# range 0 .. 31; + BOOTKEY2_5 at 16#294# range 0 .. 31; + BOOTKEY2_6 at 16#298# range 0 .. 31; + BOOTKEY2_7 at 16#29C# range 0 .. 31; + BOOTKEY2_8 at 16#2A0# range 0 .. 31; + BOOTKEY2_9 at 16#2A4# range 0 .. 31; + BOOTKEY2_10 at 16#2A8# range 0 .. 31; + BOOTKEY2_11 at 16#2AC# range 0 .. 31; + BOOTKEY2_12 at 16#2B0# range 0 .. 31; + BOOTKEY2_13 at 16#2B4# range 0 .. 31; + BOOTKEY2_14 at 16#2B8# range 0 .. 31; + BOOTKEY2_15 at 16#2BC# range 0 .. 31; + BOOTKEY3_0 at 16#2C0# range 0 .. 31; + BOOTKEY3_1 at 16#2C4# range 0 .. 31; + BOOTKEY3_2 at 16#2C8# range 0 .. 31; + BOOTKEY3_3 at 16#2CC# range 0 .. 31; + BOOTKEY3_4 at 16#2D0# range 0 .. 31; + BOOTKEY3_5 at 16#2D4# range 0 .. 31; + BOOTKEY3_6 at 16#2D8# range 0 .. 31; + BOOTKEY3_7 at 16#2DC# range 0 .. 31; + BOOTKEY3_8 at 16#2E0# range 0 .. 31; + BOOTKEY3_9 at 16#2E4# range 0 .. 31; + BOOTKEY3_10 at 16#2E8# range 0 .. 31; + BOOTKEY3_11 at 16#2EC# range 0 .. 31; + BOOTKEY3_12 at 16#2F0# range 0 .. 31; + BOOTKEY3_13 at 16#2F4# range 0 .. 31; + BOOTKEY3_14 at 16#2F8# range 0 .. 31; + BOOTKEY3_15 at 16#2FC# range 0 .. 31; + KEY1_0 at 16#3D20# range 0 .. 31; + KEY1_1 at 16#3D24# range 0 .. 31; + KEY1_2 at 16#3D28# range 0 .. 31; + KEY1_3 at 16#3D2C# range 0 .. 31; + KEY1_4 at 16#3D30# range 0 .. 31; + KEY1_5 at 16#3D34# range 0 .. 31; + KEY1_6 at 16#3D38# range 0 .. 31; + KEY1_7 at 16#3D3C# range 0 .. 31; + KEY2_0 at 16#3D40# range 0 .. 31; + KEY2_1 at 16#3D44# range 0 .. 31; + KEY2_2 at 16#3D48# range 0 .. 31; + KEY2_3 at 16#3D4C# range 0 .. 31; + KEY2_4 at 16#3D50# range 0 .. 31; + KEY2_5 at 16#3D54# range 0 .. 31; + KEY2_6 at 16#3D58# range 0 .. 31; + KEY2_7 at 16#3D5C# range 0 .. 31; + KEY3_0 at 16#3D60# range 0 .. 31; + KEY3_1 at 16#3D64# range 0 .. 31; + KEY3_2 at 16#3D68# range 0 .. 31; + KEY3_3 at 16#3D6C# range 0 .. 31; + KEY3_4 at 16#3D70# range 0 .. 31; + KEY3_5 at 16#3D74# range 0 .. 31; + KEY3_6 at 16#3D78# range 0 .. 31; + KEY3_7 at 16#3D7C# range 0 .. 31; + KEY4_0 at 16#3D80# range 0 .. 31; + KEY4_1 at 16#3D84# range 0 .. 31; + KEY4_2 at 16#3D88# range 0 .. 31; + KEY4_3 at 16#3D8C# range 0 .. 31; + KEY4_4 at 16#3D90# range 0 .. 31; + KEY4_5 at 16#3D94# range 0 .. 31; + KEY4_6 at 16#3D98# range 0 .. 31; + KEY4_7 at 16#3D9C# range 0 .. 31; + KEY5_0 at 16#3DA0# range 0 .. 31; + KEY5_1 at 16#3DA4# range 0 .. 31; + KEY5_2 at 16#3DA8# range 0 .. 31; + KEY5_3 at 16#3DAC# range 0 .. 31; + KEY5_4 at 16#3DB0# range 0 .. 31; + KEY5_5 at 16#3DB4# range 0 .. 31; + KEY5_6 at 16#3DB8# range 0 .. 31; + KEY5_7 at 16#3DBC# range 0 .. 31; + KEY6_0 at 16#3DC0# range 0 .. 31; + KEY6_1 at 16#3DC4# range 0 .. 31; + KEY6_2 at 16#3DC8# range 0 .. 31; + KEY6_3 at 16#3DCC# range 0 .. 31; + KEY6_4 at 16#3DD0# range 0 .. 31; + KEY6_5 at 16#3DD4# range 0 .. 31; + KEY6_6 at 16#3DD8# range 0 .. 31; + KEY6_7 at 16#3DDC# range 0 .. 31; + KEY1_VALID at 16#3DE4# range 0 .. 31; + KEY2_VALID at 16#3DE8# range 0 .. 31; + KEY3_VALID at 16#3DEC# range 0 .. 31; + KEY4_VALID at 16#3DF0# range 0 .. 31; + KEY5_VALID at 16#3DF4# range 0 .. 31; + KEY6_VALID at 16#3DF8# range 0 .. 31; + PAGE0_LOCK0 at 16#3E00# range 0 .. 31; + PAGE0_LOCK1 at 16#3E04# range 0 .. 31; + PAGE1_LOCK0 at 16#3E08# range 0 .. 31; + PAGE1_LOCK1 at 16#3E0C# range 0 .. 31; + PAGE2_LOCK0 at 16#3E10# range 0 .. 31; + PAGE2_LOCK1 at 16#3E14# range 0 .. 31; + PAGE3_LOCK0 at 16#3E18# range 0 .. 31; + PAGE3_LOCK1 at 16#3E1C# range 0 .. 31; + PAGE4_LOCK0 at 16#3E20# range 0 .. 31; + PAGE4_LOCK1 at 16#3E24# range 0 .. 31; + PAGE5_LOCK0 at 16#3E28# range 0 .. 31; + PAGE5_LOCK1 at 16#3E2C# range 0 .. 31; + PAGE6_LOCK0 at 16#3E30# range 0 .. 31; + PAGE6_LOCK1 at 16#3E34# range 0 .. 31; + PAGE7_LOCK0 at 16#3E38# range 0 .. 31; + PAGE7_LOCK1 at 16#3E3C# range 0 .. 31; + PAGE8_LOCK0 at 16#3E40# range 0 .. 31; + PAGE8_LOCK1 at 16#3E44# range 0 .. 31; + PAGE9_LOCK0 at 16#3E48# range 0 .. 31; + PAGE9_LOCK1 at 16#3E4C# range 0 .. 31; + PAGE10_LOCK0 at 16#3E50# range 0 .. 31; + PAGE10_LOCK1 at 16#3E54# range 0 .. 31; + PAGE11_LOCK0 at 16#3E58# range 0 .. 31; + PAGE11_LOCK1 at 16#3E5C# range 0 .. 31; + PAGE12_LOCK0 at 16#3E60# range 0 .. 31; + PAGE12_LOCK1 at 16#3E64# range 0 .. 31; + PAGE13_LOCK0 at 16#3E68# range 0 .. 31; + PAGE13_LOCK1 at 16#3E6C# range 0 .. 31; + PAGE14_LOCK0 at 16#3E70# range 0 .. 31; + PAGE14_LOCK1 at 16#3E74# range 0 .. 31; + PAGE15_LOCK0 at 16#3E78# range 0 .. 31; + PAGE15_LOCK1 at 16#3E7C# range 0 .. 31; + PAGE16_LOCK0 at 16#3E80# range 0 .. 31; + PAGE16_LOCK1 at 16#3E84# range 0 .. 31; + PAGE17_LOCK0 at 16#3E88# range 0 .. 31; + PAGE17_LOCK1 at 16#3E8C# range 0 .. 31; + PAGE18_LOCK0 at 16#3E90# range 0 .. 31; + PAGE18_LOCK1 at 16#3E94# range 0 .. 31; + PAGE19_LOCK0 at 16#3E98# range 0 .. 31; + PAGE19_LOCK1 at 16#3E9C# range 0 .. 31; + PAGE20_LOCK0 at 16#3EA0# range 0 .. 31; + PAGE20_LOCK1 at 16#3EA4# range 0 .. 31; + PAGE21_LOCK0 at 16#3EA8# range 0 .. 31; + PAGE21_LOCK1 at 16#3EAC# range 0 .. 31; + PAGE22_LOCK0 at 16#3EB0# range 0 .. 31; + PAGE22_LOCK1 at 16#3EB4# range 0 .. 31; + PAGE23_LOCK0 at 16#3EB8# range 0 .. 31; + PAGE23_LOCK1 at 16#3EBC# range 0 .. 31; + PAGE24_LOCK0 at 16#3EC0# range 0 .. 31; + PAGE24_LOCK1 at 16#3EC4# range 0 .. 31; + PAGE25_LOCK0 at 16#3EC8# range 0 .. 31; + PAGE25_LOCK1 at 16#3ECC# range 0 .. 31; + PAGE26_LOCK0 at 16#3ED0# range 0 .. 31; + PAGE26_LOCK1 at 16#3ED4# range 0 .. 31; + PAGE27_LOCK0 at 16#3ED8# range 0 .. 31; + PAGE27_LOCK1 at 16#3EDC# range 0 .. 31; + PAGE28_LOCK0 at 16#3EE0# range 0 .. 31; + PAGE28_LOCK1 at 16#3EE4# range 0 .. 31; + PAGE29_LOCK0 at 16#3EE8# range 0 .. 31; + PAGE29_LOCK1 at 16#3EEC# range 0 .. 31; + PAGE30_LOCK0 at 16#3EF0# range 0 .. 31; + PAGE30_LOCK1 at 16#3EF4# range 0 .. 31; + PAGE31_LOCK0 at 16#3EF8# range 0 .. 31; + PAGE31_LOCK1 at 16#3EFC# range 0 .. 31; + PAGE32_LOCK0 at 16#3F00# range 0 .. 31; + PAGE32_LOCK1 at 16#3F04# range 0 .. 31; + PAGE33_LOCK0 at 16#3F08# range 0 .. 31; + PAGE33_LOCK1 at 16#3F0C# range 0 .. 31; + PAGE34_LOCK0 at 16#3F10# range 0 .. 31; + PAGE34_LOCK1 at 16#3F14# range 0 .. 31; + PAGE35_LOCK0 at 16#3F18# range 0 .. 31; + PAGE35_LOCK1 at 16#3F1C# range 0 .. 31; + PAGE36_LOCK0 at 16#3F20# range 0 .. 31; + PAGE36_LOCK1 at 16#3F24# range 0 .. 31; + PAGE37_LOCK0 at 16#3F28# range 0 .. 31; + PAGE37_LOCK1 at 16#3F2C# range 0 .. 31; + PAGE38_LOCK0 at 16#3F30# range 0 .. 31; + PAGE38_LOCK1 at 16#3F34# range 0 .. 31; + PAGE39_LOCK0 at 16#3F38# range 0 .. 31; + PAGE39_LOCK1 at 16#3F3C# range 0 .. 31; + PAGE40_LOCK0 at 16#3F40# range 0 .. 31; + PAGE40_LOCK1 at 16#3F44# range 0 .. 31; + PAGE41_LOCK0 at 16#3F48# range 0 .. 31; + PAGE41_LOCK1 at 16#3F4C# range 0 .. 31; + PAGE42_LOCK0 at 16#3F50# range 0 .. 31; + PAGE42_LOCK1 at 16#3F54# range 0 .. 31; + PAGE43_LOCK0 at 16#3F58# range 0 .. 31; + PAGE43_LOCK1 at 16#3F5C# range 0 .. 31; + PAGE44_LOCK0 at 16#3F60# range 0 .. 31; + PAGE44_LOCK1 at 16#3F64# range 0 .. 31; + PAGE45_LOCK0 at 16#3F68# range 0 .. 31; + PAGE45_LOCK1 at 16#3F6C# range 0 .. 31; + PAGE46_LOCK0 at 16#3F70# range 0 .. 31; + PAGE46_LOCK1 at 16#3F74# range 0 .. 31; + PAGE47_LOCK0 at 16#3F78# range 0 .. 31; + PAGE47_LOCK1 at 16#3F7C# range 0 .. 31; + PAGE48_LOCK0 at 16#3F80# range 0 .. 31; + PAGE48_LOCK1 at 16#3F84# range 0 .. 31; + PAGE49_LOCK0 at 16#3F88# range 0 .. 31; + PAGE49_LOCK1 at 16#3F8C# range 0 .. 31; + PAGE50_LOCK0 at 16#3F90# range 0 .. 31; + PAGE50_LOCK1 at 16#3F94# range 0 .. 31; + PAGE51_LOCK0 at 16#3F98# range 0 .. 31; + PAGE51_LOCK1 at 16#3F9C# range 0 .. 31; + PAGE52_LOCK0 at 16#3FA0# range 0 .. 31; + PAGE52_LOCK1 at 16#3FA4# range 0 .. 31; + PAGE53_LOCK0 at 16#3FA8# range 0 .. 31; + PAGE53_LOCK1 at 16#3FAC# range 0 .. 31; + PAGE54_LOCK0 at 16#3FB0# range 0 .. 31; + PAGE54_LOCK1 at 16#3FB4# range 0 .. 31; + PAGE55_LOCK0 at 16#3FB8# range 0 .. 31; + PAGE55_LOCK1 at 16#3FBC# range 0 .. 31; + PAGE56_LOCK0 at 16#3FC0# range 0 .. 31; + PAGE56_LOCK1 at 16#3FC4# range 0 .. 31; + PAGE57_LOCK0 at 16#3FC8# range 0 .. 31; + PAGE57_LOCK1 at 16#3FCC# range 0 .. 31; + PAGE58_LOCK0 at 16#3FD0# range 0 .. 31; + PAGE58_LOCK1 at 16#3FD4# range 0 .. 31; + PAGE59_LOCK0 at 16#3FD8# range 0 .. 31; + PAGE59_LOCK1 at 16#3FDC# range 0 .. 31; + PAGE60_LOCK0 at 16#3FE0# range 0 .. 31; + PAGE60_LOCK1 at 16#3FE4# range 0 .. 31; + PAGE61_LOCK0 at 16#3FE8# range 0 .. 31; + PAGE61_LOCK1 at 16#3FEC# range 0 .. 31; + PAGE62_LOCK0 at 16#3FF0# range 0 .. 31; + PAGE62_LOCK1 at 16#3FF4# range 0 .. 31; + PAGE63_LOCK0 at 16#3FF8# range 0 .. 31; + PAGE63_LOCK1 at 16#3FFC# range 0 .. 31; + end record; + + -- Predefined OTP data layout for RP2350 + OTP_DATA_RAW_Periph : aliased OTP_DATA_RAW_Peripheral + with Import, Address => OTP_DATA_RAW_Base; + +end RP2350_SVD.OTP_DATA_RAW; diff --git a/src/svd/rp2350_svd-pads_bank0.ads b/src/svd/rp2350_svd-pads_bank0.ads new file mode 100644 index 0000000..30b2f39 --- /dev/null +++ b/src/svd/rp2350_svd-pads_bank0.ads @@ -0,0 +1,308 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.PADS_BANK0 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type VOLTAGE_SELECT_VOLTAGE_SELECT_Field is + (-- Set voltage to 3.3V (DVDD >= 2V5) + Val_3v3, + -- Set voltage to 1.8V (DVDD <= 1V8) + Val_1v8) + with Size => 1; + for VOLTAGE_SELECT_VOLTAGE_SELECT_Field use + (Val_3v3 => 0, + Val_1v8 => 1); + + -- Voltage select. Per bank control + type VOLTAGE_SELECT_Register is record + VOLTAGE_SELECT : VOLTAGE_SELECT_VOLTAGE_SELECT_Field := + RP2350_SVD.PADS_BANK0.Val_3v3; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VOLTAGE_SELECT_Register use record + VOLTAGE_SELECT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Drive strength. + type GPIO0_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for GPIO0_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type GPIO_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := True; + -- Pull up enable + PUE : Boolean := False; + -- Drive strength. + DRIVE : GPIO0_DRIVE_Field := RP2350_SVD.PADS_BANK0.Val_4mA; + -- Input enable + IE : Boolean := False; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := True; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Drive strength. + type SWCLK_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for SWCLK_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type SWCLK_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := False; + -- Pull up enable + PUE : Boolean := True; + -- Drive strength. + DRIVE : SWCLK_DRIVE_Field := RP2350_SVD.PADS_BANK0.Val_4mA; + -- Input enable + IE : Boolean := True; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SWCLK_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Drive strength. + type SWD_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for SWD_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type SWD_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := False; + -- Pull up enable + PUE : Boolean := True; + -- Drive strength. + DRIVE : SWD_DRIVE_Field := RP2350_SVD.PADS_BANK0.Val_4mA; + -- Input enable + IE : Boolean := True; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SWD_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type PADS_BANK0_Peripheral is record + -- Voltage select. Per bank control + VOLTAGE_SELECT : aliased VOLTAGE_SELECT_Register; + GPIO0 : aliased GPIO_Register; + GPIO1 : aliased GPIO_Register; + GPIO2 : aliased GPIO_Register; + GPIO3 : aliased GPIO_Register; + GPIO4 : aliased GPIO_Register; + GPIO5 : aliased GPIO_Register; + GPIO6 : aliased GPIO_Register; + GPIO7 : aliased GPIO_Register; + GPIO8 : aliased GPIO_Register; + GPIO9 : aliased GPIO_Register; + GPIO10 : aliased GPIO_Register; + GPIO11 : aliased GPIO_Register; + GPIO12 : aliased GPIO_Register; + GPIO13 : aliased GPIO_Register; + GPIO14 : aliased GPIO_Register; + GPIO15 : aliased GPIO_Register; + GPIO16 : aliased GPIO_Register; + GPIO17 : aliased GPIO_Register; + GPIO18 : aliased GPIO_Register; + GPIO19 : aliased GPIO_Register; + GPIO20 : aliased GPIO_Register; + GPIO21 : aliased GPIO_Register; + GPIO22 : aliased GPIO_Register; + GPIO23 : aliased GPIO_Register; + GPIO24 : aliased GPIO_Register; + GPIO25 : aliased GPIO_Register; + GPIO26 : aliased GPIO_Register; + GPIO27 : aliased GPIO_Register; + GPIO28 : aliased GPIO_Register; + GPIO29 : aliased GPIO_Register; + GPIO30 : aliased GPIO_Register; + GPIO31 : aliased GPIO_Register; + GPIO32 : aliased GPIO_Register; + GPIO33 : aliased GPIO_Register; + GPIO34 : aliased GPIO_Register; + GPIO35 : aliased GPIO_Register; + GPIO36 : aliased GPIO_Register; + GPIO37 : aliased GPIO_Register; + GPIO38 : aliased GPIO_Register; + GPIO39 : aliased GPIO_Register; + GPIO40 : aliased GPIO_Register; + GPIO41 : aliased GPIO_Register; + GPIO42 : aliased GPIO_Register; + GPIO43 : aliased GPIO_Register; + GPIO44 : aliased GPIO_Register; + GPIO45 : aliased GPIO_Register; + GPIO46 : aliased GPIO_Register; + GPIO47 : aliased GPIO_Register; + SWCLK : aliased SWCLK_Register; + SWD : aliased SWD_Register; + end record + with Volatile; + + for PADS_BANK0_Peripheral use record + VOLTAGE_SELECT at 16#0# range 0 .. 31; + GPIO0 at 16#4# range 0 .. 31; + GPIO1 at 16#8# range 0 .. 31; + GPIO2 at 16#C# range 0 .. 31; + GPIO3 at 16#10# range 0 .. 31; + GPIO4 at 16#14# range 0 .. 31; + GPIO5 at 16#18# range 0 .. 31; + GPIO6 at 16#1C# range 0 .. 31; + GPIO7 at 16#20# range 0 .. 31; + GPIO8 at 16#24# range 0 .. 31; + GPIO9 at 16#28# range 0 .. 31; + GPIO10 at 16#2C# range 0 .. 31; + GPIO11 at 16#30# range 0 .. 31; + GPIO12 at 16#34# range 0 .. 31; + GPIO13 at 16#38# range 0 .. 31; + GPIO14 at 16#3C# range 0 .. 31; + GPIO15 at 16#40# range 0 .. 31; + GPIO16 at 16#44# range 0 .. 31; + GPIO17 at 16#48# range 0 .. 31; + GPIO18 at 16#4C# range 0 .. 31; + GPIO19 at 16#50# range 0 .. 31; + GPIO20 at 16#54# range 0 .. 31; + GPIO21 at 16#58# range 0 .. 31; + GPIO22 at 16#5C# range 0 .. 31; + GPIO23 at 16#60# range 0 .. 31; + GPIO24 at 16#64# range 0 .. 31; + GPIO25 at 16#68# range 0 .. 31; + GPIO26 at 16#6C# range 0 .. 31; + GPIO27 at 16#70# range 0 .. 31; + GPIO28 at 16#74# range 0 .. 31; + GPIO29 at 16#78# range 0 .. 31; + GPIO30 at 16#7C# range 0 .. 31; + GPIO31 at 16#80# range 0 .. 31; + GPIO32 at 16#84# range 0 .. 31; + GPIO33 at 16#88# range 0 .. 31; + GPIO34 at 16#8C# range 0 .. 31; + GPIO35 at 16#90# range 0 .. 31; + GPIO36 at 16#94# range 0 .. 31; + GPIO37 at 16#98# range 0 .. 31; + GPIO38 at 16#9C# range 0 .. 31; + GPIO39 at 16#A0# range 0 .. 31; + GPIO40 at 16#A4# range 0 .. 31; + GPIO41 at 16#A8# range 0 .. 31; + GPIO42 at 16#AC# range 0 .. 31; + GPIO43 at 16#B0# range 0 .. 31; + GPIO44 at 16#B4# range 0 .. 31; + GPIO45 at 16#B8# range 0 .. 31; + GPIO46 at 16#BC# range 0 .. 31; + GPIO47 at 16#C0# range 0 .. 31; + SWCLK at 16#C4# range 0 .. 31; + SWD at 16#C8# range 0 .. 31; + end record; + + PADS_BANK0_Periph : aliased PADS_BANK0_Peripheral + with Import, Address => PADS_BANK0_Base; + +end RP2350_SVD.PADS_BANK0; diff --git a/src/svd/rp2350_svd-pads_qspi.ads b/src/svd/rp2350_svd-pads_qspi.ads new file mode 100644 index 0000000..c081a9d --- /dev/null +++ b/src/svd/rp2350_svd-pads_qspi.ads @@ -0,0 +1,223 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.PADS_QSPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type VOLTAGE_SELECT_VOLTAGE_SELECT_Field is + (-- Set voltage to 3.3V (DVDD >= 2V5) + Val_3v3, + -- Set voltage to 1.8V (DVDD <= 1V8) + Val_1v8) + with Size => 1; + for VOLTAGE_SELECT_VOLTAGE_SELECT_Field use + (Val_3v3 => 0, + Val_1v8 => 1); + + -- Voltage select. Per bank control + type VOLTAGE_SELECT_Register is record + VOLTAGE_SELECT : VOLTAGE_SELECT_VOLTAGE_SELECT_Field := + RP2350_SVD.PADS_QSPI.Val_3v3; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VOLTAGE_SELECT_Register use record + VOLTAGE_SELECT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Drive strength. + type GPIO_QSPI_SCLK_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for GPIO_QSPI_SCLK_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type GPIO_QSPI_SCLK_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := True; + -- Pull up enable + PUE : Boolean := False; + -- Drive strength. + DRIVE : GPIO_QSPI_SCLK_DRIVE_Field := + RP2350_SVD.PADS_QSPI.Val_4mA; + -- Input enable + IE : Boolean := True; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := True; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SCLK_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Drive strength. + type GPIO_QSPI_SD0_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for GPIO_QSPI_SD0_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type GPIO_QSPI_SD_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := True; + -- Pull up enable + PUE : Boolean := False; + -- Drive strength. + DRIVE : GPIO_QSPI_SD0_DRIVE_Field := + RP2350_SVD.PADS_QSPI.Val_4mA; + -- Input enable + IE : Boolean := True; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := True; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SD_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Drive strength. + type GPIO_QSPI_SS_DRIVE_Field is + (Val_2mA, + Val_4mA, + Val_8mA, + Val_12mA) + with Size => 2; + for GPIO_QSPI_SS_DRIVE_Field use + (Val_2mA => 0, + Val_4mA => 1, + Val_8mA => 2, + Val_12mA => 3); + + type GPIO_QSPI_SS_Register is record + -- Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST : Boolean := False; + -- Enable schmitt trigger + SCHMITT : Boolean := True; + -- Pull down enable + PDE : Boolean := False; + -- Pull up enable + PUE : Boolean := True; + -- Drive strength. + DRIVE : GPIO_QSPI_SS_DRIVE_Field := + RP2350_SVD.PADS_QSPI.Val_4mA; + -- Input enable + IE : Boolean := True; + -- Output disable. Has priority over output enable from peripherals + OD : Boolean := False; + -- Pad isolation control. Remove this once the pad is configured by + -- software. + ISO : Boolean := True; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_QSPI_SS_Register use record + SLEWFAST at 0 range 0 .. 0; + SCHMITT at 0 range 1 .. 1; + PDE at 0 range 2 .. 2; + PUE at 0 range 3 .. 3; + DRIVE at 0 range 4 .. 5; + IE at 0 range 6 .. 6; + OD at 0 range 7 .. 7; + ISO at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type PADS_QSPI_Peripheral is record + -- Voltage select. Per bank control + VOLTAGE_SELECT : aliased VOLTAGE_SELECT_Register; + GPIO_QSPI_SCLK : aliased GPIO_QSPI_SCLK_Register; + GPIO_QSPI_SD0 : aliased GPIO_QSPI_SD_Register; + GPIO_QSPI_SD1 : aliased GPIO_QSPI_SD_Register; + GPIO_QSPI_SD2 : aliased GPIO_QSPI_SD_Register; + GPIO_QSPI_SD3 : aliased GPIO_QSPI_SD_Register; + GPIO_QSPI_SS : aliased GPIO_QSPI_SS_Register; + end record + with Volatile; + + for PADS_QSPI_Peripheral use record + VOLTAGE_SELECT at 16#0# range 0 .. 31; + GPIO_QSPI_SCLK at 16#4# range 0 .. 31; + GPIO_QSPI_SD0 at 16#8# range 0 .. 31; + GPIO_QSPI_SD1 at 16#C# range 0 .. 31; + GPIO_QSPI_SD2 at 16#10# range 0 .. 31; + GPIO_QSPI_SD3 at 16#14# range 0 .. 31; + GPIO_QSPI_SS at 16#18# range 0 .. 31; + end record; + + PADS_QSPI_Periph : aliased PADS_QSPI_Peripheral + with Import, Address => PADS_QSPI_Base; + +end RP2350_SVD.PADS_QSPI; diff --git a/src/svd/rp2350_svd-pio0.ads b/src/svd/rp2350_svd-pio0.ads new file mode 100644 index 0000000..7527d47 --- /dev/null +++ b/src/svd/rp2350_svd-pio0.ads @@ -0,0 +1,2880 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Programmable IO block +package RP2350_SVD.PIO0 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CTRL_SM_ENABLE_Field is HAL.UInt4; + subtype CTRL_SM_RESTART_Field is HAL.UInt4; + subtype CTRL_CLKDIV_RESTART_Field is HAL.UInt4; + subtype CTRL_PREV_PIO_MASK_Field is HAL.UInt4; + subtype CTRL_NEXT_PIO_MASK_Field is HAL.UInt4; + + -- PIO control register + type CTRL_Register is record + -- Enable/disable each of the four state machines by writing 1/0 to each + -- of these four bits. When disabled, a state machine will cease + -- executing instructions, except those written directly to SMx_INSTR by + -- the system. Multiple bits can be set/cleared at once to run/halt + -- multiple state machines simultaneously. + SM_ENABLE : CTRL_SM_ENABLE_Field := 16#0#; + -- Write-only. Write 1 to instantly clear internal SM state which may be + -- otherwise difficult to access and will affect future execution. + -- Specifically, the following are cleared: input and output shift + -- counters; the contents of the input shift register; the delay + -- counter; the waiting-on-IRQ state; any stalled instruction written to + -- SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to + -- OUT_STICKY. The contents of the output shift register and the X/Y + -- scratch registers are not affected. + SM_RESTART : CTRL_SM_RESTART_Field := 16#0#; + -- Write-only. Restart a state machine's clock divider from an initial + -- phase of 0. Clock dividers are free-running, so once started, their + -- output (including fractional jitter) is completely determined by the + -- integer/fractional divisor configured in SMx_CLKDIV. This means that, + -- if multiple clock dividers with the same divisor are restarted + -- simultaneously, by writing multiple 1 bits to this field, the + -- execution clocks of those state machines will run in precise + -- lockstep. Note that setting/clearing SM_ENABLE does not stop the + -- clock divider from running, so once multiple state machines' clocks + -- are synchronised, it is safe to disable/reenable a state machine, + -- whilst keeping the clock dividers in sync. Note also that + -- CLKDIV_RESTART can be written to whilst the state machine is running, + -- and this is useful to resynchronise clock dividers after the divisors + -- (SMx_CLKDIV) have been changed on-the-fly. + CLKDIV_RESTART : CTRL_CLKDIV_RESTART_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- lower-numbered PIO block in the system (or the highest-numbered PIO + -- block if this is PIO block 0) to which to apply the operations + -- specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same + -- write. This allows state machines in a neighbouring PIO block to be + -- started/stopped/clock-synced exactly simultaneously with a write to + -- this PIO block's CTRL register. Neighbouring PIO blocks are + -- disconnected (status signals tied to 0 and control signals ignored) + -- if one block is accessible to NonSecure code, and one is not. + PREV_PIO_MASK : CTRL_PREV_PIO_MASK_Field := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- higher-numbered PIO block in the system (or PIO block 0 if this is + -- the highest-numbered PIO block) to which to apply the operations + -- specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and + -- NEXTPREV_SM_DISABLE in the same write. This allows state machines in + -- a neighbouring PIO block to be started/stopped/clock-synced exactly + -- simultaneously with a write to this PIO block's CTRL register. Note + -- that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK + -- actually indicate the same PIO block. In this case the effects are + -- applied cumulatively (as though the masks were OR'd together). + -- Neighbouring PIO blocks are disconnected (status signals tied to 0 + -- and control signals ignored) if one block is accessible to NonSecure + -- code, and one is not. + NEXT_PIO_MASK : CTRL_NEXT_PIO_MASK_Field := 16#0#; + -- Write-only. Write 1 to enable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to setting the corresponding SM_ENABLE bits + -- in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and + -- OTHERS_SM_DISABLE are set, the disable takes precedence. + NEXTPREV_SM_ENABLE : Boolean := False; + -- Write-only. Write 1 to disable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to clearing the corresponding SM_ENABLE + -- bits in those PIOs' CTRL registers. + NEXTPREV_SM_DISABLE : Boolean := False; + -- Write-only. Write 1 to restart the clock dividers of state machines + -- in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and + -- PREV_PIO_MASK in the same write. This is equivalent to writing 1 to + -- the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + NEXTPREV_CLKDIV_RESTART : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + SM_ENABLE at 0 range 0 .. 3; + SM_RESTART at 0 range 4 .. 7; + CLKDIV_RESTART at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PREV_PIO_MASK at 0 range 16 .. 19; + NEXT_PIO_MASK at 0 range 20 .. 23; + NEXTPREV_SM_ENABLE at 0 range 24 .. 24; + NEXTPREV_SM_DISABLE at 0 range 25 .. 25; + NEXTPREV_CLKDIV_RESTART at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype FSTAT_RXFULL_Field is HAL.UInt4; + subtype FSTAT_RXEMPTY_Field is HAL.UInt4; + subtype FSTAT_TXFULL_Field is HAL.UInt4; + subtype FSTAT_TXEMPTY_Field is HAL.UInt4; + + -- FIFO status register + type FSTAT_Register is record + -- Read-only. State machine RX FIFO is full + RXFULL : FSTAT_RXFULL_Field; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. State machine RX FIFO is empty + RXEMPTY : FSTAT_RXEMPTY_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. State machine TX FIFO is full + TXFULL : FSTAT_TXFULL_Field; + -- unspecified + Reserved_20_23 : HAL.UInt4; + -- Read-only. State machine TX FIFO is empty + TXEMPTY : FSTAT_TXEMPTY_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FSTAT_Register use record + RXFULL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXEMPTY at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXFULL at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXEMPTY at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FDEBUG_RXSTALL_Field is HAL.UInt4; + subtype FDEBUG_RXUNDER_Field is HAL.UInt4; + subtype FDEBUG_TXOVER_Field is HAL.UInt4; + subtype FDEBUG_TXSTALL_Field is HAL.UInt4; + + -- FIFO debug register + type FDEBUG_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on full RX FIFO during a + -- blocking PUSH, or an IN with autopush enabled. This flag is also set + -- when a nonblocking PUSH to a full FIFO took place, in which case the + -- state machine has dropped data. Write 1 to clear. + RXSTALL : FDEBUG_RXSTALL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. RX FIFO underflow (i.e. read-on-empty by the system) + -- has occurred. Write 1 to clear. Note that read-on-empty does not + -- perturb the state of the FIFO in any way, but the data returned by + -- reading from an empty FIFO is undefined, so this flag generally only + -- becomes set due to some kind of software error. + RXUNDER : FDEBUG_RXUNDER_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. TX FIFO overflow (i.e. write-on-full by the system) has + -- occurred. Write 1 to clear. Note that write-on-full does not alter + -- the state or contents of the FIFO in any way, but the data that the + -- system attempted to write is dropped, so if this flag is set, your + -- software has quite likely dropped some data on the floor. + TXOVER : FDEBUG_TXOVER_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on empty TX FIFO during a + -- blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + TXSTALL : FDEBUG_TXSTALL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FDEBUG_Register use record + RXSTALL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXUNDER at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXOVER at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXSTALL at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FLEVEL_TX0_Field is HAL.UInt4; + subtype FLEVEL_RX0_Field is HAL.UInt4; + subtype FLEVEL_TX1_Field is HAL.UInt4; + subtype FLEVEL_RX1_Field is HAL.UInt4; + subtype FLEVEL_TX2_Field is HAL.UInt4; + subtype FLEVEL_RX2_Field is HAL.UInt4; + subtype FLEVEL_TX3_Field is HAL.UInt4; + subtype FLEVEL_RX3_Field is HAL.UInt4; + + -- FIFO levels + type FLEVEL_Register is record + -- Read-only. + TX0 : FLEVEL_TX0_Field; + -- Read-only. + RX0 : FLEVEL_RX0_Field; + -- Read-only. + TX1 : FLEVEL_TX1_Field; + -- Read-only. + RX1 : FLEVEL_RX1_Field; + -- Read-only. + TX2 : FLEVEL_TX2_Field; + -- Read-only. + RX2 : FLEVEL_RX2_Field; + -- Read-only. + TX3 : FLEVEL_TX3_Field; + -- Read-only. + RX3 : FLEVEL_RX3_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FLEVEL_Register use record + TX0 at 0 range 0 .. 3; + RX0 at 0 range 4 .. 7; + TX1 at 0 range 8 .. 11; + RX1 at 0 range 12 .. 15; + TX2 at 0 range 16 .. 19; + RX2 at 0 range 20 .. 23; + TX3 at 0 range 24 .. 27; + RX3 at 0 range 28 .. 31; + end record; + + subtype IRQ_IRQ_Field is HAL.UInt8; + + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by the + -- state machines. There's no fixed association between flags and state + -- machines -- any state machine can use any flag. Any of the eight flags + -- can be used for timing synchronisation between state machines, using IRQ + -- and WAIT instructions. Any combination of the eight flags can also + -- routed out to either of the two system-level interrupt requests, + -- alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + type IRQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + IRQ : IRQ_IRQ_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_Register use record + IRQ at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype IRQ_FORCE_IRQ_FORCE_Field is HAL.UInt8; + + -- Writing a 1 to each of these bits will forcibly assert the corresponding + -- IRQ. Note this is different to the INTF register: writing here affects + -- PIO internal state. INTF just asserts the processor-facing IRQ signal + -- for testing ISRs, and is not visible to the state machines. + type IRQ_FORCE_Register is record + -- Write-only. + IRQ_FORCE : IRQ_FORCE_IRQ_FORCE_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_FORCE_Register use record + IRQ_FORCE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DBG_CFGINFO_FIFO_DEPTH_Field is HAL.UInt6; + subtype DBG_CFGINFO_SM_COUNT_Field is HAL.UInt4; + subtype DBG_CFGINFO_IMEM_SIZE_Field is HAL.UInt6; + + -- Version of the core PIO hardware. + type DBG_CFGINFO_VERSION_Field is + (-- Version 0 (RP2040) + v0, + -- Version 1 (RP2350) + v1) + with Size => 4; + for DBG_CFGINFO_VERSION_Field use + (v0 => 0, + v1 => 1); + + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are also + -- exposed here. + type DBG_CFGINFO_Register is record + -- Read-only. The depth of the state machine TX/RX FIFOs, measured in + -- words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + -- this depth. + FIFO_DEPTH : DBG_CFGINFO_FIFO_DEPTH_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. The number of state machines this PIO instance is equipped + -- with. + SM_COUNT : DBG_CFGINFO_SM_COUNT_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. The size of the instruction memory, measured in units of + -- one instruction + IMEM_SIZE : DBG_CFGINFO_IMEM_SIZE_Field; + -- unspecified + Reserved_22_27 : HAL.UInt6; + -- Read-only. Version of the core PIO hardware. + VERSION : DBG_CFGINFO_VERSION_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBG_CFGINFO_Register use record + FIFO_DEPTH at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SM_COUNT at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + IMEM_SIZE at 0 range 16 .. 21; + Reserved_22_27 at 0 range 22 .. 27; + VERSION at 0 range 28 .. 31; + end record; + + subtype INSTR_MEM0_INSTR_MEM0_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 0 + type INSTR_MEM0_Register is record + -- Write-only. + INSTR_MEM0 : INSTR_MEM0_INSTR_MEM0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM0_Register use record + INSTR_MEM0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM1_INSTR_MEM1_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 1 + type INSTR_MEM1_Register is record + -- Write-only. + INSTR_MEM1 : INSTR_MEM1_INSTR_MEM1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM1_Register use record + INSTR_MEM1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM2_INSTR_MEM2_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 2 + type INSTR_MEM2_Register is record + -- Write-only. + INSTR_MEM2 : INSTR_MEM2_INSTR_MEM2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM2_Register use record + INSTR_MEM2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM3_INSTR_MEM3_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 3 + type INSTR_MEM3_Register is record + -- Write-only. + INSTR_MEM3 : INSTR_MEM3_INSTR_MEM3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM3_Register use record + INSTR_MEM3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM4_INSTR_MEM4_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 4 + type INSTR_MEM4_Register is record + -- Write-only. + INSTR_MEM4 : INSTR_MEM4_INSTR_MEM4_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM4_Register use record + INSTR_MEM4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM5_INSTR_MEM5_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 5 + type INSTR_MEM5_Register is record + -- Write-only. + INSTR_MEM5 : INSTR_MEM5_INSTR_MEM5_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM5_Register use record + INSTR_MEM5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM6_INSTR_MEM6_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 6 + type INSTR_MEM6_Register is record + -- Write-only. + INSTR_MEM6 : INSTR_MEM6_INSTR_MEM6_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM6_Register use record + INSTR_MEM6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM7_INSTR_MEM7_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 7 + type INSTR_MEM7_Register is record + -- Write-only. + INSTR_MEM7 : INSTR_MEM7_INSTR_MEM7_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM7_Register use record + INSTR_MEM7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM8_INSTR_MEM8_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 8 + type INSTR_MEM8_Register is record + -- Write-only. + INSTR_MEM8 : INSTR_MEM8_INSTR_MEM8_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM8_Register use record + INSTR_MEM8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM9_INSTR_MEM9_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 9 + type INSTR_MEM9_Register is record + -- Write-only. + INSTR_MEM9 : INSTR_MEM9_INSTR_MEM9_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM9_Register use record + INSTR_MEM9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM10_INSTR_MEM10_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 10 + type INSTR_MEM10_Register is record + -- Write-only. + INSTR_MEM10 : INSTR_MEM10_INSTR_MEM10_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM10_Register use record + INSTR_MEM10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM11_INSTR_MEM11_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 11 + type INSTR_MEM11_Register is record + -- Write-only. + INSTR_MEM11 : INSTR_MEM11_INSTR_MEM11_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM11_Register use record + INSTR_MEM11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM12_INSTR_MEM12_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 12 + type INSTR_MEM12_Register is record + -- Write-only. + INSTR_MEM12 : INSTR_MEM12_INSTR_MEM12_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM12_Register use record + INSTR_MEM12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM13_INSTR_MEM13_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 13 + type INSTR_MEM13_Register is record + -- Write-only. + INSTR_MEM13 : INSTR_MEM13_INSTR_MEM13_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM13_Register use record + INSTR_MEM13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM14_INSTR_MEM14_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 14 + type INSTR_MEM14_Register is record + -- Write-only. + INSTR_MEM14 : INSTR_MEM14_INSTR_MEM14_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM14_Register use record + INSTR_MEM14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM15_INSTR_MEM15_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 15 + type INSTR_MEM15_Register is record + -- Write-only. + INSTR_MEM15 : INSTR_MEM15_INSTR_MEM15_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM15_Register use record + INSTR_MEM15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM16_INSTR_MEM16_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 16 + type INSTR_MEM16_Register is record + -- Write-only. + INSTR_MEM16 : INSTR_MEM16_INSTR_MEM16_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM16_Register use record + INSTR_MEM16 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM17_INSTR_MEM17_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 17 + type INSTR_MEM17_Register is record + -- Write-only. + INSTR_MEM17 : INSTR_MEM17_INSTR_MEM17_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM17_Register use record + INSTR_MEM17 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM18_INSTR_MEM18_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 18 + type INSTR_MEM18_Register is record + -- Write-only. + INSTR_MEM18 : INSTR_MEM18_INSTR_MEM18_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM18_Register use record + INSTR_MEM18 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM19_INSTR_MEM19_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 19 + type INSTR_MEM19_Register is record + -- Write-only. + INSTR_MEM19 : INSTR_MEM19_INSTR_MEM19_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM19_Register use record + INSTR_MEM19 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM20_INSTR_MEM20_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 20 + type INSTR_MEM20_Register is record + -- Write-only. + INSTR_MEM20 : INSTR_MEM20_INSTR_MEM20_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM20_Register use record + INSTR_MEM20 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM21_INSTR_MEM21_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 21 + type INSTR_MEM21_Register is record + -- Write-only. + INSTR_MEM21 : INSTR_MEM21_INSTR_MEM21_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM21_Register use record + INSTR_MEM21 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM22_INSTR_MEM22_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 22 + type INSTR_MEM22_Register is record + -- Write-only. + INSTR_MEM22 : INSTR_MEM22_INSTR_MEM22_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM22_Register use record + INSTR_MEM22 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM23_INSTR_MEM23_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 23 + type INSTR_MEM23_Register is record + -- Write-only. + INSTR_MEM23 : INSTR_MEM23_INSTR_MEM23_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM23_Register use record + INSTR_MEM23 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM24_INSTR_MEM24_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 24 + type INSTR_MEM24_Register is record + -- Write-only. + INSTR_MEM24 : INSTR_MEM24_INSTR_MEM24_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM24_Register use record + INSTR_MEM24 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM25_INSTR_MEM25_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 25 + type INSTR_MEM25_Register is record + -- Write-only. + INSTR_MEM25 : INSTR_MEM25_INSTR_MEM25_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM25_Register use record + INSTR_MEM25 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM26_INSTR_MEM26_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 26 + type INSTR_MEM26_Register is record + -- Write-only. + INSTR_MEM26 : INSTR_MEM26_INSTR_MEM26_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM26_Register use record + INSTR_MEM26 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM27_INSTR_MEM27_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 27 + type INSTR_MEM27_Register is record + -- Write-only. + INSTR_MEM27 : INSTR_MEM27_INSTR_MEM27_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM27_Register use record + INSTR_MEM27 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM28_INSTR_MEM28_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 28 + type INSTR_MEM28_Register is record + -- Write-only. + INSTR_MEM28 : INSTR_MEM28_INSTR_MEM28_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM28_Register use record + INSTR_MEM28 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM29_INSTR_MEM29_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 29 + type INSTR_MEM29_Register is record + -- Write-only. + INSTR_MEM29 : INSTR_MEM29_INSTR_MEM29_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM29_Register use record + INSTR_MEM29 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM30_INSTR_MEM30_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 30 + type INSTR_MEM30_Register is record + -- Write-only. + INSTR_MEM30 : INSTR_MEM30_INSTR_MEM30_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM30_Register use record + INSTR_MEM30 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM31_INSTR_MEM31_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 31 + type INSTR_MEM31_Register is record + -- Write-only. + INSTR_MEM31 : INSTR_MEM31_INSTR_MEM31_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM31_Register use record + INSTR_MEM31 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM0_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM0_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM0_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM0_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM0_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM0_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM0_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM0_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM0_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM0_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM0_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM0_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 0 + type SM0_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM0_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO0.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM0_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO0.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM0_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM0_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM0_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM0_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM0_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 0 + type SM0_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM0_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM0_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM0_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM0_ADDR_SM0_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 0 + type SM0_ADDR_Register is record + -- Read-only. + SM0_ADDR : SM0_ADDR_SM0_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_ADDR_Register use record + SM0_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM0_INSTR_SM0_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM0_INSTR_Register is record + SM0_INSTR : SM0_INSTR_SM0_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_INSTR_Register use record + SM0_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM0_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM0_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM0_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM0_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM0_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM0_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM0_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM0_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM0_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM0_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM1_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM1_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM1_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM1_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM1_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM1_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM1_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM1_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM1_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM1_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM1_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM1_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM1_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 1 + type SM1_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM1_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO0.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM1_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO0.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM1_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM1_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM1_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM1_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM1_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 1 + type SM1_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM1_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM1_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM1_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM1_ADDR_SM1_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 1 + type SM1_ADDR_Register is record + -- Read-only. + SM1_ADDR : SM1_ADDR_SM1_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_ADDR_Register use record + SM1_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM1_INSTR_SM1_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM1_INSTR_Register is record + SM1_INSTR : SM1_INSTR_SM1_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_INSTR_Register use record + SM1_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM1_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM1_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM1_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM1_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM1_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM1_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM1_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM1_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM1_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM1_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM1_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM2_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM2_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM2_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM2_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM2_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM2_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM2_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM2_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM2_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM2_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM2_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM2_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM2_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 2 + type SM2_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM2_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO0.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM2_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO0.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM2_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM2_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM2_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM2_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM2_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 2 + type SM2_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM2_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM2_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM2_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM2_ADDR_SM2_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 2 + type SM2_ADDR_Register is record + -- Read-only. + SM2_ADDR : SM2_ADDR_SM2_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_ADDR_Register use record + SM2_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM2_INSTR_SM2_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM2_INSTR_Register is record + SM2_INSTR : SM2_INSTR_SM2_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_INSTR_Register use record + SM2_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM2_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM2_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM2_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM2_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM2_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM2_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM2_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM2_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM2_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM2_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM2_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM3_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM3_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM3_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM3_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM3_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM3_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM3_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM3_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM3_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM3_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM3_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM3_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM3_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 3 + type SM3_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM3_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO0.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM3_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO0.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM3_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM3_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM3_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM3_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM3_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 3 + type SM3_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM3_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM3_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM3_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM3_ADDR_SM3_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 3 + type SM3_ADDR_Register is record + -- Read-only. + SM3_ADDR : SM3_ADDR_SM3_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_ADDR_Register use record + SM3_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM3_INSTR_SM3_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM3_INSTR_Register is record + SM3_INSTR : SM3_INSTR_SM3_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_INSTR_Register use record + SM3_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM3_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM3_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM3_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM3_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM3_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM3_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM3_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM3_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM3_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM3_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM3_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, + -- to access more than 32 GPIOs from PIO. Only the values 0 and 16 are + -- supported (only bit 4 is writable). + type GPIOBASE_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + GPIOBASE : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIOBASE_Register use record + Reserved_0_3 at 0 range 0 .. 3; + GPIOBASE at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- INTR_SM array + type INTR_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for INTR_SM + type INTR_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : INTR_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for INTR_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : INTR_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTE_SM array + type IRQ0_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTE_SM + type IRQ0_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq0 + type IRQ0_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTF_SM array + type IRQ0_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTF_SM + type IRQ0_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq0 + type IRQ0_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTS_SM array + type IRQ0_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTS_SM + type IRQ0_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq0 + type IRQ0_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ0_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTE_SM array + type IRQ1_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTE_SM + type IRQ1_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq1 + type IRQ1_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTF_SM array + type IRQ1_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTF_SM + type IRQ1_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq1 + type IRQ1_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTS_SM array + type IRQ1_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTS_SM + type IRQ1_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq1 + type IRQ1_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ1_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Programmable IO block + type PIO0_Peripheral is record + -- PIO control register + CTRL : aliased CTRL_Register; + -- FIFO status register + FSTAT : aliased FSTAT_Register; + -- FIFO debug register + FDEBUG : aliased FDEBUG_Register; + -- FIFO levels + FLEVEL : aliased FLEVEL_Register; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF0 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF1 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF2 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF3 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF0 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF1 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF2 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF3 : aliased HAL.UInt32; + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by + -- the state machines. There's no fixed association between flags and + -- state machines -- any state machine can use any flag. Any of the + -- eight flags can be used for timing synchronisation between state + -- machines, using IRQ and WAIT instructions. Any combination of the + -- eight flags can also routed out to either of the two system-level + -- interrupt requests, alongside FIFO status interrupts -- see e.g. + -- IRQ0_INTE. + IRQ : aliased IRQ_Register; + -- Writing a 1 to each of these bits will forcibly assert the + -- corresponding IRQ. Note this is different to the INTF register: + -- writing here affects PIO internal state. INTF just asserts the + -- processor-facing IRQ signal for testing ISRs, and is not visible to + -- the state machines. + IRQ_FORCE : aliased IRQ_FORCE_Register; + -- There is a 2-flipflop synchronizer on each GPIO input, which protects + -- PIO logic from metastabilities. This increases input delay, and for + -- fast synchronous IO (e.g. SPI) these synchronizers may need to be + -- bypassed. Each bit in this register corresponds to one GPIO. 0 -> + -- input is synchronized (default) 1 -> synchronizer is bypassed If in + -- doubt, leave this register as all zeroes. + INPUT_SYNC_BYPASS : aliased HAL.UInt32; + -- Read to sample the pad output values PIO is currently driving to the + -- GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits + -- are hardwired to 0. + DBG_PADOUT : aliased HAL.UInt32; + -- Read to sample the pad output enables (direction) PIO is currently + -- driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most + -- significant bits are hardwired to 0. + DBG_PADOE : aliased HAL.UInt32; + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are + -- also exposed here. + DBG_CFGINFO : aliased DBG_CFGINFO_Register; + -- Write-only access to instruction memory location 0 + INSTR_MEM0 : aliased INSTR_MEM0_Register; + -- Write-only access to instruction memory location 1 + INSTR_MEM1 : aliased INSTR_MEM1_Register; + -- Write-only access to instruction memory location 2 + INSTR_MEM2 : aliased INSTR_MEM2_Register; + -- Write-only access to instruction memory location 3 + INSTR_MEM3 : aliased INSTR_MEM3_Register; + -- Write-only access to instruction memory location 4 + INSTR_MEM4 : aliased INSTR_MEM4_Register; + -- Write-only access to instruction memory location 5 + INSTR_MEM5 : aliased INSTR_MEM5_Register; + -- Write-only access to instruction memory location 6 + INSTR_MEM6 : aliased INSTR_MEM6_Register; + -- Write-only access to instruction memory location 7 + INSTR_MEM7 : aliased INSTR_MEM7_Register; + -- Write-only access to instruction memory location 8 + INSTR_MEM8 : aliased INSTR_MEM8_Register; + -- Write-only access to instruction memory location 9 + INSTR_MEM9 : aliased INSTR_MEM9_Register; + -- Write-only access to instruction memory location 10 + INSTR_MEM10 : aliased INSTR_MEM10_Register; + -- Write-only access to instruction memory location 11 + INSTR_MEM11 : aliased INSTR_MEM11_Register; + -- Write-only access to instruction memory location 12 + INSTR_MEM12 : aliased INSTR_MEM12_Register; + -- Write-only access to instruction memory location 13 + INSTR_MEM13 : aliased INSTR_MEM13_Register; + -- Write-only access to instruction memory location 14 + INSTR_MEM14 : aliased INSTR_MEM14_Register; + -- Write-only access to instruction memory location 15 + INSTR_MEM15 : aliased INSTR_MEM15_Register; + -- Write-only access to instruction memory location 16 + INSTR_MEM16 : aliased INSTR_MEM16_Register; + -- Write-only access to instruction memory location 17 + INSTR_MEM17 : aliased INSTR_MEM17_Register; + -- Write-only access to instruction memory location 18 + INSTR_MEM18 : aliased INSTR_MEM18_Register; + -- Write-only access to instruction memory location 19 + INSTR_MEM19 : aliased INSTR_MEM19_Register; + -- Write-only access to instruction memory location 20 + INSTR_MEM20 : aliased INSTR_MEM20_Register; + -- Write-only access to instruction memory location 21 + INSTR_MEM21 : aliased INSTR_MEM21_Register; + -- Write-only access to instruction memory location 22 + INSTR_MEM22 : aliased INSTR_MEM22_Register; + -- Write-only access to instruction memory location 23 + INSTR_MEM23 : aliased INSTR_MEM23_Register; + -- Write-only access to instruction memory location 24 + INSTR_MEM24 : aliased INSTR_MEM24_Register; + -- Write-only access to instruction memory location 25 + INSTR_MEM25 : aliased INSTR_MEM25_Register; + -- Write-only access to instruction memory location 26 + INSTR_MEM26 : aliased INSTR_MEM26_Register; + -- Write-only access to instruction memory location 27 + INSTR_MEM27 : aliased INSTR_MEM27_Register; + -- Write-only access to instruction memory location 28 + INSTR_MEM28 : aliased INSTR_MEM28_Register; + -- Write-only access to instruction memory location 29 + INSTR_MEM29 : aliased INSTR_MEM29_Register; + -- Write-only access to instruction memory location 30 + INSTR_MEM30 : aliased INSTR_MEM30_Register; + -- Write-only access to instruction memory location 31 + INSTR_MEM31 : aliased INSTR_MEM31_Register; + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM0_CLKDIV : aliased SM0_CLKDIV_Register; + -- Execution/behavioural settings for state machine 0 + SM0_EXECCTRL : aliased SM0_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 0 + SM0_SHIFTCTRL : aliased SM0_SHIFTCTRL_Register; + -- Current instruction address of state machine 0 + SM0_ADDR : aliased SM0_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM0_INSTR : aliased SM0_INSTR_Register; + -- State machine pin control + SM0_PINCTRL : aliased SM0_PINCTRL_Register; + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM1_CLKDIV : aliased SM1_CLKDIV_Register; + -- Execution/behavioural settings for state machine 1 + SM1_EXECCTRL : aliased SM1_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 1 + SM1_SHIFTCTRL : aliased SM1_SHIFTCTRL_Register; + -- Current instruction address of state machine 1 + SM1_ADDR : aliased SM1_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM1_INSTR : aliased SM1_INSTR_Register; + -- State machine pin control + SM1_PINCTRL : aliased SM1_PINCTRL_Register; + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM2_CLKDIV : aliased SM2_CLKDIV_Register; + -- Execution/behavioural settings for state machine 2 + SM2_EXECCTRL : aliased SM2_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 2 + SM2_SHIFTCTRL : aliased SM2_SHIFTCTRL_Register; + -- Current instruction address of state machine 2 + SM2_ADDR : aliased SM2_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM2_INSTR : aliased SM2_INSTR_Register; + -- State machine pin control + SM2_PINCTRL : aliased SM2_PINCTRL_Register; + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM3_CLKDIV : aliased SM3_CLKDIV_Register; + -- Execution/behavioural settings for state machine 3 + SM3_EXECCTRL : aliased SM3_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 3 + SM3_SHIFTCTRL : aliased SM3_SHIFTCTRL_Register; + -- Current instruction address of state machine 3 + SM3_ADDR : aliased SM3_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM3_INSTR : aliased SM3_INSTR_Register; + -- State machine pin control + SM3_PINCTRL : aliased SM3_PINCTRL_Register; + -- Direct read/write access to entry 0 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET3 : aliased HAL.UInt32; + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO + -- numbering, to access more than 32 GPIOs from PIO. Only the values 0 + -- and 16 are supported (only bit 4 is writable). + GPIOBASE : aliased GPIOBASE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable for irq0 + IRQ0_INTE : aliased IRQ0_INTE_Register; + -- Interrupt Force for irq0 + IRQ0_INTF : aliased IRQ0_INTF_Register; + -- Interrupt status after masking & forcing for irq0 + IRQ0_INTS : aliased IRQ0_INTS_Register; + -- Interrupt Enable for irq1 + IRQ1_INTE : aliased IRQ1_INTE_Register; + -- Interrupt Force for irq1 + IRQ1_INTF : aliased IRQ1_INTF_Register; + -- Interrupt status after masking & forcing for irq1 + IRQ1_INTS : aliased IRQ1_INTS_Register; + end record + with Volatile; + + for PIO0_Peripheral use record + CTRL at 16#0# range 0 .. 31; + FSTAT at 16#4# range 0 .. 31; + FDEBUG at 16#8# range 0 .. 31; + FLEVEL at 16#C# range 0 .. 31; + TXF0 at 16#10# range 0 .. 31; + TXF1 at 16#14# range 0 .. 31; + TXF2 at 16#18# range 0 .. 31; + TXF3 at 16#1C# range 0 .. 31; + RXF0 at 16#20# range 0 .. 31; + RXF1 at 16#24# range 0 .. 31; + RXF2 at 16#28# range 0 .. 31; + RXF3 at 16#2C# range 0 .. 31; + IRQ at 16#30# range 0 .. 31; + IRQ_FORCE at 16#34# range 0 .. 31; + INPUT_SYNC_BYPASS at 16#38# range 0 .. 31; + DBG_PADOUT at 16#3C# range 0 .. 31; + DBG_PADOE at 16#40# range 0 .. 31; + DBG_CFGINFO at 16#44# range 0 .. 31; + INSTR_MEM0 at 16#48# range 0 .. 31; + INSTR_MEM1 at 16#4C# range 0 .. 31; + INSTR_MEM2 at 16#50# range 0 .. 31; + INSTR_MEM3 at 16#54# range 0 .. 31; + INSTR_MEM4 at 16#58# range 0 .. 31; + INSTR_MEM5 at 16#5C# range 0 .. 31; + INSTR_MEM6 at 16#60# range 0 .. 31; + INSTR_MEM7 at 16#64# range 0 .. 31; + INSTR_MEM8 at 16#68# range 0 .. 31; + INSTR_MEM9 at 16#6C# range 0 .. 31; + INSTR_MEM10 at 16#70# range 0 .. 31; + INSTR_MEM11 at 16#74# range 0 .. 31; + INSTR_MEM12 at 16#78# range 0 .. 31; + INSTR_MEM13 at 16#7C# range 0 .. 31; + INSTR_MEM14 at 16#80# range 0 .. 31; + INSTR_MEM15 at 16#84# range 0 .. 31; + INSTR_MEM16 at 16#88# range 0 .. 31; + INSTR_MEM17 at 16#8C# range 0 .. 31; + INSTR_MEM18 at 16#90# range 0 .. 31; + INSTR_MEM19 at 16#94# range 0 .. 31; + INSTR_MEM20 at 16#98# range 0 .. 31; + INSTR_MEM21 at 16#9C# range 0 .. 31; + INSTR_MEM22 at 16#A0# range 0 .. 31; + INSTR_MEM23 at 16#A4# range 0 .. 31; + INSTR_MEM24 at 16#A8# range 0 .. 31; + INSTR_MEM25 at 16#AC# range 0 .. 31; + INSTR_MEM26 at 16#B0# range 0 .. 31; + INSTR_MEM27 at 16#B4# range 0 .. 31; + INSTR_MEM28 at 16#B8# range 0 .. 31; + INSTR_MEM29 at 16#BC# range 0 .. 31; + INSTR_MEM30 at 16#C0# range 0 .. 31; + INSTR_MEM31 at 16#C4# range 0 .. 31; + SM0_CLKDIV at 16#C8# range 0 .. 31; + SM0_EXECCTRL at 16#CC# range 0 .. 31; + SM0_SHIFTCTRL at 16#D0# range 0 .. 31; + SM0_ADDR at 16#D4# range 0 .. 31; + SM0_INSTR at 16#D8# range 0 .. 31; + SM0_PINCTRL at 16#DC# range 0 .. 31; + SM1_CLKDIV at 16#E0# range 0 .. 31; + SM1_EXECCTRL at 16#E4# range 0 .. 31; + SM1_SHIFTCTRL at 16#E8# range 0 .. 31; + SM1_ADDR at 16#EC# range 0 .. 31; + SM1_INSTR at 16#F0# range 0 .. 31; + SM1_PINCTRL at 16#F4# range 0 .. 31; + SM2_CLKDIV at 16#F8# range 0 .. 31; + SM2_EXECCTRL at 16#FC# range 0 .. 31; + SM2_SHIFTCTRL at 16#100# range 0 .. 31; + SM2_ADDR at 16#104# range 0 .. 31; + SM2_INSTR at 16#108# range 0 .. 31; + SM2_PINCTRL at 16#10C# range 0 .. 31; + SM3_CLKDIV at 16#110# range 0 .. 31; + SM3_EXECCTRL at 16#114# range 0 .. 31; + SM3_SHIFTCTRL at 16#118# range 0 .. 31; + SM3_ADDR at 16#11C# range 0 .. 31; + SM3_INSTR at 16#120# range 0 .. 31; + SM3_PINCTRL at 16#124# range 0 .. 31; + RXF0_PUTGET0 at 16#128# range 0 .. 31; + RXF0_PUTGET1 at 16#12C# range 0 .. 31; + RXF0_PUTGET2 at 16#130# range 0 .. 31; + RXF0_PUTGET3 at 16#134# range 0 .. 31; + RXF1_PUTGET0 at 16#138# range 0 .. 31; + RXF1_PUTGET1 at 16#13C# range 0 .. 31; + RXF1_PUTGET2 at 16#140# range 0 .. 31; + RXF1_PUTGET3 at 16#144# range 0 .. 31; + RXF2_PUTGET0 at 16#148# range 0 .. 31; + RXF2_PUTGET1 at 16#14C# range 0 .. 31; + RXF2_PUTGET2 at 16#150# range 0 .. 31; + RXF2_PUTGET3 at 16#154# range 0 .. 31; + RXF3_PUTGET0 at 16#158# range 0 .. 31; + RXF3_PUTGET1 at 16#15C# range 0 .. 31; + RXF3_PUTGET2 at 16#160# range 0 .. 31; + RXF3_PUTGET3 at 16#164# range 0 .. 31; + GPIOBASE at 16#168# range 0 .. 31; + INTR at 16#16C# range 0 .. 31; + IRQ0_INTE at 16#170# range 0 .. 31; + IRQ0_INTF at 16#174# range 0 .. 31; + IRQ0_INTS at 16#178# range 0 .. 31; + IRQ1_INTE at 16#17C# range 0 .. 31; + IRQ1_INTF at 16#180# range 0 .. 31; + IRQ1_INTS at 16#184# range 0 .. 31; + end record; + + -- Programmable IO block + PIO0_Periph : aliased PIO0_Peripheral + with Import, Address => PIO0_Base; + +end RP2350_SVD.PIO0; diff --git a/src/svd/rp2350_svd-pio1.ads b/src/svd/rp2350_svd-pio1.ads new file mode 100644 index 0000000..9c5966c --- /dev/null +++ b/src/svd/rp2350_svd-pio1.ads @@ -0,0 +1,2880 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Programmable IO block +package RP2350_SVD.PIO1 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CTRL_SM_ENABLE_Field is HAL.UInt4; + subtype CTRL_SM_RESTART_Field is HAL.UInt4; + subtype CTRL_CLKDIV_RESTART_Field is HAL.UInt4; + subtype CTRL_PREV_PIO_MASK_Field is HAL.UInt4; + subtype CTRL_NEXT_PIO_MASK_Field is HAL.UInt4; + + -- PIO control register + type CTRL_Register is record + -- Enable/disable each of the four state machines by writing 1/0 to each + -- of these four bits. When disabled, a state machine will cease + -- executing instructions, except those written directly to SMx_INSTR by + -- the system. Multiple bits can be set/cleared at once to run/halt + -- multiple state machines simultaneously. + SM_ENABLE : CTRL_SM_ENABLE_Field := 16#0#; + -- Write-only. Write 1 to instantly clear internal SM state which may be + -- otherwise difficult to access and will affect future execution. + -- Specifically, the following are cleared: input and output shift + -- counters; the contents of the input shift register; the delay + -- counter; the waiting-on-IRQ state; any stalled instruction written to + -- SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to + -- OUT_STICKY. The contents of the output shift register and the X/Y + -- scratch registers are not affected. + SM_RESTART : CTRL_SM_RESTART_Field := 16#0#; + -- Write-only. Restart a state machine's clock divider from an initial + -- phase of 0. Clock dividers are free-running, so once started, their + -- output (including fractional jitter) is completely determined by the + -- integer/fractional divisor configured in SMx_CLKDIV. This means that, + -- if multiple clock dividers with the same divisor are restarted + -- simultaneously, by writing multiple 1 bits to this field, the + -- execution clocks of those state machines will run in precise + -- lockstep. Note that setting/clearing SM_ENABLE does not stop the + -- clock divider from running, so once multiple state machines' clocks + -- are synchronised, it is safe to disable/reenable a state machine, + -- whilst keeping the clock dividers in sync. Note also that + -- CLKDIV_RESTART can be written to whilst the state machine is running, + -- and this is useful to resynchronise clock dividers after the divisors + -- (SMx_CLKDIV) have been changed on-the-fly. + CLKDIV_RESTART : CTRL_CLKDIV_RESTART_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- lower-numbered PIO block in the system (or the highest-numbered PIO + -- block if this is PIO block 0) to which to apply the operations + -- specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same + -- write. This allows state machines in a neighbouring PIO block to be + -- started/stopped/clock-synced exactly simultaneously with a write to + -- this PIO block's CTRL register. Neighbouring PIO blocks are + -- disconnected (status signals tied to 0 and control signals ignored) + -- if one block is accessible to NonSecure code, and one is not. + PREV_PIO_MASK : CTRL_PREV_PIO_MASK_Field := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- higher-numbered PIO block in the system (or PIO block 0 if this is + -- the highest-numbered PIO block) to which to apply the operations + -- specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and + -- NEXTPREV_SM_DISABLE in the same write. This allows state machines in + -- a neighbouring PIO block to be started/stopped/clock-synced exactly + -- simultaneously with a write to this PIO block's CTRL register. Note + -- that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK + -- actually indicate the same PIO block. In this case the effects are + -- applied cumulatively (as though the masks were OR'd together). + -- Neighbouring PIO blocks are disconnected (status signals tied to 0 + -- and control signals ignored) if one block is accessible to NonSecure + -- code, and one is not. + NEXT_PIO_MASK : CTRL_NEXT_PIO_MASK_Field := 16#0#; + -- Write-only. Write 1 to enable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to setting the corresponding SM_ENABLE bits + -- in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and + -- OTHERS_SM_DISABLE are set, the disable takes precedence. + NEXTPREV_SM_ENABLE : Boolean := False; + -- Write-only. Write 1 to disable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to clearing the corresponding SM_ENABLE + -- bits in those PIOs' CTRL registers. + NEXTPREV_SM_DISABLE : Boolean := False; + -- Write-only. Write 1 to restart the clock dividers of state machines + -- in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and + -- PREV_PIO_MASK in the same write. This is equivalent to writing 1 to + -- the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + NEXTPREV_CLKDIV_RESTART : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + SM_ENABLE at 0 range 0 .. 3; + SM_RESTART at 0 range 4 .. 7; + CLKDIV_RESTART at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PREV_PIO_MASK at 0 range 16 .. 19; + NEXT_PIO_MASK at 0 range 20 .. 23; + NEXTPREV_SM_ENABLE at 0 range 24 .. 24; + NEXTPREV_SM_DISABLE at 0 range 25 .. 25; + NEXTPREV_CLKDIV_RESTART at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype FSTAT_RXFULL_Field is HAL.UInt4; + subtype FSTAT_RXEMPTY_Field is HAL.UInt4; + subtype FSTAT_TXFULL_Field is HAL.UInt4; + subtype FSTAT_TXEMPTY_Field is HAL.UInt4; + + -- FIFO status register + type FSTAT_Register is record + -- Read-only. State machine RX FIFO is full + RXFULL : FSTAT_RXFULL_Field; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. State machine RX FIFO is empty + RXEMPTY : FSTAT_RXEMPTY_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. State machine TX FIFO is full + TXFULL : FSTAT_TXFULL_Field; + -- unspecified + Reserved_20_23 : HAL.UInt4; + -- Read-only. State machine TX FIFO is empty + TXEMPTY : FSTAT_TXEMPTY_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FSTAT_Register use record + RXFULL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXEMPTY at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXFULL at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXEMPTY at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FDEBUG_RXSTALL_Field is HAL.UInt4; + subtype FDEBUG_RXUNDER_Field is HAL.UInt4; + subtype FDEBUG_TXOVER_Field is HAL.UInt4; + subtype FDEBUG_TXSTALL_Field is HAL.UInt4; + + -- FIFO debug register + type FDEBUG_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on full RX FIFO during a + -- blocking PUSH, or an IN with autopush enabled. This flag is also set + -- when a nonblocking PUSH to a full FIFO took place, in which case the + -- state machine has dropped data. Write 1 to clear. + RXSTALL : FDEBUG_RXSTALL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. RX FIFO underflow (i.e. read-on-empty by the system) + -- has occurred. Write 1 to clear. Note that read-on-empty does not + -- perturb the state of the FIFO in any way, but the data returned by + -- reading from an empty FIFO is undefined, so this flag generally only + -- becomes set due to some kind of software error. + RXUNDER : FDEBUG_RXUNDER_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. TX FIFO overflow (i.e. write-on-full by the system) has + -- occurred. Write 1 to clear. Note that write-on-full does not alter + -- the state or contents of the FIFO in any way, but the data that the + -- system attempted to write is dropped, so if this flag is set, your + -- software has quite likely dropped some data on the floor. + TXOVER : FDEBUG_TXOVER_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on empty TX FIFO during a + -- blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + TXSTALL : FDEBUG_TXSTALL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FDEBUG_Register use record + RXSTALL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXUNDER at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXOVER at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXSTALL at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FLEVEL_TX0_Field is HAL.UInt4; + subtype FLEVEL_RX0_Field is HAL.UInt4; + subtype FLEVEL_TX1_Field is HAL.UInt4; + subtype FLEVEL_RX1_Field is HAL.UInt4; + subtype FLEVEL_TX2_Field is HAL.UInt4; + subtype FLEVEL_RX2_Field is HAL.UInt4; + subtype FLEVEL_TX3_Field is HAL.UInt4; + subtype FLEVEL_RX3_Field is HAL.UInt4; + + -- FIFO levels + type FLEVEL_Register is record + -- Read-only. + TX0 : FLEVEL_TX0_Field; + -- Read-only. + RX0 : FLEVEL_RX0_Field; + -- Read-only. + TX1 : FLEVEL_TX1_Field; + -- Read-only. + RX1 : FLEVEL_RX1_Field; + -- Read-only. + TX2 : FLEVEL_TX2_Field; + -- Read-only. + RX2 : FLEVEL_RX2_Field; + -- Read-only. + TX3 : FLEVEL_TX3_Field; + -- Read-only. + RX3 : FLEVEL_RX3_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FLEVEL_Register use record + TX0 at 0 range 0 .. 3; + RX0 at 0 range 4 .. 7; + TX1 at 0 range 8 .. 11; + RX1 at 0 range 12 .. 15; + TX2 at 0 range 16 .. 19; + RX2 at 0 range 20 .. 23; + TX3 at 0 range 24 .. 27; + RX3 at 0 range 28 .. 31; + end record; + + subtype IRQ_IRQ_Field is HAL.UInt8; + + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by the + -- state machines. There's no fixed association between flags and state + -- machines -- any state machine can use any flag. Any of the eight flags + -- can be used for timing synchronisation between state machines, using IRQ + -- and WAIT instructions. Any combination of the eight flags can also + -- routed out to either of the two system-level interrupt requests, + -- alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + type IRQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + IRQ : IRQ_IRQ_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_Register use record + IRQ at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype IRQ_FORCE_IRQ_FORCE_Field is HAL.UInt8; + + -- Writing a 1 to each of these bits will forcibly assert the corresponding + -- IRQ. Note this is different to the INTF register: writing here affects + -- PIO internal state. INTF just asserts the processor-facing IRQ signal + -- for testing ISRs, and is not visible to the state machines. + type IRQ_FORCE_Register is record + -- Write-only. + IRQ_FORCE : IRQ_FORCE_IRQ_FORCE_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_FORCE_Register use record + IRQ_FORCE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DBG_CFGINFO_FIFO_DEPTH_Field is HAL.UInt6; + subtype DBG_CFGINFO_SM_COUNT_Field is HAL.UInt4; + subtype DBG_CFGINFO_IMEM_SIZE_Field is HAL.UInt6; + + -- Version of the core PIO hardware. + type DBG_CFGINFO_VERSION_Field is + (-- Version 0 (RP2040) + v0, + -- Version 1 (RP2350) + v1) + with Size => 4; + for DBG_CFGINFO_VERSION_Field use + (v0 => 0, + v1 => 1); + + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are also + -- exposed here. + type DBG_CFGINFO_Register is record + -- Read-only. The depth of the state machine TX/RX FIFOs, measured in + -- words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + -- this depth. + FIFO_DEPTH : DBG_CFGINFO_FIFO_DEPTH_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. The number of state machines this PIO instance is equipped + -- with. + SM_COUNT : DBG_CFGINFO_SM_COUNT_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. The size of the instruction memory, measured in units of + -- one instruction + IMEM_SIZE : DBG_CFGINFO_IMEM_SIZE_Field; + -- unspecified + Reserved_22_27 : HAL.UInt6; + -- Read-only. Version of the core PIO hardware. + VERSION : DBG_CFGINFO_VERSION_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBG_CFGINFO_Register use record + FIFO_DEPTH at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SM_COUNT at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + IMEM_SIZE at 0 range 16 .. 21; + Reserved_22_27 at 0 range 22 .. 27; + VERSION at 0 range 28 .. 31; + end record; + + subtype INSTR_MEM0_INSTR_MEM0_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 0 + type INSTR_MEM0_Register is record + -- Write-only. + INSTR_MEM0 : INSTR_MEM0_INSTR_MEM0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM0_Register use record + INSTR_MEM0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM1_INSTR_MEM1_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 1 + type INSTR_MEM1_Register is record + -- Write-only. + INSTR_MEM1 : INSTR_MEM1_INSTR_MEM1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM1_Register use record + INSTR_MEM1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM2_INSTR_MEM2_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 2 + type INSTR_MEM2_Register is record + -- Write-only. + INSTR_MEM2 : INSTR_MEM2_INSTR_MEM2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM2_Register use record + INSTR_MEM2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM3_INSTR_MEM3_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 3 + type INSTR_MEM3_Register is record + -- Write-only. + INSTR_MEM3 : INSTR_MEM3_INSTR_MEM3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM3_Register use record + INSTR_MEM3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM4_INSTR_MEM4_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 4 + type INSTR_MEM4_Register is record + -- Write-only. + INSTR_MEM4 : INSTR_MEM4_INSTR_MEM4_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM4_Register use record + INSTR_MEM4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM5_INSTR_MEM5_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 5 + type INSTR_MEM5_Register is record + -- Write-only. + INSTR_MEM5 : INSTR_MEM5_INSTR_MEM5_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM5_Register use record + INSTR_MEM5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM6_INSTR_MEM6_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 6 + type INSTR_MEM6_Register is record + -- Write-only. + INSTR_MEM6 : INSTR_MEM6_INSTR_MEM6_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM6_Register use record + INSTR_MEM6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM7_INSTR_MEM7_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 7 + type INSTR_MEM7_Register is record + -- Write-only. + INSTR_MEM7 : INSTR_MEM7_INSTR_MEM7_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM7_Register use record + INSTR_MEM7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM8_INSTR_MEM8_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 8 + type INSTR_MEM8_Register is record + -- Write-only. + INSTR_MEM8 : INSTR_MEM8_INSTR_MEM8_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM8_Register use record + INSTR_MEM8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM9_INSTR_MEM9_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 9 + type INSTR_MEM9_Register is record + -- Write-only. + INSTR_MEM9 : INSTR_MEM9_INSTR_MEM9_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM9_Register use record + INSTR_MEM9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM10_INSTR_MEM10_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 10 + type INSTR_MEM10_Register is record + -- Write-only. + INSTR_MEM10 : INSTR_MEM10_INSTR_MEM10_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM10_Register use record + INSTR_MEM10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM11_INSTR_MEM11_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 11 + type INSTR_MEM11_Register is record + -- Write-only. + INSTR_MEM11 : INSTR_MEM11_INSTR_MEM11_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM11_Register use record + INSTR_MEM11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM12_INSTR_MEM12_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 12 + type INSTR_MEM12_Register is record + -- Write-only. + INSTR_MEM12 : INSTR_MEM12_INSTR_MEM12_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM12_Register use record + INSTR_MEM12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM13_INSTR_MEM13_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 13 + type INSTR_MEM13_Register is record + -- Write-only. + INSTR_MEM13 : INSTR_MEM13_INSTR_MEM13_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM13_Register use record + INSTR_MEM13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM14_INSTR_MEM14_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 14 + type INSTR_MEM14_Register is record + -- Write-only. + INSTR_MEM14 : INSTR_MEM14_INSTR_MEM14_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM14_Register use record + INSTR_MEM14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM15_INSTR_MEM15_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 15 + type INSTR_MEM15_Register is record + -- Write-only. + INSTR_MEM15 : INSTR_MEM15_INSTR_MEM15_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM15_Register use record + INSTR_MEM15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM16_INSTR_MEM16_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 16 + type INSTR_MEM16_Register is record + -- Write-only. + INSTR_MEM16 : INSTR_MEM16_INSTR_MEM16_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM16_Register use record + INSTR_MEM16 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM17_INSTR_MEM17_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 17 + type INSTR_MEM17_Register is record + -- Write-only. + INSTR_MEM17 : INSTR_MEM17_INSTR_MEM17_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM17_Register use record + INSTR_MEM17 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM18_INSTR_MEM18_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 18 + type INSTR_MEM18_Register is record + -- Write-only. + INSTR_MEM18 : INSTR_MEM18_INSTR_MEM18_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM18_Register use record + INSTR_MEM18 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM19_INSTR_MEM19_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 19 + type INSTR_MEM19_Register is record + -- Write-only. + INSTR_MEM19 : INSTR_MEM19_INSTR_MEM19_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM19_Register use record + INSTR_MEM19 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM20_INSTR_MEM20_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 20 + type INSTR_MEM20_Register is record + -- Write-only. + INSTR_MEM20 : INSTR_MEM20_INSTR_MEM20_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM20_Register use record + INSTR_MEM20 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM21_INSTR_MEM21_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 21 + type INSTR_MEM21_Register is record + -- Write-only. + INSTR_MEM21 : INSTR_MEM21_INSTR_MEM21_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM21_Register use record + INSTR_MEM21 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM22_INSTR_MEM22_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 22 + type INSTR_MEM22_Register is record + -- Write-only. + INSTR_MEM22 : INSTR_MEM22_INSTR_MEM22_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM22_Register use record + INSTR_MEM22 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM23_INSTR_MEM23_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 23 + type INSTR_MEM23_Register is record + -- Write-only. + INSTR_MEM23 : INSTR_MEM23_INSTR_MEM23_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM23_Register use record + INSTR_MEM23 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM24_INSTR_MEM24_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 24 + type INSTR_MEM24_Register is record + -- Write-only. + INSTR_MEM24 : INSTR_MEM24_INSTR_MEM24_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM24_Register use record + INSTR_MEM24 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM25_INSTR_MEM25_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 25 + type INSTR_MEM25_Register is record + -- Write-only. + INSTR_MEM25 : INSTR_MEM25_INSTR_MEM25_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM25_Register use record + INSTR_MEM25 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM26_INSTR_MEM26_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 26 + type INSTR_MEM26_Register is record + -- Write-only. + INSTR_MEM26 : INSTR_MEM26_INSTR_MEM26_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM26_Register use record + INSTR_MEM26 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM27_INSTR_MEM27_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 27 + type INSTR_MEM27_Register is record + -- Write-only. + INSTR_MEM27 : INSTR_MEM27_INSTR_MEM27_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM27_Register use record + INSTR_MEM27 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM28_INSTR_MEM28_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 28 + type INSTR_MEM28_Register is record + -- Write-only. + INSTR_MEM28 : INSTR_MEM28_INSTR_MEM28_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM28_Register use record + INSTR_MEM28 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM29_INSTR_MEM29_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 29 + type INSTR_MEM29_Register is record + -- Write-only. + INSTR_MEM29 : INSTR_MEM29_INSTR_MEM29_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM29_Register use record + INSTR_MEM29 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM30_INSTR_MEM30_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 30 + type INSTR_MEM30_Register is record + -- Write-only. + INSTR_MEM30 : INSTR_MEM30_INSTR_MEM30_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM30_Register use record + INSTR_MEM30 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM31_INSTR_MEM31_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 31 + type INSTR_MEM31_Register is record + -- Write-only. + INSTR_MEM31 : INSTR_MEM31_INSTR_MEM31_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM31_Register use record + INSTR_MEM31 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM0_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM0_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM0_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM0_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM0_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM0_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM0_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM0_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM0_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM0_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM0_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM0_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 0 + type SM0_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM0_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO1.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM0_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO1.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM0_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM0_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM0_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM0_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM0_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 0 + type SM0_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM0_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM0_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM0_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM0_ADDR_SM0_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 0 + type SM0_ADDR_Register is record + -- Read-only. + SM0_ADDR : SM0_ADDR_SM0_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_ADDR_Register use record + SM0_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM0_INSTR_SM0_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM0_INSTR_Register is record + SM0_INSTR : SM0_INSTR_SM0_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_INSTR_Register use record + SM0_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM0_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM0_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM0_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM0_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM0_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM0_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM0_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM0_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM0_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM0_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM1_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM1_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM1_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM1_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM1_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM1_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM1_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM1_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM1_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM1_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM1_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM1_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM1_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 1 + type SM1_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM1_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO1.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM1_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO1.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM1_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM1_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM1_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM1_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM1_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 1 + type SM1_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM1_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM1_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM1_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM1_ADDR_SM1_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 1 + type SM1_ADDR_Register is record + -- Read-only. + SM1_ADDR : SM1_ADDR_SM1_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_ADDR_Register use record + SM1_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM1_INSTR_SM1_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM1_INSTR_Register is record + SM1_INSTR : SM1_INSTR_SM1_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_INSTR_Register use record + SM1_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM1_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM1_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM1_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM1_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM1_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM1_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM1_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM1_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM1_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM1_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM1_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM2_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM2_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM2_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM2_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM2_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM2_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM2_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM2_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM2_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM2_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM2_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM2_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM2_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 2 + type SM2_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM2_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO1.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM2_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO1.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM2_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM2_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM2_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM2_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM2_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 2 + type SM2_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM2_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM2_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM2_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM2_ADDR_SM2_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 2 + type SM2_ADDR_Register is record + -- Read-only. + SM2_ADDR : SM2_ADDR_SM2_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_ADDR_Register use record + SM2_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM2_INSTR_SM2_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM2_INSTR_Register is record + SM2_INSTR : SM2_INSTR_SM2_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_INSTR_Register use record + SM2_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM2_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM2_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM2_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM2_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM2_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM2_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM2_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM2_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM2_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM2_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM2_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM3_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM3_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM3_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM3_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM3_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM3_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM3_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM3_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM3_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM3_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM3_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM3_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM3_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 3 + type SM3_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM3_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO1.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM3_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO1.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM3_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM3_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM3_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM3_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM3_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 3 + type SM3_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM3_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM3_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM3_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM3_ADDR_SM3_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 3 + type SM3_ADDR_Register is record + -- Read-only. + SM3_ADDR : SM3_ADDR_SM3_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_ADDR_Register use record + SM3_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM3_INSTR_SM3_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM3_INSTR_Register is record + SM3_INSTR : SM3_INSTR_SM3_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_INSTR_Register use record + SM3_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM3_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM3_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM3_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM3_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM3_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM3_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM3_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM3_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM3_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM3_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM3_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, + -- to access more than 32 GPIOs from PIO. Only the values 0 and 16 are + -- supported (only bit 4 is writable). + type GPIOBASE_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + GPIOBASE : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIOBASE_Register use record + Reserved_0_3 at 0 range 0 .. 3; + GPIOBASE at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- INTR_SM array + type INTR_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for INTR_SM + type INTR_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : INTR_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for INTR_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : INTR_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTE_SM array + type IRQ0_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTE_SM + type IRQ0_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq0 + type IRQ0_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTF_SM array + type IRQ0_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTF_SM + type IRQ0_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq0 + type IRQ0_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTS_SM array + type IRQ0_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTS_SM + type IRQ0_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq0 + type IRQ0_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ0_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTE_SM array + type IRQ1_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTE_SM + type IRQ1_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq1 + type IRQ1_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTF_SM array + type IRQ1_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTF_SM + type IRQ1_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq1 + type IRQ1_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTS_SM array + type IRQ1_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTS_SM + type IRQ1_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq1 + type IRQ1_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ1_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Programmable IO block + type PIO1_Peripheral is record + -- PIO control register + CTRL : aliased CTRL_Register; + -- FIFO status register + FSTAT : aliased FSTAT_Register; + -- FIFO debug register + FDEBUG : aliased FDEBUG_Register; + -- FIFO levels + FLEVEL : aliased FLEVEL_Register; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF0 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF1 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF2 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF3 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF0 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF1 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF2 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF3 : aliased HAL.UInt32; + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by + -- the state machines. There's no fixed association between flags and + -- state machines -- any state machine can use any flag. Any of the + -- eight flags can be used for timing synchronisation between state + -- machines, using IRQ and WAIT instructions. Any combination of the + -- eight flags can also routed out to either of the two system-level + -- interrupt requests, alongside FIFO status interrupts -- see e.g. + -- IRQ0_INTE. + IRQ : aliased IRQ_Register; + -- Writing a 1 to each of these bits will forcibly assert the + -- corresponding IRQ. Note this is different to the INTF register: + -- writing here affects PIO internal state. INTF just asserts the + -- processor-facing IRQ signal for testing ISRs, and is not visible to + -- the state machines. + IRQ_FORCE : aliased IRQ_FORCE_Register; + -- There is a 2-flipflop synchronizer on each GPIO input, which protects + -- PIO logic from metastabilities. This increases input delay, and for + -- fast synchronous IO (e.g. SPI) these synchronizers may need to be + -- bypassed. Each bit in this register corresponds to one GPIO. 0 -> + -- input is synchronized (default) 1 -> synchronizer is bypassed If in + -- doubt, leave this register as all zeroes. + INPUT_SYNC_BYPASS : aliased HAL.UInt32; + -- Read to sample the pad output values PIO is currently driving to the + -- GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits + -- are hardwired to 0. + DBG_PADOUT : aliased HAL.UInt32; + -- Read to sample the pad output enables (direction) PIO is currently + -- driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most + -- significant bits are hardwired to 0. + DBG_PADOE : aliased HAL.UInt32; + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are + -- also exposed here. + DBG_CFGINFO : aliased DBG_CFGINFO_Register; + -- Write-only access to instruction memory location 0 + INSTR_MEM0 : aliased INSTR_MEM0_Register; + -- Write-only access to instruction memory location 1 + INSTR_MEM1 : aliased INSTR_MEM1_Register; + -- Write-only access to instruction memory location 2 + INSTR_MEM2 : aliased INSTR_MEM2_Register; + -- Write-only access to instruction memory location 3 + INSTR_MEM3 : aliased INSTR_MEM3_Register; + -- Write-only access to instruction memory location 4 + INSTR_MEM4 : aliased INSTR_MEM4_Register; + -- Write-only access to instruction memory location 5 + INSTR_MEM5 : aliased INSTR_MEM5_Register; + -- Write-only access to instruction memory location 6 + INSTR_MEM6 : aliased INSTR_MEM6_Register; + -- Write-only access to instruction memory location 7 + INSTR_MEM7 : aliased INSTR_MEM7_Register; + -- Write-only access to instruction memory location 8 + INSTR_MEM8 : aliased INSTR_MEM8_Register; + -- Write-only access to instruction memory location 9 + INSTR_MEM9 : aliased INSTR_MEM9_Register; + -- Write-only access to instruction memory location 10 + INSTR_MEM10 : aliased INSTR_MEM10_Register; + -- Write-only access to instruction memory location 11 + INSTR_MEM11 : aliased INSTR_MEM11_Register; + -- Write-only access to instruction memory location 12 + INSTR_MEM12 : aliased INSTR_MEM12_Register; + -- Write-only access to instruction memory location 13 + INSTR_MEM13 : aliased INSTR_MEM13_Register; + -- Write-only access to instruction memory location 14 + INSTR_MEM14 : aliased INSTR_MEM14_Register; + -- Write-only access to instruction memory location 15 + INSTR_MEM15 : aliased INSTR_MEM15_Register; + -- Write-only access to instruction memory location 16 + INSTR_MEM16 : aliased INSTR_MEM16_Register; + -- Write-only access to instruction memory location 17 + INSTR_MEM17 : aliased INSTR_MEM17_Register; + -- Write-only access to instruction memory location 18 + INSTR_MEM18 : aliased INSTR_MEM18_Register; + -- Write-only access to instruction memory location 19 + INSTR_MEM19 : aliased INSTR_MEM19_Register; + -- Write-only access to instruction memory location 20 + INSTR_MEM20 : aliased INSTR_MEM20_Register; + -- Write-only access to instruction memory location 21 + INSTR_MEM21 : aliased INSTR_MEM21_Register; + -- Write-only access to instruction memory location 22 + INSTR_MEM22 : aliased INSTR_MEM22_Register; + -- Write-only access to instruction memory location 23 + INSTR_MEM23 : aliased INSTR_MEM23_Register; + -- Write-only access to instruction memory location 24 + INSTR_MEM24 : aliased INSTR_MEM24_Register; + -- Write-only access to instruction memory location 25 + INSTR_MEM25 : aliased INSTR_MEM25_Register; + -- Write-only access to instruction memory location 26 + INSTR_MEM26 : aliased INSTR_MEM26_Register; + -- Write-only access to instruction memory location 27 + INSTR_MEM27 : aliased INSTR_MEM27_Register; + -- Write-only access to instruction memory location 28 + INSTR_MEM28 : aliased INSTR_MEM28_Register; + -- Write-only access to instruction memory location 29 + INSTR_MEM29 : aliased INSTR_MEM29_Register; + -- Write-only access to instruction memory location 30 + INSTR_MEM30 : aliased INSTR_MEM30_Register; + -- Write-only access to instruction memory location 31 + INSTR_MEM31 : aliased INSTR_MEM31_Register; + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM0_CLKDIV : aliased SM0_CLKDIV_Register; + -- Execution/behavioural settings for state machine 0 + SM0_EXECCTRL : aliased SM0_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 0 + SM0_SHIFTCTRL : aliased SM0_SHIFTCTRL_Register; + -- Current instruction address of state machine 0 + SM0_ADDR : aliased SM0_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM0_INSTR : aliased SM0_INSTR_Register; + -- State machine pin control + SM0_PINCTRL : aliased SM0_PINCTRL_Register; + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM1_CLKDIV : aliased SM1_CLKDIV_Register; + -- Execution/behavioural settings for state machine 1 + SM1_EXECCTRL : aliased SM1_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 1 + SM1_SHIFTCTRL : aliased SM1_SHIFTCTRL_Register; + -- Current instruction address of state machine 1 + SM1_ADDR : aliased SM1_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM1_INSTR : aliased SM1_INSTR_Register; + -- State machine pin control + SM1_PINCTRL : aliased SM1_PINCTRL_Register; + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM2_CLKDIV : aliased SM2_CLKDIV_Register; + -- Execution/behavioural settings for state machine 2 + SM2_EXECCTRL : aliased SM2_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 2 + SM2_SHIFTCTRL : aliased SM2_SHIFTCTRL_Register; + -- Current instruction address of state machine 2 + SM2_ADDR : aliased SM2_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM2_INSTR : aliased SM2_INSTR_Register; + -- State machine pin control + SM2_PINCTRL : aliased SM2_PINCTRL_Register; + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM3_CLKDIV : aliased SM3_CLKDIV_Register; + -- Execution/behavioural settings for state machine 3 + SM3_EXECCTRL : aliased SM3_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 3 + SM3_SHIFTCTRL : aliased SM3_SHIFTCTRL_Register; + -- Current instruction address of state machine 3 + SM3_ADDR : aliased SM3_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM3_INSTR : aliased SM3_INSTR_Register; + -- State machine pin control + SM3_PINCTRL : aliased SM3_PINCTRL_Register; + -- Direct read/write access to entry 0 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET3 : aliased HAL.UInt32; + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO + -- numbering, to access more than 32 GPIOs from PIO. Only the values 0 + -- and 16 are supported (only bit 4 is writable). + GPIOBASE : aliased GPIOBASE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable for irq0 + IRQ0_INTE : aliased IRQ0_INTE_Register; + -- Interrupt Force for irq0 + IRQ0_INTF : aliased IRQ0_INTF_Register; + -- Interrupt status after masking & forcing for irq0 + IRQ0_INTS : aliased IRQ0_INTS_Register; + -- Interrupt Enable for irq1 + IRQ1_INTE : aliased IRQ1_INTE_Register; + -- Interrupt Force for irq1 + IRQ1_INTF : aliased IRQ1_INTF_Register; + -- Interrupt status after masking & forcing for irq1 + IRQ1_INTS : aliased IRQ1_INTS_Register; + end record + with Volatile; + + for PIO1_Peripheral use record + CTRL at 16#0# range 0 .. 31; + FSTAT at 16#4# range 0 .. 31; + FDEBUG at 16#8# range 0 .. 31; + FLEVEL at 16#C# range 0 .. 31; + TXF0 at 16#10# range 0 .. 31; + TXF1 at 16#14# range 0 .. 31; + TXF2 at 16#18# range 0 .. 31; + TXF3 at 16#1C# range 0 .. 31; + RXF0 at 16#20# range 0 .. 31; + RXF1 at 16#24# range 0 .. 31; + RXF2 at 16#28# range 0 .. 31; + RXF3 at 16#2C# range 0 .. 31; + IRQ at 16#30# range 0 .. 31; + IRQ_FORCE at 16#34# range 0 .. 31; + INPUT_SYNC_BYPASS at 16#38# range 0 .. 31; + DBG_PADOUT at 16#3C# range 0 .. 31; + DBG_PADOE at 16#40# range 0 .. 31; + DBG_CFGINFO at 16#44# range 0 .. 31; + INSTR_MEM0 at 16#48# range 0 .. 31; + INSTR_MEM1 at 16#4C# range 0 .. 31; + INSTR_MEM2 at 16#50# range 0 .. 31; + INSTR_MEM3 at 16#54# range 0 .. 31; + INSTR_MEM4 at 16#58# range 0 .. 31; + INSTR_MEM5 at 16#5C# range 0 .. 31; + INSTR_MEM6 at 16#60# range 0 .. 31; + INSTR_MEM7 at 16#64# range 0 .. 31; + INSTR_MEM8 at 16#68# range 0 .. 31; + INSTR_MEM9 at 16#6C# range 0 .. 31; + INSTR_MEM10 at 16#70# range 0 .. 31; + INSTR_MEM11 at 16#74# range 0 .. 31; + INSTR_MEM12 at 16#78# range 0 .. 31; + INSTR_MEM13 at 16#7C# range 0 .. 31; + INSTR_MEM14 at 16#80# range 0 .. 31; + INSTR_MEM15 at 16#84# range 0 .. 31; + INSTR_MEM16 at 16#88# range 0 .. 31; + INSTR_MEM17 at 16#8C# range 0 .. 31; + INSTR_MEM18 at 16#90# range 0 .. 31; + INSTR_MEM19 at 16#94# range 0 .. 31; + INSTR_MEM20 at 16#98# range 0 .. 31; + INSTR_MEM21 at 16#9C# range 0 .. 31; + INSTR_MEM22 at 16#A0# range 0 .. 31; + INSTR_MEM23 at 16#A4# range 0 .. 31; + INSTR_MEM24 at 16#A8# range 0 .. 31; + INSTR_MEM25 at 16#AC# range 0 .. 31; + INSTR_MEM26 at 16#B0# range 0 .. 31; + INSTR_MEM27 at 16#B4# range 0 .. 31; + INSTR_MEM28 at 16#B8# range 0 .. 31; + INSTR_MEM29 at 16#BC# range 0 .. 31; + INSTR_MEM30 at 16#C0# range 0 .. 31; + INSTR_MEM31 at 16#C4# range 0 .. 31; + SM0_CLKDIV at 16#C8# range 0 .. 31; + SM0_EXECCTRL at 16#CC# range 0 .. 31; + SM0_SHIFTCTRL at 16#D0# range 0 .. 31; + SM0_ADDR at 16#D4# range 0 .. 31; + SM0_INSTR at 16#D8# range 0 .. 31; + SM0_PINCTRL at 16#DC# range 0 .. 31; + SM1_CLKDIV at 16#E0# range 0 .. 31; + SM1_EXECCTRL at 16#E4# range 0 .. 31; + SM1_SHIFTCTRL at 16#E8# range 0 .. 31; + SM1_ADDR at 16#EC# range 0 .. 31; + SM1_INSTR at 16#F0# range 0 .. 31; + SM1_PINCTRL at 16#F4# range 0 .. 31; + SM2_CLKDIV at 16#F8# range 0 .. 31; + SM2_EXECCTRL at 16#FC# range 0 .. 31; + SM2_SHIFTCTRL at 16#100# range 0 .. 31; + SM2_ADDR at 16#104# range 0 .. 31; + SM2_INSTR at 16#108# range 0 .. 31; + SM2_PINCTRL at 16#10C# range 0 .. 31; + SM3_CLKDIV at 16#110# range 0 .. 31; + SM3_EXECCTRL at 16#114# range 0 .. 31; + SM3_SHIFTCTRL at 16#118# range 0 .. 31; + SM3_ADDR at 16#11C# range 0 .. 31; + SM3_INSTR at 16#120# range 0 .. 31; + SM3_PINCTRL at 16#124# range 0 .. 31; + RXF0_PUTGET0 at 16#128# range 0 .. 31; + RXF0_PUTGET1 at 16#12C# range 0 .. 31; + RXF0_PUTGET2 at 16#130# range 0 .. 31; + RXF0_PUTGET3 at 16#134# range 0 .. 31; + RXF1_PUTGET0 at 16#138# range 0 .. 31; + RXF1_PUTGET1 at 16#13C# range 0 .. 31; + RXF1_PUTGET2 at 16#140# range 0 .. 31; + RXF1_PUTGET3 at 16#144# range 0 .. 31; + RXF2_PUTGET0 at 16#148# range 0 .. 31; + RXF2_PUTGET1 at 16#14C# range 0 .. 31; + RXF2_PUTGET2 at 16#150# range 0 .. 31; + RXF2_PUTGET3 at 16#154# range 0 .. 31; + RXF3_PUTGET0 at 16#158# range 0 .. 31; + RXF3_PUTGET1 at 16#15C# range 0 .. 31; + RXF3_PUTGET2 at 16#160# range 0 .. 31; + RXF3_PUTGET3 at 16#164# range 0 .. 31; + GPIOBASE at 16#168# range 0 .. 31; + INTR at 16#16C# range 0 .. 31; + IRQ0_INTE at 16#170# range 0 .. 31; + IRQ0_INTF at 16#174# range 0 .. 31; + IRQ0_INTS at 16#178# range 0 .. 31; + IRQ1_INTE at 16#17C# range 0 .. 31; + IRQ1_INTF at 16#180# range 0 .. 31; + IRQ1_INTS at 16#184# range 0 .. 31; + end record; + + -- Programmable IO block + PIO1_Periph : aliased PIO1_Peripheral + with Import, Address => PIO1_Base; + +end RP2350_SVD.PIO1; diff --git a/src/svd/rp2350_svd-pio2.ads b/src/svd/rp2350_svd-pio2.ads new file mode 100644 index 0000000..4195c5c --- /dev/null +++ b/src/svd/rp2350_svd-pio2.ads @@ -0,0 +1,2880 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Programmable IO block +package RP2350_SVD.PIO2 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CTRL_SM_ENABLE_Field is HAL.UInt4; + subtype CTRL_SM_RESTART_Field is HAL.UInt4; + subtype CTRL_CLKDIV_RESTART_Field is HAL.UInt4; + subtype CTRL_PREV_PIO_MASK_Field is HAL.UInt4; + subtype CTRL_NEXT_PIO_MASK_Field is HAL.UInt4; + + -- PIO control register + type CTRL_Register is record + -- Enable/disable each of the four state machines by writing 1/0 to each + -- of these four bits. When disabled, a state machine will cease + -- executing instructions, except those written directly to SMx_INSTR by + -- the system. Multiple bits can be set/cleared at once to run/halt + -- multiple state machines simultaneously. + SM_ENABLE : CTRL_SM_ENABLE_Field := 16#0#; + -- Write-only. Write 1 to instantly clear internal SM state which may be + -- otherwise difficult to access and will affect future execution. + -- Specifically, the following are cleared: input and output shift + -- counters; the contents of the input shift register; the delay + -- counter; the waiting-on-IRQ state; any stalled instruction written to + -- SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to + -- OUT_STICKY. The contents of the output shift register and the X/Y + -- scratch registers are not affected. + SM_RESTART : CTRL_SM_RESTART_Field := 16#0#; + -- Write-only. Restart a state machine's clock divider from an initial + -- phase of 0. Clock dividers are free-running, so once started, their + -- output (including fractional jitter) is completely determined by the + -- integer/fractional divisor configured in SMx_CLKDIV. This means that, + -- if multiple clock dividers with the same divisor are restarted + -- simultaneously, by writing multiple 1 bits to this field, the + -- execution clocks of those state machines will run in precise + -- lockstep. Note that setting/clearing SM_ENABLE does not stop the + -- clock divider from running, so once multiple state machines' clocks + -- are synchronised, it is safe to disable/reenable a state machine, + -- whilst keeping the clock dividers in sync. Note also that + -- CLKDIV_RESTART can be written to whilst the state machine is running, + -- and this is useful to resynchronise clock dividers after the divisors + -- (SMx_CLKDIV) have been changed on-the-fly. + CLKDIV_RESTART : CTRL_CLKDIV_RESTART_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- lower-numbered PIO block in the system (or the highest-numbered PIO + -- block if this is PIO block 0) to which to apply the operations + -- specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same + -- write. This allows state machines in a neighbouring PIO block to be + -- started/stopped/clock-synced exactly simultaneously with a write to + -- this PIO block's CTRL register. Neighbouring PIO blocks are + -- disconnected (status signals tied to 0 and control signals ignored) + -- if one block is accessible to NonSecure code, and one is not. + PREV_PIO_MASK : CTRL_PREV_PIO_MASK_Field := 16#0#; + -- Write-only. A mask of state machines in the neighbouring + -- higher-numbered PIO block in the system (or PIO block 0 if this is + -- the highest-numbered PIO block) to which to apply the operations + -- specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and + -- NEXTPREV_SM_DISABLE in the same write. This allows state machines in + -- a neighbouring PIO block to be started/stopped/clock-synced exactly + -- simultaneously with a write to this PIO block's CTRL register. Note + -- that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK + -- actually indicate the same PIO block. In this case the effects are + -- applied cumulatively (as though the masks were OR'd together). + -- Neighbouring PIO blocks are disconnected (status signals tied to 0 + -- and control signals ignored) if one block is accessible to NonSecure + -- code, and one is not. + NEXT_PIO_MASK : CTRL_NEXT_PIO_MASK_Field := 16#0#; + -- Write-only. Write 1 to enable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to setting the corresponding SM_ENABLE bits + -- in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and + -- OTHERS_SM_DISABLE are set, the disable takes precedence. + NEXTPREV_SM_ENABLE : Boolean := False; + -- Write-only. Write 1 to disable state machines in neighbouring PIO + -- blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same + -- write. This is equivalent to clearing the corresponding SM_ENABLE + -- bits in those PIOs' CTRL registers. + NEXTPREV_SM_DISABLE : Boolean := False; + -- Write-only. Write 1 to restart the clock dividers of state machines + -- in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and + -- PREV_PIO_MASK in the same write. This is equivalent to writing 1 to + -- the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + NEXTPREV_CLKDIV_RESTART : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + SM_ENABLE at 0 range 0 .. 3; + SM_RESTART at 0 range 4 .. 7; + CLKDIV_RESTART at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + PREV_PIO_MASK at 0 range 16 .. 19; + NEXT_PIO_MASK at 0 range 20 .. 23; + NEXTPREV_SM_ENABLE at 0 range 24 .. 24; + NEXTPREV_SM_DISABLE at 0 range 25 .. 25; + NEXTPREV_CLKDIV_RESTART at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype FSTAT_RXFULL_Field is HAL.UInt4; + subtype FSTAT_RXEMPTY_Field is HAL.UInt4; + subtype FSTAT_TXFULL_Field is HAL.UInt4; + subtype FSTAT_TXEMPTY_Field is HAL.UInt4; + + -- FIFO status register + type FSTAT_Register is record + -- Read-only. State machine RX FIFO is full + RXFULL : FSTAT_RXFULL_Field; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. State machine RX FIFO is empty + RXEMPTY : FSTAT_RXEMPTY_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. State machine TX FIFO is full + TXFULL : FSTAT_TXFULL_Field; + -- unspecified + Reserved_20_23 : HAL.UInt4; + -- Read-only. State machine TX FIFO is empty + TXEMPTY : FSTAT_TXEMPTY_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FSTAT_Register use record + RXFULL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXEMPTY at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXFULL at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXEMPTY at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FDEBUG_RXSTALL_Field is HAL.UInt4; + subtype FDEBUG_RXUNDER_Field is HAL.UInt4; + subtype FDEBUG_TXOVER_Field is HAL.UInt4; + subtype FDEBUG_TXSTALL_Field is HAL.UInt4; + + -- FIFO debug register + type FDEBUG_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on full RX FIFO during a + -- blocking PUSH, or an IN with autopush enabled. This flag is also set + -- when a nonblocking PUSH to a full FIFO took place, in which case the + -- state machine has dropped data. Write 1 to clear. + RXSTALL : FDEBUG_RXSTALL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. RX FIFO underflow (i.e. read-on-empty by the system) + -- has occurred. Write 1 to clear. Note that read-on-empty does not + -- perturb the state of the FIFO in any way, but the data returned by + -- reading from an empty FIFO is undefined, so this flag generally only + -- becomes set due to some kind of software error. + RXUNDER : FDEBUG_RXUNDER_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. TX FIFO overflow (i.e. write-on-full by the system) has + -- occurred. Write 1 to clear. Note that write-on-full does not alter + -- the state or contents of the FIFO in any way, but the data that the + -- system attempted to write is dropped, so if this flag is set, your + -- software has quite likely dropped some data on the floor. + TXOVER : FDEBUG_TXOVER_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. State machine has stalled on empty TX FIFO during a + -- blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + TXSTALL : FDEBUG_TXSTALL_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FDEBUG_Register use record + RXSTALL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + RXUNDER at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXOVER at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + TXSTALL at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype FLEVEL_TX0_Field is HAL.UInt4; + subtype FLEVEL_RX0_Field is HAL.UInt4; + subtype FLEVEL_TX1_Field is HAL.UInt4; + subtype FLEVEL_RX1_Field is HAL.UInt4; + subtype FLEVEL_TX2_Field is HAL.UInt4; + subtype FLEVEL_RX2_Field is HAL.UInt4; + subtype FLEVEL_TX3_Field is HAL.UInt4; + subtype FLEVEL_RX3_Field is HAL.UInt4; + + -- FIFO levels + type FLEVEL_Register is record + -- Read-only. + TX0 : FLEVEL_TX0_Field; + -- Read-only. + RX0 : FLEVEL_RX0_Field; + -- Read-only. + TX1 : FLEVEL_TX1_Field; + -- Read-only. + RX1 : FLEVEL_RX1_Field; + -- Read-only. + TX2 : FLEVEL_TX2_Field; + -- Read-only. + RX2 : FLEVEL_RX2_Field; + -- Read-only. + TX3 : FLEVEL_TX3_Field; + -- Read-only. + RX3 : FLEVEL_RX3_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FLEVEL_Register use record + TX0 at 0 range 0 .. 3; + RX0 at 0 range 4 .. 7; + TX1 at 0 range 8 .. 11; + RX1 at 0 range 12 .. 15; + TX2 at 0 range 16 .. 19; + RX2 at 0 range 20 .. 23; + TX3 at 0 range 24 .. 27; + RX3 at 0 range 28 .. 31; + end record; + + subtype IRQ_IRQ_Field is HAL.UInt8; + + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by the + -- state machines. There's no fixed association between flags and state + -- machines -- any state machine can use any flag. Any of the eight flags + -- can be used for timing synchronisation between state machines, using IRQ + -- and WAIT instructions. Any combination of the eight flags can also + -- routed out to either of the two system-level interrupt requests, + -- alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + type IRQ_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + IRQ : IRQ_IRQ_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_Register use record + IRQ at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype IRQ_FORCE_IRQ_FORCE_Field is HAL.UInt8; + + -- Writing a 1 to each of these bits will forcibly assert the corresponding + -- IRQ. Note this is different to the INTF register: writing here affects + -- PIO internal state. INTF just asserts the processor-facing IRQ signal + -- for testing ISRs, and is not visible to the state machines. + type IRQ_FORCE_Register is record + -- Write-only. + IRQ_FORCE : IRQ_FORCE_IRQ_FORCE_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ_FORCE_Register use record + IRQ_FORCE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DBG_CFGINFO_FIFO_DEPTH_Field is HAL.UInt6; + subtype DBG_CFGINFO_SM_COUNT_Field is HAL.UInt4; + subtype DBG_CFGINFO_IMEM_SIZE_Field is HAL.UInt6; + + -- Version of the core PIO hardware. + type DBG_CFGINFO_VERSION_Field is + (-- Version 0 (RP2040) + v0, + -- Version 1 (RP2350) + v1) + with Size => 4; + for DBG_CFGINFO_VERSION_Field use + (v0 => 0, + v1 => 1); + + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are also + -- exposed here. + type DBG_CFGINFO_Register is record + -- Read-only. The depth of the state machine TX/RX FIFOs, measured in + -- words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + -- this depth. + FIFO_DEPTH : DBG_CFGINFO_FIFO_DEPTH_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. The number of state machines this PIO instance is equipped + -- with. + SM_COUNT : DBG_CFGINFO_SM_COUNT_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. The size of the instruction memory, measured in units of + -- one instruction + IMEM_SIZE : DBG_CFGINFO_IMEM_SIZE_Field; + -- unspecified + Reserved_22_27 : HAL.UInt6; + -- Read-only. Version of the core PIO hardware. + VERSION : DBG_CFGINFO_VERSION_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBG_CFGINFO_Register use record + FIFO_DEPTH at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SM_COUNT at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + IMEM_SIZE at 0 range 16 .. 21; + Reserved_22_27 at 0 range 22 .. 27; + VERSION at 0 range 28 .. 31; + end record; + + subtype INSTR_MEM0_INSTR_MEM0_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 0 + type INSTR_MEM0_Register is record + -- Write-only. + INSTR_MEM0 : INSTR_MEM0_INSTR_MEM0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM0_Register use record + INSTR_MEM0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM1_INSTR_MEM1_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 1 + type INSTR_MEM1_Register is record + -- Write-only. + INSTR_MEM1 : INSTR_MEM1_INSTR_MEM1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM1_Register use record + INSTR_MEM1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM2_INSTR_MEM2_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 2 + type INSTR_MEM2_Register is record + -- Write-only. + INSTR_MEM2 : INSTR_MEM2_INSTR_MEM2_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM2_Register use record + INSTR_MEM2 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM3_INSTR_MEM3_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 3 + type INSTR_MEM3_Register is record + -- Write-only. + INSTR_MEM3 : INSTR_MEM3_INSTR_MEM3_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM3_Register use record + INSTR_MEM3 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM4_INSTR_MEM4_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 4 + type INSTR_MEM4_Register is record + -- Write-only. + INSTR_MEM4 : INSTR_MEM4_INSTR_MEM4_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM4_Register use record + INSTR_MEM4 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM5_INSTR_MEM5_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 5 + type INSTR_MEM5_Register is record + -- Write-only. + INSTR_MEM5 : INSTR_MEM5_INSTR_MEM5_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM5_Register use record + INSTR_MEM5 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM6_INSTR_MEM6_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 6 + type INSTR_MEM6_Register is record + -- Write-only. + INSTR_MEM6 : INSTR_MEM6_INSTR_MEM6_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM6_Register use record + INSTR_MEM6 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM7_INSTR_MEM7_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 7 + type INSTR_MEM7_Register is record + -- Write-only. + INSTR_MEM7 : INSTR_MEM7_INSTR_MEM7_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM7_Register use record + INSTR_MEM7 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM8_INSTR_MEM8_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 8 + type INSTR_MEM8_Register is record + -- Write-only. + INSTR_MEM8 : INSTR_MEM8_INSTR_MEM8_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM8_Register use record + INSTR_MEM8 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM9_INSTR_MEM9_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 9 + type INSTR_MEM9_Register is record + -- Write-only. + INSTR_MEM9 : INSTR_MEM9_INSTR_MEM9_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM9_Register use record + INSTR_MEM9 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM10_INSTR_MEM10_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 10 + type INSTR_MEM10_Register is record + -- Write-only. + INSTR_MEM10 : INSTR_MEM10_INSTR_MEM10_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM10_Register use record + INSTR_MEM10 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM11_INSTR_MEM11_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 11 + type INSTR_MEM11_Register is record + -- Write-only. + INSTR_MEM11 : INSTR_MEM11_INSTR_MEM11_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM11_Register use record + INSTR_MEM11 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM12_INSTR_MEM12_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 12 + type INSTR_MEM12_Register is record + -- Write-only. + INSTR_MEM12 : INSTR_MEM12_INSTR_MEM12_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM12_Register use record + INSTR_MEM12 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM13_INSTR_MEM13_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 13 + type INSTR_MEM13_Register is record + -- Write-only. + INSTR_MEM13 : INSTR_MEM13_INSTR_MEM13_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM13_Register use record + INSTR_MEM13 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM14_INSTR_MEM14_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 14 + type INSTR_MEM14_Register is record + -- Write-only. + INSTR_MEM14 : INSTR_MEM14_INSTR_MEM14_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM14_Register use record + INSTR_MEM14 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM15_INSTR_MEM15_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 15 + type INSTR_MEM15_Register is record + -- Write-only. + INSTR_MEM15 : INSTR_MEM15_INSTR_MEM15_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM15_Register use record + INSTR_MEM15 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM16_INSTR_MEM16_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 16 + type INSTR_MEM16_Register is record + -- Write-only. + INSTR_MEM16 : INSTR_MEM16_INSTR_MEM16_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM16_Register use record + INSTR_MEM16 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM17_INSTR_MEM17_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 17 + type INSTR_MEM17_Register is record + -- Write-only. + INSTR_MEM17 : INSTR_MEM17_INSTR_MEM17_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM17_Register use record + INSTR_MEM17 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM18_INSTR_MEM18_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 18 + type INSTR_MEM18_Register is record + -- Write-only. + INSTR_MEM18 : INSTR_MEM18_INSTR_MEM18_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM18_Register use record + INSTR_MEM18 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM19_INSTR_MEM19_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 19 + type INSTR_MEM19_Register is record + -- Write-only. + INSTR_MEM19 : INSTR_MEM19_INSTR_MEM19_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM19_Register use record + INSTR_MEM19 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM20_INSTR_MEM20_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 20 + type INSTR_MEM20_Register is record + -- Write-only. + INSTR_MEM20 : INSTR_MEM20_INSTR_MEM20_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM20_Register use record + INSTR_MEM20 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM21_INSTR_MEM21_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 21 + type INSTR_MEM21_Register is record + -- Write-only. + INSTR_MEM21 : INSTR_MEM21_INSTR_MEM21_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM21_Register use record + INSTR_MEM21 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM22_INSTR_MEM22_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 22 + type INSTR_MEM22_Register is record + -- Write-only. + INSTR_MEM22 : INSTR_MEM22_INSTR_MEM22_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM22_Register use record + INSTR_MEM22 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM23_INSTR_MEM23_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 23 + type INSTR_MEM23_Register is record + -- Write-only. + INSTR_MEM23 : INSTR_MEM23_INSTR_MEM23_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM23_Register use record + INSTR_MEM23 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM24_INSTR_MEM24_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 24 + type INSTR_MEM24_Register is record + -- Write-only. + INSTR_MEM24 : INSTR_MEM24_INSTR_MEM24_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM24_Register use record + INSTR_MEM24 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM25_INSTR_MEM25_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 25 + type INSTR_MEM25_Register is record + -- Write-only. + INSTR_MEM25 : INSTR_MEM25_INSTR_MEM25_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM25_Register use record + INSTR_MEM25 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM26_INSTR_MEM26_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 26 + type INSTR_MEM26_Register is record + -- Write-only. + INSTR_MEM26 : INSTR_MEM26_INSTR_MEM26_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM26_Register use record + INSTR_MEM26 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM27_INSTR_MEM27_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 27 + type INSTR_MEM27_Register is record + -- Write-only. + INSTR_MEM27 : INSTR_MEM27_INSTR_MEM27_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM27_Register use record + INSTR_MEM27 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM28_INSTR_MEM28_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 28 + type INSTR_MEM28_Register is record + -- Write-only. + INSTR_MEM28 : INSTR_MEM28_INSTR_MEM28_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM28_Register use record + INSTR_MEM28 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM29_INSTR_MEM29_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 29 + type INSTR_MEM29_Register is record + -- Write-only. + INSTR_MEM29 : INSTR_MEM29_INSTR_MEM29_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM29_Register use record + INSTR_MEM29 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM30_INSTR_MEM30_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 30 + type INSTR_MEM30_Register is record + -- Write-only. + INSTR_MEM30 : INSTR_MEM30_INSTR_MEM30_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM30_Register use record + INSTR_MEM30 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype INSTR_MEM31_INSTR_MEM31_Field is HAL.UInt16; + + -- Write-only access to instruction memory location 31 + type INSTR_MEM31_Register is record + -- Write-only. + INSTR_MEM31 : INSTR_MEM31_INSTR_MEM31_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INSTR_MEM31_Register use record + INSTR_MEM31 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM0_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM0_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM0_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM0_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM0_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM0_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM0_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM0_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM0_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM0_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM0_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM0_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 0 + type SM0_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM0_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO2.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM0_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO2.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM0_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM0_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM0_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM0_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM0_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM0_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 0 + type SM0_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM0_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM0_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM0_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM0_ADDR_SM0_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 0 + type SM0_ADDR_Register is record + -- Read-only. + SM0_ADDR : SM0_ADDR_SM0_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_ADDR_Register use record + SM0_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM0_INSTR_SM0_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM0_INSTR_Register is record + SM0_INSTR : SM0_INSTR_SM0_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_INSTR_Register use record + SM0_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM0_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM0_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM0_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM0_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM0_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM0_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM0_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM0_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM0_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM0_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM0_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM0_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM0_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM1_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM1_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM1_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM1_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM1_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM1_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM1_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM1_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM1_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM1_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM1_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM1_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM1_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 1 + type SM1_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM1_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO2.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM1_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO2.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM1_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM1_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM1_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM1_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM1_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM1_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 1 + type SM1_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM1_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM1_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM1_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM1_ADDR_SM1_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 1 + type SM1_ADDR_Register is record + -- Read-only. + SM1_ADDR : SM1_ADDR_SM1_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_ADDR_Register use record + SM1_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM1_INSTR_SM1_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM1_INSTR_Register is record + SM1_INSTR : SM1_INSTR_SM1_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_INSTR_Register use record + SM1_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM1_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM1_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM1_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM1_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM1_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM1_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM1_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM1_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM1_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM1_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM1_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM1_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM1_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM2_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM2_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM2_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM2_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM2_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM2_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM2_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM2_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM2_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM2_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM2_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM2_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM2_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 2 + type SM2_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM2_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO2.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM2_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO2.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM2_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM2_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM2_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM2_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM2_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM2_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 2 + type SM2_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM2_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM2_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM2_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM2_ADDR_SM2_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 2 + type SM2_ADDR_Register is record + -- Read-only. + SM2_ADDR : SM2_ADDR_SM2_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_ADDR_Register use record + SM2_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM2_INSTR_SM2_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM2_INSTR_Register is record + SM2_INSTR : SM2_INSTR_SM2_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_INSTR_Register use record + SM2_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM2_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM2_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM2_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM2_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM2_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM2_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM2_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM2_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM2_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM2_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM2_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM2_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM2_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + subtype SM3_CLKDIV_FRAC_Field is HAL.UInt8; + subtype SM3_CLKDIV_INT_Field is HAL.UInt16; + + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + type SM3_CLKDIV_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Fractional part of clock divisor + FRAC : SM3_CLKDIV_FRAC_Field := 16#0#; + -- Effective frequency is sysclk/(int + frac/256). Value of 0 is + -- interpreted as 65536. If INT is 0, FRAC must also be 0. + INT : SM3_CLKDIV_INT_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_CLKDIV_Register use record + Reserved_0_7 at 0 range 0 .. 7; + FRAC at 0 range 8 .. 15; + INT at 0 range 16 .. 31; + end record; + + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than + -- the current FIFO depth are reserved, and have undefined behaviour. + type SM3_EXECCTRL_STATUS_N_Field is + (-- Index 0-7 of an IRQ flag in this PIO block + IRQ, + -- Index 0-7 of an IRQ flag in the next lower-numbered PIO block + IRQ_PREVPIO, + -- Index 0-7 of an IRQ flag in the next higher-numbered PIO block + IRQ_NEXTPIO) + with Size => 5; + for SM3_EXECCTRL_STATUS_N_Field use + (IRQ => 0, + IRQ_PREVPIO => 8, + IRQ_NEXTPIO => 16); + + -- Comparison used for the MOV x, STATUS instruction. + type SM3_EXECCTRL_STATUS_SEL_Field is + (-- All-ones if TX FIFO level < N, otherwise all-zeroes + TXLEVEL, + -- All-ones if RX FIFO level < N, otherwise all-zeroes + RXLEVEL, + -- All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + IRQ) + with Size => 2; + for SM3_EXECCTRL_STATUS_SEL_Field use + (TXLEVEL => 0, + RXLEVEL => 1, + IRQ => 2); + + subtype SM3_EXECCTRL_WRAP_BOTTOM_Field is HAL.UInt5; + subtype SM3_EXECCTRL_WRAP_TOP_Field is HAL.UInt5; + subtype SM3_EXECCTRL_OUT_EN_SEL_Field is HAL.UInt5; + subtype SM3_EXECCTRL_JMP_PIN_Field is HAL.UInt5; + + -- Execution/behavioural settings for state machine 3 + type SM3_EXECCTRL_Register is record + -- Comparison level or IRQ index for the MOV x, STATUS instruction. If + -- STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater + -- than the current FIFO depth are reserved, and have undefined + -- behaviour. + STATUS_N : SM3_EXECCTRL_STATUS_N_Field := RP2350_SVD.PIO2.IRQ; + -- Comparison used for the MOV x, STATUS instruction. + STATUS_SEL : SM3_EXECCTRL_STATUS_SEL_Field := + RP2350_SVD.PIO2.TXLEVEL; + -- After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM : SM3_EXECCTRL_WRAP_BOTTOM_Field := 16#0#; + -- After reaching this address, execution is wrapped to wrap_bottom. If + -- the instruction is a jump, and the jump condition is true, the jump + -- takes priority. + WRAP_TOP : SM3_EXECCTRL_WRAP_TOP_Field := 16#1F#; + -- Continuously assert the most recent OUT/SET to the pins + OUT_STICKY : Boolean := False; + -- If 1, use a bit of OUT data as an auxiliary write enable When used in + -- conjunction with OUT_STICKY, writes with an enable of 0 will deassert + -- the latest pin write. This can create useful masking/override + -- behaviour due to the priority ordering of state machine pin writes + -- (SM0 < SM1 < ...) + INLINE_OUT_EN : Boolean := False; + -- Which data bit to use for inline OUT enable + OUT_EN_SEL : SM3_EXECCTRL_OUT_EN_SEL_Field := 16#0#; + -- The GPIO number to use as condition for JMP PIN. Unaffected by input + -- mapping. + JMP_PIN : SM3_EXECCTRL_JMP_PIN_Field := 16#0#; + -- If 1, side-set data is asserted to pin directions, instead of pin + -- values + SIDE_PINDIR : Boolean := False; + -- If 1, the MSB of the Delay/Side-set instruction field is used as + -- side-set enable, rather than a side-set data bit. This allows + -- instructions to perform side-set optionally, rather than on every + -- instruction, but the maximum possible side-set width is reduced from + -- 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of + -- this enable bit. + SIDE_EN : Boolean := False; + -- Read-only. If 1, an instruction written to SMx_INSTR is stalled, and + -- latched by the state machine. Will clear to 0 once this instruction + -- completes. + EXEC_STALLED : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_EXECCTRL_Register use record + STATUS_N at 0 range 0 .. 4; + STATUS_SEL at 0 range 5 .. 6; + WRAP_BOTTOM at 0 range 7 .. 11; + WRAP_TOP at 0 range 12 .. 16; + OUT_STICKY at 0 range 17 .. 17; + INLINE_OUT_EN at 0 range 18 .. 18; + OUT_EN_SEL at 0 range 19 .. 23; + JMP_PIN at 0 range 24 .. 28; + SIDE_PINDIR at 0 range 29 .. 29; + SIDE_EN at 0 range 30 .. 30; + EXEC_STALLED at 0 range 31 .. 31; + end record; + + subtype SM3_SHIFTCTRL_IN_COUNT_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PUSH_THRESH_Field is HAL.UInt5; + subtype SM3_SHIFTCTRL_PULL_THRESH_Field is HAL.UInt5; + + -- Control behaviour of the input/output shift registers for state machine + -- 3 + type SM3_SHIFTCTRL_Register is record + -- Set the number of pins which are not masked to 0 when read by an IN + -- PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT + -- of 5 means that the 5 LSBs of the IN pin group are visible (bits + -- 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is + -- encoded with a field value of 0, so the default behaviour is to not + -- perform any masking. Note this masking is applied in addition to the + -- masking usually performed by the IN instruction. This is mainly + -- useful for the MOV x, PINS instruction, which otherwise has no way of + -- masking pins. + IN_COUNT : SM3_SHIFTCTRL_IN_COUNT_Field := 16#0#; + -- unspecified + Reserved_5_13 : HAL.UInt9 := 16#0#; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random read access by the state machine (using the + -- `get` instruction) and, unless FJOIN_RX_PUT is also set, random write + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_GET : Boolean := False; + -- If 1, disable this state machine's RX FIFO, make its storage + -- available for random write access by the state machine (using the + -- `put` instruction) and, unless FJOIN_RX_GET is also set, random read + -- access by the processor (through the RXFx_PUTGETy registers). If + -- FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's + -- registers can be randomly read/written by the state machine, but are + -- completely inaccessible to the processor. Setting this bit will clear + -- the FJOIN_TX and FJOIN_RX bits. + FJOIN_RX_PUT : Boolean := False; + -- Push automatically when the input shift register is filled, i.e. on + -- an IN instruction which causes the input shift counter to reach or + -- exceed PUSH_THRESH. + AUTOPUSH : Boolean := False; + -- Pull automatically when the output shift register is emptied, i.e. on + -- or following an OUT instruction which causes the output shift counter + -- to reach or exceed PULL_THRESH. + AUTOPULL : Boolean := False; + -- 1 = shift input shift register to right (data enters from left). 0 = + -- to left. + IN_SHIFTDIR : Boolean := True; + -- 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR : Boolean := True; + -- Number of bits shifted into ISR before autopush, or conditional push + -- (PUSH IFFULL), will take place. Write 0 for value of 32. + PUSH_THRESH : SM3_SHIFTCTRL_PUSH_THRESH_Field := 16#0#; + -- Number of bits shifted out of OSR before autopull, or conditional + -- pull (PULL IFEMPTY), will take place. Write 0 for value of 32. + PULL_THRESH : SM3_SHIFTCTRL_PULL_THRESH_Field := 16#0#; + -- When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as + -- deep. RX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_TX : Boolean := False; + -- When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as + -- deep. TX FIFO is disabled as a result (always reads as both full and + -- empty). FIFOs are flushed when this bit is changed. + FJOIN_RX : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_SHIFTCTRL_Register use record + IN_COUNT at 0 range 0 .. 4; + Reserved_5_13 at 0 range 5 .. 13; + FJOIN_RX_GET at 0 range 14 .. 14; + FJOIN_RX_PUT at 0 range 15 .. 15; + AUTOPUSH at 0 range 16 .. 16; + AUTOPULL at 0 range 17 .. 17; + IN_SHIFTDIR at 0 range 18 .. 18; + OUT_SHIFTDIR at 0 range 19 .. 19; + PUSH_THRESH at 0 range 20 .. 24; + PULL_THRESH at 0 range 25 .. 29; + FJOIN_TX at 0 range 30 .. 30; + FJOIN_RX at 0 range 31 .. 31; + end record; + + subtype SM3_ADDR_SM3_ADDR_Field is HAL.UInt5; + + -- Current instruction address of state machine 3 + type SM3_ADDR_Register is record + -- Read-only. + SM3_ADDR : SM3_ADDR_SM3_ADDR_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_ADDR_Register use record + SM3_ADDR at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype SM3_INSTR_SM3_INSTR_Field is HAL.UInt16; + + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately (including + -- jumps) and then resume execution. + type SM3_INSTR_Register is record + SM3_INSTR : SM3_INSTR_SM3_INSTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_INSTR_Register use record + SM3_INSTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SM3_PINCTRL_OUT_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_SIDESET_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_IN_BASE_Field is HAL.UInt5; + subtype SM3_PINCTRL_OUT_COUNT_Field is HAL.UInt6; + subtype SM3_PINCTRL_SET_COUNT_Field is HAL.UInt3; + subtype SM3_PINCTRL_SIDESET_COUNT_Field is HAL.UInt3; + + -- State machine pin control + type SM3_PINCTRL_Register is record + -- The lowest-numbered pin that will be affected by an OUT PINS, OUT + -- PINDIRS or MOV PINS instruction. The data written to this pin will + -- always be the least-significant bit of the OUT or MOV data. + OUT_BASE : SM3_PINCTRL_OUT_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a SET PINS or SET + -- PINDIRS instruction. The data written to this pin is the + -- least-significant bit of the SET data. + SET_BASE : SM3_PINCTRL_SET_BASE_Field := 16#0#; + -- The lowest-numbered pin that will be affected by a side-set + -- operation. The MSBs of an instruction's side-set/delay field (up to + -- 5, determined by SIDESET_COUNT) are used for side-set data, with the + -- remaining LSBs used for delay. The least-significant bit of the + -- side-set portion is the bit written to this pin, with + -- more-significant bits written to higher-numbered pins. + SIDESET_BASE : SM3_PINCTRL_SIDESET_BASE_Field := 16#0#; + -- The pin which is mapped to the least-significant bit of a state + -- machine's IN data bus. Higher-numbered pins are mapped to + -- consecutively more-significant data bits, with a modulo of 32 applied + -- to pin number. + IN_BASE : SM3_PINCTRL_IN_BASE_Field := 16#0#; + -- The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS + -- instruction. In the range 0 to 32 inclusive. + OUT_COUNT : SM3_PINCTRL_OUT_COUNT_Field := 16#0#; + -- The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT : SM3_PINCTRL_SET_COUNT_Field := 16#5#; + -- The number of MSBs of the Delay/Side-set instruction field which are + -- used for side-set. Inclusive of the enable bit, if present. Minimum + -- of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no + -- delay). + SIDESET_COUNT : SM3_PINCTRL_SIDESET_COUNT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM3_PINCTRL_Register use record + OUT_BASE at 0 range 0 .. 4; + SET_BASE at 0 range 5 .. 9; + SIDESET_BASE at 0 range 10 .. 14; + IN_BASE at 0 range 15 .. 19; + OUT_COUNT at 0 range 20 .. 25; + SET_COUNT at 0 range 26 .. 28; + SIDESET_COUNT at 0 range 29 .. 31; + end record; + + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, + -- to access more than 32 GPIOs from PIO. Only the values 0 and 16 are + -- supported (only bit 4 is writable). + type GPIOBASE_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + GPIOBASE : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIOBASE_Register use record + Reserved_0_3 at 0 range 0 .. 3; + GPIOBASE at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- INTR_SM array + type INTR_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for INTR_SM + type INTR_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : INTR_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for INTR_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : INTR_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTE_SM array + type IRQ0_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTE_SM + type IRQ0_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq0 + type IRQ0_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTF_SM array + type IRQ0_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTF_SM + type IRQ0_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq0 + type IRQ0_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ0_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ0_INTS_SM array + type IRQ0_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ0_INTS_SM + type IRQ0_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ0_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ0_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq0 + type IRQ0_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ0_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTE_SM array + type IRQ1_INTE_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTE_SM + type IRQ1_INTE_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTE_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTE_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Enable for irq1 + type IRQ1_INTE_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTE_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTE_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTF_SM array + type IRQ1_INTF_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTF_SM + type IRQ1_INTF_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTF_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTF_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt Force for irq1 + type IRQ1_INTF_Register is record + SM0_RXNEMPTY : Boolean := False; + SM1_RXNEMPTY : Boolean := False; + SM2_RXNEMPTY : Boolean := False; + SM3_RXNEMPTY : Boolean := False; + SM0_TXNFULL : Boolean := False; + SM1_TXNFULL : Boolean := False; + SM2_TXNFULL : Boolean := False; + SM3_TXNFULL : Boolean := False; + SM : IRQ1_INTF_SM_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTF_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- IRQ1_INTS_SM array + type IRQ1_INTS_SM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for IRQ1_INTS_SM + type IRQ1_INTS_SM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SM as a value + Val : HAL.UInt8; + when True => + -- SM as an array + Arr : IRQ1_INTS_SM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for IRQ1_INTS_SM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Interrupt status after masking & forcing for irq1 + type IRQ1_INTS_Register is record + -- Read-only. + SM0_RXNEMPTY : Boolean; + -- Read-only. + SM1_RXNEMPTY : Boolean; + -- Read-only. + SM2_RXNEMPTY : Boolean; + -- Read-only. + SM3_RXNEMPTY : Boolean; + -- Read-only. + SM0_TXNFULL : Boolean; + -- Read-only. + SM1_TXNFULL : Boolean; + -- Read-only. + SM2_TXNFULL : Boolean; + -- Read-only. + SM3_TXNFULL : Boolean; + -- Read-only. + SM : IRQ1_INTS_SM_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTS_Register use record + SM0_RXNEMPTY at 0 range 0 .. 0; + SM1_RXNEMPTY at 0 range 1 .. 1; + SM2_RXNEMPTY at 0 range 2 .. 2; + SM3_RXNEMPTY at 0 range 3 .. 3; + SM0_TXNFULL at 0 range 4 .. 4; + SM1_TXNFULL at 0 range 5 .. 5; + SM2_TXNFULL at 0 range 6 .. 6; + SM3_TXNFULL at 0 range 7 .. 7; + SM at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Programmable IO block + type PIO2_Peripheral is record + -- PIO control register + CTRL : aliased CTRL_Register; + -- FIFO status register + FSTAT : aliased FSTAT_Register; + -- FIFO debug register + FDEBUG : aliased FDEBUG_Register; + -- FIFO levels + FLEVEL : aliased FLEVEL_Register; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF0 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF1 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF2 : aliased HAL.UInt32; + -- Direct write access to the TX FIFO for this state machine. Each write + -- pushes one word to the FIFO. Attempting to write to a full FIFO has + -- no effect on the FIFO state or contents, and sets the sticky + -- FDEBUG_TXOVER error flag for this FIFO. + TXF3 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF0 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF1 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF2 : aliased HAL.UInt32; + -- Direct read access to the RX FIFO for this state machine. Each read + -- pops one word from the FIFO. Attempting to read from an empty FIFO + -- has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER + -- error flag for this FIFO. The data returned to the system on a read + -- from an empty FIFO is undefined. + RXF3 : aliased HAL.UInt32; + -- State machine IRQ flags register. Write 1 to clear. There are eight + -- state machine IRQ flags, which can be set, cleared, and waited on by + -- the state machines. There's no fixed association between flags and + -- state machines -- any state machine can use any flag. Any of the + -- eight flags can be used for timing synchronisation between state + -- machines, using IRQ and WAIT instructions. Any combination of the + -- eight flags can also routed out to either of the two system-level + -- interrupt requests, alongside FIFO status interrupts -- see e.g. + -- IRQ0_INTE. + IRQ : aliased IRQ_Register; + -- Writing a 1 to each of these bits will forcibly assert the + -- corresponding IRQ. Note this is different to the INTF register: + -- writing here affects PIO internal state. INTF just asserts the + -- processor-facing IRQ signal for testing ISRs, and is not visible to + -- the state machines. + IRQ_FORCE : aliased IRQ_FORCE_Register; + -- There is a 2-flipflop synchronizer on each GPIO input, which protects + -- PIO logic from metastabilities. This increases input delay, and for + -- fast synchronous IO (e.g. SPI) these synchronizers may need to be + -- bypassed. Each bit in this register corresponds to one GPIO. 0 -> + -- input is synchronized (default) 1 -> synchronizer is bypassed If in + -- doubt, leave this register as all zeroes. + INPUT_SYNC_BYPASS : aliased HAL.UInt32; + -- Read to sample the pad output values PIO is currently driving to the + -- GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits + -- are hardwired to 0. + DBG_PADOUT : aliased HAL.UInt32; + -- Read to sample the pad output enables (direction) PIO is currently + -- driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most + -- significant bits are hardwired to 0. + DBG_PADOE : aliased HAL.UInt32; + -- The PIO hardware has some free parameters that may vary between chip + -- products. These should be provided in the chip datasheet, but are + -- also exposed here. + DBG_CFGINFO : aliased DBG_CFGINFO_Register; + -- Write-only access to instruction memory location 0 + INSTR_MEM0 : aliased INSTR_MEM0_Register; + -- Write-only access to instruction memory location 1 + INSTR_MEM1 : aliased INSTR_MEM1_Register; + -- Write-only access to instruction memory location 2 + INSTR_MEM2 : aliased INSTR_MEM2_Register; + -- Write-only access to instruction memory location 3 + INSTR_MEM3 : aliased INSTR_MEM3_Register; + -- Write-only access to instruction memory location 4 + INSTR_MEM4 : aliased INSTR_MEM4_Register; + -- Write-only access to instruction memory location 5 + INSTR_MEM5 : aliased INSTR_MEM5_Register; + -- Write-only access to instruction memory location 6 + INSTR_MEM6 : aliased INSTR_MEM6_Register; + -- Write-only access to instruction memory location 7 + INSTR_MEM7 : aliased INSTR_MEM7_Register; + -- Write-only access to instruction memory location 8 + INSTR_MEM8 : aliased INSTR_MEM8_Register; + -- Write-only access to instruction memory location 9 + INSTR_MEM9 : aliased INSTR_MEM9_Register; + -- Write-only access to instruction memory location 10 + INSTR_MEM10 : aliased INSTR_MEM10_Register; + -- Write-only access to instruction memory location 11 + INSTR_MEM11 : aliased INSTR_MEM11_Register; + -- Write-only access to instruction memory location 12 + INSTR_MEM12 : aliased INSTR_MEM12_Register; + -- Write-only access to instruction memory location 13 + INSTR_MEM13 : aliased INSTR_MEM13_Register; + -- Write-only access to instruction memory location 14 + INSTR_MEM14 : aliased INSTR_MEM14_Register; + -- Write-only access to instruction memory location 15 + INSTR_MEM15 : aliased INSTR_MEM15_Register; + -- Write-only access to instruction memory location 16 + INSTR_MEM16 : aliased INSTR_MEM16_Register; + -- Write-only access to instruction memory location 17 + INSTR_MEM17 : aliased INSTR_MEM17_Register; + -- Write-only access to instruction memory location 18 + INSTR_MEM18 : aliased INSTR_MEM18_Register; + -- Write-only access to instruction memory location 19 + INSTR_MEM19 : aliased INSTR_MEM19_Register; + -- Write-only access to instruction memory location 20 + INSTR_MEM20 : aliased INSTR_MEM20_Register; + -- Write-only access to instruction memory location 21 + INSTR_MEM21 : aliased INSTR_MEM21_Register; + -- Write-only access to instruction memory location 22 + INSTR_MEM22 : aliased INSTR_MEM22_Register; + -- Write-only access to instruction memory location 23 + INSTR_MEM23 : aliased INSTR_MEM23_Register; + -- Write-only access to instruction memory location 24 + INSTR_MEM24 : aliased INSTR_MEM24_Register; + -- Write-only access to instruction memory location 25 + INSTR_MEM25 : aliased INSTR_MEM25_Register; + -- Write-only access to instruction memory location 26 + INSTR_MEM26 : aliased INSTR_MEM26_Register; + -- Write-only access to instruction memory location 27 + INSTR_MEM27 : aliased INSTR_MEM27_Register; + -- Write-only access to instruction memory location 28 + INSTR_MEM28 : aliased INSTR_MEM28_Register; + -- Write-only access to instruction memory location 29 + INSTR_MEM29 : aliased INSTR_MEM29_Register; + -- Write-only access to instruction memory location 30 + INSTR_MEM30 : aliased INSTR_MEM30_Register; + -- Write-only access to instruction memory location 31 + INSTR_MEM31 : aliased INSTR_MEM31_Register; + -- Clock divisor register for state machine 0 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM0_CLKDIV : aliased SM0_CLKDIV_Register; + -- Execution/behavioural settings for state machine 0 + SM0_EXECCTRL : aliased SM0_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 0 + SM0_SHIFTCTRL : aliased SM0_SHIFTCTRL_Register; + -- Current instruction address of state machine 0 + SM0_ADDR : aliased SM0_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 0's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM0_INSTR : aliased SM0_INSTR_Register; + -- State machine pin control + SM0_PINCTRL : aliased SM0_PINCTRL_Register; + -- Clock divisor register for state machine 1 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM1_CLKDIV : aliased SM1_CLKDIV_Register; + -- Execution/behavioural settings for state machine 1 + SM1_EXECCTRL : aliased SM1_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 1 + SM1_SHIFTCTRL : aliased SM1_SHIFTCTRL_Register; + -- Current instruction address of state machine 1 + SM1_ADDR : aliased SM1_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 1's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM1_INSTR : aliased SM1_INSTR_Register; + -- State machine pin control + SM1_PINCTRL : aliased SM1_PINCTRL_Register; + -- Clock divisor register for state machine 2 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM2_CLKDIV : aliased SM2_CLKDIV_Register; + -- Execution/behavioural settings for state machine 2 + SM2_EXECCTRL : aliased SM2_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 2 + SM2_SHIFTCTRL : aliased SM2_SHIFTCTRL_Register; + -- Current instruction address of state machine 2 + SM2_ADDR : aliased SM2_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 2's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM2_INSTR : aliased SM2_INSTR_Register; + -- State machine pin control + SM2_PINCTRL : aliased SM2_PINCTRL_Register; + -- Clock divisor register for state machine 3 Frequency = clock freq / + -- (CLKDIV_INT + CLKDIV_FRAC / 256) + SM3_CLKDIV : aliased SM3_CLKDIV_Register; + -- Execution/behavioural settings for state machine 3 + SM3_EXECCTRL : aliased SM3_EXECCTRL_Register; + -- Control behaviour of the input/output shift registers for state + -- machine 3 + SM3_SHIFTCTRL : aliased SM3_SHIFTCTRL_Register; + -- Current instruction address of state machine 3 + SM3_ADDR : aliased SM3_ADDR_Register; + -- Read to see the instruction currently addressed by state machine 3's + -- program counter Write to execute an instruction immediately + -- (including jumps) and then resume execution. + SM3_INSTR : aliased SM3_INSTR_Register; + -- State machine pin control + SM3_PINCTRL : aliased SM3_PINCTRL_Register; + -- Direct read/write access to entry 0 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM0's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF0_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM1's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF1_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM2's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF2_PUTGET3 : aliased HAL.UInt32; + -- Direct read/write access to entry 0 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET0 : aliased HAL.UInt32; + -- Direct read/write access to entry 1 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET1 : aliased HAL.UInt32; + -- Direct read/write access to entry 2 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET2 : aliased HAL.UInt32; + -- Direct read/write access to entry 3 of SM3's RX FIFO, if + -- SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + RXF3_PUTGET3 : aliased HAL.UInt32; + -- Relocate GPIO 0 (from PIO's point of view) in the system GPIO + -- numbering, to access more than 32 GPIOs from PIO. Only the values 0 + -- and 16 are supported (only bit 4 is writable). + GPIOBASE : aliased GPIOBASE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable for irq0 + IRQ0_INTE : aliased IRQ0_INTE_Register; + -- Interrupt Force for irq0 + IRQ0_INTF : aliased IRQ0_INTF_Register; + -- Interrupt status after masking & forcing for irq0 + IRQ0_INTS : aliased IRQ0_INTS_Register; + -- Interrupt Enable for irq1 + IRQ1_INTE : aliased IRQ1_INTE_Register; + -- Interrupt Force for irq1 + IRQ1_INTF : aliased IRQ1_INTF_Register; + -- Interrupt status after masking & forcing for irq1 + IRQ1_INTS : aliased IRQ1_INTS_Register; + end record + with Volatile; + + for PIO2_Peripheral use record + CTRL at 16#0# range 0 .. 31; + FSTAT at 16#4# range 0 .. 31; + FDEBUG at 16#8# range 0 .. 31; + FLEVEL at 16#C# range 0 .. 31; + TXF0 at 16#10# range 0 .. 31; + TXF1 at 16#14# range 0 .. 31; + TXF2 at 16#18# range 0 .. 31; + TXF3 at 16#1C# range 0 .. 31; + RXF0 at 16#20# range 0 .. 31; + RXF1 at 16#24# range 0 .. 31; + RXF2 at 16#28# range 0 .. 31; + RXF3 at 16#2C# range 0 .. 31; + IRQ at 16#30# range 0 .. 31; + IRQ_FORCE at 16#34# range 0 .. 31; + INPUT_SYNC_BYPASS at 16#38# range 0 .. 31; + DBG_PADOUT at 16#3C# range 0 .. 31; + DBG_PADOE at 16#40# range 0 .. 31; + DBG_CFGINFO at 16#44# range 0 .. 31; + INSTR_MEM0 at 16#48# range 0 .. 31; + INSTR_MEM1 at 16#4C# range 0 .. 31; + INSTR_MEM2 at 16#50# range 0 .. 31; + INSTR_MEM3 at 16#54# range 0 .. 31; + INSTR_MEM4 at 16#58# range 0 .. 31; + INSTR_MEM5 at 16#5C# range 0 .. 31; + INSTR_MEM6 at 16#60# range 0 .. 31; + INSTR_MEM7 at 16#64# range 0 .. 31; + INSTR_MEM8 at 16#68# range 0 .. 31; + INSTR_MEM9 at 16#6C# range 0 .. 31; + INSTR_MEM10 at 16#70# range 0 .. 31; + INSTR_MEM11 at 16#74# range 0 .. 31; + INSTR_MEM12 at 16#78# range 0 .. 31; + INSTR_MEM13 at 16#7C# range 0 .. 31; + INSTR_MEM14 at 16#80# range 0 .. 31; + INSTR_MEM15 at 16#84# range 0 .. 31; + INSTR_MEM16 at 16#88# range 0 .. 31; + INSTR_MEM17 at 16#8C# range 0 .. 31; + INSTR_MEM18 at 16#90# range 0 .. 31; + INSTR_MEM19 at 16#94# range 0 .. 31; + INSTR_MEM20 at 16#98# range 0 .. 31; + INSTR_MEM21 at 16#9C# range 0 .. 31; + INSTR_MEM22 at 16#A0# range 0 .. 31; + INSTR_MEM23 at 16#A4# range 0 .. 31; + INSTR_MEM24 at 16#A8# range 0 .. 31; + INSTR_MEM25 at 16#AC# range 0 .. 31; + INSTR_MEM26 at 16#B0# range 0 .. 31; + INSTR_MEM27 at 16#B4# range 0 .. 31; + INSTR_MEM28 at 16#B8# range 0 .. 31; + INSTR_MEM29 at 16#BC# range 0 .. 31; + INSTR_MEM30 at 16#C0# range 0 .. 31; + INSTR_MEM31 at 16#C4# range 0 .. 31; + SM0_CLKDIV at 16#C8# range 0 .. 31; + SM0_EXECCTRL at 16#CC# range 0 .. 31; + SM0_SHIFTCTRL at 16#D0# range 0 .. 31; + SM0_ADDR at 16#D4# range 0 .. 31; + SM0_INSTR at 16#D8# range 0 .. 31; + SM0_PINCTRL at 16#DC# range 0 .. 31; + SM1_CLKDIV at 16#E0# range 0 .. 31; + SM1_EXECCTRL at 16#E4# range 0 .. 31; + SM1_SHIFTCTRL at 16#E8# range 0 .. 31; + SM1_ADDR at 16#EC# range 0 .. 31; + SM1_INSTR at 16#F0# range 0 .. 31; + SM1_PINCTRL at 16#F4# range 0 .. 31; + SM2_CLKDIV at 16#F8# range 0 .. 31; + SM2_EXECCTRL at 16#FC# range 0 .. 31; + SM2_SHIFTCTRL at 16#100# range 0 .. 31; + SM2_ADDR at 16#104# range 0 .. 31; + SM2_INSTR at 16#108# range 0 .. 31; + SM2_PINCTRL at 16#10C# range 0 .. 31; + SM3_CLKDIV at 16#110# range 0 .. 31; + SM3_EXECCTRL at 16#114# range 0 .. 31; + SM3_SHIFTCTRL at 16#118# range 0 .. 31; + SM3_ADDR at 16#11C# range 0 .. 31; + SM3_INSTR at 16#120# range 0 .. 31; + SM3_PINCTRL at 16#124# range 0 .. 31; + RXF0_PUTGET0 at 16#128# range 0 .. 31; + RXF0_PUTGET1 at 16#12C# range 0 .. 31; + RXF0_PUTGET2 at 16#130# range 0 .. 31; + RXF0_PUTGET3 at 16#134# range 0 .. 31; + RXF1_PUTGET0 at 16#138# range 0 .. 31; + RXF1_PUTGET1 at 16#13C# range 0 .. 31; + RXF1_PUTGET2 at 16#140# range 0 .. 31; + RXF1_PUTGET3 at 16#144# range 0 .. 31; + RXF2_PUTGET0 at 16#148# range 0 .. 31; + RXF2_PUTGET1 at 16#14C# range 0 .. 31; + RXF2_PUTGET2 at 16#150# range 0 .. 31; + RXF2_PUTGET3 at 16#154# range 0 .. 31; + RXF3_PUTGET0 at 16#158# range 0 .. 31; + RXF3_PUTGET1 at 16#15C# range 0 .. 31; + RXF3_PUTGET2 at 16#160# range 0 .. 31; + RXF3_PUTGET3 at 16#164# range 0 .. 31; + GPIOBASE at 16#168# range 0 .. 31; + INTR at 16#16C# range 0 .. 31; + IRQ0_INTE at 16#170# range 0 .. 31; + IRQ0_INTF at 16#174# range 0 .. 31; + IRQ0_INTS at 16#178# range 0 .. 31; + IRQ1_INTE at 16#17C# range 0 .. 31; + IRQ1_INTF at 16#180# range 0 .. 31; + IRQ1_INTS at 16#184# range 0 .. 31; + end record; + + -- Programmable IO block + PIO2_Periph : aliased PIO2_Peripheral + with Import, Address => PIO2_Base; + +end RP2350_SVD.PIO2; diff --git a/src/svd/rp2350_svd-pll_sys.ads b/src/svd/rp2350_svd-pll_sys.ads new file mode 100644 index 0000000..0d06894 --- /dev/null +++ b/src/svd/rp2350_svd-pll_sys.ads @@ -0,0 +1,236 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.PLL_SYS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CS_REFDIV_Field is HAL.UInt6; + + -- Control and Status GENERAL CONSTRAINTS: Reference clock frequency + -- min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency + -- min=750MHz, max=1600MHz + type CS_Register is record + -- Divides the PLL input reference clock. Behaviour is undefined for + -- div=0. PLL output will be unpredictable during refdiv changes, wait + -- for lock=1 before using it. + REFDIV : CS_REFDIV_Field := 16#1#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Passes the reference clock to the output instead of the divided VCO. + -- The VCO continues to run so the user can switch between the reference + -- clock and the divided VCO but the output will glitch when doing so. + BYPASS : Boolean := False; + -- unspecified + Reserved_9_29 : HAL.UInt21 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. PLL is not locked Ideally this is cleared when PLL lock + -- is seen and this should never normally be set + LOCK_N : Boolean := False; + -- Read-only. PLL is locked + LOCK : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CS_Register use record + REFDIV at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + BYPASS at 0 range 8 .. 8; + Reserved_9_29 at 0 range 9 .. 29; + LOCK_N at 0 range 30 .. 30; + LOCK at 0 range 31 .. 31; + end record; + + -- Controls the PLL power modes. + type PWR_Register is record + -- PLL powerdown To save power set high when PLL output not required. + PD : Boolean := True; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- PLL DSM powerdown Nothing is achieved by setting this low. + DSMPD : Boolean := True; + -- PLL post divider powerdown To save power set high when PLL output not + -- required or bypass=1. + POSTDIVPD : Boolean := True; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- PLL VCO powerdown To save power set high when PLL output not required + -- or bypass=1. + VCOPD : Boolean := True; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PWR_Register use record + PD at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DSMPD at 0 range 2 .. 2; + POSTDIVPD at 0 range 3 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + VCOPD at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype FBDIV_INT_FBDIV_INT_Field is HAL.UInt12; + + -- Feedback divisor (note: this PLL does not support fractional division) + type FBDIV_INT_Register is record + -- see ctrl reg description for constraints + FBDIV_INT : FBDIV_INT_FBDIV_INT_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FBDIV_INT_Register use record + FBDIV_INT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype PRIM_POSTDIV2_Field is HAL.UInt3; + subtype PRIM_POSTDIV1_Field is HAL.UInt3; + + -- Controls the PLL post dividers for the primary output (note: this PLL + -- does not have a secondary output) the primary output is driven from VCO + -- divided by postdiv1*postdiv2 + type PRIM_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12 := 16#0#; + -- divide by 1-7 + POSTDIV2 : PRIM_POSTDIV2_Field := 16#7#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- divide by 1-7 + POSTDIV1 : PRIM_POSTDIV1_Field := 16#7#; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRIM_Register use record + Reserved_0_11 at 0 range 0 .. 11; + POSTDIV2 at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + POSTDIV1 at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + LOCK_N_STICKY : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type PLL_SYS_Peripheral is record + -- Control and Status GENERAL CONSTRAINTS: Reference clock frequency + -- min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency + -- min=750MHz, max=1600MHz + CS : aliased CS_Register; + -- Controls the PLL power modes. + PWR : aliased PWR_Register; + -- Feedback divisor (note: this PLL does not support fractional + -- division) + FBDIV_INT : aliased FBDIV_INT_Register; + -- Controls the PLL post dividers for the primary output (note: this PLL + -- does not have a secondary output) the primary output is driven from + -- VCO divided by postdiv1*postdiv2 + PRIM : aliased PRIM_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for PLL_SYS_Peripheral use record + CS at 16#0# range 0 .. 31; + PWR at 16#4# range 0 .. 31; + FBDIV_INT at 16#8# range 0 .. 31; + PRIM at 16#C# range 0 .. 31; + INTR at 16#10# range 0 .. 31; + INTE at 16#14# range 0 .. 31; + INTF at 16#18# range 0 .. 31; + INTS at 16#1C# range 0 .. 31; + end record; + + PLL_SYS_Periph : aliased PLL_SYS_Peripheral + with Import, Address => PLL_SYS_Base; + +end RP2350_SVD.PLL_SYS; diff --git a/src/svd/rp2350_svd-pll_usb.ads b/src/svd/rp2350_svd-pll_usb.ads new file mode 100644 index 0000000..f1efb23 --- /dev/null +++ b/src/svd/rp2350_svd-pll_usb.ads @@ -0,0 +1,236 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.PLL_USB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CS_REFDIV_Field is HAL.UInt6; + + -- Control and Status GENERAL CONSTRAINTS: Reference clock frequency + -- min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency + -- min=750MHz, max=1600MHz + type CS_Register is record + -- Divides the PLL input reference clock. Behaviour is undefined for + -- div=0. PLL output will be unpredictable during refdiv changes, wait + -- for lock=1 before using it. + REFDIV : CS_REFDIV_Field := 16#1#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Passes the reference clock to the output instead of the divided VCO. + -- The VCO continues to run so the user can switch between the reference + -- clock and the divided VCO but the output will glitch when doing so. + BYPASS : Boolean := False; + -- unspecified + Reserved_9_29 : HAL.UInt21 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. PLL is not locked Ideally this is cleared when PLL lock + -- is seen and this should never normally be set + LOCK_N : Boolean := False; + -- Read-only. PLL is locked + LOCK : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CS_Register use record + REFDIV at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + BYPASS at 0 range 8 .. 8; + Reserved_9_29 at 0 range 9 .. 29; + LOCK_N at 0 range 30 .. 30; + LOCK at 0 range 31 .. 31; + end record; + + -- Controls the PLL power modes. + type PWR_Register is record + -- PLL powerdown To save power set high when PLL output not required. + PD : Boolean := True; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- PLL DSM powerdown Nothing is achieved by setting this low. + DSMPD : Boolean := True; + -- PLL post divider powerdown To save power set high when PLL output not + -- required or bypass=1. + POSTDIVPD : Boolean := True; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- PLL VCO powerdown To save power set high when PLL output not required + -- or bypass=1. + VCOPD : Boolean := True; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PWR_Register use record + PD at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DSMPD at 0 range 2 .. 2; + POSTDIVPD at 0 range 3 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + VCOPD at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype FBDIV_INT_FBDIV_INT_Field is HAL.UInt12; + + -- Feedback divisor (note: this PLL does not support fractional division) + type FBDIV_INT_Register is record + -- see ctrl reg description for constraints + FBDIV_INT : FBDIV_INT_FBDIV_INT_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FBDIV_INT_Register use record + FBDIV_INT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype PRIM_POSTDIV2_Field is HAL.UInt3; + subtype PRIM_POSTDIV1_Field is HAL.UInt3; + + -- Controls the PLL post dividers for the primary output (note: this PLL + -- does not have a secondary output) the primary output is driven from VCO + -- divided by postdiv1*postdiv2 + type PRIM_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12 := 16#0#; + -- divide by 1-7 + POSTDIV2 : PRIM_POSTDIV2_Field := 16#7#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- divide by 1-7 + POSTDIV1 : PRIM_POSTDIV1_Field := 16#7#; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PRIM_Register use record + Reserved_0_11 at 0 range 0 .. 11; + POSTDIV2 at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + POSTDIV1 at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + LOCK_N_STICKY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + LOCK_N_STICKY : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + LOCK_N_STICKY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type PLL_USB_Peripheral is record + -- Control and Status GENERAL CONSTRAINTS: Reference clock frequency + -- min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency + -- min=750MHz, max=1600MHz + CS : aliased CS_Register; + -- Controls the PLL power modes. + PWR : aliased PWR_Register; + -- Feedback divisor (note: this PLL does not support fractional + -- division) + FBDIV_INT : aliased FBDIV_INT_Register; + -- Controls the PLL post dividers for the primary output (note: this PLL + -- does not have a secondary output) the primary output is driven from + -- VCO divided by postdiv1*postdiv2 + PRIM : aliased PRIM_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for PLL_USB_Peripheral use record + CS at 16#0# range 0 .. 31; + PWR at 16#4# range 0 .. 31; + FBDIV_INT at 16#8# range 0 .. 31; + PRIM at 16#C# range 0 .. 31; + INTR at 16#10# range 0 .. 31; + INTE at 16#14# range 0 .. 31; + INTF at 16#18# range 0 .. 31; + INTS at 16#1C# range 0 .. 31; + end record; + + PLL_USB_Periph : aliased PLL_USB_Peripheral + with Import, Address => PLL_USB_Base; + +end RP2350_SVD.PLL_USB; diff --git a/src/svd/rp2350_svd-powman.ads b/src/svd/rp2350_svd-powman.ads new file mode 100644 index 0000000..c52852e --- /dev/null +++ b/src/svd/rp2350_svd-powman.ads @@ -0,0 +1,1595 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides +-- scratch register for general use and for bootcode use +package RP2350_SVD.POWMAN is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Indicates a bad password has been used + type BADPASSWD_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + BADPASSWD : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BADPASSWD_Register use record + BADPASSWD at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype VREG_CTRL_HT_TH_Field is HAL.UInt3; + + -- Voltage Regulator Control + type VREG_CTRL_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- high temperature protection threshold regulator power transistors are + -- disabled when junction temperature exceeds threshold 000 - 100C 001 - + -- 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - + -- 150C + HT_TH : VREG_CTRL_HT_TH_Field := 16#5#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- 0=not disabled, 1=enabled + DISABLE_VOLTAGE_LIMIT : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- isolates the VREG control interface 0 - not isolated (default) 1 - + -- isolated + ISOLATE : Boolean := False; + -- unlocks the VREG control interface after power up 0 - Locked + -- (default) 1 - Unlocked It cannot be relocked when it is unlocked. + UNLOCK : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- returns the regulator to its startup settings 0 - reset 1 - not reset + -- (default) + RST_N : Boolean := True; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VREG_CTRL_Register use record + Reserved_0_3 at 0 range 0 .. 3; + HT_TH at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DISABLE_VOLTAGE_LIMIT at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + ISOLATE at 0 range 12 .. 12; + UNLOCK at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + RST_N at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Voltage Regulator Status + type VREG_STS_Register is record + -- Read-only. startup status 0=startup complete, 1=starting up + STARTUP : Boolean; + -- unspecified + Reserved_1_3 : HAL.UInt3; + -- Read-only. output regulation status 0=not in regulation, 1=in + -- regulation + VOUT_OK : Boolean; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VREG_STS_Register use record + STARTUP at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VOUT_OK at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype VREG_VSEL_Field is HAL.UInt5; + + -- Voltage Regulator Settings + type VREG_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- high impedance mode select 0=not in high impedance mode, 1=in high + -- impedance mode + HIZ : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- output voltage select the regulator output voltage is limited to 1.3V + -- unless the voltage limit is disabled using the disable_voltage_limit + -- field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - + -- 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - + -- 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V + -- (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + -- 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V + -- 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V + -- 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V + -- 11111 - 3.30V + VSEL : VREG_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_14 : HAL.UInt6 := 16#0#; + -- Read-only. regulator state is being updated writes to the vreg + -- register will be ignored when this field is set + UPDATE_IN_PROGRESS : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VREG_Register use record + Reserved_0_0 at 0 range 0 .. 0; + HIZ at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_14 at 0 range 9 .. 14; + UPDATE_IN_PROGRESS at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype VREG_LP_ENTRY_VSEL_Field is HAL.UInt5; + + -- Voltage Regulator Low Power Entry Settings + type VREG_LP_ENTRY_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- high impedance mode select 0=not in high impedance mode, 1=in high + -- impedance mode + HIZ : Boolean := False; + -- selects either normal (switching) mode or low power (linear) mode low + -- power mode can only be selected for output voltages up to 1.3V 0 = + -- normal mode (switching) 1 = low power mode (linear) + MODE : Boolean := True; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- output voltage select the regulator output voltage is limited to 1.3V + -- unless the voltage limit is disabled using the disable_voltage_limit + -- field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - + -- 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - + -- 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V + -- (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + -- 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V + -- 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V + -- 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V + -- 11111 - 3.30V + VSEL : VREG_LP_ENTRY_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VREG_LP_ENTRY_Register use record + Reserved_0_0 at 0 range 0 .. 0; + HIZ at 0 range 1 .. 1; + MODE at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype VREG_LP_EXIT_VSEL_Field is HAL.UInt5; + + -- Voltage Regulator Low Power Exit Settings + type VREG_LP_EXIT_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- high impedance mode select 0=not in high impedance mode, 1=in high + -- impedance mode + HIZ : Boolean := False; + -- selects either normal (switching) mode or low power (linear) mode low + -- power mode can only be selected for output voltages up to 1.3V 0 = + -- normal mode (switching) 1 = low power mode (linear) + MODE : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- output voltage select the regulator output voltage is limited to 1.3V + -- unless the voltage limit is disabled using the disable_voltage_limit + -- field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - + -- 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - + -- 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V + -- (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V + -- 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V + -- 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V + -- 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V + -- 11111 - 3.30V + VSEL : VREG_LP_EXIT_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VREG_LP_EXIT_Register use record + Reserved_0_0 at 0 range 0 .. 0; + HIZ at 0 range 1 .. 1; + MODE at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Brown-out Detection Control + type BOD_CTRL_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12 := 16#0#; + -- isolates the brown-out detection control interface 0 - not isolated + -- (default) 1 - isolated + ISOLATE : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOD_CTRL_Register use record + Reserved_0_11 at 0 range 0 .. 11; + ISOLATE at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype BOD_VSEL_Field is HAL.UInt5; + + -- Brown-out Detection Settings + type BOD_Register is record + -- enable brown-out detection 0=not enabled, 1=enabled + EN : Boolean := True; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - + -- 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V + -- 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V + -- 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - + -- 1.161 10001 - 1.204V + VSEL : BOD_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOD_Register use record + EN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype BOD_LP_ENTRY_VSEL_Field is HAL.UInt5; + + -- Brown-out Detection Low Power Entry Settings + type BOD_LP_ENTRY_Register is record + -- enable brown-out detection 0=not enabled, 1=enabled + EN : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - + -- 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V + -- 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V + -- 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - + -- 1.161 10001 - 1.204V + VSEL : BOD_LP_ENTRY_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOD_LP_ENTRY_Register use record + EN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype BOD_LP_EXIT_VSEL_Field is HAL.UInt5; + + -- Brown-out Detection Low Power Exit Settings + type BOD_LP_EXIT_Register is record + -- enable brown-out detection 0=not enabled, 1=enabled + EN : Boolean := True; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - + -- 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V + -- 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V + -- 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - + -- 1.161 10001 - 1.204V + VSEL : BOD_LP_EXIT_VSEL_Field := 16#B#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOD_LP_EXIT_Register use record + EN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VSEL at 0 range 4 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype LPOSC_MODE_Field is HAL.UInt2; + subtype LPOSC_TRIM_Field is HAL.UInt6; + + -- Low power oscillator control register. + type LPOSC_Register is record + -- This feature has been removed + MODE : LPOSC_MODE_Field := 16#3#; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Frequency trim - the trim step is typically 1% of the reset + -- frequency, but can be up to 3% + TRIM : LPOSC_TRIM_Field := 16#20#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LPOSC_Register use record + MODE at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + TRIM at 0 range 4 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- Chip reset control and status + type CHIP_RESET_Register is record + -- This flag is set by double-tapping RUN. It tells bootcode to go into + -- the bootloader. + DOUBLE_TAP : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. This is set by a rescue reset from the RP-AP. Its + -- purpose is to halt before the bootrom before booting from flash in + -- order to recover from a boot lock-up. The debugger can then attach + -- once the bootrom has been halted and flash some working code that + -- does not lock up. + RESCUE_FLAG : Boolean := False; + -- unspecified + Reserved_5_15 : HAL.UInt11 := 16#0#; + -- Read-only. Last reset was from the power-on reset This resets: + -- double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman + -- yes swcore yes psm yes then starts the power sequencer + HAD_POR : Boolean := False; + -- Read-only. Last reset was from the brown-out detection block This + -- resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes + -- powman yes swcore yes psm yes then starts the power sequencer + HAD_BOR : Boolean := False; + -- Read-only. Last reset was from the RUN pin This resets: double_tap + -- flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore + -- yes psm yes then starts the power sequencer + HAD_RUN_LOW : Boolean := False; + -- Read-only. Last reset was an reset request from the arm debugger This + -- resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes + -- powman yes swcore yes psm yes then starts the power sequencer + HAD_DP_RESET_REQ : Boolean := False; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- Read-only. Last reset was a rescue reset from the debugger This + -- resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this + -- flag timer yes powman yes swcore yes psm yes then starts the power + -- sequencer + HAD_RESCUE : Boolean := False; + -- Read-only. Last reset was a watchdog timeout which was configured to + -- reset the power manager asynchronously This resets: double_tap flag + -- no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm + -- yes then starts the power sequencer + HAD_WATCHDOG_RESET_POWMAN_ASYNC : Boolean := False; + -- Read-only. Last reset was a watchdog timeout which was configured to + -- reset the power manager This resets: double_tap flag no DP no RPAP no + -- rescue_flag no timer yes powman yes swcore yes psm yes then starts + -- the power sequencer + HAD_WATCHDOG_RESET_POWMAN : Boolean := False; + -- Read-only. Last reset was a watchdog timeout which was configured to + -- reset the switched-core This resets: double_tap flag no DP no RPAP no + -- rescue_flag no timer no powman no swcore yes psm yes then starts the + -- power sequencer + HAD_WATCHDOG_RESET_SWCORE : Boolean := False; + -- Read-only. Last reset was a switched core powerdown This resets: + -- double_tap flag no DP no RPAP no rescue_flag no timer no powman no + -- swcore yes psm yes then starts the power sequencer + HAD_SWCORE_PD : Boolean := False; + -- Read-only. Last reset was due to a power supply glitch This resets: + -- double_tap flag no DP no RPAP no rescue_flag no timer no powman no + -- swcore no psm yes and does not change the power state + HAD_GLITCH_DETECT : Boolean := False; + -- Read-only. Last reset was a system reset from the hazard debugger + -- This resets: double_tap flag no DP no RPAP no rescue_flag no timer no + -- powman no swcore no psm yes and does not change the power state + HAD_HZD_SYS_RESET_REQ : Boolean := False; + -- Read-only. Last reset was a watchdog timeout which was configured to + -- reset the power-on state machine This resets: double_tap flag no DP + -- no RPAP no rescue_flag no timer no powman no swcore no psm yes and + -- does not change the power state + HAD_WATCHDOG_RESET_RSM : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIP_RESET_Register use record + DOUBLE_TAP at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + RESCUE_FLAG at 0 range 4 .. 4; + Reserved_5_15 at 0 range 5 .. 15; + HAD_POR at 0 range 16 .. 16; + HAD_BOR at 0 range 17 .. 17; + HAD_RUN_LOW at 0 range 18 .. 18; + HAD_DP_RESET_REQ at 0 range 19 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + HAD_RESCUE at 0 range 21 .. 21; + HAD_WATCHDOG_RESET_POWMAN_ASYNC at 0 range 22 .. 22; + HAD_WATCHDOG_RESET_POWMAN at 0 range 23 .. 23; + HAD_WATCHDOG_RESET_SWCORE at 0 range 24 .. 24; + HAD_SWCORE_PD at 0 range 25 .. 25; + HAD_GLITCH_DETECT at 0 range 26 .. 26; + HAD_HZD_SYS_RESET_REQ at 0 range 27 .. 27; + HAD_WATCHDOG_RESET_RSM at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- Allows a watchdog reset to reset the internal state of powman in + -- addition to the power-on state machine (PSM). Note that powman ignores + -- watchdog resets that do not select at least the CLOCKS stage or earlier + -- stages in the PSM. If using these bits, it's recommended to set + -- PSM_WDSEL to all-ones in addition to the desired bits in this register. + -- Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL + -- register having no effect. + type WDSEL_Register is record + -- If set to 1, a watchdog reset will restore powman defaults, reset the + -- timer, reset the switched core domain and run the full power-on state + -- machine (PSM) sequence This does not rely on clk_ref running + RESET_POWMAN_ASYNC : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- If set to 1, a watchdog reset will restore powman defaults, reset the + -- timer, reset the switched core power domain and run the full power-on + -- state machine (PSM) sequence This relies on clk_ref running. Use + -- reset_powman_async if that may not be true + RESET_POWMAN : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- If set to 1, a watchdog reset will reset the switched core power + -- domain and run the full power-on state machine (PSM) sequence From a + -- user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a + -- hardware debug perspective it has the same effect as a power-on reset + -- for the switched core power domain + RESET_SWCORE : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- If set to 1, a watchdog reset will run the full power-on state + -- machine (PSM) sequence From a user perspective it is the same as + -- setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has + -- the same effect as a reset from a glitch detector + RESET_RSM : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WDSEL_Register use record + RESET_POWMAN_ASYNC at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + RESET_POWMAN at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + RESET_SWCORE at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + RESET_RSM at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- For configuration of the power sequencer Writes are ignored while + -- POWMAN_STATE_CHANGING=1 + type SEQ_CFG_Register is record + -- Specifies the power state of SRAM1 when powering up swcore from a low + -- power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no + -- change + HW_PWRUP_SRAM1 : Boolean := False; + -- Specifies the power state of SRAM0 when powering up swcore from a low + -- power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no + -- change + HW_PWRUP_SRAM0 : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Set to 0 to prevent automatic switching to vreg low power mode when + -- switched-core is powered down This setting takes effect when the + -- swcore is next powered down + USE_VREG_LP : Boolean := True; + -- Set to 0 to prevent automatic switching to vreg high power mode when + -- switched-core is powered up This setting takes effect when the swcore + -- is next powered up + USE_VREG_HP : Boolean := True; + -- Set to 0 to prevent automatic switching to bod low power mode when + -- switched-core is powered down This setting takes effect when the + -- swcore is next powered down + USE_BOD_LP : Boolean := True; + -- Set to 0 to prevent automatic switching to bod high power mode when + -- switched-core is powered up This setting takes effect when the swcore + -- is next powered up + USE_BOD_HP : Boolean := True; + -- Set to 0 to stop the low power osc when the switched-core is powered + -- down, which is unwise if using it to clock the timer This setting + -- takes effect when the swcore is next powered down + RUN_LPOSC_IN_LP : Boolean := True; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- selects the reference clock (clk_ref) as the source of the POWMAN + -- clock when switched-core is powered. The POWMAN clock always switches + -- to the slow clock (lposc) when switched-core is powered down because + -- the fast clock stops running. 0 always run the POWMAN clock from the + -- slow clock (lposc) 1 run the POWMAN clock from the fast clock when + -- available This setting takes effect when a power up sequence is next + -- run + USE_FAST_POWCK : Boolean := True; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Read-only. Indicates the voltage regulator (VREG) mode 0 = VREG high + -- power mode which is the default 1 = VREG low power mode + USING_VREG_LP : Boolean := False; + -- Read-only. Indicates the brown-out detector (BOD) mode 0 = BOD high + -- power mode which is the default 1 = BOD low power mode + USING_BOD_LP : Boolean := False; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- Read-only. 0 indicates the POWMAN clock is running from the low power + -- oscillator (32kHz) 1 indicates the POWMAN clock is running from the + -- reference clock (2-50MHz) + USING_FAST_POWCK : Boolean := True; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SEQ_CFG_Register use record + HW_PWRUP_SRAM1 at 0 range 0 .. 0; + HW_PWRUP_SRAM0 at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + USE_VREG_LP at 0 range 4 .. 4; + USE_VREG_HP at 0 range 5 .. 5; + USE_BOD_LP at 0 range 6 .. 6; + USE_BOD_HP at 0 range 7 .. 7; + RUN_LPOSC_IN_LP at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + USE_FAST_POWCK at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + USING_VREG_LP at 0 range 16 .. 16; + USING_BOD_LP at 0 range 17 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + USING_FAST_POWCK at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype STATE_CURRENT_Field is HAL.UInt4; + subtype STATE_REQ_Field is HAL.UInt4; + + -- This register controls the power state of the 4 power domains. The + -- current power state is indicated in POWMAN_STATE_CURRENT which is + -- read-only. To change the state, write to POWMAN_STATE_REQ. The coding of + -- POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + -- defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 + -- bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is + -- written, the POWMAN_STATE_WAITING flag is set while the Power Manager + -- determines what is required. If an invalid transition is requested the + -- Power Manager will still register the request in POWMAN_STATE_REQ but + -- will also set the POWMAN_BAD_REQ flag. It will then implement the + -- power-up requests and ignore the power down requests. To do nothing + -- would risk entering an unrecoverable lock-up state. Invalid requests + -- are: any combination of power up and power down requests any request + -- that results in swcore boing powered and xip unpowered If the request is + -- to power down the switched-core domain then POWMAN_STATE_WAITING stays + -- active until the processors halt. During this time the POWMAN_STATE_REQ + -- field can be re-written to change or cancel the request. When the power + -- state transition begins the POWMAN_STATE_WAITING_flag is cleared, the + -- POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored + -- until the transition completes. + type STATE_Register is record + -- Read-only. + CURRENT : STATE_CURRENT_Field := 16#F#; + REQ : STATE_REQ_Field := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + REQ_IGNORED : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Request ignored because of a pending pwrup request. See + -- current_pwrup_req. Note this blocks powering up AND powering down. + PWRUP_WHILE_WAITING : Boolean := False; + -- Read-only. Bad software initiated state request. No action taken. + BAD_SW_REQ : Boolean := False; + -- Read-only. Bad hardware initiated state request. Went back to state 0 + -- (i.e. everything powered up) + BAD_HW_REQ : Boolean := False; + -- Read-only. + WAITING : Boolean := False; + -- Read-only. + CHANGING : Boolean := False; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATE_Register use record + CURRENT at 0 range 0 .. 3; + REQ at 0 range 4 .. 7; + REQ_IGNORED at 0 range 8 .. 8; + PWRUP_WHILE_WAITING at 0 range 9 .. 9; + BAD_SW_REQ at 0 range 10 .. 10; + BAD_HW_REQ at 0 range 11 .. 11; + WAITING at 0 range 12 .. 12; + CHANGING at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype POW_FASTDIV_POW_FASTDIV_Field is HAL.UInt11; + + type POW_FASTDIV_Register is record + -- divides the POWMAN clock to provide a tick for the delay module and + -- state machines when clk_pow is running from the slow clock it is not + -- divided when clk_pow is running from the fast clock it is divided by + -- tick_div + POW_FASTDIV : POW_FASTDIV_POW_FASTDIV_Field := 16#40#; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POW_FASTDIV_Register use record + POW_FASTDIV at 0 range 0 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype POW_DELAY_SWCORE_STEP_Field is HAL.UInt4; + subtype POW_DELAY_XIP_STEP_Field is HAL.UInt4; + subtype POW_DELAY_SRAM_STEP_Field is HAL.UInt8; + + -- power state machine delays + type POW_DELAY_Register is record + -- timing between the swcore power state machine steps measured in units + -- of the lposc period, 0 gives a delay of 1 unit + SWCORE_STEP : POW_DELAY_SWCORE_STEP_Field := 16#1#; + -- timing between the xip power state machine steps measured in units of + -- the lposc period, 0 gives a delay of 1 unit + XIP_STEP : POW_DELAY_XIP_STEP_Field := 16#1#; + -- timing between the sram0 and sram1 power state machine steps measured + -- in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + SRAM_STEP : POW_DELAY_SRAM_STEP_Field := 16#20#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for POW_DELAY_Register use record + SWCORE_STEP at 0 range 0 .. 3; + XIP_STEP at 0 range 4 .. 7; + SRAM_STEP at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype EXT_CTRL_GPIO_SELECT_Field is HAL.UInt6; + + -- Configures a gpio as a power mode aware control output + type EXT_CTRL_Register is record + -- selects from gpio 0->30 set to 31 to disable this feature + GPIO_SELECT : EXT_CTRL_GPIO_SELECT_Field := 16#3F#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + INIT : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + INIT_STATE : Boolean := False; + -- output level when entering the low power state + LP_ENTRY_STATE : Boolean := False; + -- output level when exiting the low power state + LP_EXIT_STATE : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXT_CTRL_Register use record + GPIO_SELECT at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + INIT at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + INIT_STATE at 0 range 12 .. 12; + LP_ENTRY_STATE at 0 range 13 .. 13; + LP_EXIT_STATE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype EXT_TIME_REF_SOURCE_SEL_Field is HAL.UInt2; + + -- Select a GPIO to use as a time reference, the source can be used to + -- drive the low power clock at 32kHz, or to provide a 1ms tick to the + -- timer, or provide a 1Hz tick to the timer. The tick selection is + -- controlled by the POWMAN_TIMER register. + type EXT_TIME_REF_Register is record + -- 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22 + SOURCE_SEL : EXT_TIME_REF_SOURCE_SEL_Field := 16#0#; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Use the selected GPIO to drive the 32kHz low power clock, in place of + -- LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + DRIVE_LPCK : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EXT_TIME_REF_Register use record + SOURCE_SEL at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + DRIVE_LPCK at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype LPOSC_FREQ_KHZ_INT_LPOSC_FREQ_KHZ_INT_Field is HAL.UInt6; + + -- Informs the AON Timer of the integer component of the clock frequency + -- when running off the LPOSC. + type LPOSC_FREQ_KHZ_INT_Register is record + -- Integer component of the LPOSC or GPIO clock source frequency in kHz. + -- Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 + -- or POWMAN_TIMER_USING_XOSC=1 + LPOSC_FREQ_KHZ_INT : LPOSC_FREQ_KHZ_INT_LPOSC_FREQ_KHZ_INT_Field := + 16#20#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LPOSC_FREQ_KHZ_INT_Register use record + LPOSC_FREQ_KHZ_INT at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype LPOSC_FREQ_KHZ_FRAC_LPOSC_FREQ_KHZ_FRAC_Field is HAL.UInt16; + + -- Informs the AON Timer of the fractional component of the clock frequency + -- when running off the LPOSC. + type LPOSC_FREQ_KHZ_FRAC_Register is record + -- Fractional component of the LPOSC or GPIO clock source frequency in + -- kHz. Default = 0.768 This field must only be written when + -- POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + LPOSC_FREQ_KHZ_FRAC : LPOSC_FREQ_KHZ_FRAC_LPOSC_FREQ_KHZ_FRAC_Field := + 16#C49C#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LPOSC_FREQ_KHZ_FRAC_Register use record + LPOSC_FREQ_KHZ_FRAC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype XOSC_FREQ_KHZ_INT_XOSC_FREQ_KHZ_INT_Field is HAL.UInt16; + + -- Informs the AON Timer of the integer component of the clock frequency + -- when running off the XOSC. + type XOSC_FREQ_KHZ_INT_Register is record + -- Integer component of the XOSC frequency in kHz. Default = 12000 Must + -- be >1 This field must only be written when POWMAN_TIMER_RUN=0 or + -- POWMAN_TIMER_USING_XOSC=0 + XOSC_FREQ_KHZ_INT : XOSC_FREQ_KHZ_INT_XOSC_FREQ_KHZ_INT_Field := + 16#2EE0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XOSC_FREQ_KHZ_INT_Register use record + XOSC_FREQ_KHZ_INT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype XOSC_FREQ_KHZ_FRAC_XOSC_FREQ_KHZ_FRAC_Field is HAL.UInt16; + + -- Informs the AON Timer of the fractional component of the clock frequency + -- when running off the XOSC. + type XOSC_FREQ_KHZ_FRAC_Register is record + -- Fractional component of the XOSC frequency in kHz. This field must + -- only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + XOSC_FREQ_KHZ_FRAC : XOSC_FREQ_KHZ_FRAC_XOSC_FREQ_KHZ_FRAC_Field := + 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for XOSC_FREQ_KHZ_FRAC_Register use record + XOSC_FREQ_KHZ_FRAC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SET_TIME_63TO48_SET_TIME_63TO48_Field is HAL.UInt16; + + type SET_TIME_63TO48_Register is record + -- For setting the time, do not use for reading the time, use + -- POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must + -- only be written when POWMAN_TIMER_RUN=0 + SET_TIME_63TO48 : SET_TIME_63TO48_SET_TIME_63TO48_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SET_TIME_63TO48_Register use record + SET_TIME_63TO48 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SET_TIME_47TO32_SET_TIME_47TO32_Field is HAL.UInt16; + + type SET_TIME_47TO32_Register is record + -- For setting the time, do not use for reading the time, use + -- POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must + -- only be written when POWMAN_TIMER_RUN=0 + SET_TIME_47TO32 : SET_TIME_47TO32_SET_TIME_47TO32_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SET_TIME_47TO32_Register use record + SET_TIME_47TO32 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SET_TIME_31TO16_SET_TIME_31TO16_Field is HAL.UInt16; + + type SET_TIME_31TO16_Register is record + -- For setting the time, do not use for reading the time, use + -- POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must + -- only be written when POWMAN_TIMER_RUN=0 + SET_TIME_31TO16 : SET_TIME_31TO16_SET_TIME_31TO16_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SET_TIME_31TO16_Register use record + SET_TIME_31TO16 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SET_TIME_15TO0_SET_TIME_15TO0_Field is HAL.UInt16; + + type SET_TIME_15TO0_Register is record + -- For setting the time, do not use for reading the time, use + -- POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must + -- only be written when POWMAN_TIMER_RUN=0 + SET_TIME_15TO0 : SET_TIME_15TO0_SET_TIME_15TO0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SET_TIME_15TO0_Register use record + SET_TIME_15TO0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ALARM_TIME_63TO48_ALARM_TIME_63TO48_Field is HAL.UInt16; + + type ALARM_TIME_63TO48_Register is record + -- This field must only be written when POWMAN_ALARM_ENAB=0 + ALARM_TIME_63TO48 : ALARM_TIME_63TO48_ALARM_TIME_63TO48_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALARM_TIME_63TO48_Register use record + ALARM_TIME_63TO48 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ALARM_TIME_47TO32_ALARM_TIME_47TO32_Field is HAL.UInt16; + + type ALARM_TIME_47TO32_Register is record + -- This field must only be written when POWMAN_ALARM_ENAB=0 + ALARM_TIME_47TO32 : ALARM_TIME_47TO32_ALARM_TIME_47TO32_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALARM_TIME_47TO32_Register use record + ALARM_TIME_47TO32 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ALARM_TIME_31TO16_ALARM_TIME_31TO16_Field is HAL.UInt16; + + type ALARM_TIME_31TO16_Register is record + -- This field must only be written when POWMAN_ALARM_ENAB=0 + ALARM_TIME_31TO16 : ALARM_TIME_31TO16_ALARM_TIME_31TO16_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALARM_TIME_31TO16_Register use record + ALARM_TIME_31TO16 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ALARM_TIME_15TO0_ALARM_TIME_15TO0_Field is HAL.UInt16; + + type ALARM_TIME_15TO0_Register is record + -- This field must only be written when POWMAN_ALARM_ENAB=0 + ALARM_TIME_15TO0 : ALARM_TIME_15TO0_ALARM_TIME_15TO0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ALARM_TIME_15TO0_Register use record + ALARM_TIME_15TO0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type TIMER_Register is record + -- Control whether Non-secure software can write to the timer registers. + -- All other registers are hardwired to be inaccessible to Non-secure. + NONSEC_WRITE : Boolean := False; + -- Timer enable. Setting this bit causes the timer to begin counting up + -- from its current value. Clearing this bit stops the timer from + -- counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and + -- POWMAN_XOSC_FREQ* registers to configure the count rate, and + -- initialise the current time by writing to SET_TIME_63TO48 through + -- SET_TIME_15TO0. You must not write to the SET_TIME_x registers when + -- the timer is running. Once configured, start the timer by setting + -- POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. + -- When the XOSC is available switch the reference clock to XOSC then + -- select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + RUN : Boolean := False; + -- Write-only. Clears the timer, does not disable the timer and does not + -- affect the alarm. This control can be written at any time. + CLEAR : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Enables the alarm. The alarm must be disabled while writing the alarm + -- time. + ALARM_ENAB : Boolean := False; + -- Alarm wakes the chip from low power mode + PWRUP_ON_ALARM : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Alarm has fired. Write to 1 to clear the alarm. + ALARM : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Switch to lposc as the source of the 1kHz timer tick + USE_LPOSC : Boolean := False; + -- Write-only. switch to xosc as the source of the 1kHz timer tick + USE_XOSC : Boolean := False; + -- Write-only. switch to gpio as the source of the 1kHz timer tick + USE_GPIO_1KHZ : Boolean := False; + -- unspecified + Reserved_11_12 : HAL.UInt2 := 16#0#; + -- Selects the gpio source as the reference for the sec counter. The + -- msec counter will continue to use the lposc or xosc reference. + USE_GPIO_1HZ : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Read-only. Timer is running from xosc + USING_XOSC : Boolean := False; + -- Read-only. Timer is running from lposc + USING_LPOSC : Boolean := False; + -- Read-only. Timer is running from a 1khz gpio source + USING_GPIO_1KHZ : Boolean := False; + -- Read-only. Timer is synchronised to a 1hz gpio source + USING_GPIO_1HZ : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER_Register use record + NONSEC_WRITE at 0 range 0 .. 0; + RUN at 0 range 1 .. 1; + CLEAR at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + ALARM_ENAB at 0 range 4 .. 4; + PWRUP_ON_ALARM at 0 range 5 .. 5; + ALARM at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + USE_LPOSC at 0 range 8 .. 8; + USE_XOSC at 0 range 9 .. 9; + USE_GPIO_1KHZ at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + USE_GPIO_1HZ at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + USING_XOSC at 0 range 16 .. 16; + USING_LPOSC at 0 range 17 .. 17; + USING_GPIO_1KHZ at 0 range 18 .. 18; + USING_GPIO_1HZ at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype PWRUP_SOURCE_Field is HAL.UInt6; + + type PWRUP0_DIRECTION_Field is + (low_falling, + high_rising) + with Size => 1; + for PWRUP0_DIRECTION_Field use + (low_falling => 0, + high_rising => 1); + + -- Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 + -- transition). Level will detect a 1 or 0. Both types of event get latched + -- into the current_pwrup_req register. + type PWRUP0_MODE_Field is + (level, + edge) + with Size => 1; + for PWRUP0_MODE_Field use + (level => 0, + edge => 1); + + -- 4 GPIO powerup events can be configured to wake the chip up from a low + -- power state. The pwrups are level/edge sensitive and can be set to + -- trigger on a high/rising or low/falling event The number of gpios + -- available depends on the package option. An invalid selection will be + -- ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = + -- 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects + -- qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 + -- source = 53 selects qspi_sclk level = 0 triggers the pwrup when the + -- source is low level = 1 triggers the pwrup when the source is high + type PWRUP_Register is record + SOURCE : PWRUP_SOURCE_Field := 16#3F#; + -- Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup + -- source and clear a pending wakeup event. If using edge detect a + -- latched edge needs to be cleared by writing 1 to the status register + -- also. + ENABLE : Boolean := False; + DIRECTION : PWRUP0_DIRECTION_Field := + RP2350_SVD.POWMAN.low_falling; + -- Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 + -- transition). Level will detect a 1 or 0. Both types of event get + -- latched into the current_pwrup_req register. + MODE : PWRUP0_MODE_Field := RP2350_SVD.POWMAN.level; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Status of gpio wakeup. Write to 1 to clear a latched + -- edge detect. + STATUS : Boolean := False; + -- Read-only. Value of selected gpio pin (only if enable == 1) + RAW_STATUS : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PWRUP_Register use record + SOURCE at 0 range 0 .. 5; + ENABLE at 0 range 6 .. 6; + DIRECTION at 0 range 7 .. 7; + MODE at 0 range 8 .. 8; + STATUS at 0 range 9 .. 9; + RAW_STATUS at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype CURRENT_PWRUP_REQ_CURRENT_PWRUP_REQ_Field is HAL.UInt7; + + -- Indicates current powerup request state pwrup events can be cleared by + -- removing the enable from the pwrup register. The alarm pwrup req can be + -- cleared by clearing timer.alarm_enab 0 = chip reset, for the source of + -- the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 + -- = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + type CURRENT_PWRUP_REQ_Register is record + -- Read-only. + CURRENT_PWRUP_REQ : CURRENT_PWRUP_REQ_CURRENT_PWRUP_REQ_Field; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CURRENT_PWRUP_REQ_Register use record + CURRENT_PWRUP_REQ at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype LAST_SWCORE_PWRUP_LAST_SWCORE_PWRUP_Field is HAL.UInt7; + + -- Indicates which pwrup source triggered the last switched-core power up 0 + -- = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = + -- pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = + -- alarm_pwrup + type LAST_SWCORE_PWRUP_Register is record + -- Read-only. + LAST_SWCORE_PWRUP : LAST_SWCORE_PWRUP_LAST_SWCORE_PWRUP_Field; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LAST_SWCORE_PWRUP_Register use record + LAST_SWCORE_PWRUP at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + type DBG_PWRCFG_Register is record + -- Ignore pwrup req from debugger. If pwrup req is asserted then this + -- will prevent power down and set powerdown blocked. Set ignore to stop + -- paying attention to pwrup_req + IGNORE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBG_PWRCFG_Register use record + IGNORE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Tell the bootrom to ignore the BOOT0..3 registers following the next RSM + -- reset (e.g. the next core power down/up). If an early boot stage has + -- soft-locked some OTP pages in order to protect their contents from later + -- stages, there is a risk that Secure code running at a later stage can + -- unlock the pages by powering the core up and down. This register can be + -- used to ensure that the bootloader runs as normal on the next power up, + -- preventing Secure code at a later stage from accessing OTP in its + -- unlocked state. Should be used in conjunction with the OTP BOOTDIS + -- register. + type BOOTDIS_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. When powman resets the RSM, the current value of + -- BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + -- The bootrom checks this flag before reading the BOOT0..3 registers. + -- If it is set, the bootrom clears it, and ignores the BOOT registers. + -- This prevents Secure software from diverting the boot path before a + -- bootloader has had the chance to soft lock OTP pages containing + -- sensitive data. + NOW : Boolean := False; + -- This flag always ORs writes into its current contents. It can be set + -- but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the + -- BOOTDIS_NOW bit when the core is powered down. Simultaneously, the + -- BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 + -- registers will be ignored following the next reset of the RSM by + -- powman. This flag should be set by an early boot stage that has + -- soft-locked OTP pages, to prevent later stages from unlocking it by + -- power cycling. + NEXT : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BOOTDIS_Register use record + NOW at 0 range 0 .. 0; + NEXT at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype DBGCONFIG_DP_INSTID_Field is HAL.UInt4; + + type DBGCONFIG_Register is record + -- Configure DP instance ID for SWD multidrop selection. Recommend that + -- this is NOT changed until you require debug access in multi-chip + -- environment + DP_INSTID : DBGCONFIG_DP_INSTID_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGCONFIG_Register use record + DP_INSTID at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + VREG_OUTPUT_LOW : Boolean := False; + -- Read-only. + TIMER : Boolean := False; + -- Read-only. Source is state.req_ignored + STATE_REQ_IGNORED : Boolean := False; + -- Read-only. Source is state.pwrup_while_waiting + PWRUP_WHILE_WAITING : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + VREG_OUTPUT_LOW at 0 range 0 .. 0; + TIMER at 0 range 1 .. 1; + STATE_REQ_IGNORED at 0 range 2 .. 2; + PWRUP_WHILE_WAITING at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + VREG_OUTPUT_LOW : Boolean := False; + TIMER : Boolean := False; + -- Source is state.req_ignored + STATE_REQ_IGNORED : Boolean := False; + -- Source is state.pwrup_while_waiting + PWRUP_WHILE_WAITING : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + VREG_OUTPUT_LOW at 0 range 0 .. 0; + TIMER at 0 range 1 .. 1; + STATE_REQ_IGNORED at 0 range 2 .. 2; + PWRUP_WHILE_WAITING at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + VREG_OUTPUT_LOW : Boolean := False; + TIMER : Boolean := False; + -- Source is state.req_ignored + STATE_REQ_IGNORED : Boolean := False; + -- Source is state.pwrup_while_waiting + PWRUP_WHILE_WAITING : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + VREG_OUTPUT_LOW at 0 range 0 .. 0; + TIMER at 0 range 1 .. 1; + STATE_REQ_IGNORED at 0 range 2 .. 2; + PWRUP_WHILE_WAITING at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + VREG_OUTPUT_LOW : Boolean; + -- Read-only. + TIMER : Boolean; + -- Read-only. Source is state.req_ignored + STATE_REQ_IGNORED : Boolean; + -- Read-only. Source is state.pwrup_while_waiting + PWRUP_WHILE_WAITING : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + VREG_OUTPUT_LOW at 0 range 0 .. 0; + TIMER at 0 range 1 .. 1; + STATE_REQ_IGNORED at 0 range 2 .. 2; + PWRUP_WHILE_WAITING at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Controls vreg, bor, lposc, chip resets & xosc startup, powman and + -- provides scratch register for general use and for bootcode use + type POWMAN_Peripheral is record + -- Indicates a bad password has been used + BADPASSWD : aliased BADPASSWD_Register; + -- Voltage Regulator Control + VREG_CTRL : aliased VREG_CTRL_Register; + -- Voltage Regulator Status + VREG_STS : aliased VREG_STS_Register; + -- Voltage Regulator Settings + VREG : aliased VREG_Register; + -- Voltage Regulator Low Power Entry Settings + VREG_LP_ENTRY : aliased VREG_LP_ENTRY_Register; + -- Voltage Regulator Low Power Exit Settings + VREG_LP_EXIT : aliased VREG_LP_EXIT_Register; + -- Brown-out Detection Control + BOD_CTRL : aliased BOD_CTRL_Register; + -- Brown-out Detection Settings + BOD : aliased BOD_Register; + -- Brown-out Detection Low Power Entry Settings + BOD_LP_ENTRY : aliased BOD_LP_ENTRY_Register; + -- Brown-out Detection Low Power Exit Settings + BOD_LP_EXIT : aliased BOD_LP_EXIT_Register; + -- Low power oscillator control register. + LPOSC : aliased LPOSC_Register; + -- Chip reset control and status + CHIP_RESET : aliased CHIP_RESET_Register; + -- Allows a watchdog reset to reset the internal state of powman in + -- addition to the power-on state machine (PSM). Note that powman + -- ignores watchdog resets that do not select at least the CLOCKS stage + -- or earlier stages in the PSM. If using these bits, it's recommended + -- to set PSM_WDSEL to all-ones in addition to the desired bits in this + -- register. Failing to select CLOCKS or earlier will result in the + -- POWMAN_WDSEL register having no effect. + WDSEL : aliased WDSEL_Register; + -- For configuration of the power sequencer Writes are ignored while + -- POWMAN_STATE_CHANGING=1 + SEQ_CFG : aliased SEQ_CFG_Register; + -- This register controls the power state of the 4 power domains. The + -- current power state is indicated in POWMAN_STATE_CURRENT which is + -- read-only. To change the state, write to POWMAN_STATE_REQ. The coding + -- of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power + -- states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit + -- 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When + -- POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set + -- while the Power Manager determines what is required. If an invalid + -- transition is requested the Power Manager will still register the + -- request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ + -- flag. It will then implement the power-up requests and ignore the + -- power down requests. To do nothing would risk entering an + -- unrecoverable lock-up state. Invalid requests are: any combination of + -- power up and power down requests any request that results in swcore + -- boing powered and xip unpowered If the request is to power down the + -- switched-core domain then POWMAN_STATE_WAITING stays active until the + -- processors halt. During this time the POWMAN_STATE_REQ field can be + -- re-written to change or cancel the request. When the power state + -- transition begins the POWMAN_STATE_WAITING_flag is cleared, the + -- POWMAN_STATE_CHANGING flag is set and POWMAN register writes are + -- ignored until the transition completes. + STATE : aliased STATE_Register; + POW_FASTDIV : aliased POW_FASTDIV_Register; + -- power state machine delays + POW_DELAY : aliased POW_DELAY_Register; + -- Configures a gpio as a power mode aware control output + EXT_CTRL0 : aliased EXT_CTRL_Register; + -- Configures a gpio as a power mode aware control output + EXT_CTRL1 : aliased EXT_CTRL_Register; + -- Select a GPIO to use as a time reference, the source can be used to + -- drive the low power clock at 32kHz, or to provide a 1ms tick to the + -- timer, or provide a 1Hz tick to the timer. The tick selection is + -- controlled by the POWMAN_TIMER register. + EXT_TIME_REF : aliased EXT_TIME_REF_Register; + -- Informs the AON Timer of the integer component of the clock frequency + -- when running off the LPOSC. + LPOSC_FREQ_KHZ_INT : aliased LPOSC_FREQ_KHZ_INT_Register; + -- Informs the AON Timer of the fractional component of the clock + -- frequency when running off the LPOSC. + LPOSC_FREQ_KHZ_FRAC : aliased LPOSC_FREQ_KHZ_FRAC_Register; + -- Informs the AON Timer of the integer component of the clock frequency + -- when running off the XOSC. + XOSC_FREQ_KHZ_INT : aliased XOSC_FREQ_KHZ_INT_Register; + -- Informs the AON Timer of the fractional component of the clock + -- frequency when running off the XOSC. + XOSC_FREQ_KHZ_FRAC : aliased XOSC_FREQ_KHZ_FRAC_Register; + SET_TIME_63TO48 : aliased SET_TIME_63TO48_Register; + SET_TIME_47TO32 : aliased SET_TIME_47TO32_Register; + SET_TIME_31TO16 : aliased SET_TIME_31TO16_Register; + SET_TIME_15TO0 : aliased SET_TIME_15TO0_Register; + READ_TIME_UPPER : aliased HAL.UInt32; + READ_TIME_LOWER : aliased HAL.UInt32; + ALARM_TIME_63TO48 : aliased ALARM_TIME_63TO48_Register; + ALARM_TIME_47TO32 : aliased ALARM_TIME_47TO32_Register; + ALARM_TIME_31TO16 : aliased ALARM_TIME_31TO16_Register; + ALARM_TIME_15TO0 : aliased ALARM_TIME_15TO0_Register; + TIMER : aliased TIMER_Register; + -- 4 GPIO powerup events can be configured to wake the chip up from a + -- low power state. The pwrups are level/edge sensitive and can be set + -- to trigger on a high/rising or low/falling event The number of gpios + -- available depends on the package option. An invalid selection will be + -- ignored source = 0 selects gpio0 . . source = 47 selects gpio47 + -- source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 + -- selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects + -- qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup + -- when the source is low level = 1 triggers the pwrup when the source + -- is high + PWRUP0 : aliased PWRUP_Register; + -- 4 GPIO powerup events can be configured to wake the chip up from a + -- low power state. The pwrups are level/edge sensitive and can be set + -- to trigger on a high/rising or low/falling event The number of gpios + -- available depends on the package option. An invalid selection will be + -- ignored source = 0 selects gpio0 . . source = 47 selects gpio47 + -- source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 + -- selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects + -- qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup + -- when the source is low level = 1 triggers the pwrup when the source + -- is high + PWRUP1 : aliased PWRUP_Register; + -- 4 GPIO powerup events can be configured to wake the chip up from a + -- low power state. The pwrups are level/edge sensitive and can be set + -- to trigger on a high/rising or low/falling event The number of gpios + -- available depends on the package option. An invalid selection will be + -- ignored source = 0 selects gpio0 . . source = 47 selects gpio47 + -- source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 + -- selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects + -- qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup + -- when the source is low level = 1 triggers the pwrup when the source + -- is high + PWRUP2 : aliased PWRUP_Register; + -- 4 GPIO powerup events can be configured to wake the chip up from a + -- low power state. The pwrups are level/edge sensitive and can be set + -- to trigger on a high/rising or low/falling event The number of gpios + -- available depends on the package option. An invalid selection will be + -- ignored source = 0 selects gpio0 . . source = 47 selects gpio47 + -- source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 + -- selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects + -- qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup + -- when the source is low level = 1 triggers the pwrup when the source + -- is high + PWRUP3 : aliased PWRUP_Register; + -- Indicates current powerup request state pwrup events can be cleared + -- by removing the enable from the pwrup register. The alarm pwrup req + -- can be cleared by clearing timer.alarm_enab 0 = chip reset, for the + -- source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 + -- 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + CURRENT_PWRUP_REQ : aliased CURRENT_PWRUP_REQ_Register; + -- Indicates which pwrup source triggered the last switched-core power + -- up 0 = chip reset, for the source of the last reset see + -- POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = + -- coresight_pwrup 6 = alarm_pwrup + LAST_SWCORE_PWRUP : aliased LAST_SWCORE_PWRUP_Register; + DBG_PWRCFG : aliased DBG_PWRCFG_Register; + -- Tell the bootrom to ignore the BOOT0..3 registers following the next + -- RSM reset (e.g. the next core power down/up). If an early boot stage + -- has soft-locked some OTP pages in order to protect their contents + -- from later stages, there is a risk that Secure code running at a + -- later stage can unlock the pages by powering the core up and down. + -- This register can be used to ensure that the bootloader runs as + -- normal on the next power up, preventing Secure code at a later stage + -- from accessing OTP in its unlocked state. Should be used in + -- conjunction with the OTP BOOTDIS register. + BOOTDIS : aliased BOOTDIS_Register; + DBGCONFIG : aliased DBGCONFIG_Register; + -- Scratch register. Information persists in low power mode + SCRATCH0 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH1 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH2 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH3 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH4 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH5 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH6 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + SCRATCH7 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + BOOT0 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + BOOT1 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + BOOT2 : aliased HAL.UInt32; + -- Scratch register. Information persists in low power mode + BOOT3 : aliased HAL.UInt32; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for POWMAN_Peripheral use record + BADPASSWD at 16#0# range 0 .. 31; + VREG_CTRL at 16#4# range 0 .. 31; + VREG_STS at 16#8# range 0 .. 31; + VREG at 16#C# range 0 .. 31; + VREG_LP_ENTRY at 16#10# range 0 .. 31; + VREG_LP_EXIT at 16#14# range 0 .. 31; + BOD_CTRL at 16#18# range 0 .. 31; + BOD at 16#1C# range 0 .. 31; + BOD_LP_ENTRY at 16#20# range 0 .. 31; + BOD_LP_EXIT at 16#24# range 0 .. 31; + LPOSC at 16#28# range 0 .. 31; + CHIP_RESET at 16#2C# range 0 .. 31; + WDSEL at 16#30# range 0 .. 31; + SEQ_CFG at 16#34# range 0 .. 31; + STATE at 16#38# range 0 .. 31; + POW_FASTDIV at 16#3C# range 0 .. 31; + POW_DELAY at 16#40# range 0 .. 31; + EXT_CTRL0 at 16#44# range 0 .. 31; + EXT_CTRL1 at 16#48# range 0 .. 31; + EXT_TIME_REF at 16#4C# range 0 .. 31; + LPOSC_FREQ_KHZ_INT at 16#50# range 0 .. 31; + LPOSC_FREQ_KHZ_FRAC at 16#54# range 0 .. 31; + XOSC_FREQ_KHZ_INT at 16#58# range 0 .. 31; + XOSC_FREQ_KHZ_FRAC at 16#5C# range 0 .. 31; + SET_TIME_63TO48 at 16#60# range 0 .. 31; + SET_TIME_47TO32 at 16#64# range 0 .. 31; + SET_TIME_31TO16 at 16#68# range 0 .. 31; + SET_TIME_15TO0 at 16#6C# range 0 .. 31; + READ_TIME_UPPER at 16#70# range 0 .. 31; + READ_TIME_LOWER at 16#74# range 0 .. 31; + ALARM_TIME_63TO48 at 16#78# range 0 .. 31; + ALARM_TIME_47TO32 at 16#7C# range 0 .. 31; + ALARM_TIME_31TO16 at 16#80# range 0 .. 31; + ALARM_TIME_15TO0 at 16#84# range 0 .. 31; + TIMER at 16#88# range 0 .. 31; + PWRUP0 at 16#8C# range 0 .. 31; + PWRUP1 at 16#90# range 0 .. 31; + PWRUP2 at 16#94# range 0 .. 31; + PWRUP3 at 16#98# range 0 .. 31; + CURRENT_PWRUP_REQ at 16#9C# range 0 .. 31; + LAST_SWCORE_PWRUP at 16#A0# range 0 .. 31; + DBG_PWRCFG at 16#A4# range 0 .. 31; + BOOTDIS at 16#A8# range 0 .. 31; + DBGCONFIG at 16#AC# range 0 .. 31; + SCRATCH0 at 16#B0# range 0 .. 31; + SCRATCH1 at 16#B4# range 0 .. 31; + SCRATCH2 at 16#B8# range 0 .. 31; + SCRATCH3 at 16#BC# range 0 .. 31; + SCRATCH4 at 16#C0# range 0 .. 31; + SCRATCH5 at 16#C4# range 0 .. 31; + SCRATCH6 at 16#C8# range 0 .. 31; + SCRATCH7 at 16#CC# range 0 .. 31; + BOOT0 at 16#D0# range 0 .. 31; + BOOT1 at 16#D4# range 0 .. 31; + BOOT2 at 16#D8# range 0 .. 31; + BOOT3 at 16#DC# range 0 .. 31; + INTR at 16#E0# range 0 .. 31; + INTE at 16#E4# range 0 .. 31; + INTF at 16#E8# range 0 .. 31; + INTS at 16#EC# range 0 .. 31; + end record; + + -- Controls vreg, bor, lposc, chip resets & xosc startup, powman and + -- provides scratch register for general use and for bootcode use + POWMAN_Periph : aliased POWMAN_Peripheral + with Import, Address => POWMAN_Base; + +end RP2350_SVD.POWMAN; diff --git a/src/svd/rp2350_svd-ppb.ads b/src/svd/rp2350_svd-ppb.ads new file mode 100644 index 0000000..786901c --- /dev/null +++ b/src/svd/rp2350_svd-ppb.ads @@ -0,0 +1,6436 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- TEAL registers accessible through the debug interface +package RP2350_SVD.PPB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ITM_TPR_PRIVMASK_Field is HAL.UInt4; + + -- Controls which stimulus ports can be accessed by unprivileged code + type ITM_TPR_Register is record + -- Bit mask to enable tracing on ITM stimulus ports + PRIVMASK : ITM_TPR_PRIVMASK_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_TPR_Register use record + PRIVMASK at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITM_TCR_TSPRESCALE_Field is HAL.UInt2; + subtype ITM_TCR_GTSFREQ_Field is HAL.UInt2; + subtype ITM_TCR_TRACEBUSID_Field is HAL.UInt7; + + -- Configures and controls transfers through the ITM interface + type ITM_TCR_Register is record + -- Enables the ITM + ITMENA : Boolean := False; + -- Enables Local timestamp generation + TSENA : Boolean := False; + -- Enables Synchronization packet transmission for a synchronous TPIU + SYNCENA : Boolean := False; + -- Enables forwarding of hardware event packet from the DWT unit to the + -- ITM for output to the TPIU + TXENA : Boolean := False; + -- Enables asynchronous clocking of the timestamp counter + SWOENA : Boolean := False; + -- Stall the PE to guarantee delivery of Data Trace packets. + STALLENA : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Local timestamp prescaler, used with the trace packet reference clock + TSPRESCALE : ITM_TCR_TSPRESCALE_Field := 16#0#; + -- Defines how often the ITM generates a global timestamp, based on the + -- global timestamp clock frequency, or disables generation of global + -- timestamps + GTSFREQ : ITM_TCR_GTSFREQ_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Identifier for multi-source trace stream formatting. If multi-source + -- trace is in use, the debugger must write a unique non-zero trace ID + -- value to this field + TRACEBUSID : ITM_TCR_TRACEBUSID_Field := 16#0#; + -- Read-only. Indicates whether the ITM is currently processing events + BUSY : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_TCR_Register use record + ITMENA at 0 range 0 .. 0; + TSENA at 0 range 1 .. 1; + SYNCENA at 0 range 2 .. 2; + TXENA at 0 range 3 .. 3; + SWOENA at 0 range 4 .. 4; + STALLENA at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + TSPRESCALE at 0 range 8 .. 9; + GTSFREQ at 0 range 10 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TRACEBUSID at 0 range 16 .. 22; + BUSY at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Integration Mode: Read ATB Ready + type INT_ATREADY_Register is record + -- Read-only. A read of this bit returns the value of ATREADY + ATREADY : Boolean; + -- Read-only. A read of this bit returns the value of AFVALID + AFVALID : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INT_ATREADY_Register use record + ATREADY at 0 range 0 .. 0; + AFVALID at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Integration Mode: Write ATB Valid + type INT_ATVALID_Register is record + -- A write to this bit gives the value of ATVALID + ATREADY : Boolean := False; + -- A write to this bit gives the value of AFREADY + AFREADY : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INT_ATVALID_Register use record + ATREADY at 0 range 0 .. 0; + AFREADY at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Integration Mode Control Register + type ITM_ITCTRL_Register is record + -- Integration mode enable bit - The possible values are: 0 - The trace + -- unit is not in integration mode. 1 - The trace unit is in integration + -- mode. This mode enables: A debug agent to perform topology detection. + -- SoC test software to perform integration testing. + IME : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_ITCTRL_Register use record + IME at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype ITM_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype ITM_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype ITM_DEVARCH_REVISION_Field is HAL.UInt4; + subtype ITM_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the ITM + type ITM_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : ITM_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : ITM_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : ITM_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : ITM_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype ITM_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype ITM_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : ITM_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : ITM_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR4_DES_2_Field is HAL.UInt4; + subtype ITM_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : ITM_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : ITM_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : ITM_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR1_PART_1_Field is HAL.UInt4; + subtype ITM_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : ITM_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : ITM_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR2_DES_1_Field is HAL.UInt3; + subtype ITM_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : ITM_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : ITM_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR3_CMOD_Field is HAL.UInt4; + subtype ITM_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : ITM_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : ITM_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : ITM_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype ITM_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : ITM_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : ITM_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : ITM_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : ITM_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CTRL_POSTPRESET_Field is HAL.UInt4; + subtype DWT_CTRL_POSTINIT_Field is HAL.UInt4; + subtype DWT_CTRL_SYNCTAP_Field is HAL.UInt2; + subtype DWT_CTRL_NUMCOMP_Field is HAL.UInt4; + + -- Provides configuration and status information for the DWT unit, and used + -- to control features of the unit + type DWT_CTRL_Register is record + -- Enables CYCCNT + CYCCNTENA : Boolean := False; + -- Reload value for the POSTCNT counter + POSTPRESET : DWT_CTRL_POSTPRESET_Field := 16#2#; + -- Initial value for the POSTCNT counter + POSTINIT : DWT_CTRL_POSTINIT_Field := 16#1#; + -- Selects the position of the POSTCNT tap on the CYCCNT counter + CYCTAP : Boolean := False; + -- Selects the position of the synchronization packet counter tap on the + -- CYCCNT counter. This determines the Synchronization packet rate + SYNCTAP : DWT_CTRL_SYNCTAP_Field := 16#2#; + -- Enables use of POSTCNT counter as a timer for Periodic PC Sample + -- packet generation + PCSAMPLENA : Boolean := True; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Enables generation of Exception Trace packets + EXTTRCENA : Boolean := False; + -- Enables DWT_CPICNT counter + CPIEVTENA : Boolean := False; + -- Enables DWT_EXCCNT counter + EXCEVTENA : Boolean := True; + -- Enable DWT_SLEEPCNT counter + SLEEPEVTENA : Boolean := False; + -- Enables DWT_LSUCNT counter + LSUEVTENA : Boolean := True; + -- Enables DWT_FOLDCNT counter + FOLDEVTENA : Boolean := True; + -- Enables Event Counter packet generation on POSTCNT underflow + CYCEVTENA : Boolean := True; + -- Controls whether the cycle counter is disabled in Secure state + CYCDISS : Boolean := False; + -- Read-only. Indicates whether the implementation does not include the + -- profiling counters + NOPRFCNT : Boolean := True; + -- Read-only. Indicates whether the implementation does not include a + -- cycle counter + NOCYCCNT : Boolean := True; + -- Read-only. Reserved, RAZ + NOEXTTRIG : Boolean := False; + -- Read-only. Indicates whether the implementation does not support + -- trace + NOTRCPKT : Boolean := False; + -- Read-only. Number of DWT comparators implemented + NUMCOMP : DWT_CTRL_NUMCOMP_Field := 16#7#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CTRL_Register use record + CYCCNTENA at 0 range 0 .. 0; + POSTPRESET at 0 range 1 .. 4; + POSTINIT at 0 range 5 .. 8; + CYCTAP at 0 range 9 .. 9; + SYNCTAP at 0 range 10 .. 11; + PCSAMPLENA at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + EXTTRCENA at 0 range 16 .. 16; + CPIEVTENA at 0 range 17 .. 17; + EXCEVTENA at 0 range 18 .. 18; + SLEEPEVTENA at 0 range 19 .. 19; + LSUEVTENA at 0 range 20 .. 20; + FOLDEVTENA at 0 range 21 .. 21; + CYCEVTENA at 0 range 22 .. 22; + CYCDISS at 0 range 23 .. 23; + NOPRFCNT at 0 range 24 .. 24; + NOCYCCNT at 0 range 25 .. 25; + NOEXTTRIG at 0 range 26 .. 26; + NOTRCPKT at 0 range 27 .. 27; + NUMCOMP at 0 range 28 .. 31; + end record; + + subtype DWT_EXCCNT_EXCCNT_Field is HAL.UInt8; + + -- Counts the total cycles spent in exception processing + type DWT_EXCCNT_Register is record + -- Counts one on each cycle when all of the following are true: - + -- DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is + -- executed, see DWT_CPICNT. - An exception-entry or exception-exit + -- related operation is in progress. - Either + -- SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation + -- is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + EXCCNT : DWT_EXCCNT_EXCCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_EXCCNT_Register use record + EXCCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_LSUCNT_LSUCNT_Field is HAL.UInt8; + + -- Increments on the additional cycles required to execute all load or + -- store instructions + type DWT_LSUCNT_Register is record + -- Counts one on each cycle when all of the following are true: - + -- DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is + -- executed, see DWT_CPICNT. - No exception-entry or exception-exit + -- operation is in progress, see DWT_EXCCNT. - A load-store operation is + -- in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or + -- NS-Req for the operation is set to Non-secure and + -- NoninvasiveDebugAllowed() == TRUE. + LSUCNT : DWT_LSUCNT_LSUCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_LSUCNT_Register use record + LSUCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_FOLDCNT_FOLDCNT_Field is HAL.UInt8; + + -- Increments on the additional cycles required to execute all load or + -- store instructions + type DWT_FOLDCNT_Register is record + -- Counts on each cycle when all of the following are true: - + -- DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two + -- instructions are executed, see DWT_CPICNT. - Either + -- SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure + -- state and NoninvasiveDebugAllowed() == TRUE. The counter is + -- incremented by the number of instructions executed, minus one + FOLDCNT : DWT_FOLDCNT_FOLDCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_FOLDCNT_Register use record + FOLDCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_FUNCTION_MATCH_Field is HAL.UInt4; + subtype DWT_FUNCTION_ACTION_Field is HAL.UInt2; + subtype DWT_FUNCTION_DATAVSIZE_Field is HAL.UInt2; + subtype DWT_FUNCTION_ID_Field is HAL.UInt5; + + -- Controls the operation of watchpoint comparator 0 + type DWT_FUNCTION_Register is record + -- Controls the type of match generated by this comparator + MATCH : DWT_FUNCTION_MATCH_Field := 16#0#; + -- Defines the action on a match. This field is ignored and the + -- comparator generates no actions if it is disabled by MATCH + ACTION : DWT_FUNCTION_ACTION_Field := 16#0#; + -- unspecified + Reserved_6_9 : HAL.UInt4 := 16#0#; + -- Defines the size of the object being watched for by Data Value and + -- Data Address comparators + DATAVSIZE : DWT_FUNCTION_DATAVSIZE_Field := 16#0#; + -- unspecified + Reserved_12_23 : HAL.UInt12 := 16#0#; + -- Read-only. Set to 1 when the comparator matches + MATCHED : Boolean := False; + -- unspecified + Reserved_25_26 : HAL.UInt2 := 16#0#; + -- Read-only. Identifies the capabilities for MATCH for comparator *n + ID : DWT_FUNCTION_ID_Field := 16#B#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_FUNCTION_Register use record + MATCH at 0 range 0 .. 3; + ACTION at 0 range 4 .. 5; + Reserved_6_9 at 0 range 6 .. 9; + DATAVSIZE at 0 range 10 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + MATCHED at 0 range 24 .. 24; + Reserved_25_26 at 0 range 25 .. 26; + ID at 0 range 27 .. 31; + end record; + + subtype DWT_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype DWT_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype DWT_DEVARCH_REVISION_Field is HAL.UInt4; + subtype DWT_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the DWT + type DWT_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : DWT_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : DWT_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : DWT_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : DWT_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DWT_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DWT_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : DWT_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : DWT_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR4_DES_2_Field is HAL.UInt4; + subtype DWT_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : DWT_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : DWT_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : DWT_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR1_PART_1_Field is HAL.UInt4; + subtype DWT_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : DWT_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : DWT_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR2_DES_1_Field is HAL.UInt3; + subtype DWT_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : DWT_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : DWT_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR3_CMOD_Field is HAL.UInt4; + subtype DWT_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : DWT_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : DWT_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : DWT_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype DWT_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : DWT_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : DWT_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : DWT_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : DWT_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CTRL_NUM_CODE_7_4_Field is HAL.UInt4; + subtype FP_CTRL_NUM_LIT_Field is HAL.UInt4; + subtype FP_CTRL_NUM_CODE_14_12_Field is HAL.UInt3; + subtype FP_CTRL_REV_Field is HAL.UInt4; + + -- Provides FPB implementation information, and the global enable for the + -- FPB unit + type FP_CTRL_Register is record + -- Enables the FPB + ENABLE : Boolean := False; + -- Writes to the FP_CTRL are ignored unless KEY is concurrently written + -- to one + KEY : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Read-only. Indicates the number of implemented instruction address + -- comparators. Zero indicates no Instruction Address comparators are + -- implemented. The Instruction Address comparators are numbered from 0 + -- to NUM_CODE - 1 + NUM_CODE_7_4 : FP_CTRL_NUM_CODE_7_4_Field := 16#8#; + -- Read-only. Indicates the number of implemented literal address + -- comparators. The Literal Address comparators are numbered from + -- NUM_CODE to NUM_CODE + NUM_LIT - 1 + NUM_LIT : FP_CTRL_NUM_LIT_Field := 16#5#; + -- Read-only. Indicates the number of implemented instruction address + -- comparators. Zero indicates no Instruction Address comparators are + -- implemented. The Instruction Address comparators are numbered from 0 + -- to NUM_CODE - 1 + NUM_CODE_14_12 : FP_CTRL_NUM_CODE_14_12_Field := 16#5#; + -- unspecified + Reserved_15_27 : HAL.UInt13 := 16#0#; + -- Read-only. Flash Patch and Breakpoint Unit architecture revision + REV : FP_CTRL_REV_Field := 16#6#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + KEY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + NUM_CODE_7_4 at 0 range 4 .. 7; + NUM_LIT at 0 range 8 .. 11; + NUM_CODE_14_12 at 0 range 12 .. 14; + Reserved_15_27 at 0 range 15 .. 27; + REV at 0 range 28 .. 31; + end record; + + subtype FP_REMAP_REMAP_Field is HAL.UInt24; + + -- Indicates whether the implementation supports Flash Patch remap and, if + -- it does, holds the target address for remap + type FP_REMAP_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5; + -- Read-only. Holds the bits[28:5] of the Flash Patch remap address + REMAP : FP_REMAP_REMAP_Field; + -- Read-only. Indicates whether the FPB unit supports the Flash Patch + -- remap function + RMPSPT : Boolean; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_REMAP_Register use record + Reserved_0_4 at 0 range 0 .. 4; + REMAP at 0 range 5 .. 28; + RMPSPT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Holds an address for comparison. The effect of the match depends on the + -- configuration of the FPB and whether the comparator is an instruction + -- address comparator or a literal address comparator + type FP_COMP_Register is record + -- Selects between flashpatch and breakpoint functionality + BE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_COMP_Register use record + BE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype FP_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype FP_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype FP_DEVARCH_REVISION_Field is HAL.UInt4; + subtype FP_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the FPB + type FP_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : FP_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : FP_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : FP_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : FP_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype FP_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype FP_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FPB + type FP_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : FP_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : FP_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR4_DES_2_Field is HAL.UInt4; + subtype FP_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : FP_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : FP_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : FP_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR1_PART_1_Field is HAL.UInt4; + subtype FP_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : FP_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : FP_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR2_DES_1_Field is HAL.UInt3; + subtype FP_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : FP_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : FP_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR3_CMOD_Field is HAL.UInt4; + subtype FP_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : FP_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : FP_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : FP_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype FP_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : FP_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : FP_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : FP_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : FP_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ICTR_INTLINESNUM_Field is HAL.UInt4; + + -- Provides information about the interrupt controller + type ICTR_Register is record + -- Read-only. Indicates the number of the highest implemented register + -- in each of the NVIC control register sets, or in the case of + -- NVIC_IPR*n, 4×INTLINESNUM + INTLINESNUM : ICTR_INTLINESNUM_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICTR_Register use record + INTLINESNUM at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Provides IMPLEMENTATION DEFINED configuration and control options + type ACTLR_Register is record + -- Disable dual-issue. + DISMCYCINT : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Disable dual-issue. + DISFOLD : Boolean := False; + -- unspecified + Reserved_3_8 : HAL.UInt6 := 16#0#; + -- Disable out-of-order FP instruction completion + DISOOFP : Boolean := False; + -- Disable FPU exception outputs + FPEXCODIS : Boolean := False; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Disable ATB Flush + DISITMATBFLUSH : Boolean := False; + -- unspecified + Reserved_13_28 : HAL.UInt16 := 16#0#; + -- External Exclusives Allowed with no MPU + EXTEXCLALL : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACTLR_Register use record + DISMCYCINT at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DISFOLD at 0 range 2 .. 2; + Reserved_3_8 at 0 range 3 .. 8; + DISOOFP at 0 range 9 .. 9; + FPEXCODIS at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + DISITMATBFLUSH at 0 range 12 .. 12; + Reserved_13_28 at 0 range 13 .. 28; + EXTEXCLALL at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Use the SysTick Control and Status Register to enable the SysTick + -- features. + type SYST_CSR_Register is record + -- Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled. + ENABLE : Boolean := False; + -- Enables SysTick exception request: 0 = Counting down to zero does not + -- assert the SysTick exception request. 1 = Counting down to zero to + -- asserts the SysTick exception request. + TICKINT : Boolean := False; + -- SysTick clock source. Always reads as one if SYST_CALIB reports + -- NOREF. Selects the SysTick timer clock source: 0 = External reference + -- clock. 1 = Processor clock. + CLKSOURCE : Boolean := False; + -- unspecified + Reserved_3_15 : HAL.UInt13 := 16#0#; + -- Read-only. Returns 1 if timer counted to 0 since last time this was + -- read. Clears on read by application or debugger. + COUNTFLAG : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CSR_Register use record + ENABLE at 0 range 0 .. 0; + TICKINT at 0 range 1 .. 1; + CLKSOURCE at 0 range 2 .. 2; + Reserved_3_15 at 0 range 3 .. 15; + COUNTFLAG at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype SYST_RVR_RELOAD_Field is HAL.UInt24; + + -- Use the SysTick Reload Value Register to specify the start value to load + -- into the current value register when the counter reaches 0. It can be + -- any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but + -- has no effect because the SysTick interrupt and COUNTFLAG are activated + -- when counting from 1 to 0. The reset value of this register is UNKNOWN. + -- To generate a multi-shot timer with a period of N processor clock + -- cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt + -- is required every 100 clock pulses, set RELOAD to 99. + type SYST_RVR_Register is record + -- Value to load into the SysTick Current Value Register when the + -- counter reaches 0. + RELOAD : SYST_RVR_RELOAD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_RVR_Register use record + RELOAD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SYST_CVR_CURRENT_Field is HAL.UInt24; + + -- Use the SysTick Current Value Register to find the current value in the + -- register. The reset value of this register is UNKNOWN. + type SYST_CVR_Register is record + -- Reads return the current value of the SysTick counter. This register + -- is write-clear. Writing to it with any value clears the register to + -- 0. Clearing this register also clears the COUNTFLAG bit of the + -- SysTick Control and Status Register. + CURRENT : SYST_CVR_CURRENT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CVR_Register use record + CURRENT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SYST_CALIB_TENMS_Field is HAL.UInt24; + + -- Use the SysTick Calibration Value Register to enable software to scale + -- to any required speed using divide and multiply. + type SYST_CALIB_Register is record + -- Read-only. An optional Reload value to be used for 10ms (100Hz) + -- timing, subject to system clock skew errors. If the value reads as 0, + -- the calibration value is not known. + TENMS : SYST_CALIB_TENMS_Field; + -- unspecified + Reserved_24_29 : HAL.UInt6; + -- Read-only. If reads as 1, the calibration value for 10ms is inexact + -- (due to clock frequency). + SKEW : Boolean; + -- Read-only. If reads as 1, the Reference clock is not provided - the + -- CLKSOURCE bit of the SysTick Control and Status register will be + -- forced to 1 and cannot be cleared to 0. + NOREF : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CALIB_Register use record + TENMS at 0 range 0 .. 23; + Reserved_24_29 at 0 range 24 .. 29; + SKEW at 0 range 30 .. 30; + NOREF at 0 range 31 .. 31; + end record; + + subtype NVIC_IPR_PRI_N0_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N1_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N2_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N3_Field is HAL.UInt4; + + -- Sets or reads interrupt priorities + type NVIC_IPR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+0, or + -- RES0 if the PE does not implement this interrupt + PRI_N0 : NVIC_IPR_PRI_N0_Field := 16#0#; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+1, or + -- RES0 if the PE does not implement this interrupt + PRI_N1 : NVIC_IPR_PRI_N1_Field := 16#0#; + -- unspecified + Reserved_16_19 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+2, or + -- RES0 if the PE does not implement this interrupt + PRI_N2 : NVIC_IPR_PRI_N2_Field := 16#0#; + -- unspecified + Reserved_24_27 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+3, or + -- RES0 if the PE does not implement this interrupt + PRI_N3 : NVIC_IPR_PRI_N3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NVIC_IPR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + PRI_N0 at 0 range 4 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + PRI_N1 at 0 range 12 .. 15; + Reserved_16_19 at 0 range 16 .. 19; + PRI_N2 at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + PRI_N3 at 0 range 28 .. 31; + end record; + + subtype CPUID_REVISION_Field is HAL.UInt4; + subtype CPUID_PARTNO_Field is HAL.UInt12; + subtype CPUID_ARCHITECTURE_Field is HAL.UInt4; + subtype CPUID_VARIANT_Field is HAL.UInt4; + subtype CPUID_IMPLEMENTER_Field is HAL.UInt8; + + -- Provides identification information for the PE, including an implementer + -- code for the device and a device ID number + type CPUID_Register is record + -- Read-only. IMPLEMENTATION DEFINED revision number for the device + REVISION : CPUID_REVISION_Field; + -- Read-only. IMPLEMENTATION DEFINED primary part number for the device + PARTNO : CPUID_PARTNO_Field; + -- Read-only. Defines the Architecture implemented by the PE + ARCHITECTURE : CPUID_ARCHITECTURE_Field; + -- Read-only. IMPLEMENTATION DEFINED variant number. Typically, this + -- field is used to distinguish between different product variants, or + -- major revisions of a product + VARIANT : CPUID_VARIANT_Field; + -- Read-only. This field must hold an implementer code that has been + -- assigned by ARM + IMPLEMENTER : CPUID_IMPLEMENTER_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPUID_Register use record + REVISION at 0 range 0 .. 3; + PARTNO at 0 range 4 .. 15; + ARCHITECTURE at 0 range 16 .. 19; + VARIANT at 0 range 20 .. 23; + IMPLEMENTER at 0 range 24 .. 31; + end record; + + subtype ICSR_VECTACTIVE_Field is HAL.UInt9; + subtype ICSR_VECTPENDING_Field is HAL.UInt9; + + -- Controls and provides status information for NMI, PendSV, SysTick and + -- interrupts + type ICSR_Register is record + -- Read-only. The exception number of the current executing exception + VECTACTIVE : ICSR_VECTACTIVE_Field := 16#0#; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- Read-only. In Handler mode, indicates whether there is more than one + -- active exception + RETTOBASE : Boolean := False; + -- Read-only. The exception number of the highest priority pending and + -- enabled interrupt + VECTPENDING : ICSR_VECTPENDING_Field := 16#0#; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Read-only. Indicates whether an external interrupt, generated by the + -- NVIC, is pending + ISRPENDING : Boolean := False; + -- Read-only. Indicates whether a pending exception will be serviced on + -- exit from debug halt state + ISRPREEMPT : Boolean := False; + -- Controls whether in a single SysTick implementation, the SysTick is + -- Secure or Non-secure + STTNS : Boolean := False; + -- Allows the SysTick exception pend state to be cleared `FTSSS + PENDSTCLR : Boolean := False; + -- Read-only. Indicates whether the SysTick `FTSSS exception is pending + PENDSTSET : Boolean := False; + -- Allows the PendSV exception pend state to be cleared `FTSSS + PENDSVCLR : Boolean := False; + -- Read-only. Indicates whether the PendSV `FTSSS exception is pending + PENDSVSET : Boolean := False; + -- unspecified + Reserved_29_29 : HAL.Bit := 16#0#; + -- Allows the NMI exception pend state to be cleared + PENDNMICLR : Boolean := False; + -- Read-only. Indicates whether the NMI exception is pending + PENDNMISET : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICSR_Register use record + VECTACTIVE at 0 range 0 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + RETTOBASE at 0 range 11 .. 11; + VECTPENDING at 0 range 12 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + ISRPENDING at 0 range 22 .. 22; + ISRPREEMPT at 0 range 23 .. 23; + STTNS at 0 range 24 .. 24; + PENDSTCLR at 0 range 25 .. 25; + PENDSTSET at 0 range 26 .. 26; + PENDSVCLR at 0 range 27 .. 27; + PENDSVSET at 0 range 28 .. 28; + Reserved_29_29 at 0 range 29 .. 29; + PENDNMICLR at 0 range 30 .. 30; + PENDNMISET at 0 range 31 .. 31; + end record; + + subtype VTOR_TBLOFF_Field is HAL.UInt25; + + -- The VTOR indicates the offset of the vector table base address from + -- memory address 0x00000000. + type VTOR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Vector table base offset field. It contains bits[31:7] of the offset + -- of the table base from the bottom of the memory map. + TBLOFF : VTOR_TBLOFF_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VTOR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + TBLOFF at 0 range 7 .. 31; + end record; + + subtype AIRCR_PRIGROUP_Field is HAL.UInt3; + subtype AIRCR_VECTKEY_Field is HAL.UInt16; + + -- Use the Application Interrupt and Reset Control Register to: determine + -- data endianness, clear all active state information from debug halt + -- mode, request a system reset. + type AIRCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Clears all active state information for fixed and configurable + -- exceptions. This bit: is self-clearing, can only be set by the DAP + -- when the core is halted. When set: clears all active exception status + -- of the processor, forces a return to Thread mode, forces an IPSR of + -- 0. A debugger must re-initialize the stack. + VECTCLRACTIVE : Boolean := False; + -- Writing 1 to this bit causes the SYSRESETREQ signal to the outer + -- system to be asserted to request a reset. The intention is to force a + -- large system reset of all major components except for debug. The + -- C_HALT bit in the DHCSR is cleared as a result of the system reset + -- requested. The debugger does not lose contact with the device. + SYSRESETREQ : Boolean := False; + -- System reset request, Secure state only. 0 SYSRESETREQ functionality + -- is available to both Security states. 1 SYSRESETREQ functionality is + -- only available to Secure state. + SYSRESETREQS : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Interrupt priority grouping field. This field determines the split of + -- group priority from subpriority. See + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + PRIGROUP : AIRCR_PRIGROUP_Field := 16#0#; + -- unspecified + Reserved_11_12 : HAL.UInt2 := 16#0#; + -- BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, + -- HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and + -- exceptions can target Non-secure HardFault. + BFHFNMINS : Boolean := False; + -- Prioritize Secure exceptions. The value of this bit defines whether + -- Secure exception priority boosting is enabled. 0 Priority ranges of + -- Secure and Non-secure exceptions are identical. 1 Non-secure + -- exceptions are de-prioritized. + PRIS : Boolean := False; + -- Read-only. Data endianness implemented: 0 = Little-endian. + ENDIANESS : Boolean := False; + -- Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, + -- otherwise the write is ignored. + VECTKEY : AIRCR_VECTKEY_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AIRCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTCLRACTIVE at 0 range 1 .. 1; + SYSRESETREQ at 0 range 2 .. 2; + SYSRESETREQS at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + PRIGROUP at 0 range 8 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + BFHFNMINS at 0 range 13 .. 13; + PRIS at 0 range 14 .. 14; + ENDIANESS at 0 range 15 .. 15; + VECTKEY at 0 range 16 .. 31; + end record; + + -- System Control Register. Use the System Control Register for + -- power-management functions: signal to the system when the processor can + -- enter a low power state, control how the processor enters and exits low + -- power states. + type SCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Indicates sleep-on-exit when returning from Handler mode to Thread + -- mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter + -- sleep, or deep sleep, on return from an ISR to Thread mode. Setting + -- this bit to 1 enables an interrupt driven application to avoid + -- returning to an empty main application. + SLEEPONEXIT : Boolean := False; + -- Controls whether the processor uses sleep or deep sleep as its low + -- power mode: 0 = Sleep. 1 = Deep sleep. + SLEEPDEEP : Boolean := False; + -- 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only + -- available to Secure state + SLEEPDEEPS : Boolean := False; + -- Send Event on Pending bit: 0 = Only enabled interrupts or events can + -- wakeup the processor, disabled interrupts are excluded. 1 = Enabled + -- events and all interrupts, including disabled interrupts, can wakeup + -- the processor. When an event or interrupt becomes pending, the event + -- signal wakes up the processor from WFE. If the processor is not + -- waiting for an event, the event is registered and affects the next + -- WFE. The processor also wakes up on execution of an SEV instruction + -- or an external event. + SEVONPEND : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SLEEPONEXIT at 0 range 1 .. 1; + SLEEPDEEP at 0 range 2 .. 2; + SLEEPDEEPS at 0 range 3 .. 3; + SEVONPEND at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Sets or returns configuration and control data + type CCR_Register is record + -- Read-only. Reserved, RES1 + RES1_1 : Boolean := True; + -- Determines whether unprivileged accesses are permitted to pend + -- interrupts via the STIR + USERSETMPEND : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Controls the trapping of unaligned word or halfword accesses + UNALIGN_TRP : Boolean := False; + -- Controls the generation of a DIVBYZERO UsageFault when attempting to + -- perform integer division by zero + DIV_0_TRP : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Determines the effect of precise BusFaults on handlers running at a + -- requested priority less than 0 + BFHFNMIGN : Boolean := False; + -- Read-only. Reserved, RES1 + RES1 : Boolean := True; + -- Controls the effect of a stack limit violation while executing at a + -- requested priority less than 0 + STKOFHFNMIGN : Boolean := False; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Read-only. Enables data caching of all data accesses to Normal memory + -- `FTSSS + DC : Boolean := False; + -- Read-only. This is a global enable bit for instruction caches in the + -- selected Security state + IC : Boolean := False; + -- Read-only. Enables program flow prediction `FTSSS + BP : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR_Register use record + RES1_1 at 0 range 0 .. 0; + USERSETMPEND at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + UNALIGN_TRP at 0 range 3 .. 3; + DIV_0_TRP at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + BFHFNMIGN at 0 range 8 .. 8; + RES1 at 0 range 9 .. 9; + STKOFHFNMIGN at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + DC at 0 range 16 .. 16; + IC at 0 range 17 .. 17; + BP at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype SHPR1_PRI_4_3_Field is HAL.UInt3; + subtype SHPR1_PRI_5_3_Field is HAL.UInt3; + subtype SHPR1_PRI_6_3_Field is HAL.UInt3; + subtype SHPR1_PRI_7_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 4 - 7 + type SHPR1_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Priority of system handler 4, SecureFault + PRI_4_3 : SHPR1_PRI_4_3_Field := 16#0#; + -- unspecified + Reserved_8_12 : HAL.UInt5 := 16#0#; + -- Priority of system handler 5, SecureFault + PRI_5_3 : SHPR1_PRI_5_3_Field := 16#0#; + -- unspecified + Reserved_16_20 : HAL.UInt5 := 16#0#; + -- Priority of system handler 6, SecureFault + PRI_6_3 : SHPR1_PRI_6_3_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 7, SecureFault + PRI_7_3 : SHPR1_PRI_7_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR1_Register use record + Reserved_0_4 at 0 range 0 .. 4; + PRI_4_3 at 0 range 5 .. 7; + Reserved_8_12 at 0 range 8 .. 12; + PRI_5_3 at 0 range 13 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + PRI_6_3 at 0 range 21 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_7_3 at 0 range 29 .. 31; + end record; + + subtype SHPR2_PRI_8_Field is HAL.UInt8; + subtype SHPR2_PRI_9_Field is HAL.UInt8; + subtype SHPR2_PRI_10_Field is HAL.UInt8; + subtype SHPR2_PRI_11_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 8 - 11 + type SHPR2_Register is record + -- Read-only. Reserved, RES0 + PRI_8 : SHPR2_PRI_8_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_9 : SHPR2_PRI_9_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_10 : SHPR2_PRI_10_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 11, SecureFault + PRI_11_3 : SHPR2_PRI_11_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR2_Register use record + PRI_8 at 0 range 0 .. 7; + PRI_9 at 0 range 8 .. 15; + PRI_10 at 0 range 16 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_11_3 at 0 range 29 .. 31; + end record; + + subtype SHPR3_PRI_12_3_Field is HAL.UInt3; + subtype SHPR3_PRI_13_Field is HAL.UInt8; + subtype SHPR3_PRI_14_3_Field is HAL.UInt3; + subtype SHPR3_PRI_15_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 12 - 15 + type SHPR3_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Priority of system handler 12, SecureFault + PRI_12_3 : SHPR3_PRI_12_3_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_13 : SHPR3_PRI_13_Field := 16#0#; + -- unspecified + Reserved_16_20 : HAL.UInt5 := 16#0#; + -- Priority of system handler 14, SecureFault + PRI_14_3 : SHPR3_PRI_14_3_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 15, SecureFault + PRI_15_3 : SHPR3_PRI_15_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR3_Register use record + Reserved_0_4 at 0 range 0 .. 4; + PRI_12_3 at 0 range 5 .. 7; + PRI_13 at 0 range 8 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + PRI_14_3 at 0 range 21 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_15_3 at 0 range 29 .. 31; + end record; + + -- Provides access to the active and pending status of system exceptions + type SHCSR_Register is record + -- `IAAMO the active state of the MemManage exception `FTSSS + MEMFAULTACT : Boolean := False; + -- `IAAMO the active state of the BusFault exception + BUSFAULTACT : Boolean := False; + -- Indicates and allows limited modification of the active state of the + -- HardFault exception `FTSSS + HARDFAULTACT : Boolean := False; + -- `IAAMO the active state of the UsageFault exception `FTSSS + USGFAULTACT : Boolean := False; + -- `IAAMO the active state of the SecureFault exception + SECUREFAULTACT : Boolean := False; + -- `IAAMO the active state of the NMI exception + NMIACT : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- `IAAMO the active state of the SVCall exception `FTSSS + SVCALLACT : Boolean := False; + -- `IAAMO the active state of the DebugMonitor exception + MONITORACT : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- `IAAMO the active state of the PendSV exception `FTSSS + PENDSVACT : Boolean := False; + -- `IAAMO the active state of the SysTick exception `FTSSS + SYSTICKACT : Boolean := False; + -- The UsageFault exception is banked between Security states, `IAAMO + -- the pending state of the UsageFault exception `FTSSS + USGFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the MemManage exception `FTSSS + MEMFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the BusFault exception + BUSFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the SVCall exception `FTSSS + SVCALLPENDED : Boolean := False; + -- `DW the MemManage exception is enabled `FTSSS + MEMFAULTENA : Boolean := False; + -- `DW the BusFault exception is enabled + BUSFAULTENA : Boolean := False; + -- `DW the UsageFault exception is enabled `FTSSS + USGFAULTENA : Boolean := False; + -- `DW the SecureFault exception is enabled + SECUREFAULTENA : Boolean := False; + -- `IAAMO the pending state of the SecureFault exception + SECUREFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the HardFault exception `CTTSSS + HARDFAULTPENDED : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHCSR_Register use record + MEMFAULTACT at 0 range 0 .. 0; + BUSFAULTACT at 0 range 1 .. 1; + HARDFAULTACT at 0 range 2 .. 2; + USGFAULTACT at 0 range 3 .. 3; + SECUREFAULTACT at 0 range 4 .. 4; + NMIACT at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + SVCALLACT at 0 range 7 .. 7; + MONITORACT at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PENDSVACT at 0 range 10 .. 10; + SYSTICKACT at 0 range 11 .. 11; + USGFAULTPENDED at 0 range 12 .. 12; + MEMFAULTPENDED at 0 range 13 .. 13; + BUSFAULTPENDED at 0 range 14 .. 14; + SVCALLPENDED at 0 range 15 .. 15; + MEMFAULTENA at 0 range 16 .. 16; + BUSFAULTENA at 0 range 17 .. 17; + USGFAULTENA at 0 range 18 .. 18; + SECUREFAULTENA at 0 range 19 .. 19; + SECUREFAULTPENDED at 0 range 20 .. 20; + HARDFAULTPENDED at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype CFSR_MMFSR_Field is HAL.UInt8; + + -- Contains the three Configurable Fault Status Registers. 31:16 UFSR: + -- Provides information on UsageFault exceptions 15:8 BFSR: Provides + -- information on BusFault exceptions 7:0 MMFSR: Provides information on + -- MemManage exceptions + type CFSR_Register is record + -- Provides information on MemManage exceptions + MMFSR : CFSR_MMFSR_Field := 16#0#; + -- Records whether a BusFault on an instruction prefetch has occurred + BFSR_IBUSERR : Boolean := False; + -- Records whether a precise data access error has occurred + BFSR_PRECISERR : Boolean := False; + -- Records whether an imprecise data access error has occurred + BFSR_IMPRECISERR : Boolean := False; + -- Records whether a derived BusFault occurred during exception return + -- unstacking + BFSR_UNSTKERR : Boolean := False; + -- Records whether a derived BusFault occurred during exception entry + -- stacking + BFSR_STKERR : Boolean := False; + -- Records whether a BusFault occurred during FP lazy state preservation + BFSR_LSPERR : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Indicates validity of the contents of the BFAR register + BFSR_BFARVALID : Boolean := False; + -- Sticky flag indicating whether an undefined instruction error has + -- occurred + UFSR_UNDEFINSTR : Boolean := False; + -- Sticky flag indicating whether an EPSR.T or EPSR.IT validity error + -- has occurred + UFSR_INVSTATE : Boolean := False; + -- Sticky flag indicating whether an integrity check error has occurred + UFSR_INVPC : Boolean := False; + -- Sticky flag indicating whether a coprocessor disabled or not present + -- error has occurred + UFSR_NOCP : Boolean := False; + -- Sticky flag indicating whether a stack overflow error has occurred + UFSR_STKOF : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Sticky flag indicating whether an unaligned access error has occurred + UFSR_UNALIGNED : Boolean := False; + -- Sticky flag indicating whether an integer division by zero error has + -- occurred + UFSR_DIVBYZERO : Boolean := False; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFSR_Register use record + MMFSR at 0 range 0 .. 7; + BFSR_IBUSERR at 0 range 8 .. 8; + BFSR_PRECISERR at 0 range 9 .. 9; + BFSR_IMPRECISERR at 0 range 10 .. 10; + BFSR_UNSTKERR at 0 range 11 .. 11; + BFSR_STKERR at 0 range 12 .. 12; + BFSR_LSPERR at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + BFSR_BFARVALID at 0 range 15 .. 15; + UFSR_UNDEFINSTR at 0 range 16 .. 16; + UFSR_INVSTATE at 0 range 17 .. 17; + UFSR_INVPC at 0 range 18 .. 18; + UFSR_NOCP at 0 range 19 .. 19; + UFSR_STKOF at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + UFSR_UNALIGNED at 0 range 24 .. 24; + UFSR_DIVBYZERO at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Shows the cause of any HardFaults + type HFSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Indicates when a fault has occurred because of a vector table read + -- error on exception processing + VECTTBL : Boolean := False; + -- unspecified + Reserved_2_29 : HAL.UInt28 := 16#0#; + -- Indicates that a fault with configurable priority has been escalated + -- to a HardFault exception, because it could not be made active, + -- because of priority, or because it was disabled + FORCED : Boolean := False; + -- Indicates when a Debug event has occurred + DEBUGEVT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTTBL at 0 range 1 .. 1; + Reserved_2_29 at 0 range 2 .. 29; + FORCED at 0 range 30 .. 30; + DEBUGEVT at 0 range 31 .. 31; + end record; + + -- Shows which debug event occurred + type DFSR_Register is record + -- Sticky flag indicating that a Halt request debug event or Step debug + -- event has occurred + HALTED : Boolean := False; + -- Sticky flag indicating whether a Breakpoint debug event has occurred + BKPT : Boolean := False; + -- Sticky flag indicating whether a Watchpoint debug event has occurred + DWTTRAP : Boolean := False; + -- Sticky flag indicating whether a Vector catch debug event has + -- occurred + VCATCH : Boolean := False; + -- Sticky flag indicating whether an External debug request debug event + -- has occurred + EXTERNAL : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DFSR_Register use record + HALTED at 0 range 0 .. 0; + BKPT at 0 range 1 .. 1; + DWTTRAP at 0 range 2 .. 2; + VCATCH at 0 range 3 .. 3; + EXTERNAL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- ID_PFR0_STATE array element + subtype ID_PFR0_STATE_Element is HAL.UInt4; + + -- ID_PFR0_STATE array + type ID_PFR0_STATE_Field_Array is array (0 .. 1) of ID_PFR0_STATE_Element + with Component_Size => 4, Size => 8; + + -- Type definition for ID_PFR0_STATE + type ID_PFR0_STATE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- STATE as a value + Val : HAL.UInt8; + when True => + -- STATE as an array + Arr : ID_PFR0_STATE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for ID_PFR0_STATE_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Gives top-level information about the instruction set supported by the + -- PE + type ID_PFR0_Register is record + -- Read-only. A32 instruction set support + STATE : ID_PFR0_STATE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_PFR0_Register use record + STATE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ID_PFR1_SECURITY_Field is HAL.UInt4; + subtype ID_PFR1_MPROGMOD_Field is HAL.UInt4; + + -- Gives information about the programmers' model and Extensions support + type ID_PFR1_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Identifies whether the Security Extension is implemented + SECURITY : ID_PFR1_SECURITY_Field; + -- Read-only. Identifies support for the M-Profile programmers' model + -- support + MPROGMOD : ID_PFR1_MPROGMOD_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_PFR1_Register use record + Reserved_0_3 at 0 range 0 .. 3; + SECURITY at 0 range 4 .. 7; + MPROGMOD at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype ID_DFR0_MPROFDBG_Field is HAL.UInt4; + + -- Provides top level information about the debug system + type ID_DFR0_Register is record + -- unspecified + Reserved_0_19 : HAL.UInt20; + -- Read-only. Indicates the supported M-profile debug architecture + MPROFDBG : ID_DFR0_MPROFDBG_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_DFR0_Register use record + Reserved_0_19 at 0 range 0 .. 19; + MPROFDBG at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- ID_AFR0_IMPDEF array element + subtype ID_AFR0_IMPDEF_Element is HAL.UInt4; + + -- ID_AFR0_IMPDEF array + type ID_AFR0_IMPDEF_Field_Array is array (0 .. 3) + of ID_AFR0_IMPDEF_Element + with Component_Size => 4, Size => 16; + + -- Type definition for ID_AFR0_IMPDEF + type ID_AFR0_IMPDEF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IMPDEF as a value + Val : HAL.UInt16; + when True => + -- IMPDEF as an array + Arr : ID_AFR0_IMPDEF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for ID_AFR0_IMPDEF_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Provides information about the IMPLEMENTATION DEFINED features of the PE + type ID_AFR0_Register is record + -- Read-only. IMPLEMENTATION DEFINED meaning + IMPDEF : ID_AFR0_IMPDEF_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_AFR0_Register use record + IMPDEF at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ID_MMFR0_PMSA_Field is HAL.UInt4; + subtype ID_MMFR0_OUTERSHR_Field is HAL.UInt4; + subtype ID_MMFR0_SHARELVL_Field is HAL.UInt4; + subtype ID_MMFR0_TCM_Field is HAL.UInt4; + subtype ID_MMFR0_AUXREG_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR0_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates support for the protected memory system + -- architecture (PMSA) + PMSA : ID_MMFR0_PMSA_Field; + -- Read-only. Indicates the outermost shareability domain implemented + OUTERSHR : ID_MMFR0_OUTERSHR_Field; + -- Read-only. Indicates the number of shareability levels implemented + SHARELVL : ID_MMFR0_SHARELVL_Field; + -- Read-only. Indicates support for tightly coupled memories (TCMs) + TCM : ID_MMFR0_TCM_Field; + -- Read-only. Indicates support for Auxiliary Control Registers + AUXREG : ID_MMFR0_AUXREG_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR0_Register use record + Reserved_0_3 at 0 range 0 .. 3; + PMSA at 0 range 4 .. 7; + OUTERSHR at 0 range 8 .. 11; + SHARELVL at 0 range 12 .. 15; + TCM at 0 range 16 .. 19; + AUXREG at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype ID_MMFR2_WFISTALL_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR2_Register is record + -- unspecified + Reserved_0_23 : HAL.UInt24; + -- Read-only. Indicates the support for Wait For Interrupt (WFI) + -- stalling + WFISTALL : ID_MMFR2_WFISTALL_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR2_Register use record + Reserved_0_23 at 0 range 0 .. 23; + WFISTALL at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_MMFR3_CMAINTVA_Field is HAL.UInt4; + subtype ID_MMFR3_CMAINTSW_Field is HAL.UInt4; + subtype ID_MMFR3_BPMAINT_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR3_Register is record + -- Read-only. Indicates the supported cache maintenance operations by + -- address + CMAINTVA : ID_MMFR3_CMAINTVA_Field; + -- Read-only. Indicates the supported cache maintenance operations by + -- set/way + CMAINTSW : ID_MMFR3_CMAINTSW_Field; + -- Read-only. Indicates the supported branch predictor maintenance + BPMAINT : ID_MMFR3_BPMAINT_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR3_Register use record + CMAINTVA at 0 range 0 .. 3; + CMAINTSW at 0 range 4 .. 7; + BPMAINT at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype ID_ISAR0_BITCOUNT_Field is HAL.UInt4; + subtype ID_ISAR0_BITFIELD_Field is HAL.UInt4; + subtype ID_ISAR0_CMPBRANCH_Field is HAL.UInt4; + subtype ID_ISAR0_COPROC_Field is HAL.UInt4; + subtype ID_ISAR0_DEBUG_Field is HAL.UInt4; + subtype ID_ISAR0_DIVIDE_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR0_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates the supported bit count instructions + BITCOUNT : ID_ISAR0_BITCOUNT_Field; + -- Read-only. Indicates the supported bit field instructions + BITFIELD : ID_ISAR0_BITFIELD_Field; + -- Read-only. Indicates the supported combined Compare and Branch + -- instructions + CMPBRANCH : ID_ISAR0_CMPBRANCH_Field; + -- Read-only. Indicates the supported Coprocessor instructions + COPROC : ID_ISAR0_COPROC_Field; + -- Read-only. Indicates the implemented Debug instructions + DEBUG : ID_ISAR0_DEBUG_Field; + -- Read-only. Indicates the supported Divide instructions + DIVIDE : ID_ISAR0_DIVIDE_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR0_Register use record + Reserved_0_3 at 0 range 0 .. 3; + BITCOUNT at 0 range 4 .. 7; + BITFIELD at 0 range 8 .. 11; + CMPBRANCH at 0 range 12 .. 15; + COPROC at 0 range 16 .. 19; + DEBUG at 0 range 20 .. 23; + DIVIDE at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR1_EXTEND_Field is HAL.UInt4; + subtype ID_ISAR1_IFTHEN_Field is HAL.UInt4; + subtype ID_ISAR1_IMMEDIATE_Field is HAL.UInt4; + subtype ID_ISAR1_INTERWORK_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR1_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12; + -- Read-only. Indicates the implemented Extend instructions + EXTEND : ID_ISAR1_EXTEND_Field; + -- Read-only. Indicates the implemented If-Then instructions + IFTHEN : ID_ISAR1_IFTHEN_Field; + -- Read-only. Indicates the implemented for data-processing instructions + -- with long immediates + IMMEDIATE : ID_ISAR1_IMMEDIATE_Field; + -- Read-only. Indicates the implemented Interworking instructions + INTERWORK : ID_ISAR1_INTERWORK_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR1_Register use record + Reserved_0_11 at 0 range 0 .. 11; + EXTEND at 0 range 12 .. 15; + IFTHEN at 0 range 16 .. 19; + IMMEDIATE at 0 range 20 .. 23; + INTERWORK at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR2_LOADSTORE_Field is HAL.UInt4; + subtype ID_ISAR2_MEMHINT_Field is HAL.UInt4; + subtype ID_ISAR2_MULTIACCESSINT_Field is HAL.UInt4; + subtype ID_ISAR2_MULT_Field is HAL.UInt4; + subtype ID_ISAR2_MULTS_Field is HAL.UInt4; + subtype ID_ISAR2_MULTU_Field is HAL.UInt4; + subtype ID_ISAR2_REVERSAL_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR2_Register is record + -- Read-only. Indicates the implemented additional load/store + -- instructions + LOADSTORE : ID_ISAR2_LOADSTORE_Field; + -- Read-only. Indicates the implemented Memory Hint instructions + MEMHINT : ID_ISAR2_MEMHINT_Field; + -- Read-only. Indicates the support for interruptible multi-access + -- instructions + MULTIACCESSINT : ID_ISAR2_MULTIACCESSINT_Field; + -- Read-only. Indicates the implemented additional Multiply instructions + MULT : ID_ISAR2_MULT_Field; + -- Read-only. Indicates the implemented advanced signed Multiply + -- instructions + MULTS : ID_ISAR2_MULTS_Field; + -- Read-only. Indicates the implemented advanced unsigned Multiply + -- instructions + MULTU : ID_ISAR2_MULTU_Field; + -- unspecified + Reserved_24_27 : HAL.UInt4; + -- Read-only. Indicates the implemented Reversal instructions + REVERSAL : ID_ISAR2_REVERSAL_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR2_Register use record + LOADSTORE at 0 range 0 .. 3; + MEMHINT at 0 range 4 .. 7; + MULTIACCESSINT at 0 range 8 .. 11; + MULT at 0 range 12 .. 15; + MULTS at 0 range 16 .. 19; + MULTU at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + REVERSAL at 0 range 28 .. 31; + end record; + + subtype ID_ISAR3_SATURATE_Field is HAL.UInt4; + subtype ID_ISAR3_SIMD_Field is HAL.UInt4; + subtype ID_ISAR3_SVC_Field is HAL.UInt4; + subtype ID_ISAR3_SYNCHPRIM_Field is HAL.UInt4; + subtype ID_ISAR3_TABBRANCH_Field is HAL.UInt4; + subtype ID_ISAR3_T32COPY_Field is HAL.UInt4; + subtype ID_ISAR3_TRUENOP_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR3_Register is record + -- Read-only. Indicates the implemented saturating instructions + SATURATE : ID_ISAR3_SATURATE_Field; + -- Read-only. Indicates the implemented SIMD instructions + SIMD : ID_ISAR3_SIMD_Field; + -- Read-only. Indicates the implemented SVC instructions + SVC : ID_ISAR3_SVC_Field; + -- Read-only. Used in conjunction with ID_ISAR4.SynchPrim_frac to + -- indicate the implemented Synchronization Primitive instructions + SYNCHPRIM : ID_ISAR3_SYNCHPRIM_Field; + -- Read-only. Indicates the implemented Table Branch instructions + TABBRANCH : ID_ISAR3_TABBRANCH_Field; + -- Read-only. Indicates the support for T32 non flag-setting MOV + -- instructions + T32COPY : ID_ISAR3_T32COPY_Field; + -- Read-only. Indicates the implemented true NOP instructions + TRUENOP : ID_ISAR3_TRUENOP_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR3_Register use record + SATURATE at 0 range 0 .. 3; + SIMD at 0 range 4 .. 7; + SVC at 0 range 8 .. 11; + SYNCHPRIM at 0 range 12 .. 15; + TABBRANCH at 0 range 16 .. 19; + T32COPY at 0 range 20 .. 23; + TRUENOP at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR4_UNPRIV_Field is HAL.UInt4; + subtype ID_ISAR4_WITHSHIFTS_Field is HAL.UInt4; + subtype ID_ISAR4_WRITEBACK_Field is HAL.UInt4; + subtype ID_ISAR4_BARRIER_Field is HAL.UInt4; + subtype ID_ISAR4_SYNCPRIM_FRAC_Field is HAL.UInt4; + subtype ID_ISAR4_PSR_M_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR4_Register is record + -- Read-only. Indicates the implemented unprivileged instructions + UNPRIV : ID_ISAR4_UNPRIV_Field; + -- Read-only. Indicates the support for writeback addressing modes + WITHSHIFTS : ID_ISAR4_WITHSHIFTS_Field; + -- Read-only. Indicates the support for writeback addressing modes + WRITEBACK : ID_ISAR4_WRITEBACK_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Indicates the implemented Barrier instructions + BARRIER : ID_ISAR4_BARRIER_Field; + -- Read-only. Used in conjunction with ID_ISAR3.SynchPrim to indicate + -- the implemented Synchronization Primitive instructions + SYNCPRIM_FRAC : ID_ISAR4_SYNCPRIM_FRAC_Field; + -- Read-only. Indicates the implemented M profile instructions to modify + -- the PSRs + PSR_M : ID_ISAR4_PSR_M_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR4_Register use record + UNPRIV at 0 range 0 .. 3; + WITHSHIFTS at 0 range 4 .. 7; + WRITEBACK at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + BARRIER at 0 range 16 .. 19; + SYNCPRIM_FRAC at 0 range 20 .. 23; + PSR_M at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype CTR_IMINLINE_Field is HAL.UInt4; + subtype CTR_RES1_1_Field is HAL.UInt2; + subtype CTR_DMINLINE_Field is HAL.UInt4; + subtype CTR_ERG_Field is HAL.UInt4; + subtype CTR_CWG_Field is HAL.UInt4; + + -- Provides information about the architecture of the caches. CTR is RES0 + -- if CLIDR is zero. + type CTR_Register is record + -- Read-only. Log2 of the number of words in the smallest cache line of + -- all the instruction caches that are controlled by the PE + IMINLINE : CTR_IMINLINE_Field; + -- unspecified + Reserved_4_13 : HAL.UInt10; + -- Read-only. Reserved, RES1 + RES1_1 : CTR_RES1_1_Field; + -- Read-only. Log2 of the number of words in the smallest cache line of + -- all the data caches and unified caches that are controlled by the PE + DMINLINE : CTR_DMINLINE_Field; + -- Read-only. Log2 of the number of words of the maximum size of the + -- reservation granule that has been implemented for the Load-Exclusive + -- and Store-Exclusive instructions + ERG : CTR_ERG_Field; + -- Read-only. Log2 of the number of words of the maximum size of memory + -- that can be overwritten as a result of the eviction of a cache entry + -- that has had a memory location in it modified + CWG : CTR_CWG_Field; + -- unspecified + Reserved_28_30 : HAL.UInt3; + -- Read-only. Reserved, RES1 + RES1 : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTR_Register use record + IMINLINE at 0 range 0 .. 3; + Reserved_4_13 at 0 range 4 .. 13; + RES1_1 at 0 range 14 .. 15; + DMINLINE at 0 range 16 .. 19; + ERG at 0 range 20 .. 23; + CWG at 0 range 24 .. 27; + Reserved_28_30 at 0 range 28 .. 30; + RES1 at 0 range 31 .. 31; + end record; + + -- CPACR_CP array element + subtype CPACR_CP_Element is HAL.UInt2; + + -- CPACR_CP array + type CPACR_CP_Field_Array is array (0 .. 7) of CPACR_CP_Element + with Component_Size => 2, Size => 16; + + -- Type definition for CPACR_CP + type CPACR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt16; + when True => + -- CP as an array + Arr : CPACR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for CPACR_CP_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- CPACR_CP array + type CPACR_CP_Field_Array_1 is array (10 .. 11) of CPACR_CP_Element + with Component_Size => 2, Size => 4; + + -- Type definition for CPACR_CP + type CPACR_CP_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt4; + when True => + -- CP as an array + Arr : CPACR_CP_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 4; + + for CPACR_CP_Field_1 use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Specifies the access privileges for coprocessors and the FP Extension + type CPACR_Register is record + -- Controls access privileges for coprocessor 0 + CP : CPACR_CP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_19 : HAL.UInt4 := 16#0#; + -- Defines the access rights for the floating-point functionality + CP_1 : CPACR_CP_Field_1 := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPACR_Register use record + CP at 0 range 0 .. 15; + Reserved_16_19 at 0 range 16 .. 19; + CP_1 at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- NSACR_CP array + type NSACR_CP_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for NSACR_CP + type NSACR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt8; + when True => + -- CP as an array + Arr : NSACR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for NSACR_CP_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- NSACR_CP array + type NSACR_CP_Field_Array_1 is array (10 .. 11) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for NSACR_CP + type NSACR_CP_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : NSACR_CP_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 2; + + for NSACR_CP_Field_1 use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Defines the Non-secure access permissions for both the FP Extension and + -- coprocessors CP0 to CP7 + type NSACR_Register is record + -- Enables Non-secure access to coprocessor CP0 + CP : NSACR_CP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Enables Non-secure access to the Floating-point Extension + CP_1 : NSACR_CP_Field_1 := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NSACR_Register use record + CP at 0 range 0 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + CP_1 at 0 range 10 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype MPU_TYPE_DREGION_Field is HAL.UInt8; + + -- The MPU Type Register indicates how many regions the MPU `FTSSS supports + type MPU_TYPE_Register is record + -- Read-only. Indicates support for separate instructions and data + -- address regions + SEPARATE_k : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Number of regions supported by the MPU + DREGION : MPU_TYPE_DREGION_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_TYPE_Register use record + SEPARATE_k at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + DREGION at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Enables the MPU and, when the MPU is enabled, controls whether the + -- default memory map is enabled as a background region for privileged + -- accesses, and whether the MPU is enabled for HardFaults, NMIs, and + -- exception handlers when FAULTMASK is set to 1 + type MPU_CTRL_Register is record + -- Enables the MPU + ENABLE : Boolean := False; + -- Controls whether handlers executing with priority less than 0 access + -- memory with the MPU enabled or disabled. This applies to HardFaults, + -- NMIs, and exception handlers when FAULTMASK is set to 1 + HFNMIENA : Boolean := False; + -- Controls whether the default memory map is enabled for privileged + -- software + PRIVDEFENA : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + HFNMIENA at 0 range 1 .. 1; + PRIVDEFENA at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_RNR_REGION_Field is HAL.UInt3; + + -- Selects the region currently accessed by MPU_RBAR and MPU_RLAR + type MPU_RNR_Register is record + -- Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + REGION : MPU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RNR_Register use record + REGION at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_RBAR_AP_Field is HAL.UInt2; + subtype MPU_RBAR_SH_Field is HAL.UInt2; + subtype MPU_RBAR_BASE_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the + -- currently selected MPU region `FTSSS + type MPU_RBAR_Register is record + -- Defines whether code can be executed from this region + XN : Boolean := False; + -- Defines the access permissions for this region + AP : MPU_RBAR_AP_Field := 16#0#; + -- Defines the Shareability domain of this region for Normal memory + SH : MPU_RBAR_SH_Field := 16#0#; + -- Contains bits [31:5] of the lower inclusive limit of the selected MPU + -- memory region. This value is zero extended to provide the base + -- address to be checked against + BASE : MPU_RBAR_BASE_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RBAR_Register use record + XN at 0 range 0 .. 0; + AP at 0 range 1 .. 2; + SH at 0 range 3 .. 4; + BASE at 0 range 5 .. 31; + end record; + + subtype MPU_RLAR_ATTRINDX_Field is HAL.UInt3; + subtype MPU_RLAR_LIMIT_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region `FTSSS + type MPU_RLAR_Register is record + -- Region enable + EN : Boolean := False; + -- Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + ATTRINDX : MPU_RLAR_ATTRINDX_Field := 16#0#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Contains bits [31:5] of the upper inclusive limit of the selected MPU + -- memory region. This value is postfixed with 0x1F to provide the limit + -- address to be checked against + LIMIT : MPU_RLAR_LIMIT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RLAR_Register use record + EN at 0 range 0 .. 0; + ATTRINDX at 0 range 1 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LIMIT at 0 range 5 .. 31; + end record; + + subtype MPU_RBAR_A_AP_Field is HAL.UInt2; + subtype MPU_RBAR_A_SH_Field is HAL.UInt2; + subtype MPU_RBAR_A_BASE_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the MPU + -- region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + type MPU_RBAR_A_Register is record + -- Defines whether code can be executed from this region + XN : Boolean := False; + -- Defines the access permissions for this region + AP : MPU_RBAR_A_AP_Field := 16#0#; + -- Defines the Shareability domain of this region for Normal memory + SH : MPU_RBAR_A_SH_Field := 16#0#; + -- Contains bits [31:5] of the lower inclusive limit of the selected MPU + -- memory region. This value is zero extended to provide the base + -- address to be checked against + BASE : MPU_RBAR_A_BASE_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RBAR_A_Register use record + XN at 0 range 0 .. 0; + AP at 0 range 1 .. 2; + SH at 0 range 3 .. 4; + BASE at 0 range 5 .. 31; + end record; + + subtype MPU_RLAR_A_ATTRINDX_Field is HAL.UInt3; + subtype MPU_RLAR_A_LIMIT_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + type MPU_RLAR_A_Register is record + -- Region enable + EN : Boolean := False; + -- Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + ATTRINDX : MPU_RLAR_A_ATTRINDX_Field := 16#0#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Contains bits [31:5] of the upper inclusive limit of the selected MPU + -- memory region. This value is postfixed with 0x1F to provide the limit + -- address to be checked against + LIMIT : MPU_RLAR_A_LIMIT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RLAR_A_Register use record + EN at 0 range 0 .. 0; + ATTRINDX at 0 range 1 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LIMIT at 0 range 5 .. 31; + end record; + + -- MPU_MAIR0_ATTR array element + subtype MPU_MAIR0_ATTR_Element is HAL.UInt8; + + -- MPU_MAIR0_ATTR array + type MPU_MAIR0_ATTR_Field_Array is array (0 .. 3) + of MPU_MAIR0_ATTR_Element + with Component_Size => 8, Size => 32; + + -- Along with MPU_MAIR1, provides the memory attribute encodings + -- corresponding to the AttrIndex values + type MPU_MAIR0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ATTR as a value + Val : HAL.UInt32; + when True => + -- ATTR as an array + Arr : MPU_MAIR0_ATTR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MAIR0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MPU_MAIR1_ATTR array element + subtype MPU_MAIR1_ATTR_Element is HAL.UInt8; + + -- MPU_MAIR1_ATTR array + type MPU_MAIR1_ATTR_Field_Array is array (4 .. 7) + of MPU_MAIR1_ATTR_Element + with Component_Size => 8, Size => 32; + + -- Along with MPU_MAIR0, provides the memory attribute encodings + -- corresponding to the AttrIndex values + type MPU_MAIR1_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ATTR as a value + Val : HAL.UInt32; + when True => + -- ATTR as an array + Arr : MPU_MAIR1_ATTR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MAIR1_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Allows enabling of the Security Attribution Unit + type SAU_CTRL_Register is record + -- Enables the SAU + ENABLE : Boolean := False; + -- When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked + -- as Non-secure or Secure + ALLNS : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + ALLNS at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype SAU_TYPE_SREGION_Field is HAL.UInt8; + + -- Indicates the number of regions implemented by the Security Attribution + -- Unit + type SAU_TYPE_Register is record + -- Read-only. The number of implemented SAU regions + SREGION : SAU_TYPE_SREGION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_TYPE_Register use record + SREGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype SAU_RNR_REGION_Field is HAL.UInt8; + + -- Selects the region currently accessed by SAU_RBAR and SAU_RLAR + type SAU_RNR_Register is record + -- Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + REGION : SAU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RNR_Register use record + REGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype SAU_RBAR_BADDR_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the + -- currently selected SAU region + type SAU_RBAR_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Holds bits [31:5] of the base address for the selected SAU region + BADDR : SAU_RBAR_BADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RBAR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + BADDR at 0 range 5 .. 31; + end record; + + subtype SAU_RLAR_LADDR_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected SAU region + type SAU_RLAR_Register is record + -- SAU region enable + ENABLE : Boolean := False; + -- Controls whether Non-secure state is permitted to execute an SG + -- instruction from this region + NSC : Boolean := False; + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- Holds bits [31:5] of the limit address for the selected SAU region + LADDR : SAU_RLAR_LADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RLAR_Register use record + ENABLE at 0 range 0 .. 0; + NSC at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + LADDR at 0 range 5 .. 31; + end record; + + -- Provides information about any security related faults + type SFSR_Register is record + -- This bit is set if a function call from the Non-secure state or + -- exception targets a non-SG instruction in the Secure state. This bit + -- is also set if the target address is a SG instruction, but there is + -- no matching SAU/IDAU region with the NSC flag set + INVEP : Boolean := False; + -- This bit is set if the integrity signature in an exception stack + -- frame is found to be invalid during the unstacking operation + INVIS : Boolean := False; + -- This can be caused by EXC_RETURN.DCRS being set to 0 when returning + -- from an exception in the Non-secure state, or by EXC_RETURN.ES being + -- set to 1 when returning from an exception in the Non-secure state + INVER : Boolean := False; + -- Sticky flag indicating that an attempt was made to access parts of + -- the address space that are marked as Secure with NS-Req for the + -- transaction set to Non-secure. This bit is not set if the violation + -- occurred during lazy state preservation. See LSPERR + AUVIOL : Boolean := False; + -- Sticky flag indicating that an exception was raised due to a branch + -- that was not flagged as being domain crossing causing a transition + -- from Secure to Non-secure memory + INVTRAN : Boolean := False; + -- Stick flag indicating that an SAU or IDAU violation occurred during + -- the lazy preservation of floating-point state + LSPERR : Boolean := False; + -- This bit is set when the SFAR register contains a valid value. As + -- with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this + -- bit can be cleared by other exceptions, such as BusFault + SFARVALID : Boolean := False; + -- Sticky flag indicating that an error occurred during lazy state + -- activation or deactivation + LSERR : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SFSR_Register use record + INVEP at 0 range 0 .. 0; + INVIS at 0 range 1 .. 1; + INVER at 0 range 2 .. 2; + AUVIOL at 0 range 3 .. 3; + INVTRAN at 0 range 4 .. 4; + LSPERR at 0 range 5 .. 5; + SFARVALID at 0 range 6 .. 6; + LSERR at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Controls halting debug + type DHCSR_Register is record + -- Enable Halting debug + C_DEBUGEN : Boolean := False; + -- PE enter Debug state halt request + C_HALT : Boolean := False; + -- Enable single instruction step + C_STEP : Boolean := False; + -- When debug is enabled, the debugger can write to this bit to mask + -- PendSV, SysTick and external configurable interrupts + C_MASKINTS : Boolean := False; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Allow imprecise entry to Debug state + C_SNAPSTALL : Boolean := False; + -- unspecified + Reserved_6_15 : HAL.UInt10 := 16#0#; + -- Read-only. Handshake flag to transfers through the DCRDR + S_REGRDY : Boolean := False; + -- Read-only. Indicates whether the PE is in Debug state + S_HALT : Boolean := False; + -- Read-only. Indicates whether the PE is sleeping + S_SLEEP : Boolean := False; + -- Read-only. Indicates whether the PE is in Lockup state + S_LOCKUP : Boolean := False; + -- Read-only. Indicates whether Secure invasive debug is allowed + S_SDE : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Read-only. Set to 1 every time the PE retires one of more + -- instructions + S_RETIRE_ST : Boolean := False; + -- Read-only. Indicates whether the PE has been reset since the last + -- read of the DHCSR + S_RESET_ST : Boolean := False; + -- Read-only. Indicates the PE has processed a request to clear + -- DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears + -- DHCSR.C_HALT from 1 to 0, or an External Restart Request + S_RESTART_ST : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DHCSR_Register use record + C_DEBUGEN at 0 range 0 .. 0; + C_HALT at 0 range 1 .. 1; + C_STEP at 0 range 2 .. 2; + C_MASKINTS at 0 range 3 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + C_SNAPSTALL at 0 range 5 .. 5; + Reserved_6_15 at 0 range 6 .. 15; + S_REGRDY at 0 range 16 .. 16; + S_HALT at 0 range 17 .. 17; + S_SLEEP at 0 range 18 .. 18; + S_LOCKUP at 0 range 19 .. 19; + S_SDE at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + S_RETIRE_ST at 0 range 24 .. 24; + S_RESET_ST at 0 range 25 .. 25; + S_RESTART_ST at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype DCRSR_REGSEL_Field is HAL.UInt7; + + -- With the DCRDR, provides debug access to the general-purpose registers, + -- special-purpose registers, and the FP extension registers. A write to + -- the DCRSR specifies the register to transfer, whether the transfer is a + -- read or write, and starts the transfer + type DCRSR_Register is record + -- Specifies the general-purpose register, special-purpose register, or + -- FP register to transfer + REGSEL : DCRSR_REGSEL_Field := 16#0#; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Specifies the access type for the transfer + REGWNR : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCRSR_Register use record + REGSEL at 0 range 0 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + REGWNR at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Manages vector catch behavior and DebugMonitor handling when debugging + type DEMCR_Register is record + -- Enable Reset Vector Catch. This causes a warm reset to halt a running + -- system + VC_CORERESET : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Enable halting debug trap on a MemManage exception + VC_MMERR : Boolean := False; + -- Enable halting debug trap on a UsageFault caused by an access to a + -- coprocessor + VC_NOCPERR : Boolean := False; + -- Enable halting debug trap on a UsageFault exception caused by a + -- checking error, for example an alignment check error + VC_CHKERR : Boolean := False; + -- Enable halting debug trap on a UsageFault exception caused by a state + -- information error, for example an Undefined Instruction exception + VC_STATERR : Boolean := False; + -- BusFault exception halting debug vector catch enable + VC_BUSERR : Boolean := False; + -- Enable halting debug vector catch for faults during exception entry + -- and return + VC_INTERR : Boolean := False; + -- HardFault exception halting debug vector catch enable + VC_HARDERR : Boolean := False; + -- SecureFault exception halting debug vector catch enable + VC_SFERR : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Enable the DebugMonitor exception + MON_EN : Boolean := False; + -- Sets or clears the pending state of the DebugMonitor exception + MON_PEND : Boolean := False; + -- Enable DebugMonitor stepping + MON_STEP : Boolean := False; + -- DebugMonitor semaphore bit + MON_REQ : Boolean := False; + -- Read-only. Indicates whether the DebugMonitor targets the Secure or + -- the Non-secure state and whether debug events are allowed in Secure + -- state + SDME : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Global enable for all DWT and ITM features + TRCENA : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEMCR_Register use record + VC_CORERESET at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VC_MMERR at 0 range 4 .. 4; + VC_NOCPERR at 0 range 5 .. 5; + VC_CHKERR at 0 range 6 .. 6; + VC_STATERR at 0 range 7 .. 7; + VC_BUSERR at 0 range 8 .. 8; + VC_INTERR at 0 range 9 .. 9; + VC_HARDERR at 0 range 10 .. 10; + VC_SFERR at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MON_EN at 0 range 16 .. 16; + MON_PEND at 0 range 17 .. 17; + MON_STEP at 0 range 18 .. 18; + MON_REQ at 0 range 19 .. 19; + SDME at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + TRCENA at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Provides control and status information for Secure debug + type DSCSR_Register is record + -- Controls whether the SBRSEL field or the current Security state of + -- the processor selects which version of the memory-mapped Banked + -- registers are accessed to the debugger + SBRSELEN : Boolean := False; + -- If SBRSELEN is 1 this bit selects whether the Non-secure or the + -- Secure version of the memory-mapped Banked registers are accessible + -- to the debugger + SBRSEL : Boolean := False; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- This field indicates the current Security state of the processor + CDS : Boolean := False; + -- Writes to the CDS bit are ignored unless CDSKEY is concurrently + -- written to zero + CDSKEY : Boolean := False; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DSCSR_Register use record + SBRSELEN at 0 range 0 .. 0; + SBRSEL at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + CDS at 0 range 16 .. 16; + CDSKEY at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype STIR_INTID_Field is HAL.UInt9; + + -- Provides a mechanism for software to generate an interrupt + type STIR_Register is record + -- Indicates the interrupt to be pended. The value written is + -- (ExceptionNumber - 16) + INTID : STIR_INTID_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STIR_Register use record + INTID at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Holds control data for the Floating-point extension + type FPCCR_Register is record + -- Indicates whether lazy preservation of the floating-point state is + -- active + LSPACT : Boolean := False; + -- Indicates the privilege level of the software executing when the PE + -- allocated the floating-point stack frame + USER : Boolean := True; + -- Security status of the floating-point context. This bit is only + -- present in the Secure version of the register, and behaves as RAZ/WI + -- when accessed from the Non-secure state. This bit is updated whenever + -- lazy state preservation is activated, or when a floating-point + -- instruction is executed + S : Boolean := False; + -- Indicates the PE mode when it allocated the floating-point stack + -- frame + THREAD : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the HardFault exception to + -- pending + HFRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the MemManage exception to + -- pending + MMRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the BusFault exception to + -- pending + BFRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the SecureFault exception + -- to pending. This bit is only present in the Secure version of the + -- register, and behaves as RAZ/WI when accessed from the Non-secure + -- state + SFRDY : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the DebugMonitor exception + -- to pending + MONRDY : Boolean := False; + -- This bit is banked between the Security states and indicates whether + -- the floating-point context violates the stack pointer limit that was + -- active when lazy state preservation was activated. SPLIMVIOL modifies + -- the lazy floating-point state preservation behavior + SPLIMVIOL : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the UsageFault exception + -- to pending + UFRDY : Boolean := True; + -- unspecified + Reserved_11_25 : HAL.UInt15 := 16#0#; + -- Treat floating-point registers as Secure enable + TS : Boolean := False; + -- This bit controls whether the CLRONRET bit is writeable from the + -- Non-secure state + CLRONRETS : Boolean := False; + -- Clear floating-point caller saved registers on exception return + CLRONRET : Boolean := False; + -- This bit controls whether the LSPEN bit is writeable from the + -- Non-secure state + LSPENS : Boolean := True; + -- Enables lazy context save of floating-point state + LSPEN : Boolean := False; + -- When this bit is set to 1, execution of a floating-point instruction + -- sets the CONTROL.FPCA bit to 1 + ASPEN : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCCR_Register use record + LSPACT at 0 range 0 .. 0; + USER at 0 range 1 .. 1; + S at 0 range 2 .. 2; + THREAD at 0 range 3 .. 3; + HFRDY at 0 range 4 .. 4; + MMRDY at 0 range 5 .. 5; + BFRDY at 0 range 6 .. 6; + SFRDY at 0 range 7 .. 7; + MONRDY at 0 range 8 .. 8; + SPLIMVIOL at 0 range 9 .. 9; + UFRDY at 0 range 10 .. 10; + Reserved_11_25 at 0 range 11 .. 25; + TS at 0 range 26 .. 26; + CLRONRETS at 0 range 27 .. 27; + CLRONRET at 0 range 28 .. 28; + LSPENS at 0 range 29 .. 29; + LSPEN at 0 range 30 .. 30; + ASPEN at 0 range 31 .. 31; + end record; + + subtype FPCAR_ADDRESS_Field is HAL.UInt29; + + -- Holds the location of the unpopulated floating-point register space + -- allocated on an exception stack frame + type FPCAR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- The location of the unpopulated floating-point register space + -- allocated on an exception stack frame + ADDRESS : FPCAR_ADDRESS_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCAR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + ADDRESS at 0 range 3 .. 31; + end record; + + subtype FPDSCR_RMODE_Field is HAL.UInt2; + + -- Holds the default values for the floating-point status control data that + -- the PE assigns to the FPSCR when it creates a new floating-point context + type FPDSCR_Register is record + -- unspecified + Reserved_0_21 : HAL.UInt22 := 16#0#; + -- Default value for FPSCR.RMode + RMODE : FPDSCR_RMODE_Field := 16#0#; + -- Default value for FPSCR.FZ + FZ : Boolean := False; + -- Default value for FPSCR.DN + DN : Boolean := False; + -- Default value for FPSCR.AHP + AHP : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPDSCR_Register use record + Reserved_0_21 at 0 range 0 .. 21; + RMODE at 0 range 22 .. 23; + FZ at 0 range 24 .. 24; + DN at 0 range 25 .. 25; + AHP at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype MVFR0_SIMDREG_Field is HAL.UInt4; + subtype MVFR0_FPSP_Field is HAL.UInt4; + subtype MVFR0_FPDP_Field is HAL.UInt4; + subtype MVFR0_FPDIVIDE_Field is HAL.UInt4; + subtype MVFR0_FPSQRT_Field is HAL.UInt4; + subtype MVFR0_FPROUND_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR0_Register is record + -- Read-only. Indicates size of FP register file + SIMDREG : MVFR0_SIMDREG_Field; + -- Read-only. Indicates support for FP single-precision operations + FPSP : MVFR0_FPSP_Field; + -- Read-only. Indicates support for FP double-precision operations + FPDP : MVFR0_FPDP_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Indicates the support for FP divide operations + FPDIVIDE : MVFR0_FPDIVIDE_Field; + -- Read-only. Indicates the support for FP square root operations + FPSQRT : MVFR0_FPSQRT_Field; + -- unspecified + Reserved_24_27 : HAL.UInt4; + -- Read-only. Indicates the rounding modes supported by the FP Extension + FPROUND : MVFR0_FPROUND_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR0_Register use record + SIMDREG at 0 range 0 .. 3; + FPSP at 0 range 4 .. 7; + FPDP at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FPDIVIDE at 0 range 16 .. 19; + FPSQRT at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + FPROUND at 0 range 28 .. 31; + end record; + + subtype MVFR1_FPFTZ_Field is HAL.UInt4; + subtype MVFR1_FPDNAN_Field is HAL.UInt4; + subtype MVFR1_FPHP_Field is HAL.UInt4; + subtype MVFR1_FMAC_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR1_Register is record + -- Read-only. Indicates whether subnormals are always flushed-to-zero + FPFTZ : MVFR1_FPFTZ_Field; + -- Read-only. Indicates whether the FP hardware implementation supports + -- NaN propagation + FPDNAN : MVFR1_FPDNAN_Field; + -- unspecified + Reserved_8_23 : HAL.UInt16; + -- Read-only. Indicates whether the FP Extension implements + -- half-precision FP conversion instructions + FPHP : MVFR1_FPHP_Field; + -- Read-only. Indicates whether the FP Extension implements the fused + -- multiply accumulate instructions + FMAC : MVFR1_FMAC_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR1_Register use record + FPFTZ at 0 range 0 .. 3; + FPDNAN at 0 range 4 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + FPHP at 0 range 24 .. 27; + FMAC at 0 range 28 .. 31; + end record; + + subtype MVFR2_FPMISC_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR2_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates support for miscellaneous FP features + FPMISC : MVFR2_FPMISC_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR2_Register use record + Reserved_0_3 at 0 range 0 .. 3; + FPMISC at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DDEVARCH_ARCHPART_Field is HAL.UInt12; + subtype DDEVARCH_ARCHVER_Field is HAL.UInt4; + subtype DDEVARCH_REVISION_Field is HAL.UInt4; + subtype DDEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the SCS + type DDEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : DDEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : DDEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : DDEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : DDEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DDEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DDEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DDEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DDEVTYPE_Register is record + -- Read-only. CoreSight major type + MAJOR : DDEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : DDEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DDEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR4_DES_2_Field is HAL.UInt4; + subtype DPIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : DPIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : DPIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DPIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : DPIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR1_PART_1_Field is HAL.UInt4; + subtype DPIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : DPIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : DPIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR2_DES_1_Field is HAL.UInt3; + subtype DPIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : DPIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : DPIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR3_CMOD_Field is HAL.UInt4; + subtype DPIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : DPIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : DPIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : DCIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR1_PRMBL_1_Field is HAL.UInt4; + subtype DCIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DCIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : DCIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : DCIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : DCIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : DCIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Programming Control Register + type TRCPRGCTLR_Register is record + -- Trace Unit Enable + EN : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPRGCTLR_Register use record + EN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- The TRCSTATR indicates the ETM-Teal status + type TRCSTATR_Register is record + -- Read-only. Indicates that the trace unit is inactive + IDLE : Boolean; + -- Read-only. Indicates whether the ETM-Teal registers are stable and + -- can be read + PMSTABLE : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSTATR_Register use record + IDLE at 0 range 0 .. 0; + PMSTABLE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype TRCCONFIGR_COND_Field is HAL.UInt6; + + -- The TRCCONFIGR sets the basic tracing options for the trace unit + type TRCCONFIGR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Branch broadcast mode + BB : Boolean := False; + -- Cycle counting in instruction trace + CCI : Boolean := False; + -- Conditional instruction tracing + COND : TRCCONFIGR_COND_Field := 16#0#; + -- Global timestamp tracing + TS : Boolean := False; + -- Return stack enable + RS : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCONFIGR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + BB at 0 range 3 .. 3; + CCI at 0 range 4 .. 4; + COND at 0 range 5 .. 10; + TS at 0 range 11 .. 11; + RS at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype TRCEVENTCTL0R_SEL0_Field is HAL.UInt3; + subtype TRCEVENTCTL0R_SEL1_Field is HAL.UInt3; + + -- The TRCEVENTCTL0R controls the tracing of events in the trace stream. + -- The events also drive the ETM-Teal external outputs. + type TRCEVENTCTL0R_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCEVENTCTL0R_SEL0_Field := 16#0#; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- Selects the resource number, based on the value of TYPE1: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL1[2:0] + SEL1 : TRCEVENTCTL0R_SEL1_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- Selects the resource type for event 1 + TYPE1 : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCEVENTCTL0R_Register use record + SEL0 at 0 range 0 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TYPE0 at 0 range 7 .. 7; + SEL1 at 0 range 8 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + TYPE1 at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- TRCEVENTCTL1R_INSTEN array + type TRCEVENTCTL1R_INSTEN_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TRCEVENTCTL1R_INSTEN + type TRCEVENTCTL1R_INSTEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- INSTEN as a value + Val : HAL.UInt2; + when True => + -- INSTEN as an array + Arr : TRCEVENTCTL1R_INSTEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TRCEVENTCTL1R_INSTEN_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + -- behave + type TRCEVENTCTL1R_Register is record + -- One bit per event, to enable generation of an event element in the + -- instruction trace stream when the selected event occurs + INSTEN : TRCEVENTCTL1R_INSTEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_10 : HAL.UInt9 := 16#0#; + -- ATB enabled + ATB : Boolean := False; + -- Low power state behavior override + LPOVERRIDE : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCEVENTCTL1R_Register use record + INSTEN at 0 range 0 .. 1; + Reserved_2_10 at 0 range 2 .. 10; + ATB at 0 range 11 .. 11; + LPOVERRIDE at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype TRCSTALLCTLR_LEVEL_Field is HAL.UInt2; + + -- The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal + -- FIFO goes over the programmed level to minimize risk of overflow + type TRCSTALLCTLR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Threshold at which stalling becomes active. This provides four + -- levels. This level can be varied to optimize the level of invasion + -- caused by stalling, balanced against the risk of a FIFO overflow + LEVEL : TRCSTALLCTLR_LEVEL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Stall processor based on instruction trace buffer space + ISTALL : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Read-only. Reserved, RES0 + INSTPRIORITY : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSTALLCTLR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + LEVEL at 0 range 2 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + ISTALL at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + INSTPRIORITY at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype TRCTSCTLR_SEL0_Field is HAL.UInt2; + + -- The TRCTSCTLR controls the insertion of global timestamps into the trace + -- stream. A timestamp is always inserted into the instruction trace stream + type TRCTSCTLR_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCTSCTLR_SEL0_Field := 16#0#; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCTSCTLR_Register use record + SEL0 at 0 range 0 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + TYPE0 at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCSYNCPR_PERIOD_Field is HAL.UInt5; + + -- The TRCSYNCPR specifies the period of trace synchronization of the trace + -- streams. TRCSYNCPR defines a number of bytes of trace between requests + -- for trace synchronization. This value is always a power of two + type TRCSYNCPR_Register is record + -- Read-only. Defines the number of bytes of trace between trace + -- synchronization requests as a total of the number of bytes generated + -- by the instruction stream. The number of bytes is 2N where N is the + -- value of this field: - A value of zero disables these periodic trace + -- synchronization requests, but does not disable other trace + -- synchronization requests. - The minimum value that can be programmed, + -- other than zero, is 8, providing a minimum trace synchronization + -- period of 256 bytes. - The maximum value is 20, providing a maximum + -- trace synchronization period of 2^20 bytes + PERIOD : TRCSYNCPR_PERIOD_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSYNCPR_Register use record + PERIOD at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype TRCCCCTLR_THRESHOLD_Field is HAL.UInt12; + + -- The TRCCCCTLR sets the threshold value for instruction trace cycle + -- counting. The threshold represents the minimum interval between cycle + -- count trace packets + type TRCCCCTLR_Register is record + -- Instruction trace cycle count threshold + THRESHOLD : TRCCCCTLR_THRESHOLD_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCCCTLR_Register use record + THRESHOLD at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype TRCVICTLR_SEL0_Field is HAL.UInt2; + + -- The TRCVICTLR controls instruction trace filtering + type TRCVICTLR_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCVICTLR_SEL0_Field := 16#0#; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Indicates the current status of the start/stop logic + SSSTATUS : Boolean := False; + -- Selects whether a reset exception must always be traced + TRCRESET : Boolean := False; + -- Selects whether a system error exception must always be traced + TRCERR : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- In Secure state, each bit controls whether instruction tracing is + -- enabled for the corresponding exception level + EXLEVEL_S0 : Boolean := False; + -- unspecified + Reserved_17_18 : HAL.UInt2 := 16#0#; + -- In Secure state, each bit controls whether instruction tracing is + -- enabled for the corresponding exception level + EXLEVEL_S3 : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCVICTLR_Register use record + SEL0 at 0 range 0 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + TYPE0 at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + SSSTATUS at 0 range 9 .. 9; + TRCRESET at 0 range 10 .. 10; + TRCERR at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + EXLEVEL_S0 at 0 range 16 .. 16; + Reserved_17_18 at 0 range 17 .. 18; + EXLEVEL_S3 at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype TRCCNTRLDVR0_VALUE_Field is HAL.UInt16; + + -- The TRCCNTRLDVR defines the reload value for the reduced function + -- counter + type TRCCNTRLDVR0_Register is record + -- Defines the reload value for the counter. This value is loaded into + -- the counter each time the reload event occurs + VALUE : TRCCNTRLDVR0_VALUE_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCNTRLDVR0_Register use record + VALUE at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TRCIMSPEC_SUPPORT_Field is HAL.UInt4; + + -- The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + -- features, and enables any features that are provided + type TRCIMSPEC_Register is record + -- Read-only. Reserved, RES0 + SUPPORT : TRCIMSPEC_SUPPORT_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIMSPEC_Register use record + SUPPORT at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRCIDR0_INSTP0_Field is HAL.UInt2; + subtype TRCIDR0_TRCDATA_Field is HAL.UInt2; + subtype TRCIDR0_NUMEVENT_Field is HAL.UInt2; + subtype TRCIDR0_CONDTYPE_Field is HAL.UInt2; + subtype TRCIDR0_QSUPP_Field is HAL.UInt2; + subtype TRCIDR0_TSSIZE_Field is HAL.UInt5; + + -- TRCIDR0 + type TRCIDR0_Register is record + -- Read-only. Reserved, RES1 + RES1 : Boolean; + -- Read-only. reads as `ImpDef + INSTP0 : TRCIDR0_INSTP0_Field; + -- Read-only. reads as `ImpDef + TRCDATA : TRCIDR0_TRCDATA_Field; + -- Read-only. reads as `ImpDef + TRCBB : Boolean; + -- Read-only. reads as `ImpDef + TRCCOND : Boolean; + -- Read-only. reads as `ImpDef + TRCCCI : Boolean; + -- unspecified + Reserved_8_8 : HAL.Bit; + -- Read-only. reads as `ImpDef + RETSTACK : Boolean; + -- Read-only. reads as `ImpDef + NUMEVENT : TRCIDR0_NUMEVENT_Field; + -- Read-only. reads as `ImpDef + CONDTYPE : TRCIDR0_CONDTYPE_Field; + -- Read-only. reads as `ImpDef + QFILT : Boolean; + -- Read-only. reads as `ImpDef + QSUPP : TRCIDR0_QSUPP_Field; + -- Read-only. reads as `ImpDef + TRCEXDATA : Boolean; + -- unspecified + Reserved_18_23 : HAL.UInt6; + -- Read-only. reads as `ImpDef + TSSIZE : TRCIDR0_TSSIZE_Field; + -- Read-only. reads as `ImpDef + COMMOPT : Boolean; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR0_Register use record + RES1 at 0 range 0 .. 0; + INSTP0 at 0 range 1 .. 2; + TRCDATA at 0 range 3 .. 4; + TRCBB at 0 range 5 .. 5; + TRCCOND at 0 range 6 .. 6; + TRCCCI at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + RETSTACK at 0 range 9 .. 9; + NUMEVENT at 0 range 10 .. 11; + CONDTYPE at 0 range 12 .. 13; + QFILT at 0 range 14 .. 14; + QSUPP at 0 range 15 .. 16; + TRCEXDATA at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + TSSIZE at 0 range 24 .. 28; + COMMOPT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype TRCIDR1_REVISION_Field is HAL.UInt4; + subtype TRCIDR1_TRCARCHMIN_Field is HAL.UInt4; + subtype TRCIDR1_TRCARCHMAJ_Field is HAL.UInt4; + subtype TRCIDR1_RES1_Field is HAL.UInt4; + subtype TRCIDR1_DESIGNER_Field is HAL.UInt8; + + -- TRCIDR1 + type TRCIDR1_Register is record + -- Read-only. reads as `ImpDef + REVISION : TRCIDR1_REVISION_Field; + -- Read-only. reads as 0b0000 + TRCARCHMIN : TRCIDR1_TRCARCHMIN_Field; + -- Read-only. reads as 0b0100 + TRCARCHMAJ : TRCIDR1_TRCARCHMAJ_Field; + -- Read-only. Reserved, RES1 + RES1 : TRCIDR1_RES1_Field; + -- unspecified + Reserved_16_23 : HAL.UInt8; + -- Read-only. reads as `ImpDef + DESIGNER : TRCIDR1_DESIGNER_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR1_Register use record + REVISION at 0 range 0 .. 3; + TRCARCHMIN at 0 range 4 .. 7; + TRCARCHMAJ at 0 range 8 .. 11; + RES1 at 0 range 12 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + DESIGNER at 0 range 24 .. 31; + end record; + + subtype TRCIDR2_IASIZE_Field is HAL.UInt5; + subtype TRCIDR2_CIDSIZE_Field is HAL.UInt5; + subtype TRCIDR2_VMIDSIZE_Field is HAL.UInt5; + subtype TRCIDR2_DASIZE_Field is HAL.UInt5; + subtype TRCIDR2_DVSIZE_Field is HAL.UInt5; + subtype TRCIDR2_CCSIZE_Field is HAL.UInt4; + + -- TRCIDR2 + type TRCIDR2_Register is record + -- Read-only. reads as `ImpDef + IASIZE : TRCIDR2_IASIZE_Field; + -- Read-only. reads as `ImpDef + CIDSIZE : TRCIDR2_CIDSIZE_Field; + -- Read-only. reads as `ImpDef + VMIDSIZE : TRCIDR2_VMIDSIZE_Field; + -- Read-only. reads as `ImpDef + DASIZE : TRCIDR2_DASIZE_Field; + -- Read-only. reads as `ImpDef + DVSIZE : TRCIDR2_DVSIZE_Field; + -- Read-only. reads as `ImpDef + CCSIZE : TRCIDR2_CCSIZE_Field; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR2_Register use record + IASIZE at 0 range 0 .. 4; + CIDSIZE at 0 range 5 .. 9; + VMIDSIZE at 0 range 10 .. 14; + DASIZE at 0 range 15 .. 19; + DVSIZE at 0 range 20 .. 24; + CCSIZE at 0 range 25 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype TRCIDR3_CCITMIN_Field is HAL.UInt12; + subtype TRCIDR3_EXLEVEL_S_Field is HAL.UInt4; + subtype TRCIDR3_EXLEVEL_NS_Field is HAL.UInt4; + subtype TRCIDR3_NUMPROC_Field is HAL.UInt3; + + -- TRCIDR3 + type TRCIDR3_Register is record + -- Read-only. reads as `ImpDef + CCITMIN : TRCIDR3_CCITMIN_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. reads as `ImpDef + EXLEVEL_S : TRCIDR3_EXLEVEL_S_Field; + -- Read-only. reads as `ImpDef + EXLEVEL_NS : TRCIDR3_EXLEVEL_NS_Field; + -- Read-only. reads as `ImpDef + TRCERR : Boolean; + -- Read-only. reads as `ImpDef + SYNCPR : Boolean; + -- Read-only. reads as `ImpDef + STALLCTL : Boolean; + -- Read-only. reads as `ImpDef + SYSSTALL : Boolean; + -- Read-only. reads as `ImpDef + NUMPROC : TRCIDR3_NUMPROC_Field; + -- Read-only. reads as `ImpDef + NOOVERFLOW : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR3_Register use record + CCITMIN at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + EXLEVEL_S at 0 range 16 .. 19; + EXLEVEL_NS at 0 range 20 .. 23; + TRCERR at 0 range 24 .. 24; + SYNCPR at 0 range 25 .. 25; + STALLCTL at 0 range 26 .. 26; + SYSSTALL at 0 range 27 .. 27; + NUMPROC at 0 range 28 .. 30; + NOOVERFLOW at 0 range 31 .. 31; + end record; + + subtype TRCIDR4_NUMACPAIRS_Field is HAL.UInt4; + subtype TRCIDR4_NUMDVC_Field is HAL.UInt4; + subtype TRCIDR4_NUMPC_Field is HAL.UInt4; + subtype TRCIDR4_NUMRSPAIR_Field is HAL.UInt4; + subtype TRCIDR4_NUMSSCC_Field is HAL.UInt4; + subtype TRCIDR4_NUMCIDC_Field is HAL.UInt4; + subtype TRCIDR4_NUMVMIDC_Field is HAL.UInt4; + + -- TRCIDR4 + type TRCIDR4_Register is record + -- Read-only. reads as `ImpDef + NUMACPAIRS : TRCIDR4_NUMACPAIRS_Field; + -- Read-only. reads as `ImpDef + NUMDVC : TRCIDR4_NUMDVC_Field; + -- Read-only. reads as `ImpDef + SUPPDAC : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. reads as `ImpDef + NUMPC : TRCIDR4_NUMPC_Field; + -- Read-only. reads as `ImpDef + NUMRSPAIR : TRCIDR4_NUMRSPAIR_Field; + -- Read-only. reads as `ImpDef + NUMSSCC : TRCIDR4_NUMSSCC_Field; + -- Read-only. reads as `ImpDef + NUMCIDC : TRCIDR4_NUMCIDC_Field; + -- Read-only. reads as `ImpDef + NUMVMIDC : TRCIDR4_NUMVMIDC_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR4_Register use record + NUMACPAIRS at 0 range 0 .. 3; + NUMDVC at 0 range 4 .. 7; + SUPPDAC at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + NUMPC at 0 range 12 .. 15; + NUMRSPAIR at 0 range 16 .. 19; + NUMSSCC at 0 range 20 .. 23; + NUMCIDC at 0 range 24 .. 27; + NUMVMIDC at 0 range 28 .. 31; + end record; + + subtype TRCIDR5_NUMEXTIN_Field is HAL.UInt9; + subtype TRCIDR5_NUMEXTINSEL_Field is HAL.UInt3; + subtype TRCIDR5_TRACEIDSIZE_Field is HAL.UInt6; + subtype TRCIDR5_NUMSEQSTATE_Field is HAL.UInt3; + subtype TRCIDR5_NUMCNTR_Field is HAL.UInt3; + + -- TRCIDR5 + type TRCIDR5_Register is record + -- Read-only. reads as `ImpDef + NUMEXTIN : TRCIDR5_NUMEXTIN_Field; + -- Read-only. reads as `ImpDef + NUMEXTINSEL : TRCIDR5_NUMEXTINSEL_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. reads as 0x07 + TRACEIDSIZE : TRCIDR5_TRACEIDSIZE_Field; + -- Read-only. reads as `ImpDef + ATBTRIG : Boolean; + -- Read-only. reads as `ImpDef + LPOVERRIDE : Boolean; + -- unspecified + Reserved_24_24 : HAL.Bit; + -- Read-only. reads as `ImpDef + NUMSEQSTATE : TRCIDR5_NUMSEQSTATE_Field; + -- Read-only. reads as `ImpDef + NUMCNTR : TRCIDR5_NUMCNTR_Field; + -- Read-only. reads as `ImpDef + REDFUNCNTR : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR5_Register use record + NUMEXTIN at 0 range 0 .. 8; + NUMEXTINSEL at 0 range 9 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TRACEIDSIZE at 0 range 16 .. 21; + ATBTRIG at 0 range 22 .. 22; + LPOVERRIDE at 0 range 23 .. 23; + Reserved_24_24 at 0 range 24 .. 24; + NUMSEQSTATE at 0 range 25 .. 27; + NUMCNTR at 0 range 28 .. 30; + REDFUNCNTR at 0 range 31 .. 31; + end record; + + subtype TRCRSCTLR_SELECT_Field is HAL.UInt8; + subtype TRCRSCTLR_GROUP_Field is HAL.UInt3; + + -- The TRCRSCTLR controls the trace resources + type TRCRSCTLR_Register is record + -- Selects one or more resources from the wanted group. One bit is + -- provided per resource from the group + SELECT_k : TRCRSCTLR_SELECT_Field := 16#0#; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Selects a group of resource + GROUP : TRCRSCTLR_GROUP_Field := 16#0#; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Inverts the selected resources + INV : Boolean := False; + -- Inverts the result of a combined pair of resources. This bit is only + -- implemented on the lower register for a pair of resource selectors + PAIRINV : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCRSCTLR_Register use record + SELECT_k at 0 range 0 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + GROUP at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + INV at 0 range 20 .. 20; + PAIRINV at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Controls the corresponding single-shot comparator resource + type TRCSSCSR_Register is record + -- Read-only. Reserved, RES0 + INST : Boolean := False; + -- Read-only. Reserved, RES0 + DA : Boolean := False; + -- Read-only. Reserved, RES0 + DV : Boolean := False; + -- Read-only. Reserved, RES1 + PC : Boolean := False; + -- unspecified + Reserved_4_30 : HAL.UInt27 := 16#0#; + -- Single-shot status bit. Indicates if any of the comparators, that + -- TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + STATUS : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSSCSR_Register use record + INST at 0 range 0 .. 0; + DA at 0 range 1 .. 1; + DV at 0 range 2 .. 2; + PC at 0 range 3 .. 3; + Reserved_4_30 at 0 range 4 .. 30; + STATUS at 0 range 31 .. 31; + end record; + + subtype TRCSSPCICR_PC_Field is HAL.UInt4; + + -- Selects the PE comparator inputs for Single-shot control + type TRCSSPCICR_Register is record + -- Selects one or more PE comparator inputs for Single-shot control. + -- TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for + -- each implemented PE comparator input. For example, if bit[1] == 1 + -- this selects PE comparator input 1 for Single-shot control + PC : TRCSSPCICR_PC_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSSPCICR_Register use record + PC at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Requests the system to provide power to the trace unit + type TRCPDCR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Powerup request bit: + PU : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPDCR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PU at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Returns the following information about the trace unit: - OS Lock + -- status. - Core power domain status. - Power interruption status + type TRCPDSR_Register is record + -- Read-only. Power status bit: + POWER : Boolean; + -- Read-only. Sticky powerdown status bit. Indicates whether the trace + -- register state is valid: + STICKYPD : Boolean; + -- unspecified + Reserved_2_4 : HAL.UInt3; + -- Read-only. OS Lock status bit: + OSLK : Boolean; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPDSR_Register use record + POWER at 0 range 0 .. 0; + STICKYPD at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OSLK at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype TRCITATBIDR_ID_Field is HAL.UInt7; + + -- Trace Integration ATB Identification Register + type TRCITATBIDR_Register is record + -- Trace ID + ID : TRCITATBIDR_ID_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITATBIDR_Register use record + ID at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Trace Integration Instruction ATB In Register + type TRCITIATBINR_Register is record + -- Integration Mode instruction ATREADYM in + ATREADYM : Boolean := False; + -- Integration Mode instruction AFVALIDM in + AFVALIDM : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITIATBINR_Register use record + ATREADYM at 0 range 0 .. 0; + AFVALIDM at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Trace Integration Instruction ATB Out Register + type TRCITIATBOUTR_Register is record + -- Integration Mode instruction ATVALID out + ATVALID : Boolean := False; + -- Integration Mode instruction AFREADY out + AFREADY : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITIATBOUTR_Register use record + ATVALID at 0 range 0 .. 0; + AFREADY at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- TRCCLAIMSET_SET array + type TRCCLAIMSET_SET_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for TRCCLAIMSET_SET + type TRCCLAIMSET_SET_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SET as a value + Val : HAL.UInt4; + when True => + -- SET as an array + Arr : TRCCLAIMSET_SET_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for TRCCLAIMSET_SET_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Claim Tag Set Register + type TRCCLAIMSET_Register is record + -- When a write to one of these bits occurs, with the value: + SET : TRCCLAIMSET_SET_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCLAIMSET_Register use record + SET at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- TRCCLAIMCLR_CLR array + type TRCCLAIMCLR_CLR_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for TRCCLAIMCLR_CLR + type TRCCLAIMCLR_CLR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLR as a value + Val : HAL.UInt4; + when True => + -- CLR as an array + Arr : TRCCLAIMCLR_CLR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for TRCCLAIMCLR_CLR_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Claim Tag Clear Register + type TRCCLAIMCLR_Register is record + -- When a write to one of these bits occurs, with the value: + CLR : TRCCLAIMCLR_CLR_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCLAIMCLR_Register use record + CLR at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRCAUTHSTATUS_NSID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_NSNID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_SID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_SNID_Field is HAL.UInt2; + + -- Returns the level of tracing that the trace unit can support + type TRCAUTHSTATUS_Register is record + -- Read-only. Indicates whether the trace unit supports Non-secure + -- invasive debug: + NSID : TRCAUTHSTATUS_NSID_Field; + -- Read-only. Indicates whether the system enables the trace unit to + -- support Non-secure non-invasive debug: + NSNID : TRCAUTHSTATUS_NSNID_Field; + -- Read-only. Indicates whether the trace unit supports Secure invasive + -- debug: + SID : TRCAUTHSTATUS_SID_Field; + -- Read-only. Indicates whether the system enables the trace unit to + -- support Secure non-invasive debug: + SNID : TRCAUTHSTATUS_SNID_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCAUTHSTATUS_Register use record + NSID at 0 range 0 .. 1; + NSNID at 0 range 2 .. 3; + SID at 0 range 4 .. 5; + SNID at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCDEVARCH_ARCHID_Field is HAL.UInt16; + subtype TRCDEVARCH_REVISION_Field is HAL.UInt4; + subtype TRCDEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- TRCDEVARCH + type TRCDEVARCH_Register is record + -- Read-only. reads as 0b0100101000010011 + ARCHID : TRCDEVARCH_ARCHID_Field; + -- Read-only. reads as 0b0000 + REVISION : TRCDEVARCH_REVISION_Field; + -- Read-only. reads as 0b1 + PRESENT : Boolean; + -- Read-only. reads as 0b01000111011 + ARCHITECT : TRCDEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCDEVARCH_Register use record + ARCHID at 0 range 0 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype TRCDEVTYPE_MAJOR_Field is HAL.UInt4; + subtype TRCDEVTYPE_SUB_Field is HAL.UInt4; + + -- TRCDEVTYPE + type TRCDEVTYPE_Register is record + -- Read-only. reads as 0b0011 + MAJOR : TRCDEVTYPE_MAJOR_Field; + -- Read-only. reads as 0b0001 + SUB : TRCDEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCDEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR4_DES_2_Field is HAL.UInt4; + subtype TRCPIDR4_SIZE_Field is HAL.UInt4; + + -- TRCPIDR4 + type TRCPIDR4_Register is record + -- Read-only. reads as `ImpDef + DES_2 : TRCPIDR4_DES_2_Field; + -- Read-only. reads as `ImpDef + SIZE : TRCPIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR0_PART_0_Field is HAL.UInt8; + + -- TRCPIDR0 + type TRCPIDR0_Register is record + -- Read-only. reads as `ImpDef + PART_0 : TRCPIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR1_PART_0_Field is HAL.UInt4; + subtype TRCPIDR1_DES_0_Field is HAL.UInt4; + + -- TRCPIDR1 + type TRCPIDR1_Register is record + -- Read-only. reads as `ImpDef + PART_0 : TRCPIDR1_PART_0_Field; + -- Read-only. reads as `ImpDef + DES_0 : TRCPIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR1_Register use record + PART_0 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR2_DES_0_Field is HAL.UInt3; + subtype TRCPIDR2_REVISION_Field is HAL.UInt4; + + -- TRCPIDR2 + type TRCPIDR2_Register is record + -- Read-only. reads as `ImpDef + DES_0 : TRCPIDR2_DES_0_Field; + -- Read-only. reads as 0b1 + JEDEC : Boolean; + -- Read-only. reads as `ImpDef + REVISION : TRCPIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR2_Register use record + DES_0 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR3_CMOD_Field is HAL.UInt4; + subtype TRCPIDR3_REVAND_Field is HAL.UInt4; + + -- TRCPIDR3 + type TRCPIDR3_Register is record + -- Read-only. reads as `ImpDef + CMOD : TRCPIDR3_CMOD_Field; + -- Read-only. reads as `ImpDef + REVAND : TRCPIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR0_PRMBL_0_Field is HAL.UInt8; + + -- TRCCIDR0 + type TRCCIDR0_Register is record + -- Read-only. reads as 0b00001101 + PRMBL_0 : TRCCIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR1_PRMBL_1_Field is HAL.UInt4; + subtype TRCCIDR1_CLASS_Field is HAL.UInt4; + + -- TRCCIDR1 + type TRCCIDR1_Register is record + -- Read-only. reads as 0b0000 + PRMBL_1 : TRCCIDR1_PRMBL_1_Field; + -- Read-only. reads as 0b1001 + CLASS : TRCCIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR2_PRMBL_2_Field is HAL.UInt8; + + -- TRCCIDR2 + type TRCCIDR2_Register is record + -- Read-only. reads as 0b00000101 + PRMBL_2 : TRCCIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR3_PRMBL_3_Field is HAL.UInt8; + + -- TRCCIDR3 + type TRCCIDR3_Register is record + -- Read-only. reads as 0b10110001 + PRMBL_3 : TRCCIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CTI Control Register + type CTICONTROL_Register is record + -- Enables or disables the CTI + GLBEN : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTICONTROL_Register use record + GLBEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype CTIINTACK_INTACK_Field is HAL.UInt8; + + -- CTI Interrupt Acknowledge Register + type CTIINTACK_Register is record + -- Acknowledges the corresponding ctitrigout output. There is one bit of + -- the register for each ctitrigout output. When a 1 is written to a bit + -- in this register, the corresponding ctitrigout is acknowledged, + -- causing it to be cleared. + INTACK : CTIINTACK_INTACK_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIINTACK_Register use record + INTACK at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTIAPPSET_APPSET_Field is HAL.UInt4; + + -- CTI Application Trigger Set Register + type CTIAPPSET_Register is record + -- Setting a bit HIGH generates a channel event for the selected + -- channel. There is one bit of the register for each channel + APPSET : CTIAPPSET_APPSET_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPSET_Register use record + APPSET at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIAPPCLEAR_APPCLEAR_Field is HAL.UInt4; + + -- CTI Application Trigger Clear Register + type CTIAPPCLEAR_Register is record + -- Sets the corresponding bits in the CTIAPPSET to 0. There is one bit + -- of the register for each channel. + APPCLEAR : CTIAPPCLEAR_APPCLEAR_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPCLEAR_Register use record + APPCLEAR at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIAPPPULSE_APPULSE_Field is HAL.UInt4; + + -- CTI Application Pulse Register + type CTIAPPPULSE_Register is record + -- Setting a bit HIGH generates a channel event pulse for the selected + -- channel. There is one bit of the register for each channel. + APPULSE : CTIAPPPULSE_APPULSE_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPPULSE_Register use record + APPULSE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIINEN_TRIGINEN_Field is HAL.UInt4; + + -- CTI Trigger to Channel Enable Registers + type CTIINEN_Register is record + -- Enables a cross trigger event to the corresponding channel when a + -- ctitrigin input is activated. There is one bit of the field for each + -- of the four channels + TRIGINEN : CTIINEN_TRIGINEN_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIINEN_Register use record + TRIGINEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIOUTEN_TRIGOUTEN_Field is HAL.UInt4; + + -- CTI Trigger to Channel Enable Registers + type CTIOUTEN_Register is record + -- Enables a cross trigger event to ctitrigout when the corresponding + -- channel is activated. There is one bit of the field for each of the + -- four channels. + TRIGOUTEN : CTIOUTEN_TRIGOUTEN_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIOUTEN_Register use record + TRIGOUTEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTITRIGINSTATUS_TRIGINSTATUS_Field is HAL.UInt8; + + -- CTI Trigger to Channel Enable Registers + type CTITRIGINSTATUS_Register is record + -- Read-only. Shows the status of the ctitrigin inputs. There is one bit + -- of the field for each trigger input.Because the register provides a + -- view of the raw ctitrigin inputs, the reset value is UNKNOWN. + TRIGINSTATUS : CTITRIGINSTATUS_TRIGINSTATUS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTITRIGINSTATUS_Register use record + TRIGINSTATUS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTITRIGOUTSTATUS_TRIGOUTSTATUS_Field is HAL.UInt8; + + -- CTI Trigger In Status Register + type CTITRIGOUTSTATUS_Register is record + -- Read-only. Shows the status of the ctitrigout outputs. There is one + -- bit of the field for each trigger output. + TRIGOUTSTATUS : CTITRIGOUTSTATUS_TRIGOUTSTATUS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTITRIGOUTSTATUS_Register use record + TRIGOUTSTATUS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTICHINSTATUS_CTICHOUTSTATUS_Field is HAL.UInt4; + + -- CTI Channel In Status Register + type CTICHINSTATUS_Register is record + -- Read-only. Shows the status of the ctichout outputs. There is one bit + -- of the field for each channel output + CTICHOUTSTATUS : CTICHINSTATUS_CTICHOUTSTATUS_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTICHINSTATUS_Register use record + CTICHOUTSTATUS at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- CTIGATE_CTIGATEEN array + type CTIGATE_CTIGATEEN_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for CTIGATE_CTIGATEEN + type CTIGATE_CTIGATEEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CTIGATEEN as a value + Val : HAL.UInt4; + when True => + -- CTIGATEEN as an array + Arr : CTIGATE_CTIGATEEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for CTIGATE_CTIGATEEN_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Enable CTI Channel Gate register + type CTIGATE_Register is record + -- Enable ctichout0. Set to 0 to disable channel propagation. + CTIGATEEN : CTIGATE_CTIGATEEN_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIGATE_Register use record + CTIGATEEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITCHOUT_CTCHOUT_Field is HAL.UInt4; + + -- Integration Test Channel Output register + type ITCHOUT_Register is record + -- Sets the value of the ctichout outputs + CTCHOUT : ITCHOUT_CTCHOUT_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCHOUT_Register use record + CTCHOUT at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITTRIGOUT_CTTRIGOUT_Field is HAL.UInt8; + + -- Integration Test Trigger Output register + type ITTRIGOUT_Register is record + -- Sets the value of the ctitrigout outputs + CTTRIGOUT : ITTRIGOUT_CTTRIGOUT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITTRIGOUT_Register use record + CTTRIGOUT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITCHIN_CTCHIN_Field is HAL.UInt4; + + -- Integration Test Channel Input register + type ITCHIN_Register is record + -- Read-only. Reads the value of the ctichin inputs. + CTCHIN : ITCHIN_CTCHIN_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCHIN_Register use record + CTCHIN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Integration Mode Control register + type ITCTRL_Register is record + -- Integration Mode Enable + IME : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCTRL_Register use record + IME at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype DEVARCH_ARCHID_Field is HAL.UInt16; + subtype DEVARCH_REVISION_Field is HAL.UInt4; + subtype DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Device Architecture register + type DEVARCH_Register is record + -- Read-only. Indicates the component + ARCHID : DEVARCH_ARCHID_Field; + -- Read-only. Indicates the architecture revision + REVISION : DEVARCH_REVISION_Field; + -- Read-only. Indicates whether the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Indicates the component architect + ARCHITECT : DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVARCH_Register use record + ARCHID at 0 range 0 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DEVID_EXTMUXNUM_Field is HAL.UInt5; + subtype DEVID_NUMTRIG_Field is HAL.UInt8; + subtype DEVID_NUMCH_Field is HAL.UInt4; + + -- Device Configuration register + type DEVID_Register is record + -- Read-only. Indicates the number of multiplexers available on Trigger + -- Inputs and Trigger Outputs that are using asicctl. The default value + -- of 0b00000 indicates that no multiplexing is present. This value of + -- this bit depends on the Verilog define EXTMUXNUM that you must change + -- accordingly. + EXTMUXNUM : DEVID_EXTMUXNUM_Field; + -- unspecified + Reserved_5_7 : HAL.UInt3; + -- Read-only. Number of ECT triggers available. + NUMTRIG : DEVID_NUMTRIG_Field; + -- Read-only. Number of ECT channels available + NUMCH : DEVID_NUMCH_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVID_Register use record + EXTMUXNUM at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + NUMTRIG at 0 range 8 .. 15; + NUMCH at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DEVTYPE_SUB_Field is HAL.UInt4; + + -- Device Type Identifier register + type DEVTYPE_Register is record + -- Read-only. Major classification of the type of the debug component as + -- specified in the ARM Architecture Specification for this debug and + -- trace component. + MAJOR : DEVTYPE_MAJOR_Field; + -- Read-only. Sub-classification of the type of the debug component as + -- specified in the ARM Architecture Specification within the major + -- classification as specified in the MAJOR field. + SUB : DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR4_DES_2_Field is HAL.UInt4; + subtype PIDR4_SIZE_Field is HAL.UInt4; + + -- CoreSight Peripheral ID4 + type PIDR4_Register is record + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_2 : PIDR4_DES_2_Field; + -- Read-only. Always 0b0000. Indicates that the device only occupies 4KB + -- of memory + SIZE : PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR0_PART_0_Field is HAL.UInt8; + + -- CoreSight Peripheral ID0 + type PIDR0_Register is record + -- Read-only. Bits[7:0] of the 12-bit part number of the component. The + -- designer of the component assigns this part number. + PART_0 : PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR1_PART_1_Field is HAL.UInt4; + subtype PIDR1_DES_0_Field is HAL.UInt4; + + -- CoreSight Peripheral ID1 + type PIDR1_Register is record + -- Read-only. Bits[11:8] of the 12-bit part number of the component. The + -- designer of the component assigns this part number. + PART_1 : PIDR1_PART_1_Field; + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_0 : PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR2_DES_1_Field is HAL.UInt3; + subtype PIDR2_REVISION_Field is HAL.UInt4; + + -- CoreSight Peripheral ID2 + type PIDR2_Register is record + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_1 : PIDR2_DES_1_Field; + -- Read-only. Always 1. Indicates that the JEDEC-assigned designer ID is + -- used. + JEDEC : Boolean; + -- Read-only. This device is at r1p0 + REVISION : PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR3_CMOD_Field is HAL.UInt4; + subtype PIDR3_REVAND_Field is HAL.UInt4; + + -- CoreSight Peripheral ID3 + type PIDR3_Register is record + -- Read-only. Customer Modified. Indicates whether the customer has + -- modified the behavior of the component. In most cases, this field is + -- 0b0000. Customers change this value when they make authorized + -- modifications to this component. + CMOD : PIDR3_CMOD_Field; + -- Read-only. Indicates minor errata fixes specific to the revision of + -- the component being used, for example metal fixes after + -- implementation. In most cases, this field is 0b0000. ARM recommends + -- that the component designers ensure that a metal fix can change this + -- field if required, for example, by driving it from registers that + -- reset to 0b0000. + REVAND : PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- CoreSight Component ID0 + type CIDR0_Register is record + -- Read-only. Preamble[0]. Contains bits[7:0] of the component + -- identification code + PRMBL_0 : CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype CIDR1_CLASS_Field is HAL.UInt4; + + -- CoreSight Component ID1 + type CIDR1_Register is record + -- Read-only. Preamble[1]. Contains bits[11:8] of the component + -- identification code. + PRMBL_1 : CIDR1_PRMBL_1_Field; + -- Read-only. Class of the component, for example, whether the component + -- is a ROM table or a generic CoreSight component. Contains bits[15:12] + -- of the component identification code. + CLASS : CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- CoreSight Component ID2 + type CIDR2_Register is record + -- Read-only. Preamble[2]. Contains bits[23:16] of the component + -- identification code. + PRMBL_2 : CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- CoreSight Component ID3 + type CIDR3_Register is record + -- Read-only. Preamble[3]. Contains bits[31:24] of the component + -- identification code. + PRMBL_3 : CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- TEAL registers accessible through the debug interface + type PPB_Peripheral is record + -- Provides the interface for generating Instrumentation packets + ITM_STIM0 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM1 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM2 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM3 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM4 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM5 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM6 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM7 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM8 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM9 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM10 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM11 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM12 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM13 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM14 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM15 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM16 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM17 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM18 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM19 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM20 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM21 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM22 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM23 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM24 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM25 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM26 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM27 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM28 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM29 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM30 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM31 : aliased HAL.UInt32; + -- Provide an individual enable bit for each ITM_STIM register + ITM_TER0 : aliased HAL.UInt32; + -- Controls which stimulus ports can be accessed by unprivileged code + ITM_TPR : aliased ITM_TPR_Register; + -- Configures and controls transfers through the ITM interface + ITM_TCR : aliased ITM_TCR_Register; + -- Integration Mode: Read ATB Ready + INT_ATREADY : aliased INT_ATREADY_Register; + -- Integration Mode: Write ATB Valid + INT_ATVALID : aliased INT_ATVALID_Register; + -- Integration Mode Control Register + ITM_ITCTRL : aliased ITM_ITCTRL_Register; + -- Provides CoreSight discovery information for the ITM + ITM_DEVARCH : aliased ITM_DEVARCH_Register; + -- Provides CoreSight discovery information for the ITM + ITM_DEVTYPE : aliased ITM_DEVTYPE_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR4 : aliased ITM_PIDR4_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR0 : aliased ITM_PIDR0_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR1 : aliased ITM_PIDR1_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR2 : aliased ITM_PIDR2_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR3 : aliased ITM_PIDR3_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR0 : aliased ITM_CIDR0_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR1 : aliased ITM_CIDR1_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR2 : aliased ITM_CIDR2_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR3 : aliased ITM_CIDR3_Register; + -- Provides configuration and status information for the DWT unit, and + -- used to control features of the unit + DWT_CTRL : aliased DWT_CTRL_Register; + -- Shows or sets the value of the processor cycle counter, CYCCNT + DWT_CYCCNT : aliased HAL.UInt32; + -- Counts the total cycles spent in exception processing + DWT_EXCCNT : aliased DWT_EXCCNT_Register; + -- Increments on the additional cycles required to execute all load or + -- store instructions + DWT_LSUCNT : aliased DWT_LSUCNT_Register; + -- Increments on the additional cycles required to execute all load or + -- store instructions + DWT_FOLDCNT : aliased DWT_FOLDCNT_Register; + -- Provides a reference value for use by watchpoint comparator 0 + DWT_COMP0 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 0 + DWT_FUNCTION0 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 1 + DWT_COMP1 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 1 + DWT_FUNCTION1 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 2 + DWT_COMP2 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 2 + DWT_FUNCTION2 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 3 + DWT_COMP3 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 3 + DWT_FUNCTION3 : aliased DWT_FUNCTION_Register; + -- Provides CoreSight discovery information for the DWT + DWT_DEVARCH : aliased DWT_DEVARCH_Register; + -- Provides CoreSight discovery information for the DWT + DWT_DEVTYPE : aliased DWT_DEVTYPE_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR4 : aliased DWT_PIDR4_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR0 : aliased DWT_PIDR0_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR1 : aliased DWT_PIDR1_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR2 : aliased DWT_PIDR2_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR3 : aliased DWT_PIDR3_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR0 : aliased DWT_CIDR0_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR1 : aliased DWT_CIDR1_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR2 : aliased DWT_CIDR2_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR3 : aliased DWT_CIDR3_Register; + -- Provides FPB implementation information, and the global enable for + -- the FPB unit + FP_CTRL : aliased FP_CTRL_Register; + -- Indicates whether the implementation supports Flash Patch remap and, + -- if it does, holds the target address for remap + FP_REMAP : aliased FP_REMAP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP0 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP1 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP2 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP3 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP4 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP5 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP6 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP7 : aliased FP_COMP_Register; + -- Provides CoreSight discovery information for the FPB + FP_DEVARCH : aliased FP_DEVARCH_Register; + -- Provides CoreSight discovery information for the FPB + FP_DEVTYPE : aliased FP_DEVTYPE_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR4 : aliased FP_PIDR4_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR0 : aliased FP_PIDR0_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR1 : aliased FP_PIDR1_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR2 : aliased FP_PIDR2_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR3 : aliased FP_PIDR3_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR0 : aliased FP_CIDR0_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR1 : aliased FP_CIDR1_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR2 : aliased FP_CIDR2_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR3 : aliased FP_CIDR3_Register; + -- Provides information about the interrupt controller + ICTR : aliased ICTR_Register; + -- Provides IMPLEMENTATION DEFINED configuration and control options + ACTLR : aliased ACTLR_Register; + -- Use the SysTick Control and Status Register to enable the SysTick + -- features. + SYST_CSR : aliased SYST_CSR_Register; + -- Use the SysTick Reload Value Register to specify the start value to + -- load into the current value register when the counter reaches 0. It + -- can be any value between 0 and 0x00FFFFFF. A start value of 0 is + -- possible, but has no effect because the SysTick interrupt and + -- COUNTFLAG are activated when counting from 1 to 0. The reset value of + -- this register is UNKNOWN. To generate a multi-shot timer with a + -- period of N processor clock cycles, use a RELOAD value of N-1. For + -- example, if the SysTick interrupt is required every 100 clock pulses, + -- set RELOAD to 99. + SYST_RVR : aliased SYST_RVR_Register; + -- Use the SysTick Current Value Register to find the current value in + -- the register. The reset value of this register is UNKNOWN. + SYST_CVR : aliased SYST_CVR_Register; + -- Use the SysTick Calibration Value Register to enable software to + -- scale to any required speed using divide and multiply. + SYST_CALIB : aliased SYST_CALIB_Register; + -- Enables or reads the enabled state of each group of 32 interrupts + NVIC_ISER0 : aliased HAL.UInt32; + -- Enables or reads the enabled state of each group of 32 interrupts + NVIC_ISER1 : aliased HAL.UInt32; + -- Clears or reads the enabled state of each group of 32 interrupts + NVIC_ICER0 : aliased HAL.UInt32; + -- Clears or reads the enabled state of each group of 32 interrupts + NVIC_ICER1 : aliased HAL.UInt32; + -- Enables or reads the pending state of each group of 32 interrupts + NVIC_ISPR0 : aliased HAL.UInt32; + -- Enables or reads the pending state of each group of 32 interrupts + NVIC_ISPR1 : aliased HAL.UInt32; + -- Clears or reads the pending state of each group of 32 interrupts + NVIC_ICPR0 : aliased HAL.UInt32; + -- Clears or reads the pending state of each group of 32 interrupts + NVIC_ICPR1 : aliased HAL.UInt32; + -- For each group of 32 interrupts, shows the active state of each + -- interrupt + NVIC_IABR0 : aliased HAL.UInt32; + -- For each group of 32 interrupts, shows the active state of each + -- interrupt + NVIC_IABR1 : aliased HAL.UInt32; + -- For each group of 32 interrupts, determines whether each interrupt + -- targets Non-secure or Secure state + NVIC_ITNS0 : aliased HAL.UInt32; + -- For each group of 32 interrupts, determines whether each interrupt + -- targets Non-secure or Secure state + NVIC_ITNS1 : aliased HAL.UInt32; + -- Sets or reads interrupt priorities + NVIC_IPR0 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR1 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR2 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR3 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR4 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR5 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR6 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR7 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR8 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR9 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR10 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR11 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR12 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR13 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR14 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR15 : aliased NVIC_IPR_Register; + -- Provides identification information for the PE, including an + -- implementer code for the device and a device ID number + CPUID : aliased CPUID_Register; + -- Controls and provides status information for NMI, PendSV, SysTick and + -- interrupts + ICSR : aliased ICSR_Register; + -- The VTOR indicates the offset of the vector table base address from + -- memory address 0x00000000. + VTOR : aliased VTOR_Register; + -- Use the Application Interrupt and Reset Control Register to: + -- determine data endianness, clear all active state information from + -- debug halt mode, request a system reset. + AIRCR : aliased AIRCR_Register; + -- System Control Register. Use the System Control Register for + -- power-management functions: signal to the system when the processor + -- can enter a low power state, control how the processor enters and + -- exits low power states. + SCR : aliased SCR_Register; + -- Sets or returns configuration and control data + CCR : aliased CCR_Register; + -- Sets or returns priority for system handlers 4 - 7 + SHPR1 : aliased SHPR1_Register; + -- Sets or returns priority for system handlers 8 - 11 + SHPR2 : aliased SHPR2_Register; + -- Sets or returns priority for system handlers 12 - 15 + SHPR3 : aliased SHPR3_Register; + -- Provides access to the active and pending status of system exceptions + SHCSR : aliased SHCSR_Register; + -- Contains the three Configurable Fault Status Registers. 31:16 UFSR: + -- Provides information on UsageFault exceptions 15:8 BFSR: Provides + -- information on BusFault exceptions 7:0 MMFSR: Provides information on + -- MemManage exceptions + CFSR : aliased CFSR_Register; + -- Shows the cause of any HardFaults + HFSR : aliased HFSR_Register; + -- Shows which debug event occurred + DFSR : aliased DFSR_Register; + -- Shows the address of the memory location that caused an MPU fault + MMFAR : aliased HAL.UInt32; + -- Shows the address associated with a precise data access BusFault + BFAR : aliased HAL.UInt32; + -- Gives top-level information about the instruction set supported by + -- the PE + ID_PFR0 : aliased ID_PFR0_Register; + -- Gives information about the programmers' model and Extensions support + ID_PFR1 : aliased ID_PFR1_Register; + -- Provides top level information about the debug system + ID_DFR0 : aliased ID_DFR0_Register; + -- Provides information about the IMPLEMENTATION DEFINED features of the + -- PE + ID_AFR0 : aliased ID_AFR0_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR0 : aliased ID_MMFR0_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR1 : aliased HAL.UInt32; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR2 : aliased ID_MMFR2_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR3 : aliased ID_MMFR3_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR0 : aliased ID_ISAR0_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR1 : aliased ID_ISAR1_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR2 : aliased ID_ISAR2_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR3 : aliased ID_ISAR3_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR4 : aliased ID_ISAR4_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR5 : aliased HAL.UInt32; + -- Provides information about the architecture of the caches. CTR is + -- RES0 if CLIDR is zero. + CTR : aliased CTR_Register; + -- Specifies the access privileges for coprocessors and the FP Extension + CPACR : aliased CPACR_Register; + -- Defines the Non-secure access permissions for both the FP Extension + -- and coprocessors CP0 to CP7 + NSACR : aliased NSACR_Register; + -- The MPU Type Register indicates how many regions the MPU `FTSSS + -- supports + MPU_TYPE : aliased MPU_TYPE_Register; + -- Enables the MPU and, when the MPU is enabled, controls whether the + -- default memory map is enabled as a background region for privileged + -- accesses, and whether the MPU is enabled for HardFaults, NMIs, and + -- exception handlers when FAULTMASK is set to 1 + MPU_CTRL : aliased MPU_CTRL_Register; + -- Selects the region currently accessed by MPU_RBAR and MPU_RLAR + MPU_RNR : aliased MPU_RNR_Register; + -- Provides indirect read and write access to the base address of the + -- currently selected MPU region `FTSSS + MPU_RBAR : aliased MPU_RBAR_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region `FTSSS + MPU_RLAR : aliased MPU_RLAR_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + MPU_RBAR_A1 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) + -- `FTSSS + MPU_RLAR_A1 : aliased MPU_RLAR_A_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + MPU_RBAR_A2 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) + -- `FTSSS + MPU_RLAR_A2 : aliased MPU_RLAR_A_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + MPU_RBAR_A3 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) + -- `FTSSS + MPU_RLAR_A3 : aliased MPU_RLAR_A_Register; + -- Along with MPU_MAIR1, provides the memory attribute encodings + -- corresponding to the AttrIndex values + MPU_MAIR0 : aliased MPU_MAIR0_Register; + -- Along with MPU_MAIR0, provides the memory attribute encodings + -- corresponding to the AttrIndex values + MPU_MAIR1 : aliased MPU_MAIR1_Register; + -- Allows enabling of the Security Attribution Unit + SAU_CTRL : aliased SAU_CTRL_Register; + -- Indicates the number of regions implemented by the Security + -- Attribution Unit + SAU_TYPE : aliased SAU_TYPE_Register; + -- Selects the region currently accessed by SAU_RBAR and SAU_RLAR + SAU_RNR : aliased SAU_RNR_Register; + -- Provides indirect read and write access to the base address of the + -- currently selected SAU region + SAU_RBAR : aliased SAU_RBAR_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected SAU region + SAU_RLAR : aliased SAU_RLAR_Register; + -- Provides information about any security related faults + SFSR : aliased SFSR_Register; + -- Shows the address of the memory location that caused a Security + -- violation + SFAR : aliased HAL.UInt32; + -- Controls halting debug + DHCSR : aliased DHCSR_Register; + -- With the DCRDR, provides debug access to the general-purpose + -- registers, special-purpose registers, and the FP extension registers. + -- A write to the DCRSR specifies the register to transfer, whether the + -- transfer is a read or write, and starts the transfer + DCRSR : aliased DCRSR_Register; + -- With the DCRSR, provides debug access to the general-purpose + -- registers, special-purpose registers, and the FP Extension registers. + -- If the Main Extension is implemented, it can also be used for message + -- passing between an external debugger and a debug agent running on the + -- PE + DCRDR : aliased HAL.UInt32; + -- Manages vector catch behavior and DebugMonitor handling when + -- debugging + DEMCR : aliased DEMCR_Register; + -- Provides control and status information for Secure debug + DSCSR : aliased DSCSR_Register; + -- Provides a mechanism for software to generate an interrupt + STIR : aliased STIR_Register; + -- Holds control data for the Floating-point extension + FPCCR : aliased FPCCR_Register; + -- Holds the location of the unpopulated floating-point register space + -- allocated on an exception stack frame + FPCAR : aliased FPCAR_Register; + -- Holds the default values for the floating-point status control data + -- that the PE assigns to the FPSCR when it creates a new floating-point + -- context + FPDSCR : aliased FPDSCR_Register; + -- Describes the features provided by the Floating-point Extension + MVFR0 : aliased MVFR0_Register; + -- Describes the features provided by the Floating-point Extension + MVFR1 : aliased MVFR1_Register; + -- Describes the features provided by the Floating-point Extension + MVFR2 : aliased MVFR2_Register; + -- Provides CoreSight discovery information for the SCS + DDEVARCH : aliased DDEVARCH_Register; + -- Provides CoreSight discovery information for the SCS + DDEVTYPE : aliased DDEVTYPE_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR4 : aliased DPIDR4_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR0 : aliased DPIDR0_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR1 : aliased DPIDR1_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR2 : aliased DPIDR2_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR3 : aliased DPIDR3_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR0 : aliased DCIDR0_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR1 : aliased DCIDR1_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR2 : aliased DCIDR2_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR3 : aliased DCIDR3_Register; + -- Programming Control Register + TRCPRGCTLR : aliased TRCPRGCTLR_Register; + -- The TRCSTATR indicates the ETM-Teal status + TRCSTATR : aliased TRCSTATR_Register; + -- The TRCCONFIGR sets the basic tracing options for the trace unit + TRCCONFIGR : aliased TRCCONFIGR_Register; + -- The TRCEVENTCTL0R controls the tracing of events in the trace stream. + -- The events also drive the ETM-Teal external outputs. + TRCEVENTCTL0R : aliased TRCEVENTCTL0R_Register; + -- The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + -- behave + TRCEVENTCTL1R : aliased TRCEVENTCTL1R_Register; + -- The TRCSTALLCTLR enables ETM-Teal to stall the processor if the + -- ETM-Teal FIFO goes over the programmed level to minimize risk of + -- overflow + TRCSTALLCTLR : aliased TRCSTALLCTLR_Register; + -- The TRCTSCTLR controls the insertion of global timestamps into the + -- trace stream. A timestamp is always inserted into the instruction + -- trace stream + TRCTSCTLR : aliased TRCTSCTLR_Register; + -- The TRCSYNCPR specifies the period of trace synchronization of the + -- trace streams. TRCSYNCPR defines a number of bytes of trace between + -- requests for trace synchronization. This value is always a power of + -- two + TRCSYNCPR : aliased TRCSYNCPR_Register; + -- The TRCCCCTLR sets the threshold value for instruction trace cycle + -- counting. The threshold represents the minimum interval between cycle + -- count trace packets + TRCCCCTLR : aliased TRCCCCTLR_Register; + -- The TRCVICTLR controls instruction trace filtering + TRCVICTLR : aliased TRCVICTLR_Register; + -- The TRCCNTRLDVR defines the reload value for the reduced function + -- counter + TRCCNTRLDVR0 : aliased TRCCNTRLDVR0_Register; + -- TRCIDR8 + TRCIDR8 : aliased HAL.UInt32; + -- TRCIDR9 + TRCIDR9 : aliased HAL.UInt32; + -- TRCIDR10 + TRCIDR10 : aliased HAL.UInt32; + -- TRCIDR11 + TRCIDR11 : aliased HAL.UInt32; + -- TRCIDR12 + TRCIDR12 : aliased HAL.UInt32; + -- TRCIDR13 + TRCIDR13 : aliased HAL.UInt32; + -- The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + -- features, and enables any features that are provided + TRCIMSPEC : aliased TRCIMSPEC_Register; + -- TRCIDR0 + TRCIDR0 : aliased TRCIDR0_Register; + -- TRCIDR1 + TRCIDR1 : aliased TRCIDR1_Register; + -- TRCIDR2 + TRCIDR2 : aliased TRCIDR2_Register; + -- TRCIDR3 + TRCIDR3 : aliased TRCIDR3_Register; + -- TRCIDR4 + TRCIDR4 : aliased TRCIDR4_Register; + -- TRCIDR5 + TRCIDR5 : aliased TRCIDR5_Register; + -- TRCIDR6 + TRCIDR6 : aliased HAL.UInt32; + -- TRCIDR7 + TRCIDR7 : aliased HAL.UInt32; + -- The TRCRSCTLR controls the trace resources + TRCRSCTLR2 : aliased TRCRSCTLR_Register; + -- The TRCRSCTLR controls the trace resources + TRCRSCTLR3 : aliased TRCRSCTLR_Register; + -- Controls the corresponding single-shot comparator resource + TRCSSCSR : aliased TRCSSCSR_Register; + -- Selects the PE comparator inputs for Single-shot control + TRCSSPCICR : aliased TRCSSPCICR_Register; + -- Requests the system to provide power to the trace unit + TRCPDCR : aliased TRCPDCR_Register; + -- Returns the following information about the trace unit: - OS Lock + -- status. - Core power domain status. - Power interruption status + TRCPDSR : aliased TRCPDSR_Register; + -- Trace Integration ATB Identification Register + TRCITATBIDR : aliased TRCITATBIDR_Register; + -- Trace Integration Instruction ATB In Register + TRCITIATBINR : aliased TRCITIATBINR_Register; + -- Trace Integration Instruction ATB Out Register + TRCITIATBOUTR : aliased TRCITIATBOUTR_Register; + -- Claim Tag Set Register + TRCCLAIMSET : aliased TRCCLAIMSET_Register; + -- Claim Tag Clear Register + TRCCLAIMCLR : aliased TRCCLAIMCLR_Register; + -- Returns the level of tracing that the trace unit can support + TRCAUTHSTATUS : aliased TRCAUTHSTATUS_Register; + -- TRCDEVARCH + TRCDEVARCH : aliased TRCDEVARCH_Register; + -- TRCDEVID + TRCDEVID : aliased HAL.UInt32; + -- TRCDEVTYPE + TRCDEVTYPE : aliased TRCDEVTYPE_Register; + -- TRCPIDR4 + TRCPIDR4 : aliased TRCPIDR4_Register; + -- TRCPIDR5 + TRCPIDR5 : aliased HAL.UInt32; + -- TRCPIDR6 + TRCPIDR6 : aliased HAL.UInt32; + -- TRCPIDR7 + TRCPIDR7 : aliased HAL.UInt32; + -- TRCPIDR0 + TRCPIDR0 : aliased TRCPIDR0_Register; + -- TRCPIDR1 + TRCPIDR1 : aliased TRCPIDR1_Register; + -- TRCPIDR2 + TRCPIDR2 : aliased TRCPIDR2_Register; + -- TRCPIDR3 + TRCPIDR3 : aliased TRCPIDR3_Register; + -- TRCCIDR0 + TRCCIDR0 : aliased TRCCIDR0_Register; + -- TRCCIDR1 + TRCCIDR1 : aliased TRCCIDR1_Register; + -- TRCCIDR2 + TRCCIDR2 : aliased TRCCIDR2_Register; + -- TRCCIDR3 + TRCCIDR3 : aliased TRCCIDR3_Register; + -- CTI Control Register + CTICONTROL : aliased CTICONTROL_Register; + -- CTI Interrupt Acknowledge Register + CTIINTACK : aliased CTIINTACK_Register; + -- CTI Application Trigger Set Register + CTIAPPSET : aliased CTIAPPSET_Register; + -- CTI Application Trigger Clear Register + CTIAPPCLEAR : aliased CTIAPPCLEAR_Register; + -- CTI Application Pulse Register + CTIAPPPULSE : aliased CTIAPPPULSE_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN0 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN1 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN2 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN3 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN4 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN5 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN6 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN7 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN0 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN1 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN2 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN3 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN4 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN5 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN6 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN7 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTITRIGINSTATUS : aliased CTITRIGINSTATUS_Register; + -- CTI Trigger In Status Register + CTITRIGOUTSTATUS : aliased CTITRIGOUTSTATUS_Register; + -- CTI Channel In Status Register + CTICHINSTATUS : aliased CTICHINSTATUS_Register; + -- Enable CTI Channel Gate register + CTIGATE : aliased CTIGATE_Register; + -- External Multiplexer Control register + ASICCTL : aliased HAL.UInt32; + -- Integration Test Channel Output register + ITCHOUT : aliased ITCHOUT_Register; + -- Integration Test Trigger Output register + ITTRIGOUT : aliased ITTRIGOUT_Register; + -- Integration Test Channel Input register + ITCHIN : aliased ITCHIN_Register; + -- Integration Mode Control register + ITCTRL : aliased ITCTRL_Register; + -- Device Architecture register + DEVARCH : aliased DEVARCH_Register; + -- Device Configuration register + DEVID : aliased DEVID_Register; + -- Device Type Identifier register + DEVTYPE : aliased DEVTYPE_Register; + -- CoreSight Peripheral ID4 + PIDR4 : aliased PIDR4_Register; + -- CoreSight Peripheral ID5 + PIDR5 : aliased HAL.UInt32; + -- CoreSight Peripheral ID6 + PIDR6 : aliased HAL.UInt32; + -- CoreSight Peripheral ID7 + PIDR7 : aliased HAL.UInt32; + -- CoreSight Peripheral ID0 + PIDR0 : aliased PIDR0_Register; + -- CoreSight Peripheral ID1 + PIDR1 : aliased PIDR1_Register; + -- CoreSight Peripheral ID2 + PIDR2 : aliased PIDR2_Register; + -- CoreSight Peripheral ID3 + PIDR3 : aliased PIDR3_Register; + -- CoreSight Component ID0 + CIDR0 : aliased CIDR0_Register; + -- CoreSight Component ID1 + CIDR1 : aliased CIDR1_Register; + -- CoreSight Component ID2 + CIDR2 : aliased CIDR2_Register; + -- CoreSight Component ID3 + CIDR3 : aliased CIDR3_Register; + end record + with Volatile; + + for PPB_Peripheral use record + ITM_STIM0 at 16#0# range 0 .. 31; + ITM_STIM1 at 16#4# range 0 .. 31; + ITM_STIM2 at 16#8# range 0 .. 31; + ITM_STIM3 at 16#C# range 0 .. 31; + ITM_STIM4 at 16#10# range 0 .. 31; + ITM_STIM5 at 16#14# range 0 .. 31; + ITM_STIM6 at 16#18# range 0 .. 31; + ITM_STIM7 at 16#1C# range 0 .. 31; + ITM_STIM8 at 16#20# range 0 .. 31; + ITM_STIM9 at 16#24# range 0 .. 31; + ITM_STIM10 at 16#28# range 0 .. 31; + ITM_STIM11 at 16#2C# range 0 .. 31; + ITM_STIM12 at 16#30# range 0 .. 31; + ITM_STIM13 at 16#34# range 0 .. 31; + ITM_STIM14 at 16#38# range 0 .. 31; + ITM_STIM15 at 16#3C# range 0 .. 31; + ITM_STIM16 at 16#40# range 0 .. 31; + ITM_STIM17 at 16#44# range 0 .. 31; + ITM_STIM18 at 16#48# range 0 .. 31; + ITM_STIM19 at 16#4C# range 0 .. 31; + ITM_STIM20 at 16#50# range 0 .. 31; + ITM_STIM21 at 16#54# range 0 .. 31; + ITM_STIM22 at 16#58# range 0 .. 31; + ITM_STIM23 at 16#5C# range 0 .. 31; + ITM_STIM24 at 16#60# range 0 .. 31; + ITM_STIM25 at 16#64# range 0 .. 31; + ITM_STIM26 at 16#68# range 0 .. 31; + ITM_STIM27 at 16#6C# range 0 .. 31; + ITM_STIM28 at 16#70# range 0 .. 31; + ITM_STIM29 at 16#74# range 0 .. 31; + ITM_STIM30 at 16#78# range 0 .. 31; + ITM_STIM31 at 16#7C# range 0 .. 31; + ITM_TER0 at 16#E00# range 0 .. 31; + ITM_TPR at 16#E40# range 0 .. 31; + ITM_TCR at 16#E80# range 0 .. 31; + INT_ATREADY at 16#EF0# range 0 .. 31; + INT_ATVALID at 16#EF8# range 0 .. 31; + ITM_ITCTRL at 16#F00# range 0 .. 31; + ITM_DEVARCH at 16#FBC# range 0 .. 31; + ITM_DEVTYPE at 16#FCC# range 0 .. 31; + ITM_PIDR4 at 16#FD0# range 0 .. 31; + ITM_PIDR5 at 16#FD4# range 0 .. 31; + ITM_PIDR6 at 16#FD8# range 0 .. 31; + ITM_PIDR7 at 16#FDC# range 0 .. 31; + ITM_PIDR0 at 16#FE0# range 0 .. 31; + ITM_PIDR1 at 16#FE4# range 0 .. 31; + ITM_PIDR2 at 16#FE8# range 0 .. 31; + ITM_PIDR3 at 16#FEC# range 0 .. 31; + ITM_CIDR0 at 16#FF0# range 0 .. 31; + ITM_CIDR1 at 16#FF4# range 0 .. 31; + ITM_CIDR2 at 16#FF8# range 0 .. 31; + ITM_CIDR3 at 16#FFC# range 0 .. 31; + DWT_CTRL at 16#1000# range 0 .. 31; + DWT_CYCCNT at 16#1004# range 0 .. 31; + DWT_EXCCNT at 16#100C# range 0 .. 31; + DWT_LSUCNT at 16#1014# range 0 .. 31; + DWT_FOLDCNT at 16#1018# range 0 .. 31; + DWT_COMP0 at 16#1020# range 0 .. 31; + DWT_FUNCTION0 at 16#1028# range 0 .. 31; + DWT_COMP1 at 16#1030# range 0 .. 31; + DWT_FUNCTION1 at 16#1038# range 0 .. 31; + DWT_COMP2 at 16#1040# range 0 .. 31; + DWT_FUNCTION2 at 16#1048# range 0 .. 31; + DWT_COMP3 at 16#1050# range 0 .. 31; + DWT_FUNCTION3 at 16#1058# range 0 .. 31; + DWT_DEVARCH at 16#1FBC# range 0 .. 31; + DWT_DEVTYPE at 16#1FCC# range 0 .. 31; + DWT_PIDR4 at 16#1FD0# range 0 .. 31; + DWT_PIDR5 at 16#1FD4# range 0 .. 31; + DWT_PIDR6 at 16#1FD8# range 0 .. 31; + DWT_PIDR7 at 16#1FDC# range 0 .. 31; + DWT_PIDR0 at 16#1FE0# range 0 .. 31; + DWT_PIDR1 at 16#1FE4# range 0 .. 31; + DWT_PIDR2 at 16#1FE8# range 0 .. 31; + DWT_PIDR3 at 16#1FEC# range 0 .. 31; + DWT_CIDR0 at 16#1FF0# range 0 .. 31; + DWT_CIDR1 at 16#1FF4# range 0 .. 31; + DWT_CIDR2 at 16#1FF8# range 0 .. 31; + DWT_CIDR3 at 16#1FFC# range 0 .. 31; + FP_CTRL at 16#2000# range 0 .. 31; + FP_REMAP at 16#2004# range 0 .. 31; + FP_COMP0 at 16#2008# range 0 .. 31; + FP_COMP1 at 16#200C# range 0 .. 31; + FP_COMP2 at 16#2010# range 0 .. 31; + FP_COMP3 at 16#2014# range 0 .. 31; + FP_COMP4 at 16#2018# range 0 .. 31; + FP_COMP5 at 16#201C# range 0 .. 31; + FP_COMP6 at 16#2020# range 0 .. 31; + FP_COMP7 at 16#2024# range 0 .. 31; + FP_DEVARCH at 16#2FBC# range 0 .. 31; + FP_DEVTYPE at 16#2FCC# range 0 .. 31; + FP_PIDR4 at 16#2FD0# range 0 .. 31; + FP_PIDR5 at 16#2FD4# range 0 .. 31; + FP_PIDR6 at 16#2FD8# range 0 .. 31; + FP_PIDR7 at 16#2FDC# range 0 .. 31; + FP_PIDR0 at 16#2FE0# range 0 .. 31; + FP_PIDR1 at 16#2FE4# range 0 .. 31; + FP_PIDR2 at 16#2FE8# range 0 .. 31; + FP_PIDR3 at 16#2FEC# range 0 .. 31; + FP_CIDR0 at 16#2FF0# range 0 .. 31; + FP_CIDR1 at 16#2FF4# range 0 .. 31; + FP_CIDR2 at 16#2FF8# range 0 .. 31; + FP_CIDR3 at 16#2FFC# range 0 .. 31; + ICTR at 16#E004# range 0 .. 31; + ACTLR at 16#E008# range 0 .. 31; + SYST_CSR at 16#E010# range 0 .. 31; + SYST_RVR at 16#E014# range 0 .. 31; + SYST_CVR at 16#E018# range 0 .. 31; + SYST_CALIB at 16#E01C# range 0 .. 31; + NVIC_ISER0 at 16#E100# range 0 .. 31; + NVIC_ISER1 at 16#E104# range 0 .. 31; + NVIC_ICER0 at 16#E180# range 0 .. 31; + NVIC_ICER1 at 16#E184# range 0 .. 31; + NVIC_ISPR0 at 16#E200# range 0 .. 31; + NVIC_ISPR1 at 16#E204# range 0 .. 31; + NVIC_ICPR0 at 16#E280# range 0 .. 31; + NVIC_ICPR1 at 16#E284# range 0 .. 31; + NVIC_IABR0 at 16#E300# range 0 .. 31; + NVIC_IABR1 at 16#E304# range 0 .. 31; + NVIC_ITNS0 at 16#E380# range 0 .. 31; + NVIC_ITNS1 at 16#E384# range 0 .. 31; + NVIC_IPR0 at 16#E400# range 0 .. 31; + NVIC_IPR1 at 16#E404# range 0 .. 31; + NVIC_IPR2 at 16#E408# range 0 .. 31; + NVIC_IPR3 at 16#E40C# range 0 .. 31; + NVIC_IPR4 at 16#E410# range 0 .. 31; + NVIC_IPR5 at 16#E414# range 0 .. 31; + NVIC_IPR6 at 16#E418# range 0 .. 31; + NVIC_IPR7 at 16#E41C# range 0 .. 31; + NVIC_IPR8 at 16#E420# range 0 .. 31; + NVIC_IPR9 at 16#E424# range 0 .. 31; + NVIC_IPR10 at 16#E428# range 0 .. 31; + NVIC_IPR11 at 16#E42C# range 0 .. 31; + NVIC_IPR12 at 16#E430# range 0 .. 31; + NVIC_IPR13 at 16#E434# range 0 .. 31; + NVIC_IPR14 at 16#E438# range 0 .. 31; + NVIC_IPR15 at 16#E43C# range 0 .. 31; + CPUID at 16#ED00# range 0 .. 31; + ICSR at 16#ED04# range 0 .. 31; + VTOR at 16#ED08# range 0 .. 31; + AIRCR at 16#ED0C# range 0 .. 31; + SCR at 16#ED10# range 0 .. 31; + CCR at 16#ED14# range 0 .. 31; + SHPR1 at 16#ED18# range 0 .. 31; + SHPR2 at 16#ED1C# range 0 .. 31; + SHPR3 at 16#ED20# range 0 .. 31; + SHCSR at 16#ED24# range 0 .. 31; + CFSR at 16#ED28# range 0 .. 31; + HFSR at 16#ED2C# range 0 .. 31; + DFSR at 16#ED30# range 0 .. 31; + MMFAR at 16#ED34# range 0 .. 31; + BFAR at 16#ED38# range 0 .. 31; + ID_PFR0 at 16#ED40# range 0 .. 31; + ID_PFR1 at 16#ED44# range 0 .. 31; + ID_DFR0 at 16#ED48# range 0 .. 31; + ID_AFR0 at 16#ED4C# range 0 .. 31; + ID_MMFR0 at 16#ED50# range 0 .. 31; + ID_MMFR1 at 16#ED54# range 0 .. 31; + ID_MMFR2 at 16#ED58# range 0 .. 31; + ID_MMFR3 at 16#ED5C# range 0 .. 31; + ID_ISAR0 at 16#ED60# range 0 .. 31; + ID_ISAR1 at 16#ED64# range 0 .. 31; + ID_ISAR2 at 16#ED68# range 0 .. 31; + ID_ISAR3 at 16#ED6C# range 0 .. 31; + ID_ISAR4 at 16#ED70# range 0 .. 31; + ID_ISAR5 at 16#ED74# range 0 .. 31; + CTR at 16#ED7C# range 0 .. 31; + CPACR at 16#ED88# range 0 .. 31; + NSACR at 16#ED8C# range 0 .. 31; + MPU_TYPE at 16#ED90# range 0 .. 31; + MPU_CTRL at 16#ED94# range 0 .. 31; + MPU_RNR at 16#ED98# range 0 .. 31; + MPU_RBAR at 16#ED9C# range 0 .. 31; + MPU_RLAR at 16#EDA0# range 0 .. 31; + MPU_RBAR_A1 at 16#EDA4# range 0 .. 31; + MPU_RLAR_A1 at 16#EDA8# range 0 .. 31; + MPU_RBAR_A2 at 16#EDAC# range 0 .. 31; + MPU_RLAR_A2 at 16#EDB0# range 0 .. 31; + MPU_RBAR_A3 at 16#EDB4# range 0 .. 31; + MPU_RLAR_A3 at 16#EDB8# range 0 .. 31; + MPU_MAIR0 at 16#EDC0# range 0 .. 31; + MPU_MAIR1 at 16#EDC4# range 0 .. 31; + SAU_CTRL at 16#EDD0# range 0 .. 31; + SAU_TYPE at 16#EDD4# range 0 .. 31; + SAU_RNR at 16#EDD8# range 0 .. 31; + SAU_RBAR at 16#EDDC# range 0 .. 31; + SAU_RLAR at 16#EDE0# range 0 .. 31; + SFSR at 16#EDE4# range 0 .. 31; + SFAR at 16#EDE8# range 0 .. 31; + DHCSR at 16#EDF0# range 0 .. 31; + DCRSR at 16#EDF4# range 0 .. 31; + DCRDR at 16#EDF8# range 0 .. 31; + DEMCR at 16#EDFC# range 0 .. 31; + DSCSR at 16#EE08# range 0 .. 31; + STIR at 16#EF00# range 0 .. 31; + FPCCR at 16#EF34# range 0 .. 31; + FPCAR at 16#EF38# range 0 .. 31; + FPDSCR at 16#EF3C# range 0 .. 31; + MVFR0 at 16#EF40# range 0 .. 31; + MVFR1 at 16#EF44# range 0 .. 31; + MVFR2 at 16#EF48# range 0 .. 31; + DDEVARCH at 16#EFBC# range 0 .. 31; + DDEVTYPE at 16#EFCC# range 0 .. 31; + DPIDR4 at 16#EFD0# range 0 .. 31; + DPIDR5 at 16#EFD4# range 0 .. 31; + DPIDR6 at 16#EFD8# range 0 .. 31; + DPIDR7 at 16#EFDC# range 0 .. 31; + DPIDR0 at 16#EFE0# range 0 .. 31; + DPIDR1 at 16#EFE4# range 0 .. 31; + DPIDR2 at 16#EFE8# range 0 .. 31; + DPIDR3 at 16#EFEC# range 0 .. 31; + DCIDR0 at 16#EFF0# range 0 .. 31; + DCIDR1 at 16#EFF4# range 0 .. 31; + DCIDR2 at 16#EFF8# range 0 .. 31; + DCIDR3 at 16#EFFC# range 0 .. 31; + TRCPRGCTLR at 16#41004# range 0 .. 31; + TRCSTATR at 16#4100C# range 0 .. 31; + TRCCONFIGR at 16#41010# range 0 .. 31; + TRCEVENTCTL0R at 16#41020# range 0 .. 31; + TRCEVENTCTL1R at 16#41024# range 0 .. 31; + TRCSTALLCTLR at 16#4102C# range 0 .. 31; + TRCTSCTLR at 16#41030# range 0 .. 31; + TRCSYNCPR at 16#41034# range 0 .. 31; + TRCCCCTLR at 16#41038# range 0 .. 31; + TRCVICTLR at 16#41080# range 0 .. 31; + TRCCNTRLDVR0 at 16#41140# range 0 .. 31; + TRCIDR8 at 16#41180# range 0 .. 31; + TRCIDR9 at 16#41184# range 0 .. 31; + TRCIDR10 at 16#41188# range 0 .. 31; + TRCIDR11 at 16#4118C# range 0 .. 31; + TRCIDR12 at 16#41190# range 0 .. 31; + TRCIDR13 at 16#41194# range 0 .. 31; + TRCIMSPEC at 16#411C0# range 0 .. 31; + TRCIDR0 at 16#411E0# range 0 .. 31; + TRCIDR1 at 16#411E4# range 0 .. 31; + TRCIDR2 at 16#411E8# range 0 .. 31; + TRCIDR3 at 16#411EC# range 0 .. 31; + TRCIDR4 at 16#411F0# range 0 .. 31; + TRCIDR5 at 16#411F4# range 0 .. 31; + TRCIDR6 at 16#411F8# range 0 .. 31; + TRCIDR7 at 16#411FC# range 0 .. 31; + TRCRSCTLR2 at 16#41208# range 0 .. 31; + TRCRSCTLR3 at 16#4120C# range 0 .. 31; + TRCSSCSR at 16#412A0# range 0 .. 31; + TRCSSPCICR at 16#412C0# range 0 .. 31; + TRCPDCR at 16#41310# range 0 .. 31; + TRCPDSR at 16#41314# range 0 .. 31; + TRCITATBIDR at 16#41EE4# range 0 .. 31; + TRCITIATBINR at 16#41EF4# range 0 .. 31; + TRCITIATBOUTR at 16#41EFC# range 0 .. 31; + TRCCLAIMSET at 16#41FA0# range 0 .. 31; + TRCCLAIMCLR at 16#41FA4# range 0 .. 31; + TRCAUTHSTATUS at 16#41FB8# range 0 .. 31; + TRCDEVARCH at 16#41FBC# range 0 .. 31; + TRCDEVID at 16#41FC8# range 0 .. 31; + TRCDEVTYPE at 16#41FCC# range 0 .. 31; + TRCPIDR4 at 16#41FD0# range 0 .. 31; + TRCPIDR5 at 16#41FD4# range 0 .. 31; + TRCPIDR6 at 16#41FD8# range 0 .. 31; + TRCPIDR7 at 16#41FDC# range 0 .. 31; + TRCPIDR0 at 16#41FE0# range 0 .. 31; + TRCPIDR1 at 16#41FE4# range 0 .. 31; + TRCPIDR2 at 16#41FE8# range 0 .. 31; + TRCPIDR3 at 16#41FEC# range 0 .. 31; + TRCCIDR0 at 16#41FF0# range 0 .. 31; + TRCCIDR1 at 16#41FF4# range 0 .. 31; + TRCCIDR2 at 16#41FF8# range 0 .. 31; + TRCCIDR3 at 16#41FFC# range 0 .. 31; + CTICONTROL at 16#42000# range 0 .. 31; + CTIINTACK at 16#42010# range 0 .. 31; + CTIAPPSET at 16#42014# range 0 .. 31; + CTIAPPCLEAR at 16#42018# range 0 .. 31; + CTIAPPPULSE at 16#4201C# range 0 .. 31; + CTIINEN0 at 16#42020# range 0 .. 31; + CTIINEN1 at 16#42024# range 0 .. 31; + CTIINEN2 at 16#42028# range 0 .. 31; + CTIINEN3 at 16#4202C# range 0 .. 31; + CTIINEN4 at 16#42030# range 0 .. 31; + CTIINEN5 at 16#42034# range 0 .. 31; + CTIINEN6 at 16#42038# range 0 .. 31; + CTIINEN7 at 16#4203C# range 0 .. 31; + CTIOUTEN0 at 16#420A0# range 0 .. 31; + CTIOUTEN1 at 16#420A4# range 0 .. 31; + CTIOUTEN2 at 16#420A8# range 0 .. 31; + CTIOUTEN3 at 16#420AC# range 0 .. 31; + CTIOUTEN4 at 16#420B0# range 0 .. 31; + CTIOUTEN5 at 16#420B4# range 0 .. 31; + CTIOUTEN6 at 16#420B8# range 0 .. 31; + CTIOUTEN7 at 16#420BC# range 0 .. 31; + CTITRIGINSTATUS at 16#42130# range 0 .. 31; + CTITRIGOUTSTATUS at 16#42134# range 0 .. 31; + CTICHINSTATUS at 16#42138# range 0 .. 31; + CTIGATE at 16#42140# range 0 .. 31; + ASICCTL at 16#42144# range 0 .. 31; + ITCHOUT at 16#42EE4# range 0 .. 31; + ITTRIGOUT at 16#42EE8# range 0 .. 31; + ITCHIN at 16#42EF4# range 0 .. 31; + ITCTRL at 16#42F00# range 0 .. 31; + DEVARCH at 16#42FBC# range 0 .. 31; + DEVID at 16#42FC8# range 0 .. 31; + DEVTYPE at 16#42FCC# range 0 .. 31; + PIDR4 at 16#42FD0# range 0 .. 31; + PIDR5 at 16#42FD4# range 0 .. 31; + PIDR6 at 16#42FD8# range 0 .. 31; + PIDR7 at 16#42FDC# range 0 .. 31; + PIDR0 at 16#42FE0# range 0 .. 31; + PIDR1 at 16#42FE4# range 0 .. 31; + PIDR2 at 16#42FE8# range 0 .. 31; + PIDR3 at 16#42FEC# range 0 .. 31; + CIDR0 at 16#42FF0# range 0 .. 31; + CIDR1 at 16#42FF4# range 0 .. 31; + CIDR2 at 16#42FF8# range 0 .. 31; + CIDR3 at 16#42FFC# range 0 .. 31; + end record; + + -- TEAL registers accessible through the debug interface + PPB_Periph : aliased PPB_Peripheral + with Import, Address => PPB_Base; + +end RP2350_SVD.PPB; diff --git a/src/svd/rp2350_svd-ppb_ns.ads b/src/svd/rp2350_svd-ppb_ns.ads new file mode 100644 index 0000000..ac24918 --- /dev/null +++ b/src/svd/rp2350_svd-ppb_ns.ads @@ -0,0 +1,6436 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- TEAL registers accessible through the debug interface +package RP2350_SVD.PPB_NS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ITM_TPR_PRIVMASK_Field is HAL.UInt4; + + -- Controls which stimulus ports can be accessed by unprivileged code + type ITM_TPR_Register is record + -- Bit mask to enable tracing on ITM stimulus ports + PRIVMASK : ITM_TPR_PRIVMASK_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_TPR_Register use record + PRIVMASK at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITM_TCR_TSPRESCALE_Field is HAL.UInt2; + subtype ITM_TCR_GTSFREQ_Field is HAL.UInt2; + subtype ITM_TCR_TRACEBUSID_Field is HAL.UInt7; + + -- Configures and controls transfers through the ITM interface + type ITM_TCR_Register is record + -- Enables the ITM + ITMENA : Boolean := False; + -- Enables Local timestamp generation + TSENA : Boolean := False; + -- Enables Synchronization packet transmission for a synchronous TPIU + SYNCENA : Boolean := False; + -- Enables forwarding of hardware event packet from the DWT unit to the + -- ITM for output to the TPIU + TXENA : Boolean := False; + -- Enables asynchronous clocking of the timestamp counter + SWOENA : Boolean := False; + -- Stall the PE to guarantee delivery of Data Trace packets. + STALLENA : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Local timestamp prescaler, used with the trace packet reference clock + TSPRESCALE : ITM_TCR_TSPRESCALE_Field := 16#0#; + -- Defines how often the ITM generates a global timestamp, based on the + -- global timestamp clock frequency, or disables generation of global + -- timestamps + GTSFREQ : ITM_TCR_GTSFREQ_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Identifier for multi-source trace stream formatting. If multi-source + -- trace is in use, the debugger must write a unique non-zero trace ID + -- value to this field + TRACEBUSID : ITM_TCR_TRACEBUSID_Field := 16#0#; + -- Read-only. Indicates whether the ITM is currently processing events + BUSY : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_TCR_Register use record + ITMENA at 0 range 0 .. 0; + TSENA at 0 range 1 .. 1; + SYNCENA at 0 range 2 .. 2; + TXENA at 0 range 3 .. 3; + SWOENA at 0 range 4 .. 4; + STALLENA at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + TSPRESCALE at 0 range 8 .. 9; + GTSFREQ at 0 range 10 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TRACEBUSID at 0 range 16 .. 22; + BUSY at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Integration Mode: Read ATB Ready + type INT_ATREADY_Register is record + -- Read-only. A read of this bit returns the value of ATREADY + ATREADY : Boolean; + -- Read-only. A read of this bit returns the value of AFVALID + AFVALID : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INT_ATREADY_Register use record + ATREADY at 0 range 0 .. 0; + AFVALID at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Integration Mode: Write ATB Valid + type INT_ATVALID_Register is record + -- A write to this bit gives the value of ATVALID + ATREADY : Boolean := False; + -- A write to this bit gives the value of AFREADY + AFREADY : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INT_ATVALID_Register use record + ATREADY at 0 range 0 .. 0; + AFREADY at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Integration Mode Control Register + type ITM_ITCTRL_Register is record + -- Integration mode enable bit - The possible values are: 0 - The trace + -- unit is not in integration mode. 1 - The trace unit is in integration + -- mode. This mode enables: A debug agent to perform topology detection. + -- SoC test software to perform integration testing. + IME : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_ITCTRL_Register use record + IME at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype ITM_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype ITM_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype ITM_DEVARCH_REVISION_Field is HAL.UInt4; + subtype ITM_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the ITM + type ITM_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : ITM_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : ITM_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : ITM_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : ITM_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype ITM_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype ITM_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : ITM_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : ITM_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR4_DES_2_Field is HAL.UInt4; + subtype ITM_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : ITM_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : ITM_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : ITM_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR1_PART_1_Field is HAL.UInt4; + subtype ITM_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : ITM_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : ITM_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR2_DES_1_Field is HAL.UInt3; + subtype ITM_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : ITM_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : ITM_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_PIDR3_CMOD_Field is HAL.UInt4; + subtype ITM_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : ITM_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : ITM_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : ITM_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype ITM_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : ITM_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : ITM_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : ITM_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITM_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the ITM + type ITM_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : ITM_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITM_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CTRL_POSTPRESET_Field is HAL.UInt4; + subtype DWT_CTRL_POSTINIT_Field is HAL.UInt4; + subtype DWT_CTRL_SYNCTAP_Field is HAL.UInt2; + subtype DWT_CTRL_NUMCOMP_Field is HAL.UInt4; + + -- Provides configuration and status information for the DWT unit, and used + -- to control features of the unit + type DWT_CTRL_Register is record + -- Enables CYCCNT + CYCCNTENA : Boolean := False; + -- Reload value for the POSTCNT counter + POSTPRESET : DWT_CTRL_POSTPRESET_Field := 16#2#; + -- Initial value for the POSTCNT counter + POSTINIT : DWT_CTRL_POSTINIT_Field := 16#1#; + -- Selects the position of the POSTCNT tap on the CYCCNT counter + CYCTAP : Boolean := False; + -- Selects the position of the synchronization packet counter tap on the + -- CYCCNT counter. This determines the Synchronization packet rate + SYNCTAP : DWT_CTRL_SYNCTAP_Field := 16#2#; + -- Enables use of POSTCNT counter as a timer for Periodic PC Sample + -- packet generation + PCSAMPLENA : Boolean := True; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Enables generation of Exception Trace packets + EXTTRCENA : Boolean := False; + -- Enables DWT_CPICNT counter + CPIEVTENA : Boolean := False; + -- Enables DWT_EXCCNT counter + EXCEVTENA : Boolean := True; + -- Enable DWT_SLEEPCNT counter + SLEEPEVTENA : Boolean := False; + -- Enables DWT_LSUCNT counter + LSUEVTENA : Boolean := True; + -- Enables DWT_FOLDCNT counter + FOLDEVTENA : Boolean := True; + -- Enables Event Counter packet generation on POSTCNT underflow + CYCEVTENA : Boolean := True; + -- Controls whether the cycle counter is disabled in Secure state + CYCDISS : Boolean := False; + -- Read-only. Indicates whether the implementation does not include the + -- profiling counters + NOPRFCNT : Boolean := True; + -- Read-only. Indicates whether the implementation does not include a + -- cycle counter + NOCYCCNT : Boolean := True; + -- Read-only. Reserved, RAZ + NOEXTTRIG : Boolean := False; + -- Read-only. Indicates whether the implementation does not support + -- trace + NOTRCPKT : Boolean := False; + -- Read-only. Number of DWT comparators implemented + NUMCOMP : DWT_CTRL_NUMCOMP_Field := 16#7#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CTRL_Register use record + CYCCNTENA at 0 range 0 .. 0; + POSTPRESET at 0 range 1 .. 4; + POSTINIT at 0 range 5 .. 8; + CYCTAP at 0 range 9 .. 9; + SYNCTAP at 0 range 10 .. 11; + PCSAMPLENA at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + EXTTRCENA at 0 range 16 .. 16; + CPIEVTENA at 0 range 17 .. 17; + EXCEVTENA at 0 range 18 .. 18; + SLEEPEVTENA at 0 range 19 .. 19; + LSUEVTENA at 0 range 20 .. 20; + FOLDEVTENA at 0 range 21 .. 21; + CYCEVTENA at 0 range 22 .. 22; + CYCDISS at 0 range 23 .. 23; + NOPRFCNT at 0 range 24 .. 24; + NOCYCCNT at 0 range 25 .. 25; + NOEXTTRIG at 0 range 26 .. 26; + NOTRCPKT at 0 range 27 .. 27; + NUMCOMP at 0 range 28 .. 31; + end record; + + subtype DWT_EXCCNT_EXCCNT_Field is HAL.UInt8; + + -- Counts the total cycles spent in exception processing + type DWT_EXCCNT_Register is record + -- Counts one on each cycle when all of the following are true: - + -- DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is + -- executed, see DWT_CPICNT. - An exception-entry or exception-exit + -- related operation is in progress. - Either + -- SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation + -- is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + EXCCNT : DWT_EXCCNT_EXCCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_EXCCNT_Register use record + EXCCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_LSUCNT_LSUCNT_Field is HAL.UInt8; + + -- Increments on the additional cycles required to execute all load or + -- store instructions + type DWT_LSUCNT_Register is record + -- Counts one on each cycle when all of the following are true: - + -- DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is + -- executed, see DWT_CPICNT. - No exception-entry or exception-exit + -- operation is in progress, see DWT_EXCCNT. - A load-store operation is + -- in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or + -- NS-Req for the operation is set to Non-secure and + -- NoninvasiveDebugAllowed() == TRUE. + LSUCNT : DWT_LSUCNT_LSUCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_LSUCNT_Register use record + LSUCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_FOLDCNT_FOLDCNT_Field is HAL.UInt8; + + -- Increments on the additional cycles required to execute all load or + -- store instructions + type DWT_FOLDCNT_Register is record + -- Counts on each cycle when all of the following are true: - + -- DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two + -- instructions are executed, see DWT_CPICNT. - Either + -- SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure + -- state and NoninvasiveDebugAllowed() == TRUE. The counter is + -- incremented by the number of instructions executed, minus one + FOLDCNT : DWT_FOLDCNT_FOLDCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_FOLDCNT_Register use record + FOLDCNT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_FUNCTION_MATCH_Field is HAL.UInt4; + subtype DWT_FUNCTION_ACTION_Field is HAL.UInt2; + subtype DWT_FUNCTION_DATAVSIZE_Field is HAL.UInt2; + subtype DWT_FUNCTION_ID_Field is HAL.UInt5; + + -- Controls the operation of watchpoint comparator 0 + type DWT_FUNCTION_Register is record + -- Controls the type of match generated by this comparator + MATCH : DWT_FUNCTION_MATCH_Field := 16#0#; + -- Defines the action on a match. This field is ignored and the + -- comparator generates no actions if it is disabled by MATCH + ACTION : DWT_FUNCTION_ACTION_Field := 16#0#; + -- unspecified + Reserved_6_9 : HAL.UInt4 := 16#0#; + -- Defines the size of the object being watched for by Data Value and + -- Data Address comparators + DATAVSIZE : DWT_FUNCTION_DATAVSIZE_Field := 16#0#; + -- unspecified + Reserved_12_23 : HAL.UInt12 := 16#0#; + -- Read-only. Set to 1 when the comparator matches + MATCHED : Boolean := False; + -- unspecified + Reserved_25_26 : HAL.UInt2 := 16#0#; + -- Read-only. Identifies the capabilities for MATCH for comparator *n + ID : DWT_FUNCTION_ID_Field := 16#B#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_FUNCTION_Register use record + MATCH at 0 range 0 .. 3; + ACTION at 0 range 4 .. 5; + Reserved_6_9 at 0 range 6 .. 9; + DATAVSIZE at 0 range 10 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + MATCHED at 0 range 24 .. 24; + Reserved_25_26 at 0 range 25 .. 26; + ID at 0 range 27 .. 31; + end record; + + subtype DWT_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype DWT_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype DWT_DEVARCH_REVISION_Field is HAL.UInt4; + subtype DWT_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the DWT + type DWT_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : DWT_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : DWT_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : DWT_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : DWT_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DWT_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DWT_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : DWT_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : DWT_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR4_DES_2_Field is HAL.UInt4; + subtype DWT_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : DWT_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : DWT_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : DWT_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR1_PART_1_Field is HAL.UInt4; + subtype DWT_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : DWT_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : DWT_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR2_DES_1_Field is HAL.UInt3; + subtype DWT_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : DWT_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : DWT_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_PIDR3_CMOD_Field is HAL.UInt4; + subtype DWT_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : DWT_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : DWT_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : DWT_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype DWT_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : DWT_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : DWT_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : DWT_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DWT_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the DWT + type DWT_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : DWT_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DWT_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CTRL_NUM_CODE_7_4_Field is HAL.UInt4; + subtype FP_CTRL_NUM_LIT_Field is HAL.UInt4; + subtype FP_CTRL_NUM_CODE_14_12_Field is HAL.UInt3; + subtype FP_CTRL_REV_Field is HAL.UInt4; + + -- Provides FPB implementation information, and the global enable for the + -- FPB unit + type FP_CTRL_Register is record + -- Enables the FPB + ENABLE : Boolean := False; + -- Writes to the FP_CTRL are ignored unless KEY is concurrently written + -- to one + KEY : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Read-only. Indicates the number of implemented instruction address + -- comparators. Zero indicates no Instruction Address comparators are + -- implemented. The Instruction Address comparators are numbered from 0 + -- to NUM_CODE - 1 + NUM_CODE_7_4 : FP_CTRL_NUM_CODE_7_4_Field := 16#8#; + -- Read-only. Indicates the number of implemented literal address + -- comparators. The Literal Address comparators are numbered from + -- NUM_CODE to NUM_CODE + NUM_LIT - 1 + NUM_LIT : FP_CTRL_NUM_LIT_Field := 16#5#; + -- Read-only. Indicates the number of implemented instruction address + -- comparators. Zero indicates no Instruction Address comparators are + -- implemented. The Instruction Address comparators are numbered from 0 + -- to NUM_CODE - 1 + NUM_CODE_14_12 : FP_CTRL_NUM_CODE_14_12_Field := 16#5#; + -- unspecified + Reserved_15_27 : HAL.UInt13 := 16#0#; + -- Read-only. Flash Patch and Breakpoint Unit architecture revision + REV : FP_CTRL_REV_Field := 16#6#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + KEY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + NUM_CODE_7_4 at 0 range 4 .. 7; + NUM_LIT at 0 range 8 .. 11; + NUM_CODE_14_12 at 0 range 12 .. 14; + Reserved_15_27 at 0 range 15 .. 27; + REV at 0 range 28 .. 31; + end record; + + subtype FP_REMAP_REMAP_Field is HAL.UInt24; + + -- Indicates whether the implementation supports Flash Patch remap and, if + -- it does, holds the target address for remap + type FP_REMAP_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5; + -- Read-only. Holds the bits[28:5] of the Flash Patch remap address + REMAP : FP_REMAP_REMAP_Field; + -- Read-only. Indicates whether the FPB unit supports the Flash Patch + -- remap function + RMPSPT : Boolean; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_REMAP_Register use record + Reserved_0_4 at 0 range 0 .. 4; + REMAP at 0 range 5 .. 28; + RMPSPT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Holds an address for comparison. The effect of the match depends on the + -- configuration of the FPB and whether the comparator is an instruction + -- address comparator or a literal address comparator + type FP_COMP_Register is record + -- Selects between flashpatch and breakpoint functionality + BE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_COMP_Register use record + BE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype FP_DEVARCH_ARCHPART_Field is HAL.UInt12; + subtype FP_DEVARCH_ARCHVER_Field is HAL.UInt4; + subtype FP_DEVARCH_REVISION_Field is HAL.UInt4; + subtype FP_DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the FPB + type FP_DEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : FP_DEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : FP_DEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : FP_DEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : FP_DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_DEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype FP_DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype FP_DEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FPB + type FP_DEVTYPE_Register is record + -- Read-only. Component major type + MAJOR : FP_DEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : FP_DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR4_DES_2_Field is HAL.UInt4; + subtype FP_PIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : FP_PIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : FP_PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : FP_PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR1_PART_1_Field is HAL.UInt4; + subtype FP_PIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : FP_PIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : FP_PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR2_DES_1_Field is HAL.UInt3; + subtype FP_PIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : FP_PIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : FP_PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_PIDR3_CMOD_Field is HAL.UInt4; + subtype FP_PIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_PIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : FP_PIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : FP_PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : FP_CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype FP_CIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : FP_CIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : FP_CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : FP_CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype FP_CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the FP + type FP_CIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : FP_CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FP_CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ICTR_INTLINESNUM_Field is HAL.UInt4; + + -- Provides information about the interrupt controller + type ICTR_Register is record + -- Read-only. Indicates the number of the highest implemented register + -- in each of the NVIC control register sets, or in the case of + -- NVIC_IPR*n, 4×INTLINESNUM + INTLINESNUM : ICTR_INTLINESNUM_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICTR_Register use record + INTLINESNUM at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Provides IMPLEMENTATION DEFINED configuration and control options + type ACTLR_Register is record + -- Disable dual-issue. + DISMCYCINT : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Disable dual-issue. + DISFOLD : Boolean := False; + -- unspecified + Reserved_3_8 : HAL.UInt6 := 16#0#; + -- Disable out-of-order FP instruction completion + DISOOFP : Boolean := False; + -- Disable FPU exception outputs + FPEXCODIS : Boolean := False; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Disable ATB Flush + DISITMATBFLUSH : Boolean := False; + -- unspecified + Reserved_13_28 : HAL.UInt16 := 16#0#; + -- External Exclusives Allowed with no MPU + EXTEXCLALL : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ACTLR_Register use record + DISMCYCINT at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + DISFOLD at 0 range 2 .. 2; + Reserved_3_8 at 0 range 3 .. 8; + DISOOFP at 0 range 9 .. 9; + FPEXCODIS at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + DISITMATBFLUSH at 0 range 12 .. 12; + Reserved_13_28 at 0 range 13 .. 28; + EXTEXCLALL at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Use the SysTick Control and Status Register to enable the SysTick + -- features. + type SYST_CSR_Register is record + -- Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled. + ENABLE : Boolean := False; + -- Enables SysTick exception request: 0 = Counting down to zero does not + -- assert the SysTick exception request. 1 = Counting down to zero to + -- asserts the SysTick exception request. + TICKINT : Boolean := False; + -- SysTick clock source. Always reads as one if SYST_CALIB reports + -- NOREF. Selects the SysTick timer clock source: 0 = External reference + -- clock. 1 = Processor clock. + CLKSOURCE : Boolean := False; + -- unspecified + Reserved_3_15 : HAL.UInt13 := 16#0#; + -- Read-only. Returns 1 if timer counted to 0 since last time this was + -- read. Clears on read by application or debugger. + COUNTFLAG : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CSR_Register use record + ENABLE at 0 range 0 .. 0; + TICKINT at 0 range 1 .. 1; + CLKSOURCE at 0 range 2 .. 2; + Reserved_3_15 at 0 range 3 .. 15; + COUNTFLAG at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype SYST_RVR_RELOAD_Field is HAL.UInt24; + + -- Use the SysTick Reload Value Register to specify the start value to load + -- into the current value register when the counter reaches 0. It can be + -- any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but + -- has no effect because the SysTick interrupt and COUNTFLAG are activated + -- when counting from 1 to 0. The reset value of this register is UNKNOWN. + -- To generate a multi-shot timer with a period of N processor clock + -- cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt + -- is required every 100 clock pulses, set RELOAD to 99. + type SYST_RVR_Register is record + -- Value to load into the SysTick Current Value Register when the + -- counter reaches 0. + RELOAD : SYST_RVR_RELOAD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_RVR_Register use record + RELOAD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SYST_CVR_CURRENT_Field is HAL.UInt24; + + -- Use the SysTick Current Value Register to find the current value in the + -- register. The reset value of this register is UNKNOWN. + type SYST_CVR_Register is record + -- Reads return the current value of the SysTick counter. This register + -- is write-clear. Writing to it with any value clears the register to + -- 0. Clearing this register also clears the COUNTFLAG bit of the + -- SysTick Control and Status Register. + CURRENT : SYST_CVR_CURRENT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CVR_Register use record + CURRENT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SYST_CALIB_TENMS_Field is HAL.UInt24; + + -- Use the SysTick Calibration Value Register to enable software to scale + -- to any required speed using divide and multiply. + type SYST_CALIB_Register is record + -- Read-only. An optional Reload value to be used for 10ms (100Hz) + -- timing, subject to system clock skew errors. If the value reads as 0, + -- the calibration value is not known. + TENMS : SYST_CALIB_TENMS_Field; + -- unspecified + Reserved_24_29 : HAL.UInt6; + -- Read-only. If reads as 1, the calibration value for 10ms is inexact + -- (due to clock frequency). + SKEW : Boolean; + -- Read-only. If reads as 1, the Reference clock is not provided - the + -- CLKSOURCE bit of the SysTick Control and Status register will be + -- forced to 1 and cannot be cleared to 0. + NOREF : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SYST_CALIB_Register use record + TENMS at 0 range 0 .. 23; + Reserved_24_29 at 0 range 24 .. 29; + SKEW at 0 range 30 .. 30; + NOREF at 0 range 31 .. 31; + end record; + + subtype NVIC_IPR_PRI_N0_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N1_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N2_Field is HAL.UInt4; + subtype NVIC_IPR_PRI_N3_Field is HAL.UInt4; + + -- Sets or reads interrupt priorities + type NVIC_IPR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+0, or + -- RES0 if the PE does not implement this interrupt + PRI_N0 : NVIC_IPR_PRI_N0_Field := 16#0#; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+1, or + -- RES0 if the PE does not implement this interrupt + PRI_N1 : NVIC_IPR_PRI_N1_Field := 16#0#; + -- unspecified + Reserved_16_19 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+2, or + -- RES0 if the PE does not implement this interrupt + PRI_N2 : NVIC_IPR_PRI_N2_Field := 16#0#; + -- unspecified + Reserved_24_27 : HAL.UInt4 := 16#0#; + -- For register NVIC_IPRn, the priority of interrupt number 4*n+3, or + -- RES0 if the PE does not implement this interrupt + PRI_N3 : NVIC_IPR_PRI_N3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NVIC_IPR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + PRI_N0 at 0 range 4 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + PRI_N1 at 0 range 12 .. 15; + Reserved_16_19 at 0 range 16 .. 19; + PRI_N2 at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + PRI_N3 at 0 range 28 .. 31; + end record; + + subtype CPUID_REVISION_Field is HAL.UInt4; + subtype CPUID_PARTNO_Field is HAL.UInt12; + subtype CPUID_ARCHITECTURE_Field is HAL.UInt4; + subtype CPUID_VARIANT_Field is HAL.UInt4; + subtype CPUID_IMPLEMENTER_Field is HAL.UInt8; + + -- Provides identification information for the PE, including an implementer + -- code for the device and a device ID number + type CPUID_Register is record + -- Read-only. IMPLEMENTATION DEFINED revision number for the device + REVISION : CPUID_REVISION_Field; + -- Read-only. IMPLEMENTATION DEFINED primary part number for the device + PARTNO : CPUID_PARTNO_Field; + -- Read-only. Defines the Architecture implemented by the PE + ARCHITECTURE : CPUID_ARCHITECTURE_Field; + -- Read-only. IMPLEMENTATION DEFINED variant number. Typically, this + -- field is used to distinguish between different product variants, or + -- major revisions of a product + VARIANT : CPUID_VARIANT_Field; + -- Read-only. This field must hold an implementer code that has been + -- assigned by ARM + IMPLEMENTER : CPUID_IMPLEMENTER_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPUID_Register use record + REVISION at 0 range 0 .. 3; + PARTNO at 0 range 4 .. 15; + ARCHITECTURE at 0 range 16 .. 19; + VARIANT at 0 range 20 .. 23; + IMPLEMENTER at 0 range 24 .. 31; + end record; + + subtype ICSR_VECTACTIVE_Field is HAL.UInt9; + subtype ICSR_VECTPENDING_Field is HAL.UInt9; + + -- Controls and provides status information for NMI, PendSV, SysTick and + -- interrupts + type ICSR_Register is record + -- Read-only. The exception number of the current executing exception + VECTACTIVE : ICSR_VECTACTIVE_Field := 16#0#; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- Read-only. In Handler mode, indicates whether there is more than one + -- active exception + RETTOBASE : Boolean := False; + -- Read-only. The exception number of the highest priority pending and + -- enabled interrupt + VECTPENDING : ICSR_VECTPENDING_Field := 16#0#; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Read-only. Indicates whether an external interrupt, generated by the + -- NVIC, is pending + ISRPENDING : Boolean := False; + -- Read-only. Indicates whether a pending exception will be serviced on + -- exit from debug halt state + ISRPREEMPT : Boolean := False; + -- Controls whether in a single SysTick implementation, the SysTick is + -- Secure or Non-secure + STTNS : Boolean := False; + -- Allows the SysTick exception pend state to be cleared `FTSSS + PENDSTCLR : Boolean := False; + -- Read-only. Indicates whether the SysTick `FTSSS exception is pending + PENDSTSET : Boolean := False; + -- Allows the PendSV exception pend state to be cleared `FTSSS + PENDSVCLR : Boolean := False; + -- Read-only. Indicates whether the PendSV `FTSSS exception is pending + PENDSVSET : Boolean := False; + -- unspecified + Reserved_29_29 : HAL.Bit := 16#0#; + -- Allows the NMI exception pend state to be cleared + PENDNMICLR : Boolean := False; + -- Read-only. Indicates whether the NMI exception is pending + PENDNMISET : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ICSR_Register use record + VECTACTIVE at 0 range 0 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + RETTOBASE at 0 range 11 .. 11; + VECTPENDING at 0 range 12 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + ISRPENDING at 0 range 22 .. 22; + ISRPREEMPT at 0 range 23 .. 23; + STTNS at 0 range 24 .. 24; + PENDSTCLR at 0 range 25 .. 25; + PENDSTSET at 0 range 26 .. 26; + PENDSVCLR at 0 range 27 .. 27; + PENDSVSET at 0 range 28 .. 28; + Reserved_29_29 at 0 range 29 .. 29; + PENDNMICLR at 0 range 30 .. 30; + PENDNMISET at 0 range 31 .. 31; + end record; + + subtype VTOR_TBLOFF_Field is HAL.UInt25; + + -- The VTOR indicates the offset of the vector table base address from + -- memory address 0x00000000. + type VTOR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Vector table base offset field. It contains bits[31:7] of the offset + -- of the table base from the bottom of the memory map. + TBLOFF : VTOR_TBLOFF_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for VTOR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + TBLOFF at 0 range 7 .. 31; + end record; + + subtype AIRCR_PRIGROUP_Field is HAL.UInt3; + subtype AIRCR_VECTKEY_Field is HAL.UInt16; + + -- Use the Application Interrupt and Reset Control Register to: determine + -- data endianness, clear all active state information from debug halt + -- mode, request a system reset. + type AIRCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Clears all active state information for fixed and configurable + -- exceptions. This bit: is self-clearing, can only be set by the DAP + -- when the core is halted. When set: clears all active exception status + -- of the processor, forces a return to Thread mode, forces an IPSR of + -- 0. A debugger must re-initialize the stack. + VECTCLRACTIVE : Boolean := False; + -- Writing 1 to this bit causes the SYSRESETREQ signal to the outer + -- system to be asserted to request a reset. The intention is to force a + -- large system reset of all major components except for debug. The + -- C_HALT bit in the DHCSR is cleared as a result of the system reset + -- requested. The debugger does not lose contact with the device. + SYSRESETREQ : Boolean := False; + -- System reset request, Secure state only. 0 SYSRESETREQ functionality + -- is available to both Security states. 1 SYSRESETREQ functionality is + -- only available to Secure state. + SYSRESETREQS : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Interrupt priority grouping field. This field determines the split of + -- group priority from subpriority. See + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- + -- https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + PRIGROUP : AIRCR_PRIGROUP_Field := 16#0#; + -- unspecified + Reserved_11_12 : HAL.UInt2 := 16#0#; + -- BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, + -- HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and + -- exceptions can target Non-secure HardFault. + BFHFNMINS : Boolean := False; + -- Prioritize Secure exceptions. The value of this bit defines whether + -- Secure exception priority boosting is enabled. 0 Priority ranges of + -- Secure and Non-secure exceptions are identical. 1 Non-secure + -- exceptions are de-prioritized. + PRIS : Boolean := False; + -- Read-only. Data endianness implemented: 0 = Little-endian. + ENDIANESS : Boolean := False; + -- Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, + -- otherwise the write is ignored. + VECTKEY : AIRCR_VECTKEY_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AIRCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTCLRACTIVE at 0 range 1 .. 1; + SYSRESETREQ at 0 range 2 .. 2; + SYSRESETREQS at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + PRIGROUP at 0 range 8 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + BFHFNMINS at 0 range 13 .. 13; + PRIS at 0 range 14 .. 14; + ENDIANESS at 0 range 15 .. 15; + VECTKEY at 0 range 16 .. 31; + end record; + + -- System Control Register. Use the System Control Register for + -- power-management functions: signal to the system when the processor can + -- enter a low power state, control how the processor enters and exits low + -- power states. + type SCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Indicates sleep-on-exit when returning from Handler mode to Thread + -- mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter + -- sleep, or deep sleep, on return from an ISR to Thread mode. Setting + -- this bit to 1 enables an interrupt driven application to avoid + -- returning to an empty main application. + SLEEPONEXIT : Boolean := False; + -- Controls whether the processor uses sleep or deep sleep as its low + -- power mode: 0 = Sleep. 1 = Deep sleep. + SLEEPDEEP : Boolean := False; + -- 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only + -- available to Secure state + SLEEPDEEPS : Boolean := False; + -- Send Event on Pending bit: 0 = Only enabled interrupts or events can + -- wakeup the processor, disabled interrupts are excluded. 1 = Enabled + -- events and all interrupts, including disabled interrupts, can wakeup + -- the processor. When an event or interrupt becomes pending, the event + -- signal wakes up the processor from WFE. If the processor is not + -- waiting for an event, the event is registered and affects the next + -- WFE. The processor also wakes up on execution of an SEV instruction + -- or an external event. + SEVONPEND : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SLEEPONEXIT at 0 range 1 .. 1; + SLEEPDEEP at 0 range 2 .. 2; + SLEEPDEEPS at 0 range 3 .. 3; + SEVONPEND at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Sets or returns configuration and control data + type CCR_Register is record + -- Read-only. Reserved, RES1 + RES1_1 : Boolean := True; + -- Determines whether unprivileged accesses are permitted to pend + -- interrupts via the STIR + USERSETMPEND : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Controls the trapping of unaligned word or halfword accesses + UNALIGN_TRP : Boolean := False; + -- Controls the generation of a DIVBYZERO UsageFault when attempting to + -- perform integer division by zero + DIV_0_TRP : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Determines the effect of precise BusFaults on handlers running at a + -- requested priority less than 0 + BFHFNMIGN : Boolean := False; + -- Read-only. Reserved, RES1 + RES1 : Boolean := True; + -- Controls the effect of a stack limit violation while executing at a + -- requested priority less than 0 + STKOFHFNMIGN : Boolean := False; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Read-only. Enables data caching of all data accesses to Normal memory + -- `FTSSS + DC : Boolean := False; + -- Read-only. This is a global enable bit for instruction caches in the + -- selected Security state + IC : Boolean := False; + -- Read-only. Enables program flow prediction `FTSSS + BP : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CCR_Register use record + RES1_1 at 0 range 0 .. 0; + USERSETMPEND at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + UNALIGN_TRP at 0 range 3 .. 3; + DIV_0_TRP at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + BFHFNMIGN at 0 range 8 .. 8; + RES1 at 0 range 9 .. 9; + STKOFHFNMIGN at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + DC at 0 range 16 .. 16; + IC at 0 range 17 .. 17; + BP at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype SHPR1_PRI_4_3_Field is HAL.UInt3; + subtype SHPR1_PRI_5_3_Field is HAL.UInt3; + subtype SHPR1_PRI_6_3_Field is HAL.UInt3; + subtype SHPR1_PRI_7_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 4 - 7 + type SHPR1_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Priority of system handler 4, SecureFault + PRI_4_3 : SHPR1_PRI_4_3_Field := 16#0#; + -- unspecified + Reserved_8_12 : HAL.UInt5 := 16#0#; + -- Priority of system handler 5, SecureFault + PRI_5_3 : SHPR1_PRI_5_3_Field := 16#0#; + -- unspecified + Reserved_16_20 : HAL.UInt5 := 16#0#; + -- Priority of system handler 6, SecureFault + PRI_6_3 : SHPR1_PRI_6_3_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 7, SecureFault + PRI_7_3 : SHPR1_PRI_7_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR1_Register use record + Reserved_0_4 at 0 range 0 .. 4; + PRI_4_3 at 0 range 5 .. 7; + Reserved_8_12 at 0 range 8 .. 12; + PRI_5_3 at 0 range 13 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + PRI_6_3 at 0 range 21 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_7_3 at 0 range 29 .. 31; + end record; + + subtype SHPR2_PRI_8_Field is HAL.UInt8; + subtype SHPR2_PRI_9_Field is HAL.UInt8; + subtype SHPR2_PRI_10_Field is HAL.UInt8; + subtype SHPR2_PRI_11_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 8 - 11 + type SHPR2_Register is record + -- Read-only. Reserved, RES0 + PRI_8 : SHPR2_PRI_8_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_9 : SHPR2_PRI_9_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_10 : SHPR2_PRI_10_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 11, SecureFault + PRI_11_3 : SHPR2_PRI_11_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR2_Register use record + PRI_8 at 0 range 0 .. 7; + PRI_9 at 0 range 8 .. 15; + PRI_10 at 0 range 16 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_11_3 at 0 range 29 .. 31; + end record; + + subtype SHPR3_PRI_12_3_Field is HAL.UInt3; + subtype SHPR3_PRI_13_Field is HAL.UInt8; + subtype SHPR3_PRI_14_3_Field is HAL.UInt3; + subtype SHPR3_PRI_15_3_Field is HAL.UInt3; + + -- Sets or returns priority for system handlers 12 - 15 + type SHPR3_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Priority of system handler 12, SecureFault + PRI_12_3 : SHPR3_PRI_12_3_Field := 16#0#; + -- Read-only. Reserved, RES0 + PRI_13 : SHPR3_PRI_13_Field := 16#0#; + -- unspecified + Reserved_16_20 : HAL.UInt5 := 16#0#; + -- Priority of system handler 14, SecureFault + PRI_14_3 : SHPR3_PRI_14_3_Field := 16#0#; + -- unspecified + Reserved_24_28 : HAL.UInt5 := 16#0#; + -- Priority of system handler 15, SecureFault + PRI_15_3 : SHPR3_PRI_15_3_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHPR3_Register use record + Reserved_0_4 at 0 range 0 .. 4; + PRI_12_3 at 0 range 5 .. 7; + PRI_13 at 0 range 8 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + PRI_14_3 at 0 range 21 .. 23; + Reserved_24_28 at 0 range 24 .. 28; + PRI_15_3 at 0 range 29 .. 31; + end record; + + -- Provides access to the active and pending status of system exceptions + type SHCSR_Register is record + -- `IAAMO the active state of the MemManage exception `FTSSS + MEMFAULTACT : Boolean := False; + -- `IAAMO the active state of the BusFault exception + BUSFAULTACT : Boolean := False; + -- Indicates and allows limited modification of the active state of the + -- HardFault exception `FTSSS + HARDFAULTACT : Boolean := False; + -- `IAAMO the active state of the UsageFault exception `FTSSS + USGFAULTACT : Boolean := False; + -- `IAAMO the active state of the SecureFault exception + SECUREFAULTACT : Boolean := False; + -- `IAAMO the active state of the NMI exception + NMIACT : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- `IAAMO the active state of the SVCall exception `FTSSS + SVCALLACT : Boolean := False; + -- `IAAMO the active state of the DebugMonitor exception + MONITORACT : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- `IAAMO the active state of the PendSV exception `FTSSS + PENDSVACT : Boolean := False; + -- `IAAMO the active state of the SysTick exception `FTSSS + SYSTICKACT : Boolean := False; + -- The UsageFault exception is banked between Security states, `IAAMO + -- the pending state of the UsageFault exception `FTSSS + USGFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the MemManage exception `FTSSS + MEMFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the BusFault exception + BUSFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the SVCall exception `FTSSS + SVCALLPENDED : Boolean := False; + -- `DW the MemManage exception is enabled `FTSSS + MEMFAULTENA : Boolean := False; + -- `DW the BusFault exception is enabled + BUSFAULTENA : Boolean := False; + -- `DW the UsageFault exception is enabled `FTSSS + USGFAULTENA : Boolean := False; + -- `DW the SecureFault exception is enabled + SECUREFAULTENA : Boolean := False; + -- `IAAMO the pending state of the SecureFault exception + SECUREFAULTPENDED : Boolean := False; + -- `IAAMO the pending state of the HardFault exception `CTTSSS + HARDFAULTPENDED : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SHCSR_Register use record + MEMFAULTACT at 0 range 0 .. 0; + BUSFAULTACT at 0 range 1 .. 1; + HARDFAULTACT at 0 range 2 .. 2; + USGFAULTACT at 0 range 3 .. 3; + SECUREFAULTACT at 0 range 4 .. 4; + NMIACT at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + SVCALLACT at 0 range 7 .. 7; + MONITORACT at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PENDSVACT at 0 range 10 .. 10; + SYSTICKACT at 0 range 11 .. 11; + USGFAULTPENDED at 0 range 12 .. 12; + MEMFAULTPENDED at 0 range 13 .. 13; + BUSFAULTPENDED at 0 range 14 .. 14; + SVCALLPENDED at 0 range 15 .. 15; + MEMFAULTENA at 0 range 16 .. 16; + BUSFAULTENA at 0 range 17 .. 17; + USGFAULTENA at 0 range 18 .. 18; + SECUREFAULTENA at 0 range 19 .. 19; + SECUREFAULTPENDED at 0 range 20 .. 20; + HARDFAULTPENDED at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype CFSR_MMFSR_Field is HAL.UInt8; + + -- Contains the three Configurable Fault Status Registers. 31:16 UFSR: + -- Provides information on UsageFault exceptions 15:8 BFSR: Provides + -- information on BusFault exceptions 7:0 MMFSR: Provides information on + -- MemManage exceptions + type CFSR_Register is record + -- Provides information on MemManage exceptions + MMFSR : CFSR_MMFSR_Field := 16#0#; + -- Records whether a BusFault on an instruction prefetch has occurred + BFSR_IBUSERR : Boolean := False; + -- Records whether a precise data access error has occurred + BFSR_PRECISERR : Boolean := False; + -- Records whether an imprecise data access error has occurred + BFSR_IMPRECISERR : Boolean := False; + -- Records whether a derived BusFault occurred during exception return + -- unstacking + BFSR_UNSTKERR : Boolean := False; + -- Records whether a derived BusFault occurred during exception entry + -- stacking + BFSR_STKERR : Boolean := False; + -- Records whether a BusFault occurred during FP lazy state preservation + BFSR_LSPERR : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Indicates validity of the contents of the BFAR register + BFSR_BFARVALID : Boolean := False; + -- Sticky flag indicating whether an undefined instruction error has + -- occurred + UFSR_UNDEFINSTR : Boolean := False; + -- Sticky flag indicating whether an EPSR.T or EPSR.IT validity error + -- has occurred + UFSR_INVSTATE : Boolean := False; + -- Sticky flag indicating whether an integrity check error has occurred + UFSR_INVPC : Boolean := False; + -- Sticky flag indicating whether a coprocessor disabled or not present + -- error has occurred + UFSR_NOCP : Boolean := False; + -- Sticky flag indicating whether a stack overflow error has occurred + UFSR_STKOF : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Sticky flag indicating whether an unaligned access error has occurred + UFSR_UNALIGNED : Boolean := False; + -- Sticky flag indicating whether an integer division by zero error has + -- occurred + UFSR_DIVBYZERO : Boolean := False; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CFSR_Register use record + MMFSR at 0 range 0 .. 7; + BFSR_IBUSERR at 0 range 8 .. 8; + BFSR_PRECISERR at 0 range 9 .. 9; + BFSR_IMPRECISERR at 0 range 10 .. 10; + BFSR_UNSTKERR at 0 range 11 .. 11; + BFSR_STKERR at 0 range 12 .. 12; + BFSR_LSPERR at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + BFSR_BFARVALID at 0 range 15 .. 15; + UFSR_UNDEFINSTR at 0 range 16 .. 16; + UFSR_INVSTATE at 0 range 17 .. 17; + UFSR_INVPC at 0 range 18 .. 18; + UFSR_NOCP at 0 range 19 .. 19; + UFSR_STKOF at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + UFSR_UNALIGNED at 0 range 24 .. 24; + UFSR_DIVBYZERO at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Shows the cause of any HardFaults + type HFSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Indicates when a fault has occurred because of a vector table read + -- error on exception processing + VECTTBL : Boolean := False; + -- unspecified + Reserved_2_29 : HAL.UInt28 := 16#0#; + -- Indicates that a fault with configurable priority has been escalated + -- to a HardFault exception, because it could not be made active, + -- because of priority, or because it was disabled + FORCED : Boolean := False; + -- Indicates when a Debug event has occurred + DEBUGEVT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for HFSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTTBL at 0 range 1 .. 1; + Reserved_2_29 at 0 range 2 .. 29; + FORCED at 0 range 30 .. 30; + DEBUGEVT at 0 range 31 .. 31; + end record; + + -- Shows which debug event occurred + type DFSR_Register is record + -- Sticky flag indicating that a Halt request debug event or Step debug + -- event has occurred + HALTED : Boolean := False; + -- Sticky flag indicating whether a Breakpoint debug event has occurred + BKPT : Boolean := False; + -- Sticky flag indicating whether a Watchpoint debug event has occurred + DWTTRAP : Boolean := False; + -- Sticky flag indicating whether a Vector catch debug event has + -- occurred + VCATCH : Boolean := False; + -- Sticky flag indicating whether an External debug request debug event + -- has occurred + EXTERNAL : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DFSR_Register use record + HALTED at 0 range 0 .. 0; + BKPT at 0 range 1 .. 1; + DWTTRAP at 0 range 2 .. 2; + VCATCH at 0 range 3 .. 3; + EXTERNAL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- ID_PFR0_STATE array element + subtype ID_PFR0_STATE_Element is HAL.UInt4; + + -- ID_PFR0_STATE array + type ID_PFR0_STATE_Field_Array is array (0 .. 1) of ID_PFR0_STATE_Element + with Component_Size => 4, Size => 8; + + -- Type definition for ID_PFR0_STATE + type ID_PFR0_STATE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- STATE as a value + Val : HAL.UInt8; + when True => + -- STATE as an array + Arr : ID_PFR0_STATE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for ID_PFR0_STATE_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- Gives top-level information about the instruction set supported by the + -- PE + type ID_PFR0_Register is record + -- Read-only. A32 instruction set support + STATE : ID_PFR0_STATE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_PFR0_Register use record + STATE at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ID_PFR1_SECURITY_Field is HAL.UInt4; + subtype ID_PFR1_MPROGMOD_Field is HAL.UInt4; + + -- Gives information about the programmers' model and Extensions support + type ID_PFR1_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Identifies whether the Security Extension is implemented + SECURITY : ID_PFR1_SECURITY_Field; + -- Read-only. Identifies support for the M-Profile programmers' model + -- support + MPROGMOD : ID_PFR1_MPROGMOD_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_PFR1_Register use record + Reserved_0_3 at 0 range 0 .. 3; + SECURITY at 0 range 4 .. 7; + MPROGMOD at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype ID_DFR0_MPROFDBG_Field is HAL.UInt4; + + -- Provides top level information about the debug system + type ID_DFR0_Register is record + -- unspecified + Reserved_0_19 : HAL.UInt20; + -- Read-only. Indicates the supported M-profile debug architecture + MPROFDBG : ID_DFR0_MPROFDBG_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_DFR0_Register use record + Reserved_0_19 at 0 range 0 .. 19; + MPROFDBG at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- ID_AFR0_IMPDEF array element + subtype ID_AFR0_IMPDEF_Element is HAL.UInt4; + + -- ID_AFR0_IMPDEF array + type ID_AFR0_IMPDEF_Field_Array is array (0 .. 3) + of ID_AFR0_IMPDEF_Element + with Component_Size => 4, Size => 16; + + -- Type definition for ID_AFR0_IMPDEF + type ID_AFR0_IMPDEF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IMPDEF as a value + Val : HAL.UInt16; + when True => + -- IMPDEF as an array + Arr : ID_AFR0_IMPDEF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for ID_AFR0_IMPDEF_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Provides information about the IMPLEMENTATION DEFINED features of the PE + type ID_AFR0_Register is record + -- Read-only. IMPLEMENTATION DEFINED meaning + IMPDEF : ID_AFR0_IMPDEF_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_AFR0_Register use record + IMPDEF at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ID_MMFR0_PMSA_Field is HAL.UInt4; + subtype ID_MMFR0_OUTERSHR_Field is HAL.UInt4; + subtype ID_MMFR0_SHARELVL_Field is HAL.UInt4; + subtype ID_MMFR0_TCM_Field is HAL.UInt4; + subtype ID_MMFR0_AUXREG_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR0_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates support for the protected memory system + -- architecture (PMSA) + PMSA : ID_MMFR0_PMSA_Field; + -- Read-only. Indicates the outermost shareability domain implemented + OUTERSHR : ID_MMFR0_OUTERSHR_Field; + -- Read-only. Indicates the number of shareability levels implemented + SHARELVL : ID_MMFR0_SHARELVL_Field; + -- Read-only. Indicates support for tightly coupled memories (TCMs) + TCM : ID_MMFR0_TCM_Field; + -- Read-only. Indicates support for Auxiliary Control Registers + AUXREG : ID_MMFR0_AUXREG_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR0_Register use record + Reserved_0_3 at 0 range 0 .. 3; + PMSA at 0 range 4 .. 7; + OUTERSHR at 0 range 8 .. 11; + SHARELVL at 0 range 12 .. 15; + TCM at 0 range 16 .. 19; + AUXREG at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype ID_MMFR2_WFISTALL_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR2_Register is record + -- unspecified + Reserved_0_23 : HAL.UInt24; + -- Read-only. Indicates the support for Wait For Interrupt (WFI) + -- stalling + WFISTALL : ID_MMFR2_WFISTALL_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR2_Register use record + Reserved_0_23 at 0 range 0 .. 23; + WFISTALL at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_MMFR3_CMAINTVA_Field is HAL.UInt4; + subtype ID_MMFR3_CMAINTSW_Field is HAL.UInt4; + subtype ID_MMFR3_BPMAINT_Field is HAL.UInt4; + + -- Provides information about the implemented memory model and memory + -- management support + type ID_MMFR3_Register is record + -- Read-only. Indicates the supported cache maintenance operations by + -- address + CMAINTVA : ID_MMFR3_CMAINTVA_Field; + -- Read-only. Indicates the supported cache maintenance operations by + -- set/way + CMAINTSW : ID_MMFR3_CMAINTSW_Field; + -- Read-only. Indicates the supported branch predictor maintenance + BPMAINT : ID_MMFR3_BPMAINT_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_MMFR3_Register use record + CMAINTVA at 0 range 0 .. 3; + CMAINTSW at 0 range 4 .. 7; + BPMAINT at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype ID_ISAR0_BITCOUNT_Field is HAL.UInt4; + subtype ID_ISAR0_BITFIELD_Field is HAL.UInt4; + subtype ID_ISAR0_CMPBRANCH_Field is HAL.UInt4; + subtype ID_ISAR0_COPROC_Field is HAL.UInt4; + subtype ID_ISAR0_DEBUG_Field is HAL.UInt4; + subtype ID_ISAR0_DIVIDE_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR0_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates the supported bit count instructions + BITCOUNT : ID_ISAR0_BITCOUNT_Field; + -- Read-only. Indicates the supported bit field instructions + BITFIELD : ID_ISAR0_BITFIELD_Field; + -- Read-only. Indicates the supported combined Compare and Branch + -- instructions + CMPBRANCH : ID_ISAR0_CMPBRANCH_Field; + -- Read-only. Indicates the supported Coprocessor instructions + COPROC : ID_ISAR0_COPROC_Field; + -- Read-only. Indicates the implemented Debug instructions + DEBUG : ID_ISAR0_DEBUG_Field; + -- Read-only. Indicates the supported Divide instructions + DIVIDE : ID_ISAR0_DIVIDE_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR0_Register use record + Reserved_0_3 at 0 range 0 .. 3; + BITCOUNT at 0 range 4 .. 7; + BITFIELD at 0 range 8 .. 11; + CMPBRANCH at 0 range 12 .. 15; + COPROC at 0 range 16 .. 19; + DEBUG at 0 range 20 .. 23; + DIVIDE at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR1_EXTEND_Field is HAL.UInt4; + subtype ID_ISAR1_IFTHEN_Field is HAL.UInt4; + subtype ID_ISAR1_IMMEDIATE_Field is HAL.UInt4; + subtype ID_ISAR1_INTERWORK_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR1_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12; + -- Read-only. Indicates the implemented Extend instructions + EXTEND : ID_ISAR1_EXTEND_Field; + -- Read-only. Indicates the implemented If-Then instructions + IFTHEN : ID_ISAR1_IFTHEN_Field; + -- Read-only. Indicates the implemented for data-processing instructions + -- with long immediates + IMMEDIATE : ID_ISAR1_IMMEDIATE_Field; + -- Read-only. Indicates the implemented Interworking instructions + INTERWORK : ID_ISAR1_INTERWORK_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR1_Register use record + Reserved_0_11 at 0 range 0 .. 11; + EXTEND at 0 range 12 .. 15; + IFTHEN at 0 range 16 .. 19; + IMMEDIATE at 0 range 20 .. 23; + INTERWORK at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR2_LOADSTORE_Field is HAL.UInt4; + subtype ID_ISAR2_MEMHINT_Field is HAL.UInt4; + subtype ID_ISAR2_MULTIACCESSINT_Field is HAL.UInt4; + subtype ID_ISAR2_MULT_Field is HAL.UInt4; + subtype ID_ISAR2_MULTS_Field is HAL.UInt4; + subtype ID_ISAR2_MULTU_Field is HAL.UInt4; + subtype ID_ISAR2_REVERSAL_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR2_Register is record + -- Read-only. Indicates the implemented additional load/store + -- instructions + LOADSTORE : ID_ISAR2_LOADSTORE_Field; + -- Read-only. Indicates the implemented Memory Hint instructions + MEMHINT : ID_ISAR2_MEMHINT_Field; + -- Read-only. Indicates the support for interruptible multi-access + -- instructions + MULTIACCESSINT : ID_ISAR2_MULTIACCESSINT_Field; + -- Read-only. Indicates the implemented additional Multiply instructions + MULT : ID_ISAR2_MULT_Field; + -- Read-only. Indicates the implemented advanced signed Multiply + -- instructions + MULTS : ID_ISAR2_MULTS_Field; + -- Read-only. Indicates the implemented advanced unsigned Multiply + -- instructions + MULTU : ID_ISAR2_MULTU_Field; + -- unspecified + Reserved_24_27 : HAL.UInt4; + -- Read-only. Indicates the implemented Reversal instructions + REVERSAL : ID_ISAR2_REVERSAL_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR2_Register use record + LOADSTORE at 0 range 0 .. 3; + MEMHINT at 0 range 4 .. 7; + MULTIACCESSINT at 0 range 8 .. 11; + MULT at 0 range 12 .. 15; + MULTS at 0 range 16 .. 19; + MULTU at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + REVERSAL at 0 range 28 .. 31; + end record; + + subtype ID_ISAR3_SATURATE_Field is HAL.UInt4; + subtype ID_ISAR3_SIMD_Field is HAL.UInt4; + subtype ID_ISAR3_SVC_Field is HAL.UInt4; + subtype ID_ISAR3_SYNCHPRIM_Field is HAL.UInt4; + subtype ID_ISAR3_TABBRANCH_Field is HAL.UInt4; + subtype ID_ISAR3_T32COPY_Field is HAL.UInt4; + subtype ID_ISAR3_TRUENOP_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR3_Register is record + -- Read-only. Indicates the implemented saturating instructions + SATURATE : ID_ISAR3_SATURATE_Field; + -- Read-only. Indicates the implemented SIMD instructions + SIMD : ID_ISAR3_SIMD_Field; + -- Read-only. Indicates the implemented SVC instructions + SVC : ID_ISAR3_SVC_Field; + -- Read-only. Used in conjunction with ID_ISAR4.SynchPrim_frac to + -- indicate the implemented Synchronization Primitive instructions + SYNCHPRIM : ID_ISAR3_SYNCHPRIM_Field; + -- Read-only. Indicates the implemented Table Branch instructions + TABBRANCH : ID_ISAR3_TABBRANCH_Field; + -- Read-only. Indicates the support for T32 non flag-setting MOV + -- instructions + T32COPY : ID_ISAR3_T32COPY_Field; + -- Read-only. Indicates the implemented true NOP instructions + TRUENOP : ID_ISAR3_TRUENOP_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR3_Register use record + SATURATE at 0 range 0 .. 3; + SIMD at 0 range 4 .. 7; + SVC at 0 range 8 .. 11; + SYNCHPRIM at 0 range 12 .. 15; + TABBRANCH at 0 range 16 .. 19; + T32COPY at 0 range 20 .. 23; + TRUENOP at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype ID_ISAR4_UNPRIV_Field is HAL.UInt4; + subtype ID_ISAR4_WITHSHIFTS_Field is HAL.UInt4; + subtype ID_ISAR4_WRITEBACK_Field is HAL.UInt4; + subtype ID_ISAR4_BARRIER_Field is HAL.UInt4; + subtype ID_ISAR4_SYNCPRIM_FRAC_Field is HAL.UInt4; + subtype ID_ISAR4_PSR_M_Field is HAL.UInt4; + + -- Provides information about the instruction set implemented by the PE + type ID_ISAR4_Register is record + -- Read-only. Indicates the implemented unprivileged instructions + UNPRIV : ID_ISAR4_UNPRIV_Field; + -- Read-only. Indicates the support for writeback addressing modes + WITHSHIFTS : ID_ISAR4_WITHSHIFTS_Field; + -- Read-only. Indicates the support for writeback addressing modes + WRITEBACK : ID_ISAR4_WRITEBACK_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Indicates the implemented Barrier instructions + BARRIER : ID_ISAR4_BARRIER_Field; + -- Read-only. Used in conjunction with ID_ISAR3.SynchPrim to indicate + -- the implemented Synchronization Primitive instructions + SYNCPRIM_FRAC : ID_ISAR4_SYNCPRIM_FRAC_Field; + -- Read-only. Indicates the implemented M profile instructions to modify + -- the PSRs + PSR_M : ID_ISAR4_PSR_M_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ID_ISAR4_Register use record + UNPRIV at 0 range 0 .. 3; + WITHSHIFTS at 0 range 4 .. 7; + WRITEBACK at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + BARRIER at 0 range 16 .. 19; + SYNCPRIM_FRAC at 0 range 20 .. 23; + PSR_M at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype CTR_IMINLINE_Field is HAL.UInt4; + subtype CTR_RES1_1_Field is HAL.UInt2; + subtype CTR_DMINLINE_Field is HAL.UInt4; + subtype CTR_ERG_Field is HAL.UInt4; + subtype CTR_CWG_Field is HAL.UInt4; + + -- Provides information about the architecture of the caches. CTR is RES0 + -- if CLIDR is zero. + type CTR_Register is record + -- Read-only. Log2 of the number of words in the smallest cache line of + -- all the instruction caches that are controlled by the PE + IMINLINE : CTR_IMINLINE_Field; + -- unspecified + Reserved_4_13 : HAL.UInt10; + -- Read-only. Reserved, RES1 + RES1_1 : CTR_RES1_1_Field; + -- Read-only. Log2 of the number of words in the smallest cache line of + -- all the data caches and unified caches that are controlled by the PE + DMINLINE : CTR_DMINLINE_Field; + -- Read-only. Log2 of the number of words of the maximum size of the + -- reservation granule that has been implemented for the Load-Exclusive + -- and Store-Exclusive instructions + ERG : CTR_ERG_Field; + -- Read-only. Log2 of the number of words of the maximum size of memory + -- that can be overwritten as a result of the eviction of a cache entry + -- that has had a memory location in it modified + CWG : CTR_CWG_Field; + -- unspecified + Reserved_28_30 : HAL.UInt3; + -- Read-only. Reserved, RES1 + RES1 : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTR_Register use record + IMINLINE at 0 range 0 .. 3; + Reserved_4_13 at 0 range 4 .. 13; + RES1_1 at 0 range 14 .. 15; + DMINLINE at 0 range 16 .. 19; + ERG at 0 range 20 .. 23; + CWG at 0 range 24 .. 27; + Reserved_28_30 at 0 range 28 .. 30; + RES1 at 0 range 31 .. 31; + end record; + + -- CPACR_CP array element + subtype CPACR_CP_Element is HAL.UInt2; + + -- CPACR_CP array + type CPACR_CP_Field_Array is array (0 .. 7) of CPACR_CP_Element + with Component_Size => 2, Size => 16; + + -- Type definition for CPACR_CP + type CPACR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt16; + when True => + -- CP as an array + Arr : CPACR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for CPACR_CP_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- CPACR_CP array + type CPACR_CP_Field_Array_1 is array (10 .. 11) of CPACR_CP_Element + with Component_Size => 2, Size => 4; + + -- Type definition for CPACR_CP + type CPACR_CP_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt4; + when True => + -- CP as an array + Arr : CPACR_CP_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 4; + + for CPACR_CP_Field_1 use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Specifies the access privileges for coprocessors and the FP Extension + type CPACR_Register is record + -- Controls access privileges for coprocessor 0 + CP : CPACR_CP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_19 : HAL.UInt4 := 16#0#; + -- Defines the access rights for the floating-point functionality + CP_1 : CPACR_CP_Field_1 := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CPACR_Register use record + CP at 0 range 0 .. 15; + Reserved_16_19 at 0 range 16 .. 19; + CP_1 at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- NSACR_CP array + type NSACR_CP_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for NSACR_CP + type NSACR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt8; + when True => + -- CP as an array + Arr : NSACR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for NSACR_CP_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- NSACR_CP array + type NSACR_CP_Field_Array_1 is array (10 .. 11) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for NSACR_CP + type NSACR_CP_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : NSACR_CP_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 2; + + for NSACR_CP_Field_1 use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Defines the Non-secure access permissions for both the FP Extension and + -- coprocessors CP0 to CP7 + type NSACR_Register is record + -- Enables Non-secure access to coprocessor CP0 + CP : NSACR_CP_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Enables Non-secure access to the Floating-point Extension + CP_1 : NSACR_CP_Field_1 := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NSACR_Register use record + CP at 0 range 0 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + CP_1 at 0 range 10 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype MPU_TYPE_DREGION_Field is HAL.UInt8; + + -- The MPU Type Register indicates how many regions the MPU `FTSSS supports + type MPU_TYPE_Register is record + -- Read-only. Indicates support for separate instructions and data + -- address regions + SEPARATE_k : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Number of regions supported by the MPU + DREGION : MPU_TYPE_DREGION_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_TYPE_Register use record + SEPARATE_k at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + DREGION at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Enables the MPU and, when the MPU is enabled, controls whether the + -- default memory map is enabled as a background region for privileged + -- accesses, and whether the MPU is enabled for HardFaults, NMIs, and + -- exception handlers when FAULTMASK is set to 1 + type MPU_CTRL_Register is record + -- Enables the MPU + ENABLE : Boolean := False; + -- Controls whether handlers executing with priority less than 0 access + -- memory with the MPU enabled or disabled. This applies to HardFaults, + -- NMIs, and exception handlers when FAULTMASK is set to 1 + HFNMIENA : Boolean := False; + -- Controls whether the default memory map is enabled for privileged + -- software + PRIVDEFENA : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + HFNMIENA at 0 range 1 .. 1; + PRIVDEFENA at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_RNR_REGION_Field is HAL.UInt3; + + -- Selects the region currently accessed by MPU_RBAR and MPU_RLAR + type MPU_RNR_Register is record + -- Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + REGION : MPU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RNR_Register use record + REGION at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_RBAR_AP_Field is HAL.UInt2; + subtype MPU_RBAR_SH_Field is HAL.UInt2; + subtype MPU_RBAR_BASE_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the + -- currently selected MPU region `FTSSS + type MPU_RBAR_Register is record + -- Defines whether code can be executed from this region + XN : Boolean := False; + -- Defines the access permissions for this region + AP : MPU_RBAR_AP_Field := 16#0#; + -- Defines the Shareability domain of this region for Normal memory + SH : MPU_RBAR_SH_Field := 16#0#; + -- Contains bits [31:5] of the lower inclusive limit of the selected MPU + -- memory region. This value is zero extended to provide the base + -- address to be checked against + BASE : MPU_RBAR_BASE_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RBAR_Register use record + XN at 0 range 0 .. 0; + AP at 0 range 1 .. 2; + SH at 0 range 3 .. 4; + BASE at 0 range 5 .. 31; + end record; + + subtype MPU_RLAR_ATTRINDX_Field is HAL.UInt3; + subtype MPU_RLAR_LIMIT_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region `FTSSS + type MPU_RLAR_Register is record + -- Region enable + EN : Boolean := False; + -- Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + ATTRINDX : MPU_RLAR_ATTRINDX_Field := 16#0#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Contains bits [31:5] of the upper inclusive limit of the selected MPU + -- memory region. This value is postfixed with 0x1F to provide the limit + -- address to be checked against + LIMIT : MPU_RLAR_LIMIT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RLAR_Register use record + EN at 0 range 0 .. 0; + ATTRINDX at 0 range 1 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LIMIT at 0 range 5 .. 31; + end record; + + subtype MPU_RBAR_A_AP_Field is HAL.UInt2; + subtype MPU_RBAR_A_SH_Field is HAL.UInt2; + subtype MPU_RBAR_A_BASE_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the MPU + -- region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + type MPU_RBAR_A_Register is record + -- Defines whether code can be executed from this region + XN : Boolean := False; + -- Defines the access permissions for this region + AP : MPU_RBAR_A_AP_Field := 16#0#; + -- Defines the Shareability domain of this region for Normal memory + SH : MPU_RBAR_A_SH_Field := 16#0#; + -- Contains bits [31:5] of the lower inclusive limit of the selected MPU + -- memory region. This value is zero extended to provide the base + -- address to be checked against + BASE : MPU_RBAR_A_BASE_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RBAR_A_Register use record + XN at 0 range 0 .. 0; + AP at 0 range 1 .. 2; + SH at 0 range 3 .. 4; + BASE at 0 range 5 .. 31; + end record; + + subtype MPU_RLAR_A_ATTRINDX_Field is HAL.UInt3; + subtype MPU_RLAR_A_LIMIT_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + type MPU_RLAR_A_Register is record + -- Region enable + EN : Boolean := False; + -- Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + ATTRINDX : MPU_RLAR_A_ATTRINDX_Field := 16#0#; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Contains bits [31:5] of the upper inclusive limit of the selected MPU + -- memory region. This value is postfixed with 0x1F to provide the limit + -- address to be checked against + LIMIT : MPU_RLAR_A_LIMIT_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_RLAR_A_Register use record + EN at 0 range 0 .. 0; + ATTRINDX at 0 range 1 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LIMIT at 0 range 5 .. 31; + end record; + + -- MPU_MAIR0_ATTR array element + subtype MPU_MAIR0_ATTR_Element is HAL.UInt8; + + -- MPU_MAIR0_ATTR array + type MPU_MAIR0_ATTR_Field_Array is array (0 .. 3) + of MPU_MAIR0_ATTR_Element + with Component_Size => 8, Size => 32; + + -- Along with MPU_MAIR1, provides the memory attribute encodings + -- corresponding to the AttrIndex values + type MPU_MAIR0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ATTR as a value + Val : HAL.UInt32; + when True => + -- ATTR as an array + Arr : MPU_MAIR0_ATTR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MAIR0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MPU_MAIR1_ATTR array element + subtype MPU_MAIR1_ATTR_Element is HAL.UInt8; + + -- MPU_MAIR1_ATTR array + type MPU_MAIR1_ATTR_Field_Array is array (4 .. 7) + of MPU_MAIR1_ATTR_Element + with Component_Size => 8, Size => 32; + + -- Along with MPU_MAIR0, provides the memory attribute encodings + -- corresponding to the AttrIndex values + type MPU_MAIR1_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ATTR as a value + Val : HAL.UInt32; + when True => + -- ATTR as an array + Arr : MPU_MAIR1_ATTR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MAIR1_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Allows enabling of the Security Attribution Unit + type SAU_CTRL_Register is record + -- Enables the SAU + ENABLE : Boolean := False; + -- When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked + -- as Non-secure or Secure + ALLNS : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + ALLNS at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype SAU_TYPE_SREGION_Field is HAL.UInt8; + + -- Indicates the number of regions implemented by the Security Attribution + -- Unit + type SAU_TYPE_Register is record + -- Read-only. The number of implemented SAU regions + SREGION : SAU_TYPE_SREGION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_TYPE_Register use record + SREGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype SAU_RNR_REGION_Field is HAL.UInt8; + + -- Selects the region currently accessed by SAU_RBAR and SAU_RLAR + type SAU_RNR_Register is record + -- Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + REGION : SAU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RNR_Register use record + REGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype SAU_RBAR_BADDR_Field is HAL.UInt27; + + -- Provides indirect read and write access to the base address of the + -- currently selected SAU region + type SAU_RBAR_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Holds bits [31:5] of the base address for the selected SAU region + BADDR : SAU_RBAR_BADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RBAR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + BADDR at 0 range 5 .. 31; + end record; + + subtype SAU_RLAR_LADDR_Field is HAL.UInt27; + + -- Provides indirect read and write access to the limit address of the + -- currently selected SAU region + type SAU_RLAR_Register is record + -- SAU region enable + ENABLE : Boolean := False; + -- Controls whether Non-secure state is permitted to execute an SG + -- instruction from this region + NSC : Boolean := False; + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- Holds bits [31:5] of the limit address for the selected SAU region + LADDR : SAU_RLAR_LADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SAU_RLAR_Register use record + ENABLE at 0 range 0 .. 0; + NSC at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + LADDR at 0 range 5 .. 31; + end record; + + -- Provides information about any security related faults + type SFSR_Register is record + -- This bit is set if a function call from the Non-secure state or + -- exception targets a non-SG instruction in the Secure state. This bit + -- is also set if the target address is a SG instruction, but there is + -- no matching SAU/IDAU region with the NSC flag set + INVEP : Boolean := False; + -- This bit is set if the integrity signature in an exception stack + -- frame is found to be invalid during the unstacking operation + INVIS : Boolean := False; + -- This can be caused by EXC_RETURN.DCRS being set to 0 when returning + -- from an exception in the Non-secure state, or by EXC_RETURN.ES being + -- set to 1 when returning from an exception in the Non-secure state + INVER : Boolean := False; + -- Sticky flag indicating that an attempt was made to access parts of + -- the address space that are marked as Secure with NS-Req for the + -- transaction set to Non-secure. This bit is not set if the violation + -- occurred during lazy state preservation. See LSPERR + AUVIOL : Boolean := False; + -- Sticky flag indicating that an exception was raised due to a branch + -- that was not flagged as being domain crossing causing a transition + -- from Secure to Non-secure memory + INVTRAN : Boolean := False; + -- Stick flag indicating that an SAU or IDAU violation occurred during + -- the lazy preservation of floating-point state + LSPERR : Boolean := False; + -- This bit is set when the SFAR register contains a valid value. As + -- with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this + -- bit can be cleared by other exceptions, such as BusFault + SFARVALID : Boolean := False; + -- Sticky flag indicating that an error occurred during lazy state + -- activation or deactivation + LSERR : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SFSR_Register use record + INVEP at 0 range 0 .. 0; + INVIS at 0 range 1 .. 1; + INVER at 0 range 2 .. 2; + AUVIOL at 0 range 3 .. 3; + INVTRAN at 0 range 4 .. 4; + LSPERR at 0 range 5 .. 5; + SFARVALID at 0 range 6 .. 6; + LSERR at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Controls halting debug + type DHCSR_Register is record + -- Enable Halting debug + C_DEBUGEN : Boolean := False; + -- PE enter Debug state halt request + C_HALT : Boolean := False; + -- Enable single instruction step + C_STEP : Boolean := False; + -- When debug is enabled, the debugger can write to this bit to mask + -- PendSV, SysTick and external configurable interrupts + C_MASKINTS : Boolean := False; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Allow imprecise entry to Debug state + C_SNAPSTALL : Boolean := False; + -- unspecified + Reserved_6_15 : HAL.UInt10 := 16#0#; + -- Read-only. Handshake flag to transfers through the DCRDR + S_REGRDY : Boolean := False; + -- Read-only. Indicates whether the PE is in Debug state + S_HALT : Boolean := False; + -- Read-only. Indicates whether the PE is sleeping + S_SLEEP : Boolean := False; + -- Read-only. Indicates whether the PE is in Lockup state + S_LOCKUP : Boolean := False; + -- Read-only. Indicates whether Secure invasive debug is allowed + S_SDE : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Read-only. Set to 1 every time the PE retires one of more + -- instructions + S_RETIRE_ST : Boolean := False; + -- Read-only. Indicates whether the PE has been reset since the last + -- read of the DHCSR + S_RESET_ST : Boolean := False; + -- Read-only. Indicates the PE has processed a request to clear + -- DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears + -- DHCSR.C_HALT from 1 to 0, or an External Restart Request + S_RESTART_ST : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DHCSR_Register use record + C_DEBUGEN at 0 range 0 .. 0; + C_HALT at 0 range 1 .. 1; + C_STEP at 0 range 2 .. 2; + C_MASKINTS at 0 range 3 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + C_SNAPSTALL at 0 range 5 .. 5; + Reserved_6_15 at 0 range 6 .. 15; + S_REGRDY at 0 range 16 .. 16; + S_HALT at 0 range 17 .. 17; + S_SLEEP at 0 range 18 .. 18; + S_LOCKUP at 0 range 19 .. 19; + S_SDE at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + S_RETIRE_ST at 0 range 24 .. 24; + S_RESET_ST at 0 range 25 .. 25; + S_RESTART_ST at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype DCRSR_REGSEL_Field is HAL.UInt7; + + -- With the DCRDR, provides debug access to the general-purpose registers, + -- special-purpose registers, and the FP extension registers. A write to + -- the DCRSR specifies the register to transfer, whether the transfer is a + -- read or write, and starts the transfer + type DCRSR_Register is record + -- Specifies the general-purpose register, special-purpose register, or + -- FP register to transfer + REGSEL : DCRSR_REGSEL_Field := 16#0#; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Specifies the access type for the transfer + REGWNR : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCRSR_Register use record + REGSEL at 0 range 0 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + REGWNR at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Manages vector catch behavior and DebugMonitor handling when debugging + type DEMCR_Register is record + -- Enable Reset Vector Catch. This causes a warm reset to halt a running + -- system + VC_CORERESET : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Enable halting debug trap on a MemManage exception + VC_MMERR : Boolean := False; + -- Enable halting debug trap on a UsageFault caused by an access to a + -- coprocessor + VC_NOCPERR : Boolean := False; + -- Enable halting debug trap on a UsageFault exception caused by a + -- checking error, for example an alignment check error + VC_CHKERR : Boolean := False; + -- Enable halting debug trap on a UsageFault exception caused by a state + -- information error, for example an Undefined Instruction exception + VC_STATERR : Boolean := False; + -- BusFault exception halting debug vector catch enable + VC_BUSERR : Boolean := False; + -- Enable halting debug vector catch for faults during exception entry + -- and return + VC_INTERR : Boolean := False; + -- HardFault exception halting debug vector catch enable + VC_HARDERR : Boolean := False; + -- SecureFault exception halting debug vector catch enable + VC_SFERR : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Enable the DebugMonitor exception + MON_EN : Boolean := False; + -- Sets or clears the pending state of the DebugMonitor exception + MON_PEND : Boolean := False; + -- Enable DebugMonitor stepping + MON_STEP : Boolean := False; + -- DebugMonitor semaphore bit + MON_REQ : Boolean := False; + -- Read-only. Indicates whether the DebugMonitor targets the Secure or + -- the Non-secure state and whether debug events are allowed in Secure + -- state + SDME : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Global enable for all DWT and ITM features + TRCENA : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEMCR_Register use record + VC_CORERESET at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + VC_MMERR at 0 range 4 .. 4; + VC_NOCPERR at 0 range 5 .. 5; + VC_CHKERR at 0 range 6 .. 6; + VC_STATERR at 0 range 7 .. 7; + VC_BUSERR at 0 range 8 .. 8; + VC_INTERR at 0 range 9 .. 9; + VC_HARDERR at 0 range 10 .. 10; + VC_SFERR at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MON_EN at 0 range 16 .. 16; + MON_PEND at 0 range 17 .. 17; + MON_STEP at 0 range 18 .. 18; + MON_REQ at 0 range 19 .. 19; + SDME at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + TRCENA at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Provides control and status information for Secure debug + type DSCSR_Register is record + -- Controls whether the SBRSEL field or the current Security state of + -- the processor selects which version of the memory-mapped Banked + -- registers are accessed to the debugger + SBRSELEN : Boolean := False; + -- If SBRSELEN is 1 this bit selects whether the Non-secure or the + -- Secure version of the memory-mapped Banked registers are accessible + -- to the debugger + SBRSEL : Boolean := False; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- This field indicates the current Security state of the processor + CDS : Boolean := False; + -- Writes to the CDS bit are ignored unless CDSKEY is concurrently + -- written to zero + CDSKEY : Boolean := False; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DSCSR_Register use record + SBRSELEN at 0 range 0 .. 0; + SBRSEL at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + CDS at 0 range 16 .. 16; + CDSKEY at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype STIR_INTID_Field is HAL.UInt9; + + -- Provides a mechanism for software to generate an interrupt + type STIR_Register is record + -- Indicates the interrupt to be pended. The value written is + -- (ExceptionNumber - 16) + INTID : STIR_INTID_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STIR_Register use record + INTID at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Holds control data for the Floating-point extension + type FPCCR_Register is record + -- Indicates whether lazy preservation of the floating-point state is + -- active + LSPACT : Boolean := False; + -- Indicates the privilege level of the software executing when the PE + -- allocated the floating-point stack frame + USER : Boolean := True; + -- Security status of the floating-point context. This bit is only + -- present in the Secure version of the register, and behaves as RAZ/WI + -- when accessed from the Non-secure state. This bit is updated whenever + -- lazy state preservation is activated, or when a floating-point + -- instruction is executed + S : Boolean := False; + -- Indicates the PE mode when it allocated the floating-point stack + -- frame + THREAD : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the HardFault exception to + -- pending + HFRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the MemManage exception to + -- pending + MMRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the BusFault exception to + -- pending + BFRDY : Boolean := True; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the SecureFault exception + -- to pending. This bit is only present in the Secure version of the + -- register, and behaves as RAZ/WI when accessed from the Non-secure + -- state + SFRDY : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the DebugMonitor exception + -- to pending + MONRDY : Boolean := False; + -- This bit is banked between the Security states and indicates whether + -- the floating-point context violates the stack pointer limit that was + -- active when lazy state preservation was activated. SPLIMVIOL modifies + -- the lazy floating-point state preservation behavior + SPLIMVIOL : Boolean := False; + -- Indicates whether the software executing when the PE allocated the + -- floating-point stack frame was able to set the UsageFault exception + -- to pending + UFRDY : Boolean := True; + -- unspecified + Reserved_11_25 : HAL.UInt15 := 16#0#; + -- Treat floating-point registers as Secure enable + TS : Boolean := False; + -- This bit controls whether the CLRONRET bit is writeable from the + -- Non-secure state + CLRONRETS : Boolean := False; + -- Clear floating-point caller saved registers on exception return + CLRONRET : Boolean := False; + -- This bit controls whether the LSPEN bit is writeable from the + -- Non-secure state + LSPENS : Boolean := True; + -- Enables lazy context save of floating-point state + LSPEN : Boolean := False; + -- When this bit is set to 1, execution of a floating-point instruction + -- sets the CONTROL.FPCA bit to 1 + ASPEN : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCCR_Register use record + LSPACT at 0 range 0 .. 0; + USER at 0 range 1 .. 1; + S at 0 range 2 .. 2; + THREAD at 0 range 3 .. 3; + HFRDY at 0 range 4 .. 4; + MMRDY at 0 range 5 .. 5; + BFRDY at 0 range 6 .. 6; + SFRDY at 0 range 7 .. 7; + MONRDY at 0 range 8 .. 8; + SPLIMVIOL at 0 range 9 .. 9; + UFRDY at 0 range 10 .. 10; + Reserved_11_25 at 0 range 11 .. 25; + TS at 0 range 26 .. 26; + CLRONRETS at 0 range 27 .. 27; + CLRONRET at 0 range 28 .. 28; + LSPENS at 0 range 29 .. 29; + LSPEN at 0 range 30 .. 30; + ASPEN at 0 range 31 .. 31; + end record; + + subtype FPCAR_ADDRESS_Field is HAL.UInt29; + + -- Holds the location of the unpopulated floating-point register space + -- allocated on an exception stack frame + type FPCAR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- The location of the unpopulated floating-point register space + -- allocated on an exception stack frame + ADDRESS : FPCAR_ADDRESS_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPCAR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + ADDRESS at 0 range 3 .. 31; + end record; + + subtype FPDSCR_RMODE_Field is HAL.UInt2; + + -- Holds the default values for the floating-point status control data that + -- the PE assigns to the FPSCR when it creates a new floating-point context + type FPDSCR_Register is record + -- unspecified + Reserved_0_21 : HAL.UInt22 := 16#0#; + -- Default value for FPSCR.RMode + RMODE : FPDSCR_RMODE_Field := 16#0#; + -- Default value for FPSCR.FZ + FZ : Boolean := False; + -- Default value for FPSCR.DN + DN : Boolean := False; + -- Default value for FPSCR.AHP + AHP : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FPDSCR_Register use record + Reserved_0_21 at 0 range 0 .. 21; + RMODE at 0 range 22 .. 23; + FZ at 0 range 24 .. 24; + DN at 0 range 25 .. 25; + AHP at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype MVFR0_SIMDREG_Field is HAL.UInt4; + subtype MVFR0_FPSP_Field is HAL.UInt4; + subtype MVFR0_FPDP_Field is HAL.UInt4; + subtype MVFR0_FPDIVIDE_Field is HAL.UInt4; + subtype MVFR0_FPSQRT_Field is HAL.UInt4; + subtype MVFR0_FPROUND_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR0_Register is record + -- Read-only. Indicates size of FP register file + SIMDREG : MVFR0_SIMDREG_Field; + -- Read-only. Indicates support for FP single-precision operations + FPSP : MVFR0_FPSP_Field; + -- Read-only. Indicates support for FP double-precision operations + FPDP : MVFR0_FPDP_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Indicates the support for FP divide operations + FPDIVIDE : MVFR0_FPDIVIDE_Field; + -- Read-only. Indicates the support for FP square root operations + FPSQRT : MVFR0_FPSQRT_Field; + -- unspecified + Reserved_24_27 : HAL.UInt4; + -- Read-only. Indicates the rounding modes supported by the FP Extension + FPROUND : MVFR0_FPROUND_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR0_Register use record + SIMDREG at 0 range 0 .. 3; + FPSP at 0 range 4 .. 7; + FPDP at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FPDIVIDE at 0 range 16 .. 19; + FPSQRT at 0 range 20 .. 23; + Reserved_24_27 at 0 range 24 .. 27; + FPROUND at 0 range 28 .. 31; + end record; + + subtype MVFR1_FPFTZ_Field is HAL.UInt4; + subtype MVFR1_FPDNAN_Field is HAL.UInt4; + subtype MVFR1_FPHP_Field is HAL.UInt4; + subtype MVFR1_FMAC_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR1_Register is record + -- Read-only. Indicates whether subnormals are always flushed-to-zero + FPFTZ : MVFR1_FPFTZ_Field; + -- Read-only. Indicates whether the FP hardware implementation supports + -- NaN propagation + FPDNAN : MVFR1_FPDNAN_Field; + -- unspecified + Reserved_8_23 : HAL.UInt16; + -- Read-only. Indicates whether the FP Extension implements + -- half-precision FP conversion instructions + FPHP : MVFR1_FPHP_Field; + -- Read-only. Indicates whether the FP Extension implements the fused + -- multiply accumulate instructions + FMAC : MVFR1_FMAC_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR1_Register use record + FPFTZ at 0 range 0 .. 3; + FPDNAN at 0 range 4 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + FPHP at 0 range 24 .. 27; + FMAC at 0 range 28 .. 31; + end record; + + subtype MVFR2_FPMISC_Field is HAL.UInt4; + + -- Describes the features provided by the Floating-point Extension + type MVFR2_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Indicates support for miscellaneous FP features + FPMISC : MVFR2_FPMISC_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MVFR2_Register use record + Reserved_0_3 at 0 range 0 .. 3; + FPMISC at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DDEVARCH_ARCHPART_Field is HAL.UInt12; + subtype DDEVARCH_ARCHVER_Field is HAL.UInt4; + subtype DDEVARCH_REVISION_Field is HAL.UInt4; + subtype DDEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Provides CoreSight discovery information for the SCS + type DDEVARCH_Register is record + -- Read-only. Defines the architecture of the component + ARCHPART : DDEVARCH_ARCHPART_Field; + -- Read-only. Defines the architecture version of the component + ARCHVER : DDEVARCH_ARCHVER_Field; + -- Read-only. Defines the architecture revision of the component + REVISION : DDEVARCH_REVISION_Field; + -- Read-only. Defines that the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Defines the architect of the component. Bits [31:28] are + -- the JEP106 continuation code (JEP106 bank ID, minus 1) and bits + -- [27:21] are the JEP106 ID code. + ARCHITECT : DDEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DDEVARCH_Register use record + ARCHPART at 0 range 0 .. 11; + ARCHVER at 0 range 12 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DDEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DDEVTYPE_SUB_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DDEVTYPE_Register is record + -- Read-only. CoreSight major type + MAJOR : DDEVTYPE_MAJOR_Field; + -- Read-only. Component sub-type + SUB : DDEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DDEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR4_DES_2_Field is HAL.UInt4; + subtype DPIDR4_SIZE_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR4_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_2 : DPIDR4_DES_2_Field; + -- Read-only. See CoreSight Architecture Specification + SIZE : DPIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR0_PART_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DPIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_0 : DPIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR1_PART_1_Field is HAL.UInt4; + subtype DPIDR1_DES_0_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PART_1 : DPIDR1_PART_1_Field; + -- Read-only. See CoreSight Architecture Specification + DES_0 : DPIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR2_DES_1_Field is HAL.UInt3; + subtype DPIDR2_REVISION_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + DES_1 : DPIDR2_DES_1_Field; + -- Read-only. See CoreSight Architecture Specification + JEDEC : Boolean; + -- Read-only. See CoreSight Architecture Specification + REVISION : DPIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DPIDR3_CMOD_Field is HAL.UInt4; + subtype DPIDR3_REVAND_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DPIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + CMOD : DPIDR3_CMOD_Field; + -- Read-only. See CoreSight Architecture Specification + REVAND : DPIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DPIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR0_PRMBL_0_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR0_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_0 : DCIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR1_PRMBL_1_Field is HAL.UInt4; + subtype DCIDR1_CLASS_Field is HAL.UInt4; + + -- Provides CoreSight discovery information for the SCS + type DCIDR1_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_1 : DCIDR1_PRMBL_1_Field; + -- Read-only. See CoreSight Architecture Specification + CLASS : DCIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR2_PRMBL_2_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR2_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_2 : DCIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DCIDR3_PRMBL_3_Field is HAL.UInt8; + + -- Provides CoreSight discovery information for the SCS + type DCIDR3_Register is record + -- Read-only. See CoreSight Architecture Specification + PRMBL_3 : DCIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DCIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Programming Control Register + type TRCPRGCTLR_Register is record + -- Trace Unit Enable + EN : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPRGCTLR_Register use record + EN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- The TRCSTATR indicates the ETM-Teal status + type TRCSTATR_Register is record + -- Read-only. Indicates that the trace unit is inactive + IDLE : Boolean; + -- Read-only. Indicates whether the ETM-Teal registers are stable and + -- can be read + PMSTABLE : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSTATR_Register use record + IDLE at 0 range 0 .. 0; + PMSTABLE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype TRCCONFIGR_COND_Field is HAL.UInt6; + + -- The TRCCONFIGR sets the basic tracing options for the trace unit + type TRCCONFIGR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Branch broadcast mode + BB : Boolean := False; + -- Cycle counting in instruction trace + CCI : Boolean := False; + -- Conditional instruction tracing + COND : TRCCONFIGR_COND_Field := 16#0#; + -- Global timestamp tracing + TS : Boolean := False; + -- Return stack enable + RS : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCONFIGR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + BB at 0 range 3 .. 3; + CCI at 0 range 4 .. 4; + COND at 0 range 5 .. 10; + TS at 0 range 11 .. 11; + RS at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype TRCEVENTCTL0R_SEL0_Field is HAL.UInt3; + subtype TRCEVENTCTL0R_SEL1_Field is HAL.UInt3; + + -- The TRCEVENTCTL0R controls the tracing of events in the trace stream. + -- The events also drive the ETM-Teal external outputs. + type TRCEVENTCTL0R_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCEVENTCTL0R_SEL0_Field := 16#0#; + -- unspecified + Reserved_3_6 : HAL.UInt4 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- Selects the resource number, based on the value of TYPE1: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL1[2:0] + SEL1 : TRCEVENTCTL0R_SEL1_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- Selects the resource type for event 1 + TYPE1 : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCEVENTCTL0R_Register use record + SEL0 at 0 range 0 .. 2; + Reserved_3_6 at 0 range 3 .. 6; + TYPE0 at 0 range 7 .. 7; + SEL1 at 0 range 8 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + TYPE1 at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- TRCEVENTCTL1R_INSTEN array + type TRCEVENTCTL1R_INSTEN_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TRCEVENTCTL1R_INSTEN + type TRCEVENTCTL1R_INSTEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- INSTEN as a value + Val : HAL.UInt2; + when True => + -- INSTEN as an array + Arr : TRCEVENTCTL1R_INSTEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TRCEVENTCTL1R_INSTEN_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + -- behave + type TRCEVENTCTL1R_Register is record + -- One bit per event, to enable generation of an event element in the + -- instruction trace stream when the selected event occurs + INSTEN : TRCEVENTCTL1R_INSTEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_10 : HAL.UInt9 := 16#0#; + -- ATB enabled + ATB : Boolean := False; + -- Low power state behavior override + LPOVERRIDE : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCEVENTCTL1R_Register use record + INSTEN at 0 range 0 .. 1; + Reserved_2_10 at 0 range 2 .. 10; + ATB at 0 range 11 .. 11; + LPOVERRIDE at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype TRCSTALLCTLR_LEVEL_Field is HAL.UInt2; + + -- The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal + -- FIFO goes over the programmed level to minimize risk of overflow + type TRCSTALLCTLR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Threshold at which stalling becomes active. This provides four + -- levels. This level can be varied to optimize the level of invasion + -- caused by stalling, balanced against the risk of a FIFO overflow + LEVEL : TRCSTALLCTLR_LEVEL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Stall processor based on instruction trace buffer space + ISTALL : Boolean := False; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- Read-only. Reserved, RES0 + INSTPRIORITY : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSTALLCTLR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + LEVEL at 0 range 2 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + ISTALL at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + INSTPRIORITY at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype TRCTSCTLR_SEL0_Field is HAL.UInt2; + + -- The TRCTSCTLR controls the insertion of global timestamps into the trace + -- stream. A timestamp is always inserted into the instruction trace stream + type TRCTSCTLR_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCTSCTLR_SEL0_Field := 16#0#; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCTSCTLR_Register use record + SEL0 at 0 range 0 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + TYPE0 at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCSYNCPR_PERIOD_Field is HAL.UInt5; + + -- The TRCSYNCPR specifies the period of trace synchronization of the trace + -- streams. TRCSYNCPR defines a number of bytes of trace between requests + -- for trace synchronization. This value is always a power of two + type TRCSYNCPR_Register is record + -- Read-only. Defines the number of bytes of trace between trace + -- synchronization requests as a total of the number of bytes generated + -- by the instruction stream. The number of bytes is 2N where N is the + -- value of this field: - A value of zero disables these periodic trace + -- synchronization requests, but does not disable other trace + -- synchronization requests. - The minimum value that can be programmed, + -- other than zero, is 8, providing a minimum trace synchronization + -- period of 256 bytes. - The maximum value is 20, providing a maximum + -- trace synchronization period of 2^20 bytes + PERIOD : TRCSYNCPR_PERIOD_Field; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSYNCPR_Register use record + PERIOD at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype TRCCCCTLR_THRESHOLD_Field is HAL.UInt12; + + -- The TRCCCCTLR sets the threshold value for instruction trace cycle + -- counting. The threshold represents the minimum interval between cycle + -- count trace packets + type TRCCCCTLR_Register is record + -- Instruction trace cycle count threshold + THRESHOLD : TRCCCCTLR_THRESHOLD_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCCCTLR_Register use record + THRESHOLD at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype TRCVICTLR_SEL0_Field is HAL.UInt2; + + -- The TRCVICTLR controls instruction trace filtering + type TRCVICTLR_Register is record + -- Selects the resource number, based on the value of TYPE0: When TYPE1 + -- is 0, selects a single selected resource from 0-15 defined by + -- SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair + -- from 0-7 defined by SEL0[2:0] + SEL0 : TRCVICTLR_SEL0_Field := 16#0#; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Selects the resource type for event 0 + TYPE0 : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Indicates the current status of the start/stop logic + SSSTATUS : Boolean := False; + -- Selects whether a reset exception must always be traced + TRCRESET : Boolean := False; + -- Selects whether a system error exception must always be traced + TRCERR : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- In Secure state, each bit controls whether instruction tracing is + -- enabled for the corresponding exception level + EXLEVEL_S0 : Boolean := False; + -- unspecified + Reserved_17_18 : HAL.UInt2 := 16#0#; + -- In Secure state, each bit controls whether instruction tracing is + -- enabled for the corresponding exception level + EXLEVEL_S3 : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCVICTLR_Register use record + SEL0 at 0 range 0 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + TYPE0 at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + SSSTATUS at 0 range 9 .. 9; + TRCRESET at 0 range 10 .. 10; + TRCERR at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + EXLEVEL_S0 at 0 range 16 .. 16; + Reserved_17_18 at 0 range 17 .. 18; + EXLEVEL_S3 at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype TRCCNTRLDVR0_VALUE_Field is HAL.UInt16; + + -- The TRCCNTRLDVR defines the reload value for the reduced function + -- counter + type TRCCNTRLDVR0_Register is record + -- Defines the reload value for the counter. This value is loaded into + -- the counter each time the reload event occurs + VALUE : TRCCNTRLDVR0_VALUE_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCNTRLDVR0_Register use record + VALUE at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype TRCIMSPEC_SUPPORT_Field is HAL.UInt4; + + -- The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + -- features, and enables any features that are provided + type TRCIMSPEC_Register is record + -- Read-only. Reserved, RES0 + SUPPORT : TRCIMSPEC_SUPPORT_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIMSPEC_Register use record + SUPPORT at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRCIDR0_INSTP0_Field is HAL.UInt2; + subtype TRCIDR0_TRCDATA_Field is HAL.UInt2; + subtype TRCIDR0_NUMEVENT_Field is HAL.UInt2; + subtype TRCIDR0_CONDTYPE_Field is HAL.UInt2; + subtype TRCIDR0_QSUPP_Field is HAL.UInt2; + subtype TRCIDR0_TSSIZE_Field is HAL.UInt5; + + -- TRCIDR0 + type TRCIDR0_Register is record + -- Read-only. Reserved, RES1 + RES1 : Boolean; + -- Read-only. reads as `ImpDef + INSTP0 : TRCIDR0_INSTP0_Field; + -- Read-only. reads as `ImpDef + TRCDATA : TRCIDR0_TRCDATA_Field; + -- Read-only. reads as `ImpDef + TRCBB : Boolean; + -- Read-only. reads as `ImpDef + TRCCOND : Boolean; + -- Read-only. reads as `ImpDef + TRCCCI : Boolean; + -- unspecified + Reserved_8_8 : HAL.Bit; + -- Read-only. reads as `ImpDef + RETSTACK : Boolean; + -- Read-only. reads as `ImpDef + NUMEVENT : TRCIDR0_NUMEVENT_Field; + -- Read-only. reads as `ImpDef + CONDTYPE : TRCIDR0_CONDTYPE_Field; + -- Read-only. reads as `ImpDef + QFILT : Boolean; + -- Read-only. reads as `ImpDef + QSUPP : TRCIDR0_QSUPP_Field; + -- Read-only. reads as `ImpDef + TRCEXDATA : Boolean; + -- unspecified + Reserved_18_23 : HAL.UInt6; + -- Read-only. reads as `ImpDef + TSSIZE : TRCIDR0_TSSIZE_Field; + -- Read-only. reads as `ImpDef + COMMOPT : Boolean; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR0_Register use record + RES1 at 0 range 0 .. 0; + INSTP0 at 0 range 1 .. 2; + TRCDATA at 0 range 3 .. 4; + TRCBB at 0 range 5 .. 5; + TRCCOND at 0 range 6 .. 6; + TRCCCI at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + RETSTACK at 0 range 9 .. 9; + NUMEVENT at 0 range 10 .. 11; + CONDTYPE at 0 range 12 .. 13; + QFILT at 0 range 14 .. 14; + QSUPP at 0 range 15 .. 16; + TRCEXDATA at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + TSSIZE at 0 range 24 .. 28; + COMMOPT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype TRCIDR1_REVISION_Field is HAL.UInt4; + subtype TRCIDR1_TRCARCHMIN_Field is HAL.UInt4; + subtype TRCIDR1_TRCARCHMAJ_Field is HAL.UInt4; + subtype TRCIDR1_RES1_Field is HAL.UInt4; + subtype TRCIDR1_DESIGNER_Field is HAL.UInt8; + + -- TRCIDR1 + type TRCIDR1_Register is record + -- Read-only. reads as `ImpDef + REVISION : TRCIDR1_REVISION_Field; + -- Read-only. reads as 0b0000 + TRCARCHMIN : TRCIDR1_TRCARCHMIN_Field; + -- Read-only. reads as 0b0100 + TRCARCHMAJ : TRCIDR1_TRCARCHMAJ_Field; + -- Read-only. Reserved, RES1 + RES1 : TRCIDR1_RES1_Field; + -- unspecified + Reserved_16_23 : HAL.UInt8; + -- Read-only. reads as `ImpDef + DESIGNER : TRCIDR1_DESIGNER_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR1_Register use record + REVISION at 0 range 0 .. 3; + TRCARCHMIN at 0 range 4 .. 7; + TRCARCHMAJ at 0 range 8 .. 11; + RES1 at 0 range 12 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + DESIGNER at 0 range 24 .. 31; + end record; + + subtype TRCIDR2_IASIZE_Field is HAL.UInt5; + subtype TRCIDR2_CIDSIZE_Field is HAL.UInt5; + subtype TRCIDR2_VMIDSIZE_Field is HAL.UInt5; + subtype TRCIDR2_DASIZE_Field is HAL.UInt5; + subtype TRCIDR2_DVSIZE_Field is HAL.UInt5; + subtype TRCIDR2_CCSIZE_Field is HAL.UInt4; + + -- TRCIDR2 + type TRCIDR2_Register is record + -- Read-only. reads as `ImpDef + IASIZE : TRCIDR2_IASIZE_Field; + -- Read-only. reads as `ImpDef + CIDSIZE : TRCIDR2_CIDSIZE_Field; + -- Read-only. reads as `ImpDef + VMIDSIZE : TRCIDR2_VMIDSIZE_Field; + -- Read-only. reads as `ImpDef + DASIZE : TRCIDR2_DASIZE_Field; + -- Read-only. reads as `ImpDef + DVSIZE : TRCIDR2_DVSIZE_Field; + -- Read-only. reads as `ImpDef + CCSIZE : TRCIDR2_CCSIZE_Field; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR2_Register use record + IASIZE at 0 range 0 .. 4; + CIDSIZE at 0 range 5 .. 9; + VMIDSIZE at 0 range 10 .. 14; + DASIZE at 0 range 15 .. 19; + DVSIZE at 0 range 20 .. 24; + CCSIZE at 0 range 25 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype TRCIDR3_CCITMIN_Field is HAL.UInt12; + subtype TRCIDR3_EXLEVEL_S_Field is HAL.UInt4; + subtype TRCIDR3_EXLEVEL_NS_Field is HAL.UInt4; + subtype TRCIDR3_NUMPROC_Field is HAL.UInt3; + + -- TRCIDR3 + type TRCIDR3_Register is record + -- Read-only. reads as `ImpDef + CCITMIN : TRCIDR3_CCITMIN_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. reads as `ImpDef + EXLEVEL_S : TRCIDR3_EXLEVEL_S_Field; + -- Read-only. reads as `ImpDef + EXLEVEL_NS : TRCIDR3_EXLEVEL_NS_Field; + -- Read-only. reads as `ImpDef + TRCERR : Boolean; + -- Read-only. reads as `ImpDef + SYNCPR : Boolean; + -- Read-only. reads as `ImpDef + STALLCTL : Boolean; + -- Read-only. reads as `ImpDef + SYSSTALL : Boolean; + -- Read-only. reads as `ImpDef + NUMPROC : TRCIDR3_NUMPROC_Field; + -- Read-only. reads as `ImpDef + NOOVERFLOW : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR3_Register use record + CCITMIN at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + EXLEVEL_S at 0 range 16 .. 19; + EXLEVEL_NS at 0 range 20 .. 23; + TRCERR at 0 range 24 .. 24; + SYNCPR at 0 range 25 .. 25; + STALLCTL at 0 range 26 .. 26; + SYSSTALL at 0 range 27 .. 27; + NUMPROC at 0 range 28 .. 30; + NOOVERFLOW at 0 range 31 .. 31; + end record; + + subtype TRCIDR4_NUMACPAIRS_Field is HAL.UInt4; + subtype TRCIDR4_NUMDVC_Field is HAL.UInt4; + subtype TRCIDR4_NUMPC_Field is HAL.UInt4; + subtype TRCIDR4_NUMRSPAIR_Field is HAL.UInt4; + subtype TRCIDR4_NUMSSCC_Field is HAL.UInt4; + subtype TRCIDR4_NUMCIDC_Field is HAL.UInt4; + subtype TRCIDR4_NUMVMIDC_Field is HAL.UInt4; + + -- TRCIDR4 + type TRCIDR4_Register is record + -- Read-only. reads as `ImpDef + NUMACPAIRS : TRCIDR4_NUMACPAIRS_Field; + -- Read-only. reads as `ImpDef + NUMDVC : TRCIDR4_NUMDVC_Field; + -- Read-only. reads as `ImpDef + SUPPDAC : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. reads as `ImpDef + NUMPC : TRCIDR4_NUMPC_Field; + -- Read-only. reads as `ImpDef + NUMRSPAIR : TRCIDR4_NUMRSPAIR_Field; + -- Read-only. reads as `ImpDef + NUMSSCC : TRCIDR4_NUMSSCC_Field; + -- Read-only. reads as `ImpDef + NUMCIDC : TRCIDR4_NUMCIDC_Field; + -- Read-only. reads as `ImpDef + NUMVMIDC : TRCIDR4_NUMVMIDC_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR4_Register use record + NUMACPAIRS at 0 range 0 .. 3; + NUMDVC at 0 range 4 .. 7; + SUPPDAC at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + NUMPC at 0 range 12 .. 15; + NUMRSPAIR at 0 range 16 .. 19; + NUMSSCC at 0 range 20 .. 23; + NUMCIDC at 0 range 24 .. 27; + NUMVMIDC at 0 range 28 .. 31; + end record; + + subtype TRCIDR5_NUMEXTIN_Field is HAL.UInt9; + subtype TRCIDR5_NUMEXTINSEL_Field is HAL.UInt3; + subtype TRCIDR5_TRACEIDSIZE_Field is HAL.UInt6; + subtype TRCIDR5_NUMSEQSTATE_Field is HAL.UInt3; + subtype TRCIDR5_NUMCNTR_Field is HAL.UInt3; + + -- TRCIDR5 + type TRCIDR5_Register is record + -- Read-only. reads as `ImpDef + NUMEXTIN : TRCIDR5_NUMEXTIN_Field; + -- Read-only. reads as `ImpDef + NUMEXTINSEL : TRCIDR5_NUMEXTINSEL_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. reads as 0x07 + TRACEIDSIZE : TRCIDR5_TRACEIDSIZE_Field; + -- Read-only. reads as `ImpDef + ATBTRIG : Boolean; + -- Read-only. reads as `ImpDef + LPOVERRIDE : Boolean; + -- unspecified + Reserved_24_24 : HAL.Bit; + -- Read-only. reads as `ImpDef + NUMSEQSTATE : TRCIDR5_NUMSEQSTATE_Field; + -- Read-only. reads as `ImpDef + NUMCNTR : TRCIDR5_NUMCNTR_Field; + -- Read-only. reads as `ImpDef + REDFUNCNTR : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCIDR5_Register use record + NUMEXTIN at 0 range 0 .. 8; + NUMEXTINSEL at 0 range 9 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TRACEIDSIZE at 0 range 16 .. 21; + ATBTRIG at 0 range 22 .. 22; + LPOVERRIDE at 0 range 23 .. 23; + Reserved_24_24 at 0 range 24 .. 24; + NUMSEQSTATE at 0 range 25 .. 27; + NUMCNTR at 0 range 28 .. 30; + REDFUNCNTR at 0 range 31 .. 31; + end record; + + subtype TRCRSCTLR_SELECT_Field is HAL.UInt8; + subtype TRCRSCTLR_GROUP_Field is HAL.UInt3; + + -- The TRCRSCTLR controls the trace resources + type TRCRSCTLR_Register is record + -- Selects one or more resources from the wanted group. One bit is + -- provided per resource from the group + SELECT_k : TRCRSCTLR_SELECT_Field := 16#0#; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Selects a group of resource + GROUP : TRCRSCTLR_GROUP_Field := 16#0#; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Inverts the selected resources + INV : Boolean := False; + -- Inverts the result of a combined pair of resources. This bit is only + -- implemented on the lower register for a pair of resource selectors + PAIRINV : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCRSCTLR_Register use record + SELECT_k at 0 range 0 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + GROUP at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + INV at 0 range 20 .. 20; + PAIRINV at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Controls the corresponding single-shot comparator resource + type TRCSSCSR_Register is record + -- Read-only. Reserved, RES0 + INST : Boolean := False; + -- Read-only. Reserved, RES0 + DA : Boolean := False; + -- Read-only. Reserved, RES0 + DV : Boolean := False; + -- Read-only. Reserved, RES1 + PC : Boolean := False; + -- unspecified + Reserved_4_30 : HAL.UInt27 := 16#0#; + -- Single-shot status bit. Indicates if any of the comparators, that + -- TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + STATUS : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSSCSR_Register use record + INST at 0 range 0 .. 0; + DA at 0 range 1 .. 1; + DV at 0 range 2 .. 2; + PC at 0 range 3 .. 3; + Reserved_4_30 at 0 range 4 .. 30; + STATUS at 0 range 31 .. 31; + end record; + + subtype TRCSSPCICR_PC_Field is HAL.UInt4; + + -- Selects the PE comparator inputs for Single-shot control + type TRCSSPCICR_Register is record + -- Selects one or more PE comparator inputs for Single-shot control. + -- TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for + -- each implemented PE comparator input. For example, if bit[1] == 1 + -- this selects PE comparator input 1 for Single-shot control + PC : TRCSSPCICR_PC_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCSSPCICR_Register use record + PC at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Requests the system to provide power to the trace unit + type TRCPDCR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- Powerup request bit: + PU : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPDCR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + PU at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Returns the following information about the trace unit: - OS Lock + -- status. - Core power domain status. - Power interruption status + type TRCPDSR_Register is record + -- Read-only. Power status bit: + POWER : Boolean; + -- Read-only. Sticky powerdown status bit. Indicates whether the trace + -- register state is valid: + STICKYPD : Boolean; + -- unspecified + Reserved_2_4 : HAL.UInt3; + -- Read-only. OS Lock status bit: + OSLK : Boolean; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPDSR_Register use record + POWER at 0 range 0 .. 0; + STICKYPD at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OSLK at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype TRCITATBIDR_ID_Field is HAL.UInt7; + + -- Trace Integration ATB Identification Register + type TRCITATBIDR_Register is record + -- Trace ID + ID : TRCITATBIDR_ID_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITATBIDR_Register use record + ID at 0 range 0 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Trace Integration Instruction ATB In Register + type TRCITIATBINR_Register is record + -- Integration Mode instruction ATREADYM in + ATREADYM : Boolean := False; + -- Integration Mode instruction AFVALIDM in + AFVALIDM : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITIATBINR_Register use record + ATREADYM at 0 range 0 .. 0; + AFVALIDM at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Trace Integration Instruction ATB Out Register + type TRCITIATBOUTR_Register is record + -- Integration Mode instruction ATVALID out + ATVALID : Boolean := False; + -- Integration Mode instruction AFREADY out + AFREADY : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCITIATBOUTR_Register use record + ATVALID at 0 range 0 .. 0; + AFREADY at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- TRCCLAIMSET_SET array + type TRCCLAIMSET_SET_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for TRCCLAIMSET_SET + type TRCCLAIMSET_SET_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SET as a value + Val : HAL.UInt4; + when True => + -- SET as an array + Arr : TRCCLAIMSET_SET_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for TRCCLAIMSET_SET_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Claim Tag Set Register + type TRCCLAIMSET_Register is record + -- When a write to one of these bits occurs, with the value: + SET : TRCCLAIMSET_SET_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCLAIMSET_Register use record + SET at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- TRCCLAIMCLR_CLR array + type TRCCLAIMCLR_CLR_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for TRCCLAIMCLR_CLR + type TRCCLAIMCLR_CLR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CLR as a value + Val : HAL.UInt4; + when True => + -- CLR as an array + Arr : TRCCLAIMCLR_CLR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for TRCCLAIMCLR_CLR_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Claim Tag Clear Register + type TRCCLAIMCLR_Register is record + -- When a write to one of these bits occurs, with the value: + CLR : TRCCLAIMCLR_CLR_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCLAIMCLR_Register use record + CLR at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRCAUTHSTATUS_NSID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_NSNID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_SID_Field is HAL.UInt2; + subtype TRCAUTHSTATUS_SNID_Field is HAL.UInt2; + + -- Returns the level of tracing that the trace unit can support + type TRCAUTHSTATUS_Register is record + -- Read-only. Indicates whether the trace unit supports Non-secure + -- invasive debug: + NSID : TRCAUTHSTATUS_NSID_Field; + -- Read-only. Indicates whether the system enables the trace unit to + -- support Non-secure non-invasive debug: + NSNID : TRCAUTHSTATUS_NSNID_Field; + -- Read-only. Indicates whether the trace unit supports Secure invasive + -- debug: + SID : TRCAUTHSTATUS_SID_Field; + -- Read-only. Indicates whether the system enables the trace unit to + -- support Secure non-invasive debug: + SNID : TRCAUTHSTATUS_SNID_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCAUTHSTATUS_Register use record + NSID at 0 range 0 .. 1; + NSNID at 0 range 2 .. 3; + SID at 0 range 4 .. 5; + SNID at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCDEVARCH_ARCHID_Field is HAL.UInt16; + subtype TRCDEVARCH_REVISION_Field is HAL.UInt4; + subtype TRCDEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- TRCDEVARCH + type TRCDEVARCH_Register is record + -- Read-only. reads as 0b0100101000010011 + ARCHID : TRCDEVARCH_ARCHID_Field; + -- Read-only. reads as 0b0000 + REVISION : TRCDEVARCH_REVISION_Field; + -- Read-only. reads as 0b1 + PRESENT : Boolean; + -- Read-only. reads as 0b01000111011 + ARCHITECT : TRCDEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCDEVARCH_Register use record + ARCHID at 0 range 0 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype TRCDEVTYPE_MAJOR_Field is HAL.UInt4; + subtype TRCDEVTYPE_SUB_Field is HAL.UInt4; + + -- TRCDEVTYPE + type TRCDEVTYPE_Register is record + -- Read-only. reads as 0b0011 + MAJOR : TRCDEVTYPE_MAJOR_Field; + -- Read-only. reads as 0b0001 + SUB : TRCDEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCDEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR4_DES_2_Field is HAL.UInt4; + subtype TRCPIDR4_SIZE_Field is HAL.UInt4; + + -- TRCPIDR4 + type TRCPIDR4_Register is record + -- Read-only. reads as `ImpDef + DES_2 : TRCPIDR4_DES_2_Field; + -- Read-only. reads as `ImpDef + SIZE : TRCPIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR0_PART_0_Field is HAL.UInt8; + + -- TRCPIDR0 + type TRCPIDR0_Register is record + -- Read-only. reads as `ImpDef + PART_0 : TRCPIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR1_PART_0_Field is HAL.UInt4; + subtype TRCPIDR1_DES_0_Field is HAL.UInt4; + + -- TRCPIDR1 + type TRCPIDR1_Register is record + -- Read-only. reads as `ImpDef + PART_0 : TRCPIDR1_PART_0_Field; + -- Read-only. reads as `ImpDef + DES_0 : TRCPIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR1_Register use record + PART_0 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR2_DES_0_Field is HAL.UInt3; + subtype TRCPIDR2_REVISION_Field is HAL.UInt4; + + -- TRCPIDR2 + type TRCPIDR2_Register is record + -- Read-only. reads as `ImpDef + DES_0 : TRCPIDR2_DES_0_Field; + -- Read-only. reads as 0b1 + JEDEC : Boolean; + -- Read-only. reads as `ImpDef + REVISION : TRCPIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR2_Register use record + DES_0 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCPIDR3_CMOD_Field is HAL.UInt4; + subtype TRCPIDR3_REVAND_Field is HAL.UInt4; + + -- TRCPIDR3 + type TRCPIDR3_Register is record + -- Read-only. reads as `ImpDef + CMOD : TRCPIDR3_CMOD_Field; + -- Read-only. reads as `ImpDef + REVAND : TRCPIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCPIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR0_PRMBL_0_Field is HAL.UInt8; + + -- TRCCIDR0 + type TRCCIDR0_Register is record + -- Read-only. reads as 0b00001101 + PRMBL_0 : TRCCIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR1_PRMBL_1_Field is HAL.UInt4; + subtype TRCCIDR1_CLASS_Field is HAL.UInt4; + + -- TRCCIDR1 + type TRCCIDR1_Register is record + -- Read-only. reads as 0b0000 + PRMBL_1 : TRCCIDR1_PRMBL_1_Field; + -- Read-only. reads as 0b1001 + CLASS : TRCCIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR2_PRMBL_2_Field is HAL.UInt8; + + -- TRCCIDR2 + type TRCCIDR2_Register is record + -- Read-only. reads as 0b00000101 + PRMBL_2 : TRCCIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TRCCIDR3_PRMBL_3_Field is HAL.UInt8; + + -- TRCCIDR3 + type TRCCIDR3_Register is record + -- Read-only. reads as 0b10110001 + PRMBL_3 : TRCCIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRCCIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- CTI Control Register + type CTICONTROL_Register is record + -- Enables or disables the CTI + GLBEN : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTICONTROL_Register use record + GLBEN at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype CTIINTACK_INTACK_Field is HAL.UInt8; + + -- CTI Interrupt Acknowledge Register + type CTIINTACK_Register is record + -- Acknowledges the corresponding ctitrigout output. There is one bit of + -- the register for each ctitrigout output. When a 1 is written to a bit + -- in this register, the corresponding ctitrigout is acknowledged, + -- causing it to be cleared. + INTACK : CTIINTACK_INTACK_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIINTACK_Register use record + INTACK at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTIAPPSET_APPSET_Field is HAL.UInt4; + + -- CTI Application Trigger Set Register + type CTIAPPSET_Register is record + -- Setting a bit HIGH generates a channel event for the selected + -- channel. There is one bit of the register for each channel + APPSET : CTIAPPSET_APPSET_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPSET_Register use record + APPSET at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIAPPCLEAR_APPCLEAR_Field is HAL.UInt4; + + -- CTI Application Trigger Clear Register + type CTIAPPCLEAR_Register is record + -- Sets the corresponding bits in the CTIAPPSET to 0. There is one bit + -- of the register for each channel. + APPCLEAR : CTIAPPCLEAR_APPCLEAR_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPCLEAR_Register use record + APPCLEAR at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIAPPPULSE_APPULSE_Field is HAL.UInt4; + + -- CTI Application Pulse Register + type CTIAPPPULSE_Register is record + -- Setting a bit HIGH generates a channel event pulse for the selected + -- channel. There is one bit of the register for each channel. + APPULSE : CTIAPPPULSE_APPULSE_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIAPPPULSE_Register use record + APPULSE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIINEN_TRIGINEN_Field is HAL.UInt4; + + -- CTI Trigger to Channel Enable Registers + type CTIINEN_Register is record + -- Enables a cross trigger event to the corresponding channel when a + -- ctitrigin input is activated. There is one bit of the field for each + -- of the four channels + TRIGINEN : CTIINEN_TRIGINEN_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIINEN_Register use record + TRIGINEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTIOUTEN_TRIGOUTEN_Field is HAL.UInt4; + + -- CTI Trigger to Channel Enable Registers + type CTIOUTEN_Register is record + -- Enables a cross trigger event to ctitrigout when the corresponding + -- channel is activated. There is one bit of the field for each of the + -- four channels. + TRIGOUTEN : CTIOUTEN_TRIGOUTEN_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIOUTEN_Register use record + TRIGOUTEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype CTITRIGINSTATUS_TRIGINSTATUS_Field is HAL.UInt8; + + -- CTI Trigger to Channel Enable Registers + type CTITRIGINSTATUS_Register is record + -- Read-only. Shows the status of the ctitrigin inputs. There is one bit + -- of the field for each trigger input.Because the register provides a + -- view of the raw ctitrigin inputs, the reset value is UNKNOWN. + TRIGINSTATUS : CTITRIGINSTATUS_TRIGINSTATUS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTITRIGINSTATUS_Register use record + TRIGINSTATUS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTITRIGOUTSTATUS_TRIGOUTSTATUS_Field is HAL.UInt8; + + -- CTI Trigger In Status Register + type CTITRIGOUTSTATUS_Register is record + -- Read-only. Shows the status of the ctitrigout outputs. There is one + -- bit of the field for each trigger output. + TRIGOUTSTATUS : CTITRIGOUTSTATUS_TRIGOUTSTATUS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTITRIGOUTSTATUS_Register use record + TRIGOUTSTATUS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CTICHINSTATUS_CTICHOUTSTATUS_Field is HAL.UInt4; + + -- CTI Channel In Status Register + type CTICHINSTATUS_Register is record + -- Read-only. Shows the status of the ctichout outputs. There is one bit + -- of the field for each channel output + CTICHOUTSTATUS : CTICHINSTATUS_CTICHOUTSTATUS_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTICHINSTATUS_Register use record + CTICHOUTSTATUS at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- CTIGATE_CTIGATEEN array + type CTIGATE_CTIGATEEN_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for CTIGATE_CTIGATEEN + type CTIGATE_CTIGATEEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CTIGATEEN as a value + Val : HAL.UInt4; + when True => + -- CTIGATEEN as an array + Arr : CTIGATE_CTIGATEEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for CTIGATE_CTIGATEEN_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Enable CTI Channel Gate register + type CTIGATE_Register is record + -- Enable ctichout0. Set to 0 to disable channel propagation. + CTIGATEEN : CTIGATE_CTIGATEEN_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTIGATE_Register use record + CTIGATEEN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITCHOUT_CTCHOUT_Field is HAL.UInt4; + + -- Integration Test Channel Output register + type ITCHOUT_Register is record + -- Sets the value of the ctichout outputs + CTCHOUT : ITCHOUT_CTCHOUT_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCHOUT_Register use record + CTCHOUT at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ITTRIGOUT_CTTRIGOUT_Field is HAL.UInt8; + + -- Integration Test Trigger Output register + type ITTRIGOUT_Register is record + -- Sets the value of the ctitrigout outputs + CTTRIGOUT : ITTRIGOUT_CTTRIGOUT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITTRIGOUT_Register use record + CTTRIGOUT at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype ITCHIN_CTCHIN_Field is HAL.UInt4; + + -- Integration Test Channel Input register + type ITCHIN_Register is record + -- Read-only. Reads the value of the ctichin inputs. + CTCHIN : ITCHIN_CTCHIN_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCHIN_Register use record + CTCHIN at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Integration Mode Control register + type ITCTRL_Register is record + -- Integration Mode Enable + IME : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ITCTRL_Register use record + IME at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype DEVARCH_ARCHID_Field is HAL.UInt16; + subtype DEVARCH_REVISION_Field is HAL.UInt4; + subtype DEVARCH_ARCHITECT_Field is HAL.UInt11; + + -- Device Architecture register + type DEVARCH_Register is record + -- Read-only. Indicates the component + ARCHID : DEVARCH_ARCHID_Field; + -- Read-only. Indicates the architecture revision + REVISION : DEVARCH_REVISION_Field; + -- Read-only. Indicates whether the DEVARCH register is present + PRESENT : Boolean; + -- Read-only. Indicates the component architect + ARCHITECT : DEVARCH_ARCHITECT_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVARCH_Register use record + ARCHID at 0 range 0 .. 15; + REVISION at 0 range 16 .. 19; + PRESENT at 0 range 20 .. 20; + ARCHITECT at 0 range 21 .. 31; + end record; + + subtype DEVID_EXTMUXNUM_Field is HAL.UInt5; + subtype DEVID_NUMTRIG_Field is HAL.UInt8; + subtype DEVID_NUMCH_Field is HAL.UInt4; + + -- Device Configuration register + type DEVID_Register is record + -- Read-only. Indicates the number of multiplexers available on Trigger + -- Inputs and Trigger Outputs that are using asicctl. The default value + -- of 0b00000 indicates that no multiplexing is present. This value of + -- this bit depends on the Verilog define EXTMUXNUM that you must change + -- accordingly. + EXTMUXNUM : DEVID_EXTMUXNUM_Field; + -- unspecified + Reserved_5_7 : HAL.UInt3; + -- Read-only. Number of ECT triggers available. + NUMTRIG : DEVID_NUMTRIG_Field; + -- Read-only. Number of ECT channels available + NUMCH : DEVID_NUMCH_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVID_Register use record + EXTMUXNUM at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + NUMTRIG at 0 range 8 .. 15; + NUMCH at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype DEVTYPE_MAJOR_Field is HAL.UInt4; + subtype DEVTYPE_SUB_Field is HAL.UInt4; + + -- Device Type Identifier register + type DEVTYPE_Register is record + -- Read-only. Major classification of the type of the debug component as + -- specified in the ARM Architecture Specification for this debug and + -- trace component. + MAJOR : DEVTYPE_MAJOR_Field; + -- Read-only. Sub-classification of the type of the debug component as + -- specified in the ARM Architecture Specification within the major + -- classification as specified in the MAJOR field. + SUB : DEVTYPE_SUB_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEVTYPE_Register use record + MAJOR at 0 range 0 .. 3; + SUB at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR4_DES_2_Field is HAL.UInt4; + subtype PIDR4_SIZE_Field is HAL.UInt4; + + -- CoreSight Peripheral ID4 + type PIDR4_Register is record + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_2 : PIDR4_DES_2_Field; + -- Read-only. Always 0b0000. Indicates that the device only occupies 4KB + -- of memory + SIZE : PIDR4_SIZE_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR4_Register use record + DES_2 at 0 range 0 .. 3; + SIZE at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR0_PART_0_Field is HAL.UInt8; + + -- CoreSight Peripheral ID0 + type PIDR0_Register is record + -- Read-only. Bits[7:0] of the 12-bit part number of the component. The + -- designer of the component assigns this part number. + PART_0 : PIDR0_PART_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR0_Register use record + PART_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR1_PART_1_Field is HAL.UInt4; + subtype PIDR1_DES_0_Field is HAL.UInt4; + + -- CoreSight Peripheral ID1 + type PIDR1_Register is record + -- Read-only. Bits[11:8] of the 12-bit part number of the component. The + -- designer of the component assigns this part number. + PART_1 : PIDR1_PART_1_Field; + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_0 : PIDR1_DES_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR1_Register use record + PART_1 at 0 range 0 .. 3; + DES_0 at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR2_DES_1_Field is HAL.UInt3; + subtype PIDR2_REVISION_Field is HAL.UInt4; + + -- CoreSight Peripheral ID2 + type PIDR2_Register is record + -- Read-only. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 + -- identify the designer of the component. + DES_1 : PIDR2_DES_1_Field; + -- Read-only. Always 1. Indicates that the JEDEC-assigned designer ID is + -- used. + JEDEC : Boolean; + -- Read-only. This device is at r1p0 + REVISION : PIDR2_REVISION_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR2_Register use record + DES_1 at 0 range 0 .. 2; + JEDEC at 0 range 3 .. 3; + REVISION at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PIDR3_CMOD_Field is HAL.UInt4; + subtype PIDR3_REVAND_Field is HAL.UInt4; + + -- CoreSight Peripheral ID3 + type PIDR3_Register is record + -- Read-only. Customer Modified. Indicates whether the customer has + -- modified the behavior of the component. In most cases, this field is + -- 0b0000. Customers change this value when they make authorized + -- modifications to this component. + CMOD : PIDR3_CMOD_Field; + -- Read-only. Indicates minor errata fixes specific to the revision of + -- the component being used, for example metal fixes after + -- implementation. In most cases, this field is 0b0000. ARM recommends + -- that the component designers ensure that a metal fix can change this + -- field if required, for example, by driving it from registers that + -- reset to 0b0000. + REVAND : PIDR3_REVAND_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PIDR3_Register use record + CMOD at 0 range 0 .. 3; + REVAND at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR0_PRMBL_0_Field is HAL.UInt8; + + -- CoreSight Component ID0 + type CIDR0_Register is record + -- Read-only. Preamble[0]. Contains bits[7:0] of the component + -- identification code + PRMBL_0 : CIDR0_PRMBL_0_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR0_Register use record + PRMBL_0 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR1_PRMBL_1_Field is HAL.UInt4; + subtype CIDR1_CLASS_Field is HAL.UInt4; + + -- CoreSight Component ID1 + type CIDR1_Register is record + -- Read-only. Preamble[1]. Contains bits[11:8] of the component + -- identification code. + PRMBL_1 : CIDR1_PRMBL_1_Field; + -- Read-only. Class of the component, for example, whether the component + -- is a ROM table or a generic CoreSight component. Contains bits[15:12] + -- of the component identification code. + CLASS : CIDR1_CLASS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR1_Register use record + PRMBL_1 at 0 range 0 .. 3; + CLASS at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR2_PRMBL_2_Field is HAL.UInt8; + + -- CoreSight Component ID2 + type CIDR2_Register is record + -- Read-only. Preamble[2]. Contains bits[23:16] of the component + -- identification code. + PRMBL_2 : CIDR2_PRMBL_2_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR2_Register use record + PRMBL_2 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CIDR3_PRMBL_3_Field is HAL.UInt8; + + -- CoreSight Component ID3 + type CIDR3_Register is record + -- Read-only. Preamble[3]. Contains bits[31:24] of the component + -- identification code. + PRMBL_3 : CIDR3_PRMBL_3_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CIDR3_Register use record + PRMBL_3 at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- TEAL registers accessible through the debug interface + type PPB_NS_Peripheral is record + -- Provides the interface for generating Instrumentation packets + ITM_STIM0 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM1 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM2 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM3 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM4 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM5 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM6 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM7 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM8 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM9 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM10 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM11 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM12 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM13 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM14 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM15 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM16 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM17 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM18 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM19 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM20 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM21 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM22 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM23 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM24 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM25 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM26 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM27 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM28 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM29 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM30 : aliased HAL.UInt32; + -- Provides the interface for generating Instrumentation packets + ITM_STIM31 : aliased HAL.UInt32; + -- Provide an individual enable bit for each ITM_STIM register + ITM_TER0 : aliased HAL.UInt32; + -- Controls which stimulus ports can be accessed by unprivileged code + ITM_TPR : aliased ITM_TPR_Register; + -- Configures and controls transfers through the ITM interface + ITM_TCR : aliased ITM_TCR_Register; + -- Integration Mode: Read ATB Ready + INT_ATREADY : aliased INT_ATREADY_Register; + -- Integration Mode: Write ATB Valid + INT_ATVALID : aliased INT_ATVALID_Register; + -- Integration Mode Control Register + ITM_ITCTRL : aliased ITM_ITCTRL_Register; + -- Provides CoreSight discovery information for the ITM + ITM_DEVARCH : aliased ITM_DEVARCH_Register; + -- Provides CoreSight discovery information for the ITM + ITM_DEVTYPE : aliased ITM_DEVTYPE_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR4 : aliased ITM_PIDR4_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR0 : aliased ITM_PIDR0_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR1 : aliased ITM_PIDR1_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR2 : aliased ITM_PIDR2_Register; + -- Provides CoreSight discovery information for the ITM + ITM_PIDR3 : aliased ITM_PIDR3_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR0 : aliased ITM_CIDR0_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR1 : aliased ITM_CIDR1_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR2 : aliased ITM_CIDR2_Register; + -- Provides CoreSight discovery information for the ITM + ITM_CIDR3 : aliased ITM_CIDR3_Register; + -- Provides configuration and status information for the DWT unit, and + -- used to control features of the unit + DWT_CTRL : aliased DWT_CTRL_Register; + -- Shows or sets the value of the processor cycle counter, CYCCNT + DWT_CYCCNT : aliased HAL.UInt32; + -- Counts the total cycles spent in exception processing + DWT_EXCCNT : aliased DWT_EXCCNT_Register; + -- Increments on the additional cycles required to execute all load or + -- store instructions + DWT_LSUCNT : aliased DWT_LSUCNT_Register; + -- Increments on the additional cycles required to execute all load or + -- store instructions + DWT_FOLDCNT : aliased DWT_FOLDCNT_Register; + -- Provides a reference value for use by watchpoint comparator 0 + DWT_COMP0 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 0 + DWT_FUNCTION0 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 1 + DWT_COMP1 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 1 + DWT_FUNCTION1 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 2 + DWT_COMP2 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 2 + DWT_FUNCTION2 : aliased DWT_FUNCTION_Register; + -- Provides a reference value for use by watchpoint comparator 3 + DWT_COMP3 : aliased HAL.UInt32; + -- Controls the operation of watchpoint comparator 3 + DWT_FUNCTION3 : aliased DWT_FUNCTION_Register; + -- Provides CoreSight discovery information for the DWT + DWT_DEVARCH : aliased DWT_DEVARCH_Register; + -- Provides CoreSight discovery information for the DWT + DWT_DEVTYPE : aliased DWT_DEVTYPE_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR4 : aliased DWT_PIDR4_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR0 : aliased DWT_PIDR0_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR1 : aliased DWT_PIDR1_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR2 : aliased DWT_PIDR2_Register; + -- Provides CoreSight discovery information for the DWT + DWT_PIDR3 : aliased DWT_PIDR3_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR0 : aliased DWT_CIDR0_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR1 : aliased DWT_CIDR1_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR2 : aliased DWT_CIDR2_Register; + -- Provides CoreSight discovery information for the DWT + DWT_CIDR3 : aliased DWT_CIDR3_Register; + -- Provides FPB implementation information, and the global enable for + -- the FPB unit + FP_CTRL : aliased FP_CTRL_Register; + -- Indicates whether the implementation supports Flash Patch remap and, + -- if it does, holds the target address for remap + FP_REMAP : aliased FP_REMAP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP0 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP1 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP2 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP3 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP4 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP5 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP6 : aliased FP_COMP_Register; + -- Holds an address for comparison. The effect of the match depends on + -- the configuration of the FPB and whether the comparator is an + -- instruction address comparator or a literal address comparator + FP_COMP7 : aliased FP_COMP_Register; + -- Provides CoreSight discovery information for the FPB + FP_DEVARCH : aliased FP_DEVARCH_Register; + -- Provides CoreSight discovery information for the FPB + FP_DEVTYPE : aliased FP_DEVTYPE_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR4 : aliased FP_PIDR4_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the FP + FP_PIDR0 : aliased FP_PIDR0_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR1 : aliased FP_PIDR1_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR2 : aliased FP_PIDR2_Register; + -- Provides CoreSight discovery information for the FP + FP_PIDR3 : aliased FP_PIDR3_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR0 : aliased FP_CIDR0_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR1 : aliased FP_CIDR1_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR2 : aliased FP_CIDR2_Register; + -- Provides CoreSight discovery information for the FP + FP_CIDR3 : aliased FP_CIDR3_Register; + -- Provides information about the interrupt controller + ICTR : aliased ICTR_Register; + -- Provides IMPLEMENTATION DEFINED configuration and control options + ACTLR : aliased ACTLR_Register; + -- Use the SysTick Control and Status Register to enable the SysTick + -- features. + SYST_CSR : aliased SYST_CSR_Register; + -- Use the SysTick Reload Value Register to specify the start value to + -- load into the current value register when the counter reaches 0. It + -- can be any value between 0 and 0x00FFFFFF. A start value of 0 is + -- possible, but has no effect because the SysTick interrupt and + -- COUNTFLAG are activated when counting from 1 to 0. The reset value of + -- this register is UNKNOWN. To generate a multi-shot timer with a + -- period of N processor clock cycles, use a RELOAD value of N-1. For + -- example, if the SysTick interrupt is required every 100 clock pulses, + -- set RELOAD to 99. + SYST_RVR : aliased SYST_RVR_Register; + -- Use the SysTick Current Value Register to find the current value in + -- the register. The reset value of this register is UNKNOWN. + SYST_CVR : aliased SYST_CVR_Register; + -- Use the SysTick Calibration Value Register to enable software to + -- scale to any required speed using divide and multiply. + SYST_CALIB : aliased SYST_CALIB_Register; + -- Enables or reads the enabled state of each group of 32 interrupts + NVIC_ISER0 : aliased HAL.UInt32; + -- Enables or reads the enabled state of each group of 32 interrupts + NVIC_ISER1 : aliased HAL.UInt32; + -- Clears or reads the enabled state of each group of 32 interrupts + NVIC_ICER0 : aliased HAL.UInt32; + -- Clears or reads the enabled state of each group of 32 interrupts + NVIC_ICER1 : aliased HAL.UInt32; + -- Enables or reads the pending state of each group of 32 interrupts + NVIC_ISPR0 : aliased HAL.UInt32; + -- Enables or reads the pending state of each group of 32 interrupts + NVIC_ISPR1 : aliased HAL.UInt32; + -- Clears or reads the pending state of each group of 32 interrupts + NVIC_ICPR0 : aliased HAL.UInt32; + -- Clears or reads the pending state of each group of 32 interrupts + NVIC_ICPR1 : aliased HAL.UInt32; + -- For each group of 32 interrupts, shows the active state of each + -- interrupt + NVIC_IABR0 : aliased HAL.UInt32; + -- For each group of 32 interrupts, shows the active state of each + -- interrupt + NVIC_IABR1 : aliased HAL.UInt32; + -- For each group of 32 interrupts, determines whether each interrupt + -- targets Non-secure or Secure state + NVIC_ITNS0 : aliased HAL.UInt32; + -- For each group of 32 interrupts, determines whether each interrupt + -- targets Non-secure or Secure state + NVIC_ITNS1 : aliased HAL.UInt32; + -- Sets or reads interrupt priorities + NVIC_IPR0 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR1 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR2 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR3 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR4 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR5 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR6 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR7 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR8 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR9 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR10 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR11 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR12 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR13 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR14 : aliased NVIC_IPR_Register; + -- Sets or reads interrupt priorities + NVIC_IPR15 : aliased NVIC_IPR_Register; + -- Provides identification information for the PE, including an + -- implementer code for the device and a device ID number + CPUID : aliased CPUID_Register; + -- Controls and provides status information for NMI, PendSV, SysTick and + -- interrupts + ICSR : aliased ICSR_Register; + -- The VTOR indicates the offset of the vector table base address from + -- memory address 0x00000000. + VTOR : aliased VTOR_Register; + -- Use the Application Interrupt and Reset Control Register to: + -- determine data endianness, clear all active state information from + -- debug halt mode, request a system reset. + AIRCR : aliased AIRCR_Register; + -- System Control Register. Use the System Control Register for + -- power-management functions: signal to the system when the processor + -- can enter a low power state, control how the processor enters and + -- exits low power states. + SCR : aliased SCR_Register; + -- Sets or returns configuration and control data + CCR : aliased CCR_Register; + -- Sets or returns priority for system handlers 4 - 7 + SHPR1 : aliased SHPR1_Register; + -- Sets or returns priority for system handlers 8 - 11 + SHPR2 : aliased SHPR2_Register; + -- Sets or returns priority for system handlers 12 - 15 + SHPR3 : aliased SHPR3_Register; + -- Provides access to the active and pending status of system exceptions + SHCSR : aliased SHCSR_Register; + -- Contains the three Configurable Fault Status Registers. 31:16 UFSR: + -- Provides information on UsageFault exceptions 15:8 BFSR: Provides + -- information on BusFault exceptions 7:0 MMFSR: Provides information on + -- MemManage exceptions + CFSR : aliased CFSR_Register; + -- Shows the cause of any HardFaults + HFSR : aliased HFSR_Register; + -- Shows which debug event occurred + DFSR : aliased DFSR_Register; + -- Shows the address of the memory location that caused an MPU fault + MMFAR : aliased HAL.UInt32; + -- Shows the address associated with a precise data access BusFault + BFAR : aliased HAL.UInt32; + -- Gives top-level information about the instruction set supported by + -- the PE + ID_PFR0 : aliased ID_PFR0_Register; + -- Gives information about the programmers' model and Extensions support + ID_PFR1 : aliased ID_PFR1_Register; + -- Provides top level information about the debug system + ID_DFR0 : aliased ID_DFR0_Register; + -- Provides information about the IMPLEMENTATION DEFINED features of the + -- PE + ID_AFR0 : aliased ID_AFR0_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR0 : aliased ID_MMFR0_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR1 : aliased HAL.UInt32; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR2 : aliased ID_MMFR2_Register; + -- Provides information about the implemented memory model and memory + -- management support + ID_MMFR3 : aliased ID_MMFR3_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR0 : aliased ID_ISAR0_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR1 : aliased ID_ISAR1_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR2 : aliased ID_ISAR2_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR3 : aliased ID_ISAR3_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR4 : aliased ID_ISAR4_Register; + -- Provides information about the instruction set implemented by the PE + ID_ISAR5 : aliased HAL.UInt32; + -- Provides information about the architecture of the caches. CTR is + -- RES0 if CLIDR is zero. + CTR : aliased CTR_Register; + -- Specifies the access privileges for coprocessors and the FP Extension + CPACR : aliased CPACR_Register; + -- Defines the Non-secure access permissions for both the FP Extension + -- and coprocessors CP0 to CP7 + NSACR : aliased NSACR_Register; + -- The MPU Type Register indicates how many regions the MPU `FTSSS + -- supports + MPU_TYPE : aliased MPU_TYPE_Register; + -- Enables the MPU and, when the MPU is enabled, controls whether the + -- default memory map is enabled as a background region for privileged + -- accesses, and whether the MPU is enabled for HardFaults, NMIs, and + -- exception handlers when FAULTMASK is set to 1 + MPU_CTRL : aliased MPU_CTRL_Register; + -- Selects the region currently accessed by MPU_RBAR and MPU_RLAR + MPU_RNR : aliased MPU_RNR_Register; + -- Provides indirect read and write access to the base address of the + -- currently selected MPU region `FTSSS + MPU_RBAR : aliased MPU_RBAR_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region `FTSSS + MPU_RLAR : aliased MPU_RLAR_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + MPU_RBAR_A1 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) + -- `FTSSS + MPU_RLAR_A1 : aliased MPU_RLAR_A_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + MPU_RBAR_A2 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) + -- `FTSSS + MPU_RLAR_A2 : aliased MPU_RLAR_A_Register; + -- Provides indirect read and write access to the base address of the + -- MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + MPU_RBAR_A3 : aliased MPU_RBAR_A_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) + -- `FTSSS + MPU_RLAR_A3 : aliased MPU_RLAR_A_Register; + -- Along with MPU_MAIR1, provides the memory attribute encodings + -- corresponding to the AttrIndex values + MPU_MAIR0 : aliased MPU_MAIR0_Register; + -- Along with MPU_MAIR0, provides the memory attribute encodings + -- corresponding to the AttrIndex values + MPU_MAIR1 : aliased MPU_MAIR1_Register; + -- Allows enabling of the Security Attribution Unit + SAU_CTRL : aliased SAU_CTRL_Register; + -- Indicates the number of regions implemented by the Security + -- Attribution Unit + SAU_TYPE : aliased SAU_TYPE_Register; + -- Selects the region currently accessed by SAU_RBAR and SAU_RLAR + SAU_RNR : aliased SAU_RNR_Register; + -- Provides indirect read and write access to the base address of the + -- currently selected SAU region + SAU_RBAR : aliased SAU_RBAR_Register; + -- Provides indirect read and write access to the limit address of the + -- currently selected SAU region + SAU_RLAR : aliased SAU_RLAR_Register; + -- Provides information about any security related faults + SFSR : aliased SFSR_Register; + -- Shows the address of the memory location that caused a Security + -- violation + SFAR : aliased HAL.UInt32; + -- Controls halting debug + DHCSR : aliased DHCSR_Register; + -- With the DCRDR, provides debug access to the general-purpose + -- registers, special-purpose registers, and the FP extension registers. + -- A write to the DCRSR specifies the register to transfer, whether the + -- transfer is a read or write, and starts the transfer + DCRSR : aliased DCRSR_Register; + -- With the DCRSR, provides debug access to the general-purpose + -- registers, special-purpose registers, and the FP Extension registers. + -- If the Main Extension is implemented, it can also be used for message + -- passing between an external debugger and a debug agent running on the + -- PE + DCRDR : aliased HAL.UInt32; + -- Manages vector catch behavior and DebugMonitor handling when + -- debugging + DEMCR : aliased DEMCR_Register; + -- Provides control and status information for Secure debug + DSCSR : aliased DSCSR_Register; + -- Provides a mechanism for software to generate an interrupt + STIR : aliased STIR_Register; + -- Holds control data for the Floating-point extension + FPCCR : aliased FPCCR_Register; + -- Holds the location of the unpopulated floating-point register space + -- allocated on an exception stack frame + FPCAR : aliased FPCAR_Register; + -- Holds the default values for the floating-point status control data + -- that the PE assigns to the FPSCR when it creates a new floating-point + -- context + FPDSCR : aliased FPDSCR_Register; + -- Describes the features provided by the Floating-point Extension + MVFR0 : aliased MVFR0_Register; + -- Describes the features provided by the Floating-point Extension + MVFR1 : aliased MVFR1_Register; + -- Describes the features provided by the Floating-point Extension + MVFR2 : aliased MVFR2_Register; + -- Provides CoreSight discovery information for the SCS + DDEVARCH : aliased DDEVARCH_Register; + -- Provides CoreSight discovery information for the SCS + DDEVTYPE : aliased DDEVTYPE_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR4 : aliased DPIDR4_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR5 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR6 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR7 : aliased HAL.UInt32; + -- Provides CoreSight discovery information for the SCS + DPIDR0 : aliased DPIDR0_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR1 : aliased DPIDR1_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR2 : aliased DPIDR2_Register; + -- Provides CoreSight discovery information for the SCS + DPIDR3 : aliased DPIDR3_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR0 : aliased DCIDR0_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR1 : aliased DCIDR1_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR2 : aliased DCIDR2_Register; + -- Provides CoreSight discovery information for the SCS + DCIDR3 : aliased DCIDR3_Register; + -- Programming Control Register + TRCPRGCTLR : aliased TRCPRGCTLR_Register; + -- The TRCSTATR indicates the ETM-Teal status + TRCSTATR : aliased TRCSTATR_Register; + -- The TRCCONFIGR sets the basic tracing options for the trace unit + TRCCONFIGR : aliased TRCCONFIGR_Register; + -- The TRCEVENTCTL0R controls the tracing of events in the trace stream. + -- The events also drive the ETM-Teal external outputs. + TRCEVENTCTL0R : aliased TRCEVENTCTL0R_Register; + -- The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + -- behave + TRCEVENTCTL1R : aliased TRCEVENTCTL1R_Register; + -- The TRCSTALLCTLR enables ETM-Teal to stall the processor if the + -- ETM-Teal FIFO goes over the programmed level to minimize risk of + -- overflow + TRCSTALLCTLR : aliased TRCSTALLCTLR_Register; + -- The TRCTSCTLR controls the insertion of global timestamps into the + -- trace stream. A timestamp is always inserted into the instruction + -- trace stream + TRCTSCTLR : aliased TRCTSCTLR_Register; + -- The TRCSYNCPR specifies the period of trace synchronization of the + -- trace streams. TRCSYNCPR defines a number of bytes of trace between + -- requests for trace synchronization. This value is always a power of + -- two + TRCSYNCPR : aliased TRCSYNCPR_Register; + -- The TRCCCCTLR sets the threshold value for instruction trace cycle + -- counting. The threshold represents the minimum interval between cycle + -- count trace packets + TRCCCCTLR : aliased TRCCCCTLR_Register; + -- The TRCVICTLR controls instruction trace filtering + TRCVICTLR : aliased TRCVICTLR_Register; + -- The TRCCNTRLDVR defines the reload value for the reduced function + -- counter + TRCCNTRLDVR0 : aliased TRCCNTRLDVR0_Register; + -- TRCIDR8 + TRCIDR8 : aliased HAL.UInt32; + -- TRCIDR9 + TRCIDR9 : aliased HAL.UInt32; + -- TRCIDR10 + TRCIDR10 : aliased HAL.UInt32; + -- TRCIDR11 + TRCIDR11 : aliased HAL.UInt32; + -- TRCIDR12 + TRCIDR12 : aliased HAL.UInt32; + -- TRCIDR13 + TRCIDR13 : aliased HAL.UInt32; + -- The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + -- features, and enables any features that are provided + TRCIMSPEC : aliased TRCIMSPEC_Register; + -- TRCIDR0 + TRCIDR0 : aliased TRCIDR0_Register; + -- TRCIDR1 + TRCIDR1 : aliased TRCIDR1_Register; + -- TRCIDR2 + TRCIDR2 : aliased TRCIDR2_Register; + -- TRCIDR3 + TRCIDR3 : aliased TRCIDR3_Register; + -- TRCIDR4 + TRCIDR4 : aliased TRCIDR4_Register; + -- TRCIDR5 + TRCIDR5 : aliased TRCIDR5_Register; + -- TRCIDR6 + TRCIDR6 : aliased HAL.UInt32; + -- TRCIDR7 + TRCIDR7 : aliased HAL.UInt32; + -- The TRCRSCTLR controls the trace resources + TRCRSCTLR2 : aliased TRCRSCTLR_Register; + -- The TRCRSCTLR controls the trace resources + TRCRSCTLR3 : aliased TRCRSCTLR_Register; + -- Controls the corresponding single-shot comparator resource + TRCSSCSR : aliased TRCSSCSR_Register; + -- Selects the PE comparator inputs for Single-shot control + TRCSSPCICR : aliased TRCSSPCICR_Register; + -- Requests the system to provide power to the trace unit + TRCPDCR : aliased TRCPDCR_Register; + -- Returns the following information about the trace unit: - OS Lock + -- status. - Core power domain status. - Power interruption status + TRCPDSR : aliased TRCPDSR_Register; + -- Trace Integration ATB Identification Register + TRCITATBIDR : aliased TRCITATBIDR_Register; + -- Trace Integration Instruction ATB In Register + TRCITIATBINR : aliased TRCITIATBINR_Register; + -- Trace Integration Instruction ATB Out Register + TRCITIATBOUTR : aliased TRCITIATBOUTR_Register; + -- Claim Tag Set Register + TRCCLAIMSET : aliased TRCCLAIMSET_Register; + -- Claim Tag Clear Register + TRCCLAIMCLR : aliased TRCCLAIMCLR_Register; + -- Returns the level of tracing that the trace unit can support + TRCAUTHSTATUS : aliased TRCAUTHSTATUS_Register; + -- TRCDEVARCH + TRCDEVARCH : aliased TRCDEVARCH_Register; + -- TRCDEVID + TRCDEVID : aliased HAL.UInt32; + -- TRCDEVTYPE + TRCDEVTYPE : aliased TRCDEVTYPE_Register; + -- TRCPIDR4 + TRCPIDR4 : aliased TRCPIDR4_Register; + -- TRCPIDR5 + TRCPIDR5 : aliased HAL.UInt32; + -- TRCPIDR6 + TRCPIDR6 : aliased HAL.UInt32; + -- TRCPIDR7 + TRCPIDR7 : aliased HAL.UInt32; + -- TRCPIDR0 + TRCPIDR0 : aliased TRCPIDR0_Register; + -- TRCPIDR1 + TRCPIDR1 : aliased TRCPIDR1_Register; + -- TRCPIDR2 + TRCPIDR2 : aliased TRCPIDR2_Register; + -- TRCPIDR3 + TRCPIDR3 : aliased TRCPIDR3_Register; + -- TRCCIDR0 + TRCCIDR0 : aliased TRCCIDR0_Register; + -- TRCCIDR1 + TRCCIDR1 : aliased TRCCIDR1_Register; + -- TRCCIDR2 + TRCCIDR2 : aliased TRCCIDR2_Register; + -- TRCCIDR3 + TRCCIDR3 : aliased TRCCIDR3_Register; + -- CTI Control Register + CTICONTROL : aliased CTICONTROL_Register; + -- CTI Interrupt Acknowledge Register + CTIINTACK : aliased CTIINTACK_Register; + -- CTI Application Trigger Set Register + CTIAPPSET : aliased CTIAPPSET_Register; + -- CTI Application Trigger Clear Register + CTIAPPCLEAR : aliased CTIAPPCLEAR_Register; + -- CTI Application Pulse Register + CTIAPPPULSE : aliased CTIAPPPULSE_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN0 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN1 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN2 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN3 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN4 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN5 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN6 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIINEN7 : aliased CTIINEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN0 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN1 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN2 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN3 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN4 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN5 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN6 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTIOUTEN7 : aliased CTIOUTEN_Register; + -- CTI Trigger to Channel Enable Registers + CTITRIGINSTATUS : aliased CTITRIGINSTATUS_Register; + -- CTI Trigger In Status Register + CTITRIGOUTSTATUS : aliased CTITRIGOUTSTATUS_Register; + -- CTI Channel In Status Register + CTICHINSTATUS : aliased CTICHINSTATUS_Register; + -- Enable CTI Channel Gate register + CTIGATE : aliased CTIGATE_Register; + -- External Multiplexer Control register + ASICCTL : aliased HAL.UInt32; + -- Integration Test Channel Output register + ITCHOUT : aliased ITCHOUT_Register; + -- Integration Test Trigger Output register + ITTRIGOUT : aliased ITTRIGOUT_Register; + -- Integration Test Channel Input register + ITCHIN : aliased ITCHIN_Register; + -- Integration Mode Control register + ITCTRL : aliased ITCTRL_Register; + -- Device Architecture register + DEVARCH : aliased DEVARCH_Register; + -- Device Configuration register + DEVID : aliased DEVID_Register; + -- Device Type Identifier register + DEVTYPE : aliased DEVTYPE_Register; + -- CoreSight Peripheral ID4 + PIDR4 : aliased PIDR4_Register; + -- CoreSight Peripheral ID5 + PIDR5 : aliased HAL.UInt32; + -- CoreSight Peripheral ID6 + PIDR6 : aliased HAL.UInt32; + -- CoreSight Peripheral ID7 + PIDR7 : aliased HAL.UInt32; + -- CoreSight Peripheral ID0 + PIDR0 : aliased PIDR0_Register; + -- CoreSight Peripheral ID1 + PIDR1 : aliased PIDR1_Register; + -- CoreSight Peripheral ID2 + PIDR2 : aliased PIDR2_Register; + -- CoreSight Peripheral ID3 + PIDR3 : aliased PIDR3_Register; + -- CoreSight Component ID0 + CIDR0 : aliased CIDR0_Register; + -- CoreSight Component ID1 + CIDR1 : aliased CIDR1_Register; + -- CoreSight Component ID2 + CIDR2 : aliased CIDR2_Register; + -- CoreSight Component ID3 + CIDR3 : aliased CIDR3_Register; + end record + with Volatile; + + for PPB_NS_Peripheral use record + ITM_STIM0 at 16#0# range 0 .. 31; + ITM_STIM1 at 16#4# range 0 .. 31; + ITM_STIM2 at 16#8# range 0 .. 31; + ITM_STIM3 at 16#C# range 0 .. 31; + ITM_STIM4 at 16#10# range 0 .. 31; + ITM_STIM5 at 16#14# range 0 .. 31; + ITM_STIM6 at 16#18# range 0 .. 31; + ITM_STIM7 at 16#1C# range 0 .. 31; + ITM_STIM8 at 16#20# range 0 .. 31; + ITM_STIM9 at 16#24# range 0 .. 31; + ITM_STIM10 at 16#28# range 0 .. 31; + ITM_STIM11 at 16#2C# range 0 .. 31; + ITM_STIM12 at 16#30# range 0 .. 31; + ITM_STIM13 at 16#34# range 0 .. 31; + ITM_STIM14 at 16#38# range 0 .. 31; + ITM_STIM15 at 16#3C# range 0 .. 31; + ITM_STIM16 at 16#40# range 0 .. 31; + ITM_STIM17 at 16#44# range 0 .. 31; + ITM_STIM18 at 16#48# range 0 .. 31; + ITM_STIM19 at 16#4C# range 0 .. 31; + ITM_STIM20 at 16#50# range 0 .. 31; + ITM_STIM21 at 16#54# range 0 .. 31; + ITM_STIM22 at 16#58# range 0 .. 31; + ITM_STIM23 at 16#5C# range 0 .. 31; + ITM_STIM24 at 16#60# range 0 .. 31; + ITM_STIM25 at 16#64# range 0 .. 31; + ITM_STIM26 at 16#68# range 0 .. 31; + ITM_STIM27 at 16#6C# range 0 .. 31; + ITM_STIM28 at 16#70# range 0 .. 31; + ITM_STIM29 at 16#74# range 0 .. 31; + ITM_STIM30 at 16#78# range 0 .. 31; + ITM_STIM31 at 16#7C# range 0 .. 31; + ITM_TER0 at 16#E00# range 0 .. 31; + ITM_TPR at 16#E40# range 0 .. 31; + ITM_TCR at 16#E80# range 0 .. 31; + INT_ATREADY at 16#EF0# range 0 .. 31; + INT_ATVALID at 16#EF8# range 0 .. 31; + ITM_ITCTRL at 16#F00# range 0 .. 31; + ITM_DEVARCH at 16#FBC# range 0 .. 31; + ITM_DEVTYPE at 16#FCC# range 0 .. 31; + ITM_PIDR4 at 16#FD0# range 0 .. 31; + ITM_PIDR5 at 16#FD4# range 0 .. 31; + ITM_PIDR6 at 16#FD8# range 0 .. 31; + ITM_PIDR7 at 16#FDC# range 0 .. 31; + ITM_PIDR0 at 16#FE0# range 0 .. 31; + ITM_PIDR1 at 16#FE4# range 0 .. 31; + ITM_PIDR2 at 16#FE8# range 0 .. 31; + ITM_PIDR3 at 16#FEC# range 0 .. 31; + ITM_CIDR0 at 16#FF0# range 0 .. 31; + ITM_CIDR1 at 16#FF4# range 0 .. 31; + ITM_CIDR2 at 16#FF8# range 0 .. 31; + ITM_CIDR3 at 16#FFC# range 0 .. 31; + DWT_CTRL at 16#1000# range 0 .. 31; + DWT_CYCCNT at 16#1004# range 0 .. 31; + DWT_EXCCNT at 16#100C# range 0 .. 31; + DWT_LSUCNT at 16#1014# range 0 .. 31; + DWT_FOLDCNT at 16#1018# range 0 .. 31; + DWT_COMP0 at 16#1020# range 0 .. 31; + DWT_FUNCTION0 at 16#1028# range 0 .. 31; + DWT_COMP1 at 16#1030# range 0 .. 31; + DWT_FUNCTION1 at 16#1038# range 0 .. 31; + DWT_COMP2 at 16#1040# range 0 .. 31; + DWT_FUNCTION2 at 16#1048# range 0 .. 31; + DWT_COMP3 at 16#1050# range 0 .. 31; + DWT_FUNCTION3 at 16#1058# range 0 .. 31; + DWT_DEVARCH at 16#1FBC# range 0 .. 31; + DWT_DEVTYPE at 16#1FCC# range 0 .. 31; + DWT_PIDR4 at 16#1FD0# range 0 .. 31; + DWT_PIDR5 at 16#1FD4# range 0 .. 31; + DWT_PIDR6 at 16#1FD8# range 0 .. 31; + DWT_PIDR7 at 16#1FDC# range 0 .. 31; + DWT_PIDR0 at 16#1FE0# range 0 .. 31; + DWT_PIDR1 at 16#1FE4# range 0 .. 31; + DWT_PIDR2 at 16#1FE8# range 0 .. 31; + DWT_PIDR3 at 16#1FEC# range 0 .. 31; + DWT_CIDR0 at 16#1FF0# range 0 .. 31; + DWT_CIDR1 at 16#1FF4# range 0 .. 31; + DWT_CIDR2 at 16#1FF8# range 0 .. 31; + DWT_CIDR3 at 16#1FFC# range 0 .. 31; + FP_CTRL at 16#2000# range 0 .. 31; + FP_REMAP at 16#2004# range 0 .. 31; + FP_COMP0 at 16#2008# range 0 .. 31; + FP_COMP1 at 16#200C# range 0 .. 31; + FP_COMP2 at 16#2010# range 0 .. 31; + FP_COMP3 at 16#2014# range 0 .. 31; + FP_COMP4 at 16#2018# range 0 .. 31; + FP_COMP5 at 16#201C# range 0 .. 31; + FP_COMP6 at 16#2020# range 0 .. 31; + FP_COMP7 at 16#2024# range 0 .. 31; + FP_DEVARCH at 16#2FBC# range 0 .. 31; + FP_DEVTYPE at 16#2FCC# range 0 .. 31; + FP_PIDR4 at 16#2FD0# range 0 .. 31; + FP_PIDR5 at 16#2FD4# range 0 .. 31; + FP_PIDR6 at 16#2FD8# range 0 .. 31; + FP_PIDR7 at 16#2FDC# range 0 .. 31; + FP_PIDR0 at 16#2FE0# range 0 .. 31; + FP_PIDR1 at 16#2FE4# range 0 .. 31; + FP_PIDR2 at 16#2FE8# range 0 .. 31; + FP_PIDR3 at 16#2FEC# range 0 .. 31; + FP_CIDR0 at 16#2FF0# range 0 .. 31; + FP_CIDR1 at 16#2FF4# range 0 .. 31; + FP_CIDR2 at 16#2FF8# range 0 .. 31; + FP_CIDR3 at 16#2FFC# range 0 .. 31; + ICTR at 16#E004# range 0 .. 31; + ACTLR at 16#E008# range 0 .. 31; + SYST_CSR at 16#E010# range 0 .. 31; + SYST_RVR at 16#E014# range 0 .. 31; + SYST_CVR at 16#E018# range 0 .. 31; + SYST_CALIB at 16#E01C# range 0 .. 31; + NVIC_ISER0 at 16#E100# range 0 .. 31; + NVIC_ISER1 at 16#E104# range 0 .. 31; + NVIC_ICER0 at 16#E180# range 0 .. 31; + NVIC_ICER1 at 16#E184# range 0 .. 31; + NVIC_ISPR0 at 16#E200# range 0 .. 31; + NVIC_ISPR1 at 16#E204# range 0 .. 31; + NVIC_ICPR0 at 16#E280# range 0 .. 31; + NVIC_ICPR1 at 16#E284# range 0 .. 31; + NVIC_IABR0 at 16#E300# range 0 .. 31; + NVIC_IABR1 at 16#E304# range 0 .. 31; + NVIC_ITNS0 at 16#E380# range 0 .. 31; + NVIC_ITNS1 at 16#E384# range 0 .. 31; + NVIC_IPR0 at 16#E400# range 0 .. 31; + NVIC_IPR1 at 16#E404# range 0 .. 31; + NVIC_IPR2 at 16#E408# range 0 .. 31; + NVIC_IPR3 at 16#E40C# range 0 .. 31; + NVIC_IPR4 at 16#E410# range 0 .. 31; + NVIC_IPR5 at 16#E414# range 0 .. 31; + NVIC_IPR6 at 16#E418# range 0 .. 31; + NVIC_IPR7 at 16#E41C# range 0 .. 31; + NVIC_IPR8 at 16#E420# range 0 .. 31; + NVIC_IPR9 at 16#E424# range 0 .. 31; + NVIC_IPR10 at 16#E428# range 0 .. 31; + NVIC_IPR11 at 16#E42C# range 0 .. 31; + NVIC_IPR12 at 16#E430# range 0 .. 31; + NVIC_IPR13 at 16#E434# range 0 .. 31; + NVIC_IPR14 at 16#E438# range 0 .. 31; + NVIC_IPR15 at 16#E43C# range 0 .. 31; + CPUID at 16#ED00# range 0 .. 31; + ICSR at 16#ED04# range 0 .. 31; + VTOR at 16#ED08# range 0 .. 31; + AIRCR at 16#ED0C# range 0 .. 31; + SCR at 16#ED10# range 0 .. 31; + CCR at 16#ED14# range 0 .. 31; + SHPR1 at 16#ED18# range 0 .. 31; + SHPR2 at 16#ED1C# range 0 .. 31; + SHPR3 at 16#ED20# range 0 .. 31; + SHCSR at 16#ED24# range 0 .. 31; + CFSR at 16#ED28# range 0 .. 31; + HFSR at 16#ED2C# range 0 .. 31; + DFSR at 16#ED30# range 0 .. 31; + MMFAR at 16#ED34# range 0 .. 31; + BFAR at 16#ED38# range 0 .. 31; + ID_PFR0 at 16#ED40# range 0 .. 31; + ID_PFR1 at 16#ED44# range 0 .. 31; + ID_DFR0 at 16#ED48# range 0 .. 31; + ID_AFR0 at 16#ED4C# range 0 .. 31; + ID_MMFR0 at 16#ED50# range 0 .. 31; + ID_MMFR1 at 16#ED54# range 0 .. 31; + ID_MMFR2 at 16#ED58# range 0 .. 31; + ID_MMFR3 at 16#ED5C# range 0 .. 31; + ID_ISAR0 at 16#ED60# range 0 .. 31; + ID_ISAR1 at 16#ED64# range 0 .. 31; + ID_ISAR2 at 16#ED68# range 0 .. 31; + ID_ISAR3 at 16#ED6C# range 0 .. 31; + ID_ISAR4 at 16#ED70# range 0 .. 31; + ID_ISAR5 at 16#ED74# range 0 .. 31; + CTR at 16#ED7C# range 0 .. 31; + CPACR at 16#ED88# range 0 .. 31; + NSACR at 16#ED8C# range 0 .. 31; + MPU_TYPE at 16#ED90# range 0 .. 31; + MPU_CTRL at 16#ED94# range 0 .. 31; + MPU_RNR at 16#ED98# range 0 .. 31; + MPU_RBAR at 16#ED9C# range 0 .. 31; + MPU_RLAR at 16#EDA0# range 0 .. 31; + MPU_RBAR_A1 at 16#EDA4# range 0 .. 31; + MPU_RLAR_A1 at 16#EDA8# range 0 .. 31; + MPU_RBAR_A2 at 16#EDAC# range 0 .. 31; + MPU_RLAR_A2 at 16#EDB0# range 0 .. 31; + MPU_RBAR_A3 at 16#EDB4# range 0 .. 31; + MPU_RLAR_A3 at 16#EDB8# range 0 .. 31; + MPU_MAIR0 at 16#EDC0# range 0 .. 31; + MPU_MAIR1 at 16#EDC4# range 0 .. 31; + SAU_CTRL at 16#EDD0# range 0 .. 31; + SAU_TYPE at 16#EDD4# range 0 .. 31; + SAU_RNR at 16#EDD8# range 0 .. 31; + SAU_RBAR at 16#EDDC# range 0 .. 31; + SAU_RLAR at 16#EDE0# range 0 .. 31; + SFSR at 16#EDE4# range 0 .. 31; + SFAR at 16#EDE8# range 0 .. 31; + DHCSR at 16#EDF0# range 0 .. 31; + DCRSR at 16#EDF4# range 0 .. 31; + DCRDR at 16#EDF8# range 0 .. 31; + DEMCR at 16#EDFC# range 0 .. 31; + DSCSR at 16#EE08# range 0 .. 31; + STIR at 16#EF00# range 0 .. 31; + FPCCR at 16#EF34# range 0 .. 31; + FPCAR at 16#EF38# range 0 .. 31; + FPDSCR at 16#EF3C# range 0 .. 31; + MVFR0 at 16#EF40# range 0 .. 31; + MVFR1 at 16#EF44# range 0 .. 31; + MVFR2 at 16#EF48# range 0 .. 31; + DDEVARCH at 16#EFBC# range 0 .. 31; + DDEVTYPE at 16#EFCC# range 0 .. 31; + DPIDR4 at 16#EFD0# range 0 .. 31; + DPIDR5 at 16#EFD4# range 0 .. 31; + DPIDR6 at 16#EFD8# range 0 .. 31; + DPIDR7 at 16#EFDC# range 0 .. 31; + DPIDR0 at 16#EFE0# range 0 .. 31; + DPIDR1 at 16#EFE4# range 0 .. 31; + DPIDR2 at 16#EFE8# range 0 .. 31; + DPIDR3 at 16#EFEC# range 0 .. 31; + DCIDR0 at 16#EFF0# range 0 .. 31; + DCIDR1 at 16#EFF4# range 0 .. 31; + DCIDR2 at 16#EFF8# range 0 .. 31; + DCIDR3 at 16#EFFC# range 0 .. 31; + TRCPRGCTLR at 16#41004# range 0 .. 31; + TRCSTATR at 16#4100C# range 0 .. 31; + TRCCONFIGR at 16#41010# range 0 .. 31; + TRCEVENTCTL0R at 16#41020# range 0 .. 31; + TRCEVENTCTL1R at 16#41024# range 0 .. 31; + TRCSTALLCTLR at 16#4102C# range 0 .. 31; + TRCTSCTLR at 16#41030# range 0 .. 31; + TRCSYNCPR at 16#41034# range 0 .. 31; + TRCCCCTLR at 16#41038# range 0 .. 31; + TRCVICTLR at 16#41080# range 0 .. 31; + TRCCNTRLDVR0 at 16#41140# range 0 .. 31; + TRCIDR8 at 16#41180# range 0 .. 31; + TRCIDR9 at 16#41184# range 0 .. 31; + TRCIDR10 at 16#41188# range 0 .. 31; + TRCIDR11 at 16#4118C# range 0 .. 31; + TRCIDR12 at 16#41190# range 0 .. 31; + TRCIDR13 at 16#41194# range 0 .. 31; + TRCIMSPEC at 16#411C0# range 0 .. 31; + TRCIDR0 at 16#411E0# range 0 .. 31; + TRCIDR1 at 16#411E4# range 0 .. 31; + TRCIDR2 at 16#411E8# range 0 .. 31; + TRCIDR3 at 16#411EC# range 0 .. 31; + TRCIDR4 at 16#411F0# range 0 .. 31; + TRCIDR5 at 16#411F4# range 0 .. 31; + TRCIDR6 at 16#411F8# range 0 .. 31; + TRCIDR7 at 16#411FC# range 0 .. 31; + TRCRSCTLR2 at 16#41208# range 0 .. 31; + TRCRSCTLR3 at 16#4120C# range 0 .. 31; + TRCSSCSR at 16#412A0# range 0 .. 31; + TRCSSPCICR at 16#412C0# range 0 .. 31; + TRCPDCR at 16#41310# range 0 .. 31; + TRCPDSR at 16#41314# range 0 .. 31; + TRCITATBIDR at 16#41EE4# range 0 .. 31; + TRCITIATBINR at 16#41EF4# range 0 .. 31; + TRCITIATBOUTR at 16#41EFC# range 0 .. 31; + TRCCLAIMSET at 16#41FA0# range 0 .. 31; + TRCCLAIMCLR at 16#41FA4# range 0 .. 31; + TRCAUTHSTATUS at 16#41FB8# range 0 .. 31; + TRCDEVARCH at 16#41FBC# range 0 .. 31; + TRCDEVID at 16#41FC8# range 0 .. 31; + TRCDEVTYPE at 16#41FCC# range 0 .. 31; + TRCPIDR4 at 16#41FD0# range 0 .. 31; + TRCPIDR5 at 16#41FD4# range 0 .. 31; + TRCPIDR6 at 16#41FD8# range 0 .. 31; + TRCPIDR7 at 16#41FDC# range 0 .. 31; + TRCPIDR0 at 16#41FE0# range 0 .. 31; + TRCPIDR1 at 16#41FE4# range 0 .. 31; + TRCPIDR2 at 16#41FE8# range 0 .. 31; + TRCPIDR3 at 16#41FEC# range 0 .. 31; + TRCCIDR0 at 16#41FF0# range 0 .. 31; + TRCCIDR1 at 16#41FF4# range 0 .. 31; + TRCCIDR2 at 16#41FF8# range 0 .. 31; + TRCCIDR3 at 16#41FFC# range 0 .. 31; + CTICONTROL at 16#42000# range 0 .. 31; + CTIINTACK at 16#42010# range 0 .. 31; + CTIAPPSET at 16#42014# range 0 .. 31; + CTIAPPCLEAR at 16#42018# range 0 .. 31; + CTIAPPPULSE at 16#4201C# range 0 .. 31; + CTIINEN0 at 16#42020# range 0 .. 31; + CTIINEN1 at 16#42024# range 0 .. 31; + CTIINEN2 at 16#42028# range 0 .. 31; + CTIINEN3 at 16#4202C# range 0 .. 31; + CTIINEN4 at 16#42030# range 0 .. 31; + CTIINEN5 at 16#42034# range 0 .. 31; + CTIINEN6 at 16#42038# range 0 .. 31; + CTIINEN7 at 16#4203C# range 0 .. 31; + CTIOUTEN0 at 16#420A0# range 0 .. 31; + CTIOUTEN1 at 16#420A4# range 0 .. 31; + CTIOUTEN2 at 16#420A8# range 0 .. 31; + CTIOUTEN3 at 16#420AC# range 0 .. 31; + CTIOUTEN4 at 16#420B0# range 0 .. 31; + CTIOUTEN5 at 16#420B4# range 0 .. 31; + CTIOUTEN6 at 16#420B8# range 0 .. 31; + CTIOUTEN7 at 16#420BC# range 0 .. 31; + CTITRIGINSTATUS at 16#42130# range 0 .. 31; + CTITRIGOUTSTATUS at 16#42134# range 0 .. 31; + CTICHINSTATUS at 16#42138# range 0 .. 31; + CTIGATE at 16#42140# range 0 .. 31; + ASICCTL at 16#42144# range 0 .. 31; + ITCHOUT at 16#42EE4# range 0 .. 31; + ITTRIGOUT at 16#42EE8# range 0 .. 31; + ITCHIN at 16#42EF4# range 0 .. 31; + ITCTRL at 16#42F00# range 0 .. 31; + DEVARCH at 16#42FBC# range 0 .. 31; + DEVID at 16#42FC8# range 0 .. 31; + DEVTYPE at 16#42FCC# range 0 .. 31; + PIDR4 at 16#42FD0# range 0 .. 31; + PIDR5 at 16#42FD4# range 0 .. 31; + PIDR6 at 16#42FD8# range 0 .. 31; + PIDR7 at 16#42FDC# range 0 .. 31; + PIDR0 at 16#42FE0# range 0 .. 31; + PIDR1 at 16#42FE4# range 0 .. 31; + PIDR2 at 16#42FE8# range 0 .. 31; + PIDR3 at 16#42FEC# range 0 .. 31; + CIDR0 at 16#42FF0# range 0 .. 31; + CIDR1 at 16#42FF4# range 0 .. 31; + CIDR2 at 16#42FF8# range 0 .. 31; + CIDR3 at 16#42FFC# range 0 .. 31; + end record; + + -- TEAL registers accessible through the debug interface + PPB_NS_Periph : aliased PPB_NS_Peripheral + with Import, Address => PPB_NS_Base; + +end RP2350_SVD.PPB_NS; diff --git a/src/svd/rp2350_svd-psm.ads b/src/svd/rp2350_svd-psm.ads new file mode 100644 index 0000000..5c8ab6a --- /dev/null +++ b/src/svd/rp2350_svd-psm.ads @@ -0,0 +1,424 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.PSM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- FRCE_ON_SRAM array + type FRCE_ON_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for FRCE_ON_SRAM + type FRCE_ON_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SRAM as a value + Val : HAL.UInt10; + when True => + -- SRAM as an array + Arr : FRCE_ON_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for FRCE_ON_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- FRCE_ON_PROC array + type FRCE_ON_PROC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for FRCE_ON_PROC + type FRCE_ON_PROC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PROC as a value + Val : HAL.UInt2; + when True => + -- PROC as an array + Arr : FRCE_ON_PROC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for FRCE_ON_PROC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Force block out of reset (i.e. power it on) + type FRCE_ON_Register is record + PROC_COLD : Boolean := False; + OTP : Boolean := False; + ROSC : Boolean := False; + XOSC : Boolean := False; + RESETS : Boolean := False; + CLOCKS : Boolean := False; + PSM_READY : Boolean := False; + BUSFABRIC : Boolean := False; + ROM : Boolean := False; + BOOTRAM : Boolean := False; + SRAM : FRCE_ON_SRAM_Field := + (As_Array => False, Val => 16#0#); + XIP : Boolean := False; + SIO : Boolean := False; + ACCESSCTRL : Boolean := False; + PROC : FRCE_ON_PROC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRCE_ON_Register use record + PROC_COLD at 0 range 0 .. 0; + OTP at 0 range 1 .. 1; + ROSC at 0 range 2 .. 2; + XOSC at 0 range 3 .. 3; + RESETS at 0 range 4 .. 4; + CLOCKS at 0 range 5 .. 5; + PSM_READY at 0 range 6 .. 6; + BUSFABRIC at 0 range 7 .. 7; + ROM at 0 range 8 .. 8; + BOOTRAM at 0 range 9 .. 9; + SRAM at 0 range 10 .. 19; + XIP at 0 range 20 .. 20; + SIO at 0 range 21 .. 21; + ACCESSCTRL at 0 range 22 .. 22; + PROC at 0 range 23 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- FRCE_OFF_SRAM array + type FRCE_OFF_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for FRCE_OFF_SRAM + type FRCE_OFF_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SRAM as a value + Val : HAL.UInt10; + when True => + -- SRAM as an array + Arr : FRCE_OFF_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for FRCE_OFF_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- FRCE_OFF_PROC array + type FRCE_OFF_PROC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for FRCE_OFF_PROC + type FRCE_OFF_PROC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PROC as a value + Val : HAL.UInt2; + when True => + -- PROC as an array + Arr : FRCE_OFF_PROC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for FRCE_OFF_PROC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Force into reset (i.e. power it off) + type FRCE_OFF_Register is record + PROC_COLD : Boolean := False; + OTP : Boolean := False; + ROSC : Boolean := False; + XOSC : Boolean := False; + RESETS : Boolean := False; + CLOCKS : Boolean := False; + PSM_READY : Boolean := False; + BUSFABRIC : Boolean := False; + ROM : Boolean := False; + BOOTRAM : Boolean := False; + SRAM : FRCE_OFF_SRAM_Field := + (As_Array => False, Val => 16#0#); + XIP : Boolean := False; + SIO : Boolean := False; + ACCESSCTRL : Boolean := False; + PROC : FRCE_OFF_PROC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FRCE_OFF_Register use record + PROC_COLD at 0 range 0 .. 0; + OTP at 0 range 1 .. 1; + ROSC at 0 range 2 .. 2; + XOSC at 0 range 3 .. 3; + RESETS at 0 range 4 .. 4; + CLOCKS at 0 range 5 .. 5; + PSM_READY at 0 range 6 .. 6; + BUSFABRIC at 0 range 7 .. 7; + ROM at 0 range 8 .. 8; + BOOTRAM at 0 range 9 .. 9; + SRAM at 0 range 10 .. 19; + XIP at 0 range 20 .. 20; + SIO at 0 range 21 .. 21; + ACCESSCTRL at 0 range 22 .. 22; + PROC at 0 range 23 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- WDSEL_SRAM array + type WDSEL_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for WDSEL_SRAM + type WDSEL_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SRAM as a value + Val : HAL.UInt10; + when True => + -- SRAM as an array + Arr : WDSEL_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for WDSEL_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- WDSEL_PROC array + type WDSEL_PROC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WDSEL_PROC + type WDSEL_PROC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PROC as a value + Val : HAL.UInt2; + when True => + -- PROC as an array + Arr : WDSEL_PROC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WDSEL_PROC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Set to 1 if the watchdog should reset this + type WDSEL_Register is record + PROC_COLD : Boolean := False; + OTP : Boolean := False; + ROSC : Boolean := False; + XOSC : Boolean := False; + RESETS : Boolean := False; + CLOCKS : Boolean := False; + PSM_READY : Boolean := False; + BUSFABRIC : Boolean := False; + ROM : Boolean := False; + BOOTRAM : Boolean := False; + SRAM : WDSEL_SRAM_Field := (As_Array => False, Val => 16#0#); + XIP : Boolean := False; + SIO : Boolean := False; + ACCESSCTRL : Boolean := False; + PROC : WDSEL_PROC_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WDSEL_Register use record + PROC_COLD at 0 range 0 .. 0; + OTP at 0 range 1 .. 1; + ROSC at 0 range 2 .. 2; + XOSC at 0 range 3 .. 3; + RESETS at 0 range 4 .. 4; + CLOCKS at 0 range 5 .. 5; + PSM_READY at 0 range 6 .. 6; + BUSFABRIC at 0 range 7 .. 7; + ROM at 0 range 8 .. 8; + BOOTRAM at 0 range 9 .. 9; + SRAM at 0 range 10 .. 19; + XIP at 0 range 20 .. 20; + SIO at 0 range 21 .. 21; + ACCESSCTRL at 0 range 22 .. 22; + PROC at 0 range 23 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- DONE_SRAM array + type DONE_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for DONE_SRAM + type DONE_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SRAM as a value + Val : HAL.UInt10; + when True => + -- SRAM as an array + Arr : DONE_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for DONE_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- DONE_PROC array + type DONE_PROC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DONE_PROC + type DONE_PROC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PROC as a value + Val : HAL.UInt2; + when True => + -- PROC as an array + Arr : DONE_PROC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DONE_PROC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Is the subsystem ready? + type DONE_Register is record + -- Read-only. + PROC_COLD : Boolean; + -- Read-only. + OTP : Boolean; + -- Read-only. + ROSC : Boolean; + -- Read-only. + XOSC : Boolean; + -- Read-only. + RESETS : Boolean; + -- Read-only. + CLOCKS : Boolean; + -- Read-only. + PSM_READY : Boolean; + -- Read-only. + BUSFABRIC : Boolean; + -- Read-only. + ROM : Boolean; + -- Read-only. + BOOTRAM : Boolean; + -- Read-only. + SRAM : DONE_SRAM_Field; + -- Read-only. + XIP : Boolean; + -- Read-only. + SIO : Boolean; + -- Read-only. + ACCESSCTRL : Boolean; + -- Read-only. + PROC : DONE_PROC_Field; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DONE_Register use record + PROC_COLD at 0 range 0 .. 0; + OTP at 0 range 1 .. 1; + ROSC at 0 range 2 .. 2; + XOSC at 0 range 3 .. 3; + RESETS at 0 range 4 .. 4; + CLOCKS at 0 range 5 .. 5; + PSM_READY at 0 range 6 .. 6; + BUSFABRIC at 0 range 7 .. 7; + ROM at 0 range 8 .. 8; + BOOTRAM at 0 range 9 .. 9; + SRAM at 0 range 10 .. 19; + XIP at 0 range 20 .. 20; + SIO at 0 range 21 .. 21; + ACCESSCTRL at 0 range 22 .. 22; + PROC at 0 range 23 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type PSM_Peripheral is record + -- Force block out of reset (i.e. power it on) + FRCE_ON : aliased FRCE_ON_Register; + -- Force into reset (i.e. power it off) + FRCE_OFF : aliased FRCE_OFF_Register; + -- Set to 1 if the watchdog should reset this + WDSEL : aliased WDSEL_Register; + -- Is the subsystem ready? + DONE : aliased DONE_Register; + end record + with Volatile; + + for PSM_Peripheral use record + FRCE_ON at 16#0# range 0 .. 31; + FRCE_OFF at 16#4# range 0 .. 31; + WDSEL at 16#8# range 0 .. 31; + DONE at 16#C# range 0 .. 31; + end record; + + PSM_Periph : aliased PSM_Peripheral + with Import, Address => PSM_Base; + +end RP2350_SVD.PSM; diff --git a/src/svd/rp2350_svd-pwm.ads b/src/svd/rp2350_svd-pwm.ads new file mode 100644 index 0000000..9daf0be --- /dev/null +++ b/src/svd/rp2350_svd-pwm.ads @@ -0,0 +1,2036 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Simple PWM +package RP2350_SVD.PWM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + type CH0_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH0_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH0_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH0_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH0_DIV_FRAC_Field is HAL.UInt4; + subtype CH0_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH0_DIV_Register is record + FRAC : CH0_DIV_FRAC_Field := 16#0#; + INT : CH0_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH0_CTR_CH0_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH0_CTR_Register is record + CH0_CTR : CH0_CTR_CH0_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_CTR_Register use record + CH0_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH0_CC_A_Field is HAL.UInt16; + subtype CH0_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH0_CC_Register is record + A : CH0_CC_A_Field := 16#0#; + B : CH0_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH0_TOP_CH0_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH0_TOP_Register is record + CH0_TOP : CH0_TOP_CH0_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH0_TOP_Register use record + CH0_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH1_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH1_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH1_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH1_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH1_DIV_FRAC_Field is HAL.UInt4; + subtype CH1_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH1_DIV_Register is record + FRAC : CH1_DIV_FRAC_Field := 16#0#; + INT : CH1_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH1_CTR_CH1_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH1_CTR_Register is record + CH1_CTR : CH1_CTR_CH1_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_CTR_Register use record + CH1_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH1_CC_A_Field is HAL.UInt16; + subtype CH1_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH1_CC_Register is record + A : CH1_CC_A_Field := 16#0#; + B : CH1_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH1_TOP_CH1_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH1_TOP_Register is record + CH1_TOP : CH1_TOP_CH1_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH1_TOP_Register use record + CH1_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH2_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH2_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH2_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH2_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH2_DIV_FRAC_Field is HAL.UInt4; + subtype CH2_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH2_DIV_Register is record + FRAC : CH2_DIV_FRAC_Field := 16#0#; + INT : CH2_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH2_CTR_CH2_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH2_CTR_Register is record + CH2_CTR : CH2_CTR_CH2_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_CTR_Register use record + CH2_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH2_CC_A_Field is HAL.UInt16; + subtype CH2_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH2_CC_Register is record + A : CH2_CC_A_Field := 16#0#; + B : CH2_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH2_TOP_CH2_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH2_TOP_Register is record + CH2_TOP : CH2_TOP_CH2_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH2_TOP_Register use record + CH2_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH3_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH3_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH3_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH3_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH3_DIV_FRAC_Field is HAL.UInt4; + subtype CH3_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH3_DIV_Register is record + FRAC : CH3_DIV_FRAC_Field := 16#0#; + INT : CH3_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH3_CTR_CH3_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH3_CTR_Register is record + CH3_CTR : CH3_CTR_CH3_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_CTR_Register use record + CH3_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH3_CC_A_Field is HAL.UInt16; + subtype CH3_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH3_CC_Register is record + A : CH3_CC_A_Field := 16#0#; + B : CH3_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH3_TOP_CH3_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH3_TOP_Register is record + CH3_TOP : CH3_TOP_CH3_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH3_TOP_Register use record + CH3_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH4_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH4_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH4_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH4_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH4_DIV_FRAC_Field is HAL.UInt4; + subtype CH4_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH4_DIV_Register is record + FRAC : CH4_DIV_FRAC_Field := 16#0#; + INT : CH4_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH4_CTR_CH4_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH4_CTR_Register is record + CH4_CTR : CH4_CTR_CH4_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_CTR_Register use record + CH4_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH4_CC_A_Field is HAL.UInt16; + subtype CH4_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH4_CC_Register is record + A : CH4_CC_A_Field := 16#0#; + B : CH4_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH4_TOP_CH4_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH4_TOP_Register is record + CH4_TOP : CH4_TOP_CH4_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH4_TOP_Register use record + CH4_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH5_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH5_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH5_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH5_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH5_DIV_FRAC_Field is HAL.UInt4; + subtype CH5_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH5_DIV_Register is record + FRAC : CH5_DIV_FRAC_Field := 16#0#; + INT : CH5_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH5_CTR_CH5_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH5_CTR_Register is record + CH5_CTR : CH5_CTR_CH5_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_CTR_Register use record + CH5_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH5_CC_A_Field is HAL.UInt16; + subtype CH5_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH5_CC_Register is record + A : CH5_CC_A_Field := 16#0#; + B : CH5_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH5_TOP_CH5_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH5_TOP_Register is record + CH5_TOP : CH5_TOP_CH5_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH5_TOP_Register use record + CH5_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH6_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH6_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH6_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH6_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH6_DIV_FRAC_Field is HAL.UInt4; + subtype CH6_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH6_DIV_Register is record + FRAC : CH6_DIV_FRAC_Field := 16#0#; + INT : CH6_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH6_CTR_CH6_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH6_CTR_Register is record + CH6_CTR : CH6_CTR_CH6_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_CTR_Register use record + CH6_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH6_CC_A_Field is HAL.UInt16; + subtype CH6_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH6_CC_Register is record + A : CH6_CC_A_Field := 16#0#; + B : CH6_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH6_TOP_CH6_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH6_TOP_Register is record + CH6_TOP : CH6_TOP_CH6_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH6_TOP_Register use record + CH6_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH7_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH7_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH7_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH7_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH7_DIV_FRAC_Field is HAL.UInt4; + subtype CH7_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH7_DIV_Register is record + FRAC : CH7_DIV_FRAC_Field := 16#0#; + INT : CH7_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH7_CTR_CH7_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH7_CTR_Register is record + CH7_CTR : CH7_CTR_CH7_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_CTR_Register use record + CH7_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH7_CC_A_Field is HAL.UInt16; + subtype CH7_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH7_CC_Register is record + A : CH7_CC_A_Field := 16#0#; + B : CH7_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH7_TOP_CH7_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH7_TOP_Register is record + CH7_TOP : CH7_TOP_CH7_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH7_TOP_Register use record + CH7_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH8_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH8_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH8_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH8_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH8_DIV_FRAC_Field is HAL.UInt4; + subtype CH8_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH8_DIV_Register is record + FRAC : CH8_DIV_FRAC_Field := 16#0#; + INT : CH8_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH8_CTR_CH8_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH8_CTR_Register is record + CH8_CTR : CH8_CTR_CH8_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_CTR_Register use record + CH8_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH8_CC_A_Field is HAL.UInt16; + subtype CH8_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH8_CC_Register is record + A : CH8_CC_A_Field := 16#0#; + B : CH8_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH8_TOP_CH8_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH8_TOP_Register is record + CH8_TOP : CH8_TOP_CH8_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH8_TOP_Register use record + CH8_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH9_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH9_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH9_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH9_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH9_DIV_FRAC_Field is HAL.UInt4; + subtype CH9_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH9_DIV_Register is record + FRAC : CH9_DIV_FRAC_Field := 16#0#; + INT : CH9_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH9_CTR_CH9_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH9_CTR_Register is record + CH9_CTR : CH9_CTR_CH9_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_CTR_Register use record + CH9_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH9_CC_A_Field is HAL.UInt16; + subtype CH9_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH9_CC_Register is record + A : CH9_CC_A_Field := 16#0#; + B : CH9_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH9_TOP_CH9_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH9_TOP_Register is record + CH9_TOP : CH9_TOP_CH9_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH9_TOP_Register use record + CH9_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH10_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH10_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH10_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH10_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH10_DIV_FRAC_Field is HAL.UInt4; + subtype CH10_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH10_DIV_Register is record + FRAC : CH10_DIV_FRAC_Field := 16#0#; + INT : CH10_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH10_CTR_CH10_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH10_CTR_Register is record + CH10_CTR : CH10_CTR_CH10_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_CTR_Register use record + CH10_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH10_CC_A_Field is HAL.UInt16; + subtype CH10_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH10_CC_Register is record + A : CH10_CC_A_Field := 16#0#; + B : CH10_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH10_TOP_CH10_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH10_TOP_Register is record + CH10_TOP : CH10_TOP_CH10_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH10_TOP_Register use record + CH10_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + type CH11_CSR_DIVMODE_Field is + (-- Free-running counting at rate dictated by fractional divider + div, + -- Fractional divider operation is gated by the PWM B pin. + level, + -- Counter advances with each rising edge of the PWM B pin. + rise, + -- Counter advances with each falling edge of the PWM B pin. + fall) + with Size => 2; + for CH11_CSR_DIVMODE_Field use + (div => 0, + level => 1, + rise => 2, + fall => 3); + + -- Control and status register + type CH11_CSR_Register is record + -- Enable the PWM channel. + EN : Boolean := False; + -- 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT : Boolean := False; + -- Invert output A + A_INV : Boolean := False; + -- Invert output B + B_INV : Boolean := False; + DIVMODE : CH11_CSR_DIVMODE_Field := RP2350_SVD.PWM.div; + -- Write-only. Retard the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running. + PH_RET : Boolean := False; + -- Write-only. Advance the phase of the counter by 1 count, while it is + -- running. Self-clearing. Write a 1, and poll until low. Counter must + -- be running at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_CSR_Register use record + EN at 0 range 0 .. 0; + PH_CORRECT at 0 range 1 .. 1; + A_INV at 0 range 2 .. 2; + B_INV at 0 range 3 .. 3; + DIVMODE at 0 range 4 .. 5; + PH_RET at 0 range 6 .. 6; + PH_ADV at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype CH11_DIV_FRAC_Field is HAL.UInt4; + subtype CH11_DIV_INT_Field is HAL.UInt8; + + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division uses + -- simple 1st-order sigma-delta. + type CH11_DIV_Register is record + FRAC : CH11_DIV_FRAC_Field := 16#0#; + INT : CH11_DIV_INT_Field := 16#1#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_DIV_Register use record + FRAC at 0 range 0 .. 3; + INT at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype CH11_CTR_CH11_CTR_Field is HAL.UInt16; + + -- Direct access to the PWM counter + type CH11_CTR_Register is record + CH11_CTR : CH11_CTR_CH11_CTR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_CTR_Register use record + CH11_CTR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype CH11_CC_A_Field is HAL.UInt16; + subtype CH11_CC_B_Field is HAL.UInt16; + + -- Counter compare values + type CH11_CC_Register is record + A : CH11_CC_A_Field := 16#0#; + B : CH11_CC_B_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_CC_Register use record + A at 0 range 0 .. 15; + B at 0 range 16 .. 31; + end record; + + subtype CH11_TOP_CH11_TOP_Field is HAL.UInt16; + + -- Counter wrap value + type CH11_TOP_Register is record + CH11_TOP : CH11_TOP_CH11_TOP_Field := 16#FFFF#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CH11_TOP_Register use record + CH11_TOP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- EN_CH array + type EN_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for EN_CH + type EN_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : EN_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for EN_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- This register aliases the CSR_EN bits for all channels. Writing to this + -- register allows multiple channels to be enabled or disabled + -- simultaneously, so they can run in perfect sync. For each channel, there + -- is only one physical EN register bit, which can be accessed through here + -- or CHx_CSR. + type EN_Register is record + CH : EN_CH_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EN_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- INTR_CH array + type INTR_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for INTR_CH + type INTR_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : INTR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for INTR_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + CH : INTR_CH_Field := (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ0_INTE_CH array + type IRQ0_INTE_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ0_INTE_CH + type IRQ0_INTE_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ0_INTE_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ0_INTE_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt Enable for irq0 + type IRQ0_INTE_Register is record + CH : IRQ0_INTE_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTE_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ0_INTF_CH array + type IRQ0_INTF_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ0_INTF_CH + type IRQ0_INTF_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ0_INTF_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ0_INTF_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt Force for irq0 + type IRQ0_INTF_Register is record + CH : IRQ0_INTF_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTF_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ0_INTS_CH array + type IRQ0_INTS_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ0_INTS_CH + type IRQ0_INTS_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ0_INTS_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ0_INTS_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt status after masking & forcing for irq0 + type IRQ0_INTS_Register is record + -- Read-only. + CH : IRQ0_INTS_CH_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ0_INTS_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ1_INTE_CH array + type IRQ1_INTE_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ1_INTE_CH + type IRQ1_INTE_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ1_INTE_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ1_INTE_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt Enable for irq1 + type IRQ1_INTE_Register is record + CH : IRQ1_INTE_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTE_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ1_INTF_CH array + type IRQ1_INTF_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ1_INTF_CH + type IRQ1_INTF_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ1_INTF_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ1_INTF_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt Force for irq1 + type IRQ1_INTF_Register is record + CH : IRQ1_INTF_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTF_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- IRQ1_INTS_CH array + type IRQ1_INTS_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for IRQ1_INTS_CH + type IRQ1_INTS_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : IRQ1_INTS_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for IRQ1_INTS_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Interrupt status after masking & forcing for irq1 + type IRQ1_INTS_Register is record + -- Read-only. + CH : IRQ1_INTS_CH_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for IRQ1_INTS_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Simple PWM + type PWM_Peripheral is record + -- Control and status register + CH0_CSR : aliased CH0_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH0_DIV : aliased CH0_DIV_Register; + -- Direct access to the PWM counter + CH0_CTR : aliased CH0_CTR_Register; + -- Counter compare values + CH0_CC : aliased CH0_CC_Register; + -- Counter wrap value + CH0_TOP : aliased CH0_TOP_Register; + -- Control and status register + CH1_CSR : aliased CH1_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH1_DIV : aliased CH1_DIV_Register; + -- Direct access to the PWM counter + CH1_CTR : aliased CH1_CTR_Register; + -- Counter compare values + CH1_CC : aliased CH1_CC_Register; + -- Counter wrap value + CH1_TOP : aliased CH1_TOP_Register; + -- Control and status register + CH2_CSR : aliased CH2_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH2_DIV : aliased CH2_DIV_Register; + -- Direct access to the PWM counter + CH2_CTR : aliased CH2_CTR_Register; + -- Counter compare values + CH2_CC : aliased CH2_CC_Register; + -- Counter wrap value + CH2_TOP : aliased CH2_TOP_Register; + -- Control and status register + CH3_CSR : aliased CH3_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH3_DIV : aliased CH3_DIV_Register; + -- Direct access to the PWM counter + CH3_CTR : aliased CH3_CTR_Register; + -- Counter compare values + CH3_CC : aliased CH3_CC_Register; + -- Counter wrap value + CH3_TOP : aliased CH3_TOP_Register; + -- Control and status register + CH4_CSR : aliased CH4_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH4_DIV : aliased CH4_DIV_Register; + -- Direct access to the PWM counter + CH4_CTR : aliased CH4_CTR_Register; + -- Counter compare values + CH4_CC : aliased CH4_CC_Register; + -- Counter wrap value + CH4_TOP : aliased CH4_TOP_Register; + -- Control and status register + CH5_CSR : aliased CH5_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH5_DIV : aliased CH5_DIV_Register; + -- Direct access to the PWM counter + CH5_CTR : aliased CH5_CTR_Register; + -- Counter compare values + CH5_CC : aliased CH5_CC_Register; + -- Counter wrap value + CH5_TOP : aliased CH5_TOP_Register; + -- Control and status register + CH6_CSR : aliased CH6_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH6_DIV : aliased CH6_DIV_Register; + -- Direct access to the PWM counter + CH6_CTR : aliased CH6_CTR_Register; + -- Counter compare values + CH6_CC : aliased CH6_CC_Register; + -- Counter wrap value + CH6_TOP : aliased CH6_TOP_Register; + -- Control and status register + CH7_CSR : aliased CH7_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH7_DIV : aliased CH7_DIV_Register; + -- Direct access to the PWM counter + CH7_CTR : aliased CH7_CTR_Register; + -- Counter compare values + CH7_CC : aliased CH7_CC_Register; + -- Counter wrap value + CH7_TOP : aliased CH7_TOP_Register; + -- Control and status register + CH8_CSR : aliased CH8_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH8_DIV : aliased CH8_DIV_Register; + -- Direct access to the PWM counter + CH8_CTR : aliased CH8_CTR_Register; + -- Counter compare values + CH8_CC : aliased CH8_CC_Register; + -- Counter wrap value + CH8_TOP : aliased CH8_TOP_Register; + -- Control and status register + CH9_CSR : aliased CH9_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH9_DIV : aliased CH9_DIV_Register; + -- Direct access to the PWM counter + CH9_CTR : aliased CH9_CTR_Register; + -- Counter compare values + CH9_CC : aliased CH9_CC_Register; + -- Counter wrap value + CH9_TOP : aliased CH9_TOP_Register; + -- Control and status register + CH10_CSR : aliased CH10_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH10_DIV : aliased CH10_DIV_Register; + -- Direct access to the PWM counter + CH10_CTR : aliased CH10_CTR_Register; + -- Counter compare values + CH10_CC : aliased CH10_CC_Register; + -- Counter wrap value + CH10_TOP : aliased CH10_TOP_Register; + -- Control and status register + CH11_CSR : aliased CH11_CSR_Register; + -- INT and FRAC form a fixed-point fractional number. Counting rate is + -- system clock frequency divided by this number. Fractional division + -- uses simple 1st-order sigma-delta. + CH11_DIV : aliased CH11_DIV_Register; + -- Direct access to the PWM counter + CH11_CTR : aliased CH11_CTR_Register; + -- Counter compare values + CH11_CC : aliased CH11_CC_Register; + -- Counter wrap value + CH11_TOP : aliased CH11_TOP_Register; + -- This register aliases the CSR_EN bits for all channels. Writing to + -- this register allows multiple channels to be enabled or disabled + -- simultaneously, so they can run in perfect sync. For each channel, + -- there is only one physical EN register bit, which can be accessed + -- through here or CHx_CSR. + EN : aliased EN_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable for irq0 + IRQ0_INTE : aliased IRQ0_INTE_Register; + -- Interrupt Force for irq0 + IRQ0_INTF : aliased IRQ0_INTF_Register; + -- Interrupt status after masking & forcing for irq0 + IRQ0_INTS : aliased IRQ0_INTS_Register; + -- Interrupt Enable for irq1 + IRQ1_INTE : aliased IRQ1_INTE_Register; + -- Interrupt Force for irq1 + IRQ1_INTF : aliased IRQ1_INTF_Register; + -- Interrupt status after masking & forcing for irq1 + IRQ1_INTS : aliased IRQ1_INTS_Register; + end record + with Volatile; + + for PWM_Peripheral use record + CH0_CSR at 16#0# range 0 .. 31; + CH0_DIV at 16#4# range 0 .. 31; + CH0_CTR at 16#8# range 0 .. 31; + CH0_CC at 16#C# range 0 .. 31; + CH0_TOP at 16#10# range 0 .. 31; + CH1_CSR at 16#14# range 0 .. 31; + CH1_DIV at 16#18# range 0 .. 31; + CH1_CTR at 16#1C# range 0 .. 31; + CH1_CC at 16#20# range 0 .. 31; + CH1_TOP at 16#24# range 0 .. 31; + CH2_CSR at 16#28# range 0 .. 31; + CH2_DIV at 16#2C# range 0 .. 31; + CH2_CTR at 16#30# range 0 .. 31; + CH2_CC at 16#34# range 0 .. 31; + CH2_TOP at 16#38# range 0 .. 31; + CH3_CSR at 16#3C# range 0 .. 31; + CH3_DIV at 16#40# range 0 .. 31; + CH3_CTR at 16#44# range 0 .. 31; + CH3_CC at 16#48# range 0 .. 31; + CH3_TOP at 16#4C# range 0 .. 31; + CH4_CSR at 16#50# range 0 .. 31; + CH4_DIV at 16#54# range 0 .. 31; + CH4_CTR at 16#58# range 0 .. 31; + CH4_CC at 16#5C# range 0 .. 31; + CH4_TOP at 16#60# range 0 .. 31; + CH5_CSR at 16#64# range 0 .. 31; + CH5_DIV at 16#68# range 0 .. 31; + CH5_CTR at 16#6C# range 0 .. 31; + CH5_CC at 16#70# range 0 .. 31; + CH5_TOP at 16#74# range 0 .. 31; + CH6_CSR at 16#78# range 0 .. 31; + CH6_DIV at 16#7C# range 0 .. 31; + CH6_CTR at 16#80# range 0 .. 31; + CH6_CC at 16#84# range 0 .. 31; + CH6_TOP at 16#88# range 0 .. 31; + CH7_CSR at 16#8C# range 0 .. 31; + CH7_DIV at 16#90# range 0 .. 31; + CH7_CTR at 16#94# range 0 .. 31; + CH7_CC at 16#98# range 0 .. 31; + CH7_TOP at 16#9C# range 0 .. 31; + CH8_CSR at 16#A0# range 0 .. 31; + CH8_DIV at 16#A4# range 0 .. 31; + CH8_CTR at 16#A8# range 0 .. 31; + CH8_CC at 16#AC# range 0 .. 31; + CH8_TOP at 16#B0# range 0 .. 31; + CH9_CSR at 16#B4# range 0 .. 31; + CH9_DIV at 16#B8# range 0 .. 31; + CH9_CTR at 16#BC# range 0 .. 31; + CH9_CC at 16#C0# range 0 .. 31; + CH9_TOP at 16#C4# range 0 .. 31; + CH10_CSR at 16#C8# range 0 .. 31; + CH10_DIV at 16#CC# range 0 .. 31; + CH10_CTR at 16#D0# range 0 .. 31; + CH10_CC at 16#D4# range 0 .. 31; + CH10_TOP at 16#D8# range 0 .. 31; + CH11_CSR at 16#DC# range 0 .. 31; + CH11_DIV at 16#E0# range 0 .. 31; + CH11_CTR at 16#E4# range 0 .. 31; + CH11_CC at 16#E8# range 0 .. 31; + CH11_TOP at 16#EC# range 0 .. 31; + EN at 16#F0# range 0 .. 31; + INTR at 16#F4# range 0 .. 31; + IRQ0_INTE at 16#F8# range 0 .. 31; + IRQ0_INTF at 16#FC# range 0 .. 31; + IRQ0_INTS at 16#100# range 0 .. 31; + IRQ1_INTE at 16#104# range 0 .. 31; + IRQ1_INTF at 16#108# range 0 .. 31; + IRQ1_INTS at 16#10C# range 0 .. 31; + end record; + + -- Simple PWM + PWM_Periph : aliased PWM_Peripheral + with Import, Address => PWM_Base; + +end RP2350_SVD.PWM; diff --git a/src/svd/rp2350_svd-qmi.ads b/src/svd/rp2350_svd-qmi.ads new file mode 100644 index 0000000..d239314 --- /dev/null +++ b/src/svd/rp2350_svd-qmi.ads @@ -0,0 +1,1634 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- QSPI Memory Interface. +-- +-- Provides a memory-mapped interface to up to two SPI/DSPI/QSPI +-- flash or PSRAM devices. Also provides a serial interface for programming +-- and configuration of the external device. +package RP2350_SVD.QMI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype DIRECT_CSR_TXLEVEL_Field is HAL.UInt3; + subtype DIRECT_CSR_RXLEVEL_Field is HAL.UInt3; + subtype DIRECT_CSR_CLKDIV_Field is HAL.UInt8; + subtype DIRECT_CSR_RXDELAY_Field is HAL.UInt2; + + -- Control and status for direct serial mode Direct serial mode allows the + -- processor to send and receive raw serial frames, for programming, + -- configuration and control of the external memory devices. Only SPI mode + -- 0 (CPOL=0 CPHA=0) is supported. + type DIRECT_CSR_Register is record + -- Enable direct mode. In direct mode, software controls the chip select + -- lines, and can perform direct SPI transfers by pushing data to the + -- DIRECT_TX FIFO, and popping the same amount of data from the + -- DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when + -- direct serial mode is enabled. + EN : Boolean := False; + -- Read-only. Direct mode busy flag. If 1, data is currently being + -- shifted in/out (or would be if the interface were not stalled on the + -- RX FIFO), and the chip select must not yet be deasserted. The busy + -- flag will also be set to 1 if a memory-mapped transfer is still in + -- progress when direct mode is enabled. Direct mode blocks new + -- memory-mapped transfers, but can't halt a transfer that is already in + -- progress. If there is a chance that memory-mapped transfers may be in + -- progress, the busy flag should be polled for 0 before asserting the + -- chip select. (In practice you will usually discover this timing + -- condition through other means, because any subsequent memory-mapped + -- transfers when direct mode is enabled will return bus errors, which + -- are difficult to ignore.) + BUSY : Boolean := False; + -- When 1, assert (i.e. drive low) the CS0n chip select line. Note that + -- this applies even when DIRECT_CSR_EN is 0. + ASSERT_CS0N : Boolean := False; + -- When 1, assert (i.e. drive low) the CS1n chip select line. Note that + -- this applies even when DIRECT_CSR_EN is 0. + ASSERT_CS1N : Boolean := False; + -- unspecified + Reserved_4_5 : HAL.UInt2 := 16#0#; + -- When 1, automatically assert the CS0n chip select line whenever the + -- BUSY flag is set. + AUTO_CS0N : Boolean := False; + -- When 1, automatically assert the CS1n chip select line whenever the + -- BUSY flag is set. + AUTO_CS1N : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Read-only. When 1, the DIRECT_TX FIFO is currently full. If the + -- processor tries to write more data, that data will be ignored. + TXFULL : Boolean := False; + -- Read-only. When 1, the DIRECT_TX FIFO is currently empty. Unless the + -- processor pushes more data, transmission will stop and BUSY will go + -- low once the current 8-bit serial frame completes. + TXEMPTY : Boolean := False; + -- Read-only. Current level of DIRECT_TX FIFO + TXLEVEL : DIRECT_CSR_TXLEVEL_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Read-only. When 1, the DIRECT_RX FIFO is currently empty. If the + -- processor attempts to read more data, the FIFO state is not affected, + -- but the value returned to the processor is undefined. + RXEMPTY : Boolean := False; + -- Read-only. When 1, the DIRECT_RX FIFO is currently full. The serial + -- interface will be stalled until data is popped; the interface will + -- not begin a new serial frame when the DIRECT_TX FIFO is empty or the + -- DIRECT_RX FIFO is full. + RXFULL : Boolean := False; + -- Read-only. Current level of DIRECT_RX FIFO + RXLEVEL : DIRECT_CSR_RXLEVEL_Field := 16#0#; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Clock divisor for direct serial mode. Divisors of 1..255 are encoded + -- directly, and the maximum divisor of 256 is encoded by a value of + -- CLKDIV=0. The clock divisor can be changed on-the-fly by software, + -- without halting or otherwise coordinating with the serial interface. + -- The serial interface will sample the latest clock divisor each time + -- it begins the transmission of a new byte. + CLKDIV : DIRECT_CSR_CLKDIV_Field := 16#6#; + -- Delay the read data sample timing, in units of one half of a system + -- clock cycle. (Not necessarily half of an SCK cycle.) + RXDELAY : DIRECT_CSR_RXDELAY_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIRECT_CSR_Register use record + EN at 0 range 0 .. 0; + BUSY at 0 range 1 .. 1; + ASSERT_CS0N at 0 range 2 .. 2; + ASSERT_CS1N at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + AUTO_CS0N at 0 range 6 .. 6; + AUTO_CS1N at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + TXFULL at 0 range 10 .. 10; + TXEMPTY at 0 range 11 .. 11; + TXLEVEL at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + RXEMPTY at 0 range 16 .. 16; + RXFULL at 0 range 17 .. 17; + RXLEVEL at 0 range 18 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + CLKDIV at 0 range 22 .. 29; + RXDELAY at 0 range 30 .. 31; + end record; + + subtype DIRECT_TX_DATA_Field is HAL.UInt16; + + -- Configure whether this FIFO record is transferred with single/dual/quad + -- interface width (0/1/2). Different widths can be mixed freely. + type DIRECT_TX_IWIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for DIRECT_TX_IWIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Transmit FIFO for direct mode + type DIRECT_TX_Register is record + -- Write-only. Data pushed here will be clocked out falling edges of SCK + -- (or before the very first rising edge of SCK, if this is the first + -- pulse). For each byte clocked out, the interface will simultaneously + -- sample one byte, on rising edges of SCK, and push this to the + -- DIRECT_RX FIFO. For 16-bit data, the least-significant byte is + -- transmitted first. + DATA : DIRECT_TX_DATA_Field := 16#0#; + -- Write-only. Configure whether this FIFO record is transferred with + -- single/dual/quad interface width (0/1/2). Different widths can be + -- mixed freely. + IWIDTH : DIRECT_TX_IWIDTH_Field := RP2350_SVD.QMI.S; + -- Write-only. Data width. If 0, hardware will transmit the 8 LSBs of + -- the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of + -- DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit + -- transfers can be mixed freely. + DWIDTH : Boolean := False; + -- Write-only. Output enable (active-high). For single width (SPI), this + -- field is ignored, and SD0 is always set to output, with SD1 always + -- set to input. For dual and quad width (DSPI/QSPI), this sets whether + -- the relevant SDx pads are set to output whilst transferring this FIFO + -- record. In this case the command/address should have OE set, and the + -- data transfer should have OE set or clear depending on the direction + -- of the transfer. + OE : Boolean := False; + -- Write-only. Inhibit the RX FIFO push that would correspond to this TX + -- FIFO entry. Useful to avoid garbage appearing in the RX FIFO when + -- pushing the command at the beginning of a SPI transfer. + NOPUSH : Boolean := False; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIRECT_TX_Register use record + DATA at 0 range 0 .. 15; + IWIDTH at 0 range 16 .. 17; + DWIDTH at 0 range 18 .. 18; + OE at 0 range 19 .. 19; + NOPUSH at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype DIRECT_RX_DIRECT_RX_Field is HAL.UInt16; + + -- Receive FIFO for direct mode + type DIRECT_RX_Register is record + -- Read-only. *** This field is modified following a read operation ***. + -- With each byte clocked out on the serial interface, one byte will + -- simultaneously be clocked in, and will appear in this FIFO. The + -- serial interface will stall when this FIFO is full, to avoid dropping + -- data. When 16-bit data is pushed into the TX FIFO, the corresponding + -- RX FIFO push will also contain 16 bits of data. The least-significant + -- byte is the first one received. + DIRECT_RX : DIRECT_RX_DIRECT_RX_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIRECT_RX_Register use record + DIRECT_RX at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype M0_TIMING_CLKDIV_Field is HAL.UInt8; + subtype M0_TIMING_RXDELAY_Field is HAL.UInt3; + subtype M0_TIMING_MIN_DESELECT_Field is HAL.UInt5; + subtype M0_TIMING_MAX_SELECT_Field is HAL.UInt6; + subtype M0_TIMING_SELECT_HOLD_Field is HAL.UInt2; + + -- When page break is enabled, chip select will automatically deassert when + -- crossing certain power-of-2-aligned address boundaries. The next access + -- will always begin a new read/write SPI burst, even if the address of the + -- next access follows in sequence with the last access before the page + -- boundary. Some flash and PSRAM devices forbid crossing page boundaries + -- with a single read/write transfer, or restrict the operating frequency + -- for transfers that do cross page a boundary. This option allows the QMI + -- to safely support those devices. This field has no effect when COOLDOWN + -- is disabled. + type M0_TIMING_PAGEBREAK_Field is + (-- No page boundary is enforced + NONE, + -- Break bursts crossing a 256-byte page boundary + Val_256, + -- Break bursts crossing a 1024-byte quad-page boundary + Val_1024, + -- Break bursts crossing a 4096-byte sector boundary + Val_4096) + with Size => 2; + for M0_TIMING_PAGEBREAK_Field use + (NONE => 0, + Val_256 => 1, + Val_1024 => 2, + Val_4096 => 3); + + subtype M0_TIMING_COOLDOWN_Field is HAL.UInt2; + + -- Timing configuration register for memory address window 0. + type M0_TIMING_Register is record + -- Clock divisor. Odd and even divisors are supported. Defines the SCK + -- clock period in units of 1 system clock cycle. Divisors 1..255 are + -- encoded directly, and a divisor of 256 is encoded with a value of + -- CLKDIV=0. The clock divisor can be changed on-the-fly, even when the + -- QMI is currently accessing memory in this address window. All other + -- parameters must only be changed when the QMI is idle. If software is + -- increasing CLKDIV in anticipation of an increase in the system clock + -- frequency, a dummy access to either memory window (and appropriate + -- processor barriers/fences) must be inserted after the Mx_TIMING write + -- to ensure the SCK divisor change is in effect _before_ the system + -- clock is changed. + CLKDIV : M0_TIMING_CLKDIV_Field := 16#4#; + -- Delay the read data sample timing, in units of one half of a system + -- clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 + -- means the sample is captured at the SDI input registers + -- simultaneously with the rising edge of SCK launched from the SCK + -- output register. At higher SCK frequencies, RXDELAY may need to be + -- increased to account for the round trip delay of the pads, and the + -- clock-to-Q delay of the QSPI memory device. + RXDELAY : M0_TIMING_RXDELAY_Field := 16#0#; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- After this window's chip select is deasserted, it remains deasserted + -- for half an SCK cycle (rounded up to an integer number of system + -- clock cycles), plus MIN_DESELECT additional system clock cycles, + -- before the QMI reasserts either chip select pin. Nonzero values may + -- be required for PSRAM devices which enforce a longer minimum CS + -- deselect time, so that they can perform internal DRAM refresh cycles + -- whilst deselected. + MIN_DESELECT : M0_TIMING_MIN_DESELECT_Field := 16#0#; + -- Enforce a maximum assertion duration for this window's chip select, + -- in units of 64 system clock cycles. If 0, the QMI is permitted to + -- keep the chip select asserted indefinitely when servicing sequential + -- memory accesses (see COOLDOWN). This feature is required to meet + -- timing constraints of PSRAM devices, which specify a maximum chip + -- select assertion so they can perform DRAM refresh cycles. See also + -- MIN_DESELECT, which can enforce a minimum deselect time. If a memory + -- access is in progress at the time MAX_SELECT is reached, the QMI will + -- wait for the access to complete before deasserting the chip select. + -- This additional time must be accounted for to calculate a safe + -- MAX_SELECT value. In the worst case, this may be a fully-formed + -- serial transfer, including command prefix and address, with a data + -- payload as large as one cache line. + MAX_SELECT : M0_TIMING_MAX_SELECT_Field := 16#0#; + -- Add up to three additional system clock cycles of active hold between + -- the last falling edge of SCK and the deassertion of this window's + -- chip select. The default hold time is one system clock cycle. Note + -- that flash datasheets usually give chip select active hold time from + -- the last *rising* edge of SCK, and so even zero hold from the last + -- falling edge would be safe. Note that this is a minimum hold time + -- guaranteed by the QMI: the actual chip select active hold may be + -- slightly longer for read transfers with low clock divisors and/or + -- high sample delays. Specifically, if the point two cycles after the + -- last RX data sample is later than the last SCK falling edge, then the + -- hold time is measured from *this* point. Note also that, in case the + -- final SCK pulse is masked to save energy (true for non-DTR reads when + -- COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing + -- logic behaves as though the clock pulse were still present. The + -- SELECT_HOLD time is applied from the point where the last SCK falling + -- edge would be if the clock pulse were not masked. + SELECT_HOLD : M0_TIMING_SELECT_HOLD_Field := 16#0#; + -- Add up to one additional system clock cycle of setup between chip + -- select assertion and the first rising edge of SCK. The default setup + -- time is one half SCK period, which is usually sufficient except for + -- very high SCK frequencies with some flash devices. + SELECT_SETUP : Boolean := False; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- When page break is enabled, chip select will automatically deassert + -- when crossing certain power-of-2-aligned address boundaries. The next + -- access will always begin a new read/write SPI burst, even if the + -- address of the next access follows in sequence with the last access + -- before the page boundary. Some flash and PSRAM devices forbid + -- crossing page boundaries with a single read/write transfer, or + -- restrict the operating frequency for transfers that do cross page a + -- boundary. This option allows the QMI to safely support those devices. + -- This field has no effect when COOLDOWN is disabled. + PAGEBREAK : M0_TIMING_PAGEBREAK_Field := RP2350_SVD.QMI.NONE; + -- Chip select cooldown period. When a memory transfer finishes, the + -- chip select remains asserted for 64 x COOLDOWN system clock cycles, + -- plus half an SCK clock period (rounded up for odd SCK divisors). + -- After this cooldown expires, the chip select is always deasserted to + -- save power. If the next memory access arrives within the cooldown + -- period, the QMI may be able to append more SCK cycles to the + -- currently ongoing SPI transfer, rather than starting a new transfer. + -- This reduces access latency and increases bus throughput. + -- Specifically, the next access must be in the same direction + -- (read/write), access the same memory window (chip select 0/1), and + -- follow sequentially the address of the last transfer. If any of these + -- are false, the new access will first deassert the chip select, then + -- begin a new transfer. If COOLDOWN is 0, the address alignment + -- configured by PAGEBREAK has been reached, or the total chip select + -- assertion limit MAX_SELECT has been reached, the cooldown period is + -- skipped, and the chip select will always be deasserted one half SCK + -- period after the transfer finishes. + COOLDOWN : M0_TIMING_COOLDOWN_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M0_TIMING_Register use record + CLKDIV at 0 range 0 .. 7; + RXDELAY at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + MIN_DESELECT at 0 range 12 .. 16; + MAX_SELECT at 0 range 17 .. 22; + SELECT_HOLD at 0 range 23 .. 24; + SELECT_SETUP at 0 range 25 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + PAGEBREAK at 0 range 28 .. 29; + COOLDOWN at 0 range 30 .. 31; + end record; + + -- The transfer width used for the command prefix, if any + type M0_RFMT_PREFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_RFMT_PREFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + type M0_RFMT_ADDR_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_RFMT_ADDR_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the post-address command suffix, if any + type M0_RFMT_SUFFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_RFMT_SUFFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the dummy phase, if any. If width is single, SD0/MOSI + -- is held asserted low during the dummy phase, and SD1...SD3 are + -- tristated. If width is dual/quad, all IOs are tristated during the dummy + -- phase. + type M0_RFMT_DUMMY_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_RFMT_DUMMY_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the data transfer + type M0_RFMT_DATA_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_RFMT_DATA_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + type M0_RFMT_PREFIX_LEN_Field is + (-- No prefix + NONE, + -- 8-bit prefix + Val_8) + with Size => 1; + for M0_RFMT_PREFIX_LEN_Field use + (NONE => 0, + Val_8 => 1); + + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle + -- for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits + -- are supported. + type M0_RFMT_SUFFIX_LEN_Field is + (-- No suffix + NONE, + -- 8-bit suffix + Val_8) + with Size => 2; + for M0_RFMT_SUFFIX_LEN_Field use + (NONE => 0, + Val_8 => 2); + + -- Length of dummy phase between command suffix and data phase, in units of + -- 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + type M0_RFMT_DUMMY_LEN_Field is + (-- No dummy phase + NONE, + -- 4 dummy bits + Val_4, + -- 8 dummy bits + Val_8, + -- 12 dummy bits + Val_12, + -- 16 dummy bits + Val_16, + -- 20 dummy bits + Val_20, + -- 24 dummy bits + Val_24, + -- 28 dummy bits + Val_28) + with Size => 3; + for M0_RFMT_DUMMY_LEN_Field use + (NONE => 0, + Val_4 => 1, + Val_8 => 2, + Val_12 => 3, + Val_16 => 4, + Val_20 => 5, + Val_24 => 6, + Val_28 => 7); + + -- Read transfer format configuration for memory address window 0. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command suffix + -- and dummy/turnaround transfer phases. Only 24-bit addresses are + -- supported. The reset value of the M0_RFMT register is configured to + -- support a basic 03h serial read transfer with no additional + -- configuration. + type M0_RFMT_Register is record + -- The transfer width used for the command prefix, if any + PREFIX_WIDTH : M0_RFMT_PREFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + ADDR_WIDTH : M0_RFMT_ADDR_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the post-address command suffix, if any + SUFFIX_WIDTH : M0_RFMT_SUFFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the dummy phase, if any. If width is single, + -- SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 + -- are tristated. If width is dual/quad, all IOs are tristated during + -- the dummy phase. + DUMMY_WIDTH : M0_RFMT_DUMMY_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the data transfer + DATA_WIDTH : M0_RFMT_DATA_WIDTH_Field := RP2350_SVD.QMI.S; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + PREFIX_LEN : M0_RFMT_PREFIX_LEN_Field := RP2350_SVD.QMI.Val_8; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 + -- cycle for quad width, 2 for dual, 4 for single) Only values of 0 and + -- 8 bits are supported. + SUFFIX_LEN : M0_RFMT_SUFFIX_LEN_Field := RP2350_SVD.QMI.NONE; + -- Length of dummy phase between command suffix and data phase, in units + -- of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + DUMMY_LEN : M0_RFMT_DUMMY_LEN_Field := RP2350_SVD.QMI.NONE; + -- unspecified + Reserved_19_27 : HAL.UInt9 := 16#0#; + -- Enable double transfer rate (DTR) for read commands: address, suffix + -- and read data phases are active on both edges of SCK. SDO data is + -- launched centre-aligned on each SCK edge, and SDI data is captured on + -- the SCK edge that follows its launch. DTR is implemented by halving + -- the clock rate; SCK has a period of 2 x CLK_DIV throughout the + -- transfer. The prefix and dummy phases are still single transfer rate. + -- If the suffix is quad-width, it must be 0 or 8 bits in length, to + -- ensure an even number of SCK edges. + DTR : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M0_RFMT_Register use record + PREFIX_WIDTH at 0 range 0 .. 1; + ADDR_WIDTH at 0 range 2 .. 3; + SUFFIX_WIDTH at 0 range 4 .. 5; + DUMMY_WIDTH at 0 range 6 .. 7; + DATA_WIDTH at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + PREFIX_LEN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SUFFIX_LEN at 0 range 14 .. 15; + DUMMY_LEN at 0 range 16 .. 18; + Reserved_19_27 at 0 range 19 .. 27; + DTR at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype M0_RCMD_PREFIX_Field is HAL.UInt8; + subtype M0_RCMD_SUFFIX_Field is HAL.UInt8; + + -- Command constants used for reads from memory address window 0. The reset + -- value of the M0_RCMD register is configured to support a basic 03h + -- serial read transfer with no additional configuration. + type M0_RCMD_Register is record + -- The command prefix bits to prepend on each new transfer, if + -- Mx_RFMT_PREFIX_LEN is nonzero. + PREFIX : M0_RCMD_PREFIX_Field := 16#3#; + -- The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN + -- is nonzero. + SUFFIX : M0_RCMD_SUFFIX_Field := 16#A0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M0_RCMD_Register use record + PREFIX at 0 range 0 .. 7; + SUFFIX at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- The transfer width used for the command prefix, if any + type M0_WFMT_PREFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_WFMT_PREFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + type M0_WFMT_ADDR_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_WFMT_ADDR_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the post-address command suffix, if any + type M0_WFMT_SUFFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_WFMT_SUFFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the dummy phase, if any. If width is single, SD0/MOSI + -- is held asserted low during the dummy phase, and SD1...SD3 are + -- tristated. If width is dual/quad, all IOs are tristated during the dummy + -- phase. + type M0_WFMT_DUMMY_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_WFMT_DUMMY_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the data transfer + type M0_WFMT_DATA_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M0_WFMT_DATA_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + type M0_WFMT_PREFIX_LEN_Field is + (-- No prefix + NONE, + -- 8-bit prefix + Val_8) + with Size => 1; + for M0_WFMT_PREFIX_LEN_Field use + (NONE => 0, + Val_8 => 1); + + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle + -- for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits + -- are supported. + type M0_WFMT_SUFFIX_LEN_Field is + (-- No suffix + NONE, + -- 8-bit suffix + Val_8) + with Size => 2; + for M0_WFMT_SUFFIX_LEN_Field use + (NONE => 0, + Val_8 => 2); + + -- Length of dummy phase between command suffix and data phase, in units of + -- 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + type M0_WFMT_DUMMY_LEN_Field is + (-- No dummy phase + NONE, + -- 4 dummy bits + Val_4, + -- 8 dummy bits + Val_8, + -- 12 dummy bits + Val_12, + -- 16 dummy bits + Val_16, + -- 20 dummy bits + Val_20, + -- 24 dummy bits + Val_24, + -- 28 dummy bits + Val_28) + with Size => 3; + for M0_WFMT_DUMMY_LEN_Field use + (NONE => 0, + Val_4 => 1, + Val_8 => 2, + Val_12 => 3, + Val_16 => 4, + Val_20 => 5, + Val_24 => 6, + Val_28 => 7); + + -- Write transfer format configuration for memory address window 0. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command suffix + -- and dummy/turnaround transfer phases. Only 24-bit addresses are + -- supported. The reset value of the M0_WFMT register is configured to + -- support a basic 02h serial write transfer. However, writes to this + -- window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP + -- memory is read-only by default. + type M0_WFMT_Register is record + -- The transfer width used for the command prefix, if any + PREFIX_WIDTH : M0_WFMT_PREFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + ADDR_WIDTH : M0_WFMT_ADDR_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the post-address command suffix, if any + SUFFIX_WIDTH : M0_WFMT_SUFFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the dummy phase, if any. If width is single, + -- SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 + -- are tristated. If width is dual/quad, all IOs are tristated during + -- the dummy phase. + DUMMY_WIDTH : M0_WFMT_DUMMY_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the data transfer + DATA_WIDTH : M0_WFMT_DATA_WIDTH_Field := RP2350_SVD.QMI.S; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + PREFIX_LEN : M0_WFMT_PREFIX_LEN_Field := RP2350_SVD.QMI.Val_8; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 + -- cycle for quad width, 2 for dual, 4 for single) Only values of 0 and + -- 8 bits are supported. + SUFFIX_LEN : M0_WFMT_SUFFIX_LEN_Field := RP2350_SVD.QMI.NONE; + -- Length of dummy phase between command suffix and data phase, in units + -- of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + DUMMY_LEN : M0_WFMT_DUMMY_LEN_Field := RP2350_SVD.QMI.NONE; + -- unspecified + Reserved_19_27 : HAL.UInt9 := 16#0#; + -- Enable double transfer rate (DTR) for write commands: address, suffix + -- and write data phases are active on both edges of SCK. SDO data is + -- launched centre-aligned on each SCK edge, and SDI data is captured on + -- the SCK edge that follows its launch. DTR is implemented by halving + -- the clock rate; SCK has a period of 2 x CLK_DIV throughout the + -- transfer. The prefix and dummy phases are still single transfer rate. + -- If the suffix is quad-width, it must be 0 or 8 bits in length, to + -- ensure an even number of SCK edges. + DTR : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M0_WFMT_Register use record + PREFIX_WIDTH at 0 range 0 .. 1; + ADDR_WIDTH at 0 range 2 .. 3; + SUFFIX_WIDTH at 0 range 4 .. 5; + DUMMY_WIDTH at 0 range 6 .. 7; + DATA_WIDTH at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + PREFIX_LEN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SUFFIX_LEN at 0 range 14 .. 15; + DUMMY_LEN at 0 range 16 .. 18; + Reserved_19_27 at 0 range 19 .. 27; + DTR at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype M0_WCMD_PREFIX_Field is HAL.UInt8; + subtype M0_WCMD_SUFFIX_Field is HAL.UInt8; + + -- Command constants used for writes to memory address window 0. The reset + -- value of the M0_WCMD register is configured to support a basic 02h + -- serial write transfer with no additional configuration. + type M0_WCMD_Register is record + -- The command prefix bits to prepend on each new transfer, if + -- Mx_WFMT_PREFIX_LEN is nonzero. + PREFIX : M0_WCMD_PREFIX_Field := 16#2#; + -- The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN + -- is nonzero. + SUFFIX : M0_WCMD_SUFFIX_Field := 16#A0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M0_WCMD_Register use record + PREFIX at 0 range 0 .. 7; + SUFFIX at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype M1_TIMING_CLKDIV_Field is HAL.UInt8; + subtype M1_TIMING_RXDELAY_Field is HAL.UInt3; + subtype M1_TIMING_MIN_DESELECT_Field is HAL.UInt5; + subtype M1_TIMING_MAX_SELECT_Field is HAL.UInt6; + subtype M1_TIMING_SELECT_HOLD_Field is HAL.UInt2; + + -- When page break is enabled, chip select will automatically deassert when + -- crossing certain power-of-2-aligned address boundaries. The next access + -- will always begin a new read/write SPI burst, even if the address of the + -- next access follows in sequence with the last access before the page + -- boundary. Some flash and PSRAM devices forbid crossing page boundaries + -- with a single read/write transfer, or restrict the operating frequency + -- for transfers that do cross page a boundary. This option allows the QMI + -- to safely support those devices. This field has no effect when COOLDOWN + -- is disabled. + type M1_TIMING_PAGEBREAK_Field is + (-- No page boundary is enforced + NONE, + -- Break bursts crossing a 256-byte page boundary + Val_256, + -- Break bursts crossing a 1024-byte quad-page boundary + Val_1024, + -- Break bursts crossing a 4096-byte sector boundary + Val_4096) + with Size => 2; + for M1_TIMING_PAGEBREAK_Field use + (NONE => 0, + Val_256 => 1, + Val_1024 => 2, + Val_4096 => 3); + + subtype M1_TIMING_COOLDOWN_Field is HAL.UInt2; + + -- Timing configuration register for memory address window 1. + type M1_TIMING_Register is record + -- Clock divisor. Odd and even divisors are supported. Defines the SCK + -- clock period in units of 1 system clock cycle. Divisors 1..255 are + -- encoded directly, and a divisor of 256 is encoded with a value of + -- CLKDIV=0. The clock divisor can be changed on-the-fly, even when the + -- QMI is currently accessing memory in this address window. All other + -- parameters must only be changed when the QMI is idle. If software is + -- increasing CLKDIV in anticipation of an increase in the system clock + -- frequency, a dummy access to either memory window (and appropriate + -- processor barriers/fences) must be inserted after the Mx_TIMING write + -- to ensure the SCK divisor change is in effect _before_ the system + -- clock is changed. + CLKDIV : M1_TIMING_CLKDIV_Field := 16#4#; + -- Delay the read data sample timing, in units of one half of a system + -- clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 + -- means the sample is captured at the SDI input registers + -- simultaneously with the rising edge of SCK launched from the SCK + -- output register. At higher SCK frequencies, RXDELAY may need to be + -- increased to account for the round trip delay of the pads, and the + -- clock-to-Q delay of the QSPI memory device. + RXDELAY : M1_TIMING_RXDELAY_Field := 16#0#; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- After this window's chip select is deasserted, it remains deasserted + -- for half an SCK cycle (rounded up to an integer number of system + -- clock cycles), plus MIN_DESELECT additional system clock cycles, + -- before the QMI reasserts either chip select pin. Nonzero values may + -- be required for PSRAM devices which enforce a longer minimum CS + -- deselect time, so that they can perform internal DRAM refresh cycles + -- whilst deselected. + MIN_DESELECT : M1_TIMING_MIN_DESELECT_Field := 16#0#; + -- Enforce a maximum assertion duration for this window's chip select, + -- in units of 64 system clock cycles. If 0, the QMI is permitted to + -- keep the chip select asserted indefinitely when servicing sequential + -- memory accesses (see COOLDOWN). This feature is required to meet + -- timing constraints of PSRAM devices, which specify a maximum chip + -- select assertion so they can perform DRAM refresh cycles. See also + -- MIN_DESELECT, which can enforce a minimum deselect time. If a memory + -- access is in progress at the time MAX_SELECT is reached, the QMI will + -- wait for the access to complete before deasserting the chip select. + -- This additional time must be accounted for to calculate a safe + -- MAX_SELECT value. In the worst case, this may be a fully-formed + -- serial transfer, including command prefix and address, with a data + -- payload as large as one cache line. + MAX_SELECT : M1_TIMING_MAX_SELECT_Field := 16#0#; + -- Add up to three additional system clock cycles of active hold between + -- the last falling edge of SCK and the deassertion of this window's + -- chip select. The default hold time is one system clock cycle. Note + -- that flash datasheets usually give chip select active hold time from + -- the last *rising* edge of SCK, and so even zero hold from the last + -- falling edge would be safe. Note that this is a minimum hold time + -- guaranteed by the QMI: the actual chip select active hold may be + -- slightly longer for read transfers with low clock divisors and/or + -- high sample delays. Specifically, if the point two cycles after the + -- last RX data sample is later than the last SCK falling edge, then the + -- hold time is measured from *this* point. Note also that, in case the + -- final SCK pulse is masked to save energy (true for non-DTR reads when + -- COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing + -- logic behaves as though the clock pulse were still present. The + -- SELECT_HOLD time is applied from the point where the last SCK falling + -- edge would be if the clock pulse were not masked. + SELECT_HOLD : M1_TIMING_SELECT_HOLD_Field := 16#0#; + -- Add up to one additional system clock cycle of setup between chip + -- select assertion and the first rising edge of SCK. The default setup + -- time is one half SCK period, which is usually sufficient except for + -- very high SCK frequencies with some flash devices. + SELECT_SETUP : Boolean := False; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- When page break is enabled, chip select will automatically deassert + -- when crossing certain power-of-2-aligned address boundaries. The next + -- access will always begin a new read/write SPI burst, even if the + -- address of the next access follows in sequence with the last access + -- before the page boundary. Some flash and PSRAM devices forbid + -- crossing page boundaries with a single read/write transfer, or + -- restrict the operating frequency for transfers that do cross page a + -- boundary. This option allows the QMI to safely support those devices. + -- This field has no effect when COOLDOWN is disabled. + PAGEBREAK : M1_TIMING_PAGEBREAK_Field := RP2350_SVD.QMI.NONE; + -- Chip select cooldown period. When a memory transfer finishes, the + -- chip select remains asserted for 64 x COOLDOWN system clock cycles, + -- plus half an SCK clock period (rounded up for odd SCK divisors). + -- After this cooldown expires, the chip select is always deasserted to + -- save power. If the next memory access arrives within the cooldown + -- period, the QMI may be able to append more SCK cycles to the + -- currently ongoing SPI transfer, rather than starting a new transfer. + -- This reduces access latency and increases bus throughput. + -- Specifically, the next access must be in the same direction + -- (read/write), access the same memory window (chip select 0/1), and + -- follow sequentially the address of the last transfer. If any of these + -- are false, the new access will first deassert the chip select, then + -- begin a new transfer. If COOLDOWN is 0, the address alignment + -- configured by PAGEBREAK has been reached, or the total chip select + -- assertion limit MAX_SELECT has been reached, the cooldown period is + -- skipped, and the chip select will always be deasserted one half SCK + -- period after the transfer finishes. + COOLDOWN : M1_TIMING_COOLDOWN_Field := 16#1#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M1_TIMING_Register use record + CLKDIV at 0 range 0 .. 7; + RXDELAY at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + MIN_DESELECT at 0 range 12 .. 16; + MAX_SELECT at 0 range 17 .. 22; + SELECT_HOLD at 0 range 23 .. 24; + SELECT_SETUP at 0 range 25 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + PAGEBREAK at 0 range 28 .. 29; + COOLDOWN at 0 range 30 .. 31; + end record; + + -- The transfer width used for the command prefix, if any + type M1_RFMT_PREFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_RFMT_PREFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + type M1_RFMT_ADDR_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_RFMT_ADDR_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the post-address command suffix, if any + type M1_RFMT_SUFFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_RFMT_SUFFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the dummy phase, if any. If width is single, SD0/MOSI + -- is held asserted low during the dummy phase, and SD1...SD3 are + -- tristated. If width is dual/quad, all IOs are tristated during the dummy + -- phase. + type M1_RFMT_DUMMY_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_RFMT_DUMMY_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the data transfer + type M1_RFMT_DATA_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_RFMT_DATA_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + type M1_RFMT_PREFIX_LEN_Field is + (-- No prefix + NONE, + -- 8-bit prefix + Val_8) + with Size => 1; + for M1_RFMT_PREFIX_LEN_Field use + (NONE => 0, + Val_8 => 1); + + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle + -- for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits + -- are supported. + type M1_RFMT_SUFFIX_LEN_Field is + (-- No suffix + NONE, + -- 8-bit suffix + Val_8) + with Size => 2; + for M1_RFMT_SUFFIX_LEN_Field use + (NONE => 0, + Val_8 => 2); + + -- Length of dummy phase between command suffix and data phase, in units of + -- 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + type M1_RFMT_DUMMY_LEN_Field is + (-- No dummy phase + NONE, + -- 4 dummy bits + Val_4, + -- 8 dummy bits + Val_8, + -- 12 dummy bits + Val_12, + -- 16 dummy bits + Val_16, + -- 20 dummy bits + Val_20, + -- 24 dummy bits + Val_24, + -- 28 dummy bits + Val_28) + with Size => 3; + for M1_RFMT_DUMMY_LEN_Field use + (NONE => 0, + Val_4 => 1, + Val_8 => 2, + Val_12 => 3, + Val_16 => 4, + Val_20 => 5, + Val_24 => 6, + Val_28 => 7); + + -- Read transfer format configuration for memory address window 1. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command suffix + -- and dummy/turnaround transfer phases. Only 24-bit addresses are + -- supported. The reset value of the M1_RFMT register is configured to + -- support a basic 03h serial read transfer with no additional + -- configuration. + type M1_RFMT_Register is record + -- The transfer width used for the command prefix, if any + PREFIX_WIDTH : M1_RFMT_PREFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + ADDR_WIDTH : M1_RFMT_ADDR_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the post-address command suffix, if any + SUFFIX_WIDTH : M1_RFMT_SUFFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the dummy phase, if any. If width is single, + -- SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 + -- are tristated. If width is dual/quad, all IOs are tristated during + -- the dummy phase. + DUMMY_WIDTH : M1_RFMT_DUMMY_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the data transfer + DATA_WIDTH : M1_RFMT_DATA_WIDTH_Field := RP2350_SVD.QMI.S; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + PREFIX_LEN : M1_RFMT_PREFIX_LEN_Field := RP2350_SVD.QMI.Val_8; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 + -- cycle for quad width, 2 for dual, 4 for single) Only values of 0 and + -- 8 bits are supported. + SUFFIX_LEN : M1_RFMT_SUFFIX_LEN_Field := RP2350_SVD.QMI.NONE; + -- Length of dummy phase between command suffix and data phase, in units + -- of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + DUMMY_LEN : M1_RFMT_DUMMY_LEN_Field := RP2350_SVD.QMI.NONE; + -- unspecified + Reserved_19_27 : HAL.UInt9 := 16#0#; + -- Enable double transfer rate (DTR) for read commands: address, suffix + -- and read data phases are active on both edges of SCK. SDO data is + -- launched centre-aligned on each SCK edge, and SDI data is captured on + -- the SCK edge that follows its launch. DTR is implemented by halving + -- the clock rate; SCK has a period of 2 x CLK_DIV throughout the + -- transfer. The prefix and dummy phases are still single transfer rate. + -- If the suffix is quad-width, it must be 0 or 8 bits in length, to + -- ensure an even number of SCK edges. + DTR : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M1_RFMT_Register use record + PREFIX_WIDTH at 0 range 0 .. 1; + ADDR_WIDTH at 0 range 2 .. 3; + SUFFIX_WIDTH at 0 range 4 .. 5; + DUMMY_WIDTH at 0 range 6 .. 7; + DATA_WIDTH at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + PREFIX_LEN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SUFFIX_LEN at 0 range 14 .. 15; + DUMMY_LEN at 0 range 16 .. 18; + Reserved_19_27 at 0 range 19 .. 27; + DTR at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype M1_RCMD_PREFIX_Field is HAL.UInt8; + subtype M1_RCMD_SUFFIX_Field is HAL.UInt8; + + -- Command constants used for reads from memory address window 1. The reset + -- value of the M1_RCMD register is configured to support a basic 03h + -- serial read transfer with no additional configuration. + type M1_RCMD_Register is record + -- The command prefix bits to prepend on each new transfer, if + -- Mx_RFMT_PREFIX_LEN is nonzero. + PREFIX : M1_RCMD_PREFIX_Field := 16#3#; + -- The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN + -- is nonzero. + SUFFIX : M1_RCMD_SUFFIX_Field := 16#A0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M1_RCMD_Register use record + PREFIX at 0 range 0 .. 7; + SUFFIX at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- The transfer width used for the command prefix, if any + type M1_WFMT_PREFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_WFMT_PREFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + type M1_WFMT_ADDR_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_WFMT_ADDR_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the post-address command suffix, if any + type M1_WFMT_SUFFIX_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_WFMT_SUFFIX_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the dummy phase, if any. If width is single, SD0/MOSI + -- is held asserted low during the dummy phase, and SD1...SD3 are + -- tristated. If width is dual/quad, all IOs are tristated during the dummy + -- phase. + type M1_WFMT_DUMMY_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_WFMT_DUMMY_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- The width used for the data transfer + type M1_WFMT_DATA_WIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for M1_WFMT_DATA_WIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + type M1_WFMT_PREFIX_LEN_Field is + (-- No prefix + NONE, + -- 8-bit prefix + Val_8) + with Size => 1; + for M1_WFMT_PREFIX_LEN_Field use + (NONE => 0, + Val_8 => 1); + + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle + -- for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits + -- are supported. + type M1_WFMT_SUFFIX_LEN_Field is + (-- No suffix + NONE, + -- 8-bit suffix + Val_8) + with Size => 2; + for M1_WFMT_SUFFIX_LEN_Field use + (NONE => 0, + Val_8 => 2); + + -- Length of dummy phase between command suffix and data phase, in units of + -- 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + type M1_WFMT_DUMMY_LEN_Field is + (-- No dummy phase + NONE, + -- 4 dummy bits + Val_4, + -- 8 dummy bits + Val_8, + -- 12 dummy bits + Val_12, + -- 16 dummy bits + Val_16, + -- 20 dummy bits + Val_20, + -- 24 dummy bits + Val_24, + -- 28 dummy bits + Val_28) + with Size => 3; + for M1_WFMT_DUMMY_LEN_Field use + (NONE => 0, + Val_4 => 1, + Val_8 => 2, + Val_12 => 3, + Val_16 => 4, + Val_20 => 5, + Val_24 => 6, + Val_28 => 7); + + -- Write transfer format configuration for memory address window 1. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command suffix + -- and dummy/turnaround transfer phases. Only 24-bit addresses are + -- supported. The reset value of the M1_WFMT register is configured to + -- support a basic 02h serial write transfer. However, writes to this + -- window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP + -- memory is read-only by default. + type M1_WFMT_Register is record + -- The transfer width used for the command prefix, if any + PREFIX_WIDTH : M1_WFMT_PREFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The transfer width used for the address. The address phase always + -- transfers 24 bits in total. + ADDR_WIDTH : M1_WFMT_ADDR_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the post-address command suffix, if any + SUFFIX_WIDTH : M1_WFMT_SUFFIX_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the dummy phase, if any. If width is single, + -- SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 + -- are tristated. If width is dual/quad, all IOs are tristated during + -- the dummy phase. + DUMMY_WIDTH : M1_WFMT_DUMMY_WIDTH_Field := RP2350_SVD.QMI.S; + -- The width used for the data transfer + DATA_WIDTH : M1_WFMT_DATA_WIDTH_Field := RP2350_SVD.QMI.S; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad + -- width, 4 for dual, 8 for single) + PREFIX_LEN : M1_WFMT_PREFIX_LEN_Field := RP2350_SVD.QMI.Val_8; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Length of post-address command suffix, in units of 4 bits. (i.e. 1 + -- cycle for quad width, 2 for dual, 4 for single) Only values of 0 and + -- 8 bits are supported. + SUFFIX_LEN : M1_WFMT_SUFFIX_LEN_Field := RP2350_SVD.QMI.NONE; + -- Length of dummy phase between command suffix and data phase, in units + -- of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + DUMMY_LEN : M1_WFMT_DUMMY_LEN_Field := RP2350_SVD.QMI.NONE; + -- unspecified + Reserved_19_27 : HAL.UInt9 := 16#0#; + -- Enable double transfer rate (DTR) for write commands: address, suffix + -- and write data phases are active on both edges of SCK. SDO data is + -- launched centre-aligned on each SCK edge, and SDI data is captured on + -- the SCK edge that follows its launch. DTR is implemented by halving + -- the clock rate; SCK has a period of 2 x CLK_DIV throughout the + -- transfer. The prefix and dummy phases are still single transfer rate. + -- If the suffix is quad-width, it must be 0 or 8 bits in length, to + -- ensure an even number of SCK edges. + DTR : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M1_WFMT_Register use record + PREFIX_WIDTH at 0 range 0 .. 1; + ADDR_WIDTH at 0 range 2 .. 3; + SUFFIX_WIDTH at 0 range 4 .. 5; + DUMMY_WIDTH at 0 range 6 .. 7; + DATA_WIDTH at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + PREFIX_LEN at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + SUFFIX_LEN at 0 range 14 .. 15; + DUMMY_LEN at 0 range 16 .. 18; + Reserved_19_27 at 0 range 19 .. 27; + DTR at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype M1_WCMD_PREFIX_Field is HAL.UInt8; + subtype M1_WCMD_SUFFIX_Field is HAL.UInt8; + + -- Command constants used for writes to memory address window 1. The reset + -- value of the M1_WCMD register is configured to support a basic 02h + -- serial write transfer with no additional configuration. + type M1_WCMD_Register is record + -- The command prefix bits to prepend on each new transfer, if + -- Mx_WFMT_PREFIX_LEN is nonzero. + PREFIX : M1_WCMD_PREFIX_Field := 16#2#; + -- The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN + -- is nonzero. + SUFFIX : M1_WCMD_SUFFIX_Field := 16#A0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for M1_WCMD_Register use record + PREFIX at 0 range 0 .. 7; + SUFFIX at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ATRANS_BASE_Field is HAL.UInt12; + subtype ATRANS_SIZE_Field is HAL.UInt11; + + -- Configure address translation for XIP virtual addresses 0x000000 through + -- 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows + -- a program image to be executed in place at multiple physical flash + -- addresses (for example, a double-buffered flash image for over-the-air + -- updates), without the overhead of position-independent code. At reset, + -- the address translation registers are initialised to an identity + -- mapping, so that they can be ignored if address translation is not + -- required. Note that the XIP cache is fully virtually addressed, so a + -- cache flush is required after changing the address translation. + type ATRANS_Register is record + -- Physical address base for this virtual address range, in units of 4 + -- kiB (one flash sector). Taking a 24-bit virtual address, firstly bits + -- 23:22 (the two MSBs) are masked to zero, and then BASE is added to + -- bits 23:12 (the upper 12 bits) to form the physical address. + -- Translation wraps on a 16 MiB boundary. + BASE : ATRANS_BASE_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Translation aperture size for this virtual address range, in units of + -- 4 kiB (one flash sector). Bits 21:12 of the virtual address are + -- compared to SIZE. Offsets greater than SIZE return a bus error, and + -- do not cause a QSPI access. + SIZE : ATRANS_SIZE_Field := 16#400#; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ATRANS_Register use record + BASE at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + SIZE at 0 range 16 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- QSPI Memory Interface. Provides a memory-mapped interface to up to two + -- SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface + -- for programming and configuration of the external device. + type QMI_Peripheral is record + -- Control and status for direct serial mode Direct serial mode allows + -- the processor to send and receive raw serial frames, for programming, + -- configuration and control of the external memory devices. Only SPI + -- mode 0 (CPOL=0 CPHA=0) is supported. + DIRECT_CSR : aliased DIRECT_CSR_Register; + -- Transmit FIFO for direct mode + DIRECT_TX : aliased DIRECT_TX_Register; + -- Receive FIFO for direct mode + DIRECT_RX : aliased DIRECT_RX_Register; + -- Timing configuration register for memory address window 0. + M0_TIMING : aliased M0_TIMING_Register; + -- Read transfer format configuration for memory address window 0. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command + -- suffix and dummy/turnaround transfer phases. Only 24-bit addresses + -- are supported. The reset value of the M0_RFMT register is configured + -- to support a basic 03h serial read transfer with no additional + -- configuration. + M0_RFMT : aliased M0_RFMT_Register; + -- Command constants used for reads from memory address window 0. The + -- reset value of the M0_RCMD register is configured to support a basic + -- 03h serial read transfer with no additional configuration. + M0_RCMD : aliased M0_RCMD_Register; + -- Write transfer format configuration for memory address window 0. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command + -- suffix and dummy/turnaround transfer phases. Only 24-bit addresses + -- are supported. The reset value of the M0_WFMT register is configured + -- to support a basic 02h serial write transfer. However, writes to this + -- window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP + -- memory is read-only by default. + M0_WFMT : aliased M0_WFMT_Register; + -- Command constants used for writes to memory address window 0. The + -- reset value of the M0_WCMD register is configured to support a basic + -- 02h serial write transfer with no additional configuration. + M0_WCMD : aliased M0_WCMD_Register; + -- Timing configuration register for memory address window 1. + M1_TIMING : aliased M1_TIMING_Register; + -- Read transfer format configuration for memory address window 1. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command + -- suffix and dummy/turnaround transfer phases. Only 24-bit addresses + -- are supported. The reset value of the M1_RFMT register is configured + -- to support a basic 03h serial read transfer with no additional + -- configuration. + M1_RFMT : aliased M1_RFMT_Register; + -- Command constants used for reads from memory address window 1. The + -- reset value of the M1_RCMD register is configured to support a basic + -- 03h serial read transfer with no additional configuration. + M1_RCMD : aliased M1_RCMD_Register; + -- Write transfer format configuration for memory address window 1. + -- Configure the bus width of each transfer phase individually, and + -- configure the length or presence of the command prefix, command + -- suffix and dummy/turnaround transfer phases. Only 24-bit addresses + -- are supported. The reset value of the M1_WFMT register is configured + -- to support a basic 02h serial write transfer. However, writes to this + -- window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP + -- memory is read-only by default. + M1_WFMT : aliased M1_WFMT_Register; + -- Command constants used for writes to memory address window 1. The + -- reset value of the M1_WCMD register is configured to support a basic + -- 02h serial write transfer with no additional configuration. + M1_WCMD : aliased M1_WCMD_Register; + -- Configure address translation for XIP virtual addresses 0x000000 + -- through 0x3fffff (a 4 MiB window starting at +0 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS0 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x400000 + -- through 0x7fffff (a 4 MiB window starting at +4 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS1 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x800000 + -- through 0xbfffff (a 4 MiB window starting at +8 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS2 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0xc00000 + -- through 0xffffff (a 4 MiB window starting at +12 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS3 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x1000000 + -- through 0x13fffff (a 4 MiB window starting at +16 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS4 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x1400000 + -- through 0x17fffff (a 4 MiB window starting at +20 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS5 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x1800000 + -- through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS6 : aliased ATRANS_Register; + -- Configure address translation for XIP virtual addresses 0x1c00000 + -- through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address + -- translation allows a program image to be executed in place at + -- multiple physical flash addresses (for example, a double-buffered + -- flash image for over-the-air updates), without the overhead of + -- position-independent code. At reset, the address translation + -- registers are initialised to an identity mapping, so that they can be + -- ignored if address translation is not required. Note that the XIP + -- cache is fully virtually addressed, so a cache flush is required + -- after changing the address translation. + ATRANS7 : aliased ATRANS_Register; + end record + with Volatile; + + for QMI_Peripheral use record + DIRECT_CSR at 16#0# range 0 .. 31; + DIRECT_TX at 16#4# range 0 .. 31; + DIRECT_RX at 16#8# range 0 .. 31; + M0_TIMING at 16#C# range 0 .. 31; + M0_RFMT at 16#10# range 0 .. 31; + M0_RCMD at 16#14# range 0 .. 31; + M0_WFMT at 16#18# range 0 .. 31; + M0_WCMD at 16#1C# range 0 .. 31; + M1_TIMING at 16#20# range 0 .. 31; + M1_RFMT at 16#24# range 0 .. 31; + M1_RCMD at 16#28# range 0 .. 31; + M1_WFMT at 16#2C# range 0 .. 31; + M1_WCMD at 16#30# range 0 .. 31; + ATRANS0 at 16#34# range 0 .. 31; + ATRANS1 at 16#38# range 0 .. 31; + ATRANS2 at 16#3C# range 0 .. 31; + ATRANS3 at 16#40# range 0 .. 31; + ATRANS4 at 16#44# range 0 .. 31; + ATRANS5 at 16#48# range 0 .. 31; + ATRANS6 at 16#4C# range 0 .. 31; + ATRANS7 at 16#50# range 0 .. 31; + end record; + + -- QSPI Memory Interface. Provides a memory-mapped interface to up to two + -- SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface + -- for programming and configuration of the external device. + QMI_Periph : aliased QMI_Peripheral + with Import, Address => QMI_Base; + +end RP2350_SVD.QMI; diff --git a/src/svd/rp2350_svd-resets.ads b/src/svd/rp2350_svd-resets.ads new file mode 100644 index 0000000..48b3107 --- /dev/null +++ b/src/svd/rp2350_svd-resets.ads @@ -0,0 +1,593 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.RESETS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- RESET_I2C array + type RESET_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_I2C + type RESET_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- I2C as a value + Val : HAL.UInt2; + when True => + -- I2C as an array + Arr : RESET_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_PIO array + type RESET_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for RESET_PIO + type RESET_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIO as a value + Val : HAL.UInt3; + when True => + -- PIO as an array + Arr : RESET_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for RESET_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- RESET_SPI array + type RESET_SPI_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_SPI + type RESET_SPI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SPI as a value + Val : HAL.UInt2; + when True => + -- SPI as an array + Arr : RESET_SPI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_SPI_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_TIMER array + type RESET_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_TIMER + type RESET_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TIMER as a value + Val : HAL.UInt2; + when True => + -- TIMER as an array + Arr : RESET_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_UART array + type RESET_UART_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_UART + type RESET_UART_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UART as a value + Val : HAL.UInt2; + when True => + -- UART as an array + Arr : RESET_UART_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_UART_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + type RESET_Register is record + ADC : Boolean := True; + BUSCTRL : Boolean := True; + DMA : Boolean := True; + HSTX : Boolean := True; + I2C : RESET_I2C_Field := (As_Array => False, Val => 16#1#); + IO_BANK0 : Boolean := True; + IO_QSPI : Boolean := True; + JTAG : Boolean := True; + PADS_BANK0 : Boolean := True; + PADS_QSPI : Boolean := True; + PIO : RESET_PIO_Field := (As_Array => False, Val => 16#1#); + PLL_SYS : Boolean := True; + PLL_USB : Boolean := True; + PWM : Boolean := True; + SHA256 : Boolean := True; + SPI : RESET_SPI_Field := (As_Array => False, Val => 16#1#); + SYSCFG : Boolean := True; + SYSINFO : Boolean := True; + TBMAN : Boolean := True; + TIMER : RESET_TIMER_Field := (As_Array => False, Val => 16#1#); + TRNG : Boolean := True; + UART : RESET_UART_Field := (As_Array => False, Val => 16#1#); + USBCTRL : Boolean := True; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESET_Register use record + ADC at 0 range 0 .. 0; + BUSCTRL at 0 range 1 .. 1; + DMA at 0 range 2 .. 2; + HSTX at 0 range 3 .. 3; + I2C at 0 range 4 .. 5; + IO_BANK0 at 0 range 6 .. 6; + IO_QSPI at 0 range 7 .. 7; + JTAG at 0 range 8 .. 8; + PADS_BANK0 at 0 range 9 .. 9; + PADS_QSPI at 0 range 10 .. 10; + PIO at 0 range 11 .. 13; + PLL_SYS at 0 range 14 .. 14; + PLL_USB at 0 range 15 .. 15; + PWM at 0 range 16 .. 16; + SHA256 at 0 range 17 .. 17; + SPI at 0 range 18 .. 19; + SYSCFG at 0 range 20 .. 20; + SYSINFO at 0 range 21 .. 21; + TBMAN at 0 range 22 .. 22; + TIMER at 0 range 23 .. 24; + TRNG at 0 range 25 .. 25; + UART at 0 range 26 .. 27; + USBCTRL at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- WDSEL_I2C array + type WDSEL_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WDSEL_I2C + type WDSEL_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- I2C as a value + Val : HAL.UInt2; + when True => + -- I2C as an array + Arr : WDSEL_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WDSEL_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- WDSEL_PIO array + type WDSEL_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for WDSEL_PIO + type WDSEL_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIO as a value + Val : HAL.UInt3; + when True => + -- PIO as an array + Arr : WDSEL_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for WDSEL_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- WDSEL_SPI array + type WDSEL_SPI_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WDSEL_SPI + type WDSEL_SPI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SPI as a value + Val : HAL.UInt2; + when True => + -- SPI as an array + Arr : WDSEL_SPI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WDSEL_SPI_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- WDSEL_TIMER array + type WDSEL_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WDSEL_TIMER + type WDSEL_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TIMER as a value + Val : HAL.UInt2; + when True => + -- TIMER as an array + Arr : WDSEL_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WDSEL_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- WDSEL_UART array + type WDSEL_UART_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for WDSEL_UART + type WDSEL_UART_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UART as a value + Val : HAL.UInt2; + when True => + -- UART as an array + Arr : WDSEL_UART_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for WDSEL_UART_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + type WDSEL_Register is record + ADC : Boolean := False; + BUSCTRL : Boolean := False; + DMA : Boolean := False; + HSTX : Boolean := False; + I2C : WDSEL_I2C_Field := (As_Array => False, Val => 16#0#); + IO_BANK0 : Boolean := False; + IO_QSPI : Boolean := False; + JTAG : Boolean := False; + PADS_BANK0 : Boolean := False; + PADS_QSPI : Boolean := False; + PIO : WDSEL_PIO_Field := (As_Array => False, Val => 16#0#); + PLL_SYS : Boolean := False; + PLL_USB : Boolean := False; + PWM : Boolean := False; + SHA256 : Boolean := False; + SPI : WDSEL_SPI_Field := (As_Array => False, Val => 16#0#); + SYSCFG : Boolean := False; + SYSINFO : Boolean := False; + TBMAN : Boolean := False; + TIMER : WDSEL_TIMER_Field := (As_Array => False, Val => 16#0#); + TRNG : Boolean := False; + UART : WDSEL_UART_Field := (As_Array => False, Val => 16#0#); + USBCTRL : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WDSEL_Register use record + ADC at 0 range 0 .. 0; + BUSCTRL at 0 range 1 .. 1; + DMA at 0 range 2 .. 2; + HSTX at 0 range 3 .. 3; + I2C at 0 range 4 .. 5; + IO_BANK0 at 0 range 6 .. 6; + IO_QSPI at 0 range 7 .. 7; + JTAG at 0 range 8 .. 8; + PADS_BANK0 at 0 range 9 .. 9; + PADS_QSPI at 0 range 10 .. 10; + PIO at 0 range 11 .. 13; + PLL_SYS at 0 range 14 .. 14; + PLL_USB at 0 range 15 .. 15; + PWM at 0 range 16 .. 16; + SHA256 at 0 range 17 .. 17; + SPI at 0 range 18 .. 19; + SYSCFG at 0 range 20 .. 20; + SYSINFO at 0 range 21 .. 21; + TBMAN at 0 range 22 .. 22; + TIMER at 0 range 23 .. 24; + TRNG at 0 range 25 .. 25; + UART at 0 range 26 .. 27; + USBCTRL at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- RESET_DONE_I2C array + type RESET_DONE_I2C_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_DONE_I2C + type RESET_DONE_I2C_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- I2C as a value + Val : HAL.UInt2; + when True => + -- I2C as an array + Arr : RESET_DONE_I2C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_DONE_I2C_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_DONE_PIO array + type RESET_DONE_PIO_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for RESET_DONE_PIO + type RESET_DONE_PIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PIO as a value + Val : HAL.UInt3; + when True => + -- PIO as an array + Arr : RESET_DONE_PIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for RESET_DONE_PIO_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- RESET_DONE_SPI array + type RESET_DONE_SPI_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_DONE_SPI + type RESET_DONE_SPI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SPI as a value + Val : HAL.UInt2; + when True => + -- SPI as an array + Arr : RESET_DONE_SPI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_DONE_SPI_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_DONE_TIMER array + type RESET_DONE_TIMER_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_DONE_TIMER + type RESET_DONE_TIMER_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TIMER as a value + Val : HAL.UInt2; + when True => + -- TIMER as an array + Arr : RESET_DONE_TIMER_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_DONE_TIMER_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- RESET_DONE_UART array + type RESET_DONE_UART_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for RESET_DONE_UART + type RESET_DONE_UART_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- UART as a value + Val : HAL.UInt2; + when True => + -- UART as an array + Arr : RESET_DONE_UART_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for RESET_DONE_UART_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + type RESET_DONE_Register is record + -- Read-only. + ADC : Boolean; + -- Read-only. + BUSCTRL : Boolean; + -- Read-only. + DMA : Boolean; + -- Read-only. + HSTX : Boolean; + -- Read-only. + I2C : RESET_DONE_I2C_Field; + -- Read-only. + IO_BANK0 : Boolean; + -- Read-only. + IO_QSPI : Boolean; + -- Read-only. + JTAG : Boolean; + -- Read-only. + PADS_BANK0 : Boolean; + -- Read-only. + PADS_QSPI : Boolean; + -- Read-only. + PIO : RESET_DONE_PIO_Field; + -- Read-only. + PLL_SYS : Boolean; + -- Read-only. + PLL_USB : Boolean; + -- Read-only. + PWM : Boolean; + -- Read-only. + SHA256 : Boolean; + -- Read-only. + SPI : RESET_DONE_SPI_Field; + -- Read-only. + SYSCFG : Boolean; + -- Read-only. + SYSINFO : Boolean; + -- Read-only. + TBMAN : Boolean; + -- Read-only. + TIMER : RESET_DONE_TIMER_Field; + -- Read-only. + TRNG : Boolean; + -- Read-only. + UART : RESET_DONE_UART_Field; + -- Read-only. + USBCTRL : Boolean; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RESET_DONE_Register use record + ADC at 0 range 0 .. 0; + BUSCTRL at 0 range 1 .. 1; + DMA at 0 range 2 .. 2; + HSTX at 0 range 3 .. 3; + I2C at 0 range 4 .. 5; + IO_BANK0 at 0 range 6 .. 6; + IO_QSPI at 0 range 7 .. 7; + JTAG at 0 range 8 .. 8; + PADS_BANK0 at 0 range 9 .. 9; + PADS_QSPI at 0 range 10 .. 10; + PIO at 0 range 11 .. 13; + PLL_SYS at 0 range 14 .. 14; + PLL_USB at 0 range 15 .. 15; + PWM at 0 range 16 .. 16; + SHA256 at 0 range 17 .. 17; + SPI at 0 range 18 .. 19; + SYSCFG at 0 range 20 .. 20; + SYSINFO at 0 range 21 .. 21; + TBMAN at 0 range 22 .. 22; + TIMER at 0 range 23 .. 24; + TRNG at 0 range 25 .. 25; + UART at 0 range 26 .. 27; + USBCTRL at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type RESETS_Peripheral is record + RESET : aliased RESET_Register; + WDSEL : aliased WDSEL_Register; + RESET_DONE : aliased RESET_DONE_Register; + end record + with Volatile; + + for RESETS_Peripheral use record + RESET at 16#0# range 0 .. 31; + WDSEL at 16#4# range 0 .. 31; + RESET_DONE at 16#8# range 0 .. 31; + end record; + + RESETS_Periph : aliased RESETS_Peripheral + with Import, Address => RESETS_Base; + +end RP2350_SVD.RESETS; diff --git a/src/svd/rp2350_svd-rosc.ads b/src/svd/rp2350_svd-rosc.ads new file mode 100644 index 0000000..59564ee --- /dev/null +++ b/src/svd/rp2350_svd-rosc.ads @@ -0,0 +1,379 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.ROSC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Controls the number of delay stages in the ROSC ring LOW uses stages 0 + -- to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses + -- stages 6 to 7 and should not be used because its frequency exceeds + -- design specifications The clock output will not glitch when changing the + -- range up one step at a time The clock output will glitch when changing + -- the range down Note: the values here are gray coded which is why HIGH + -- comes before TOOHIGH + type CTRL_FREQ_RANGE_Field is + (-- Reset value for the field + CTRL_FREQ_RANGE_Field_Reset, + LOW, + MEDIUM, + TOOHIGH, + HIGH) + with Size => 12; + for CTRL_FREQ_RANGE_Field use + (CTRL_FREQ_RANGE_Field_Reset => 2720, + LOW => 4004, + MEDIUM => 4005, + TOOHIGH => 4006, + HIGH => 4007); + + -- On power-up this field is initialised to ENABLE The system clock must be + -- switched to another source before setting this field to DISABLE + -- otherwise the chip will lock up The 12-bit code is intended to give some + -- protection against accidental writes. An invalid setting will enable the + -- oscillator. + type CTRL_ENABLE_Field is + (-- Reset value for the field + CTRL_ENABLE_Field_Reset, + DISABLE, + ENABLE) + with Size => 12; + for CTRL_ENABLE_Field use + (CTRL_ENABLE_Field_Reset => 0, + DISABLE => 3358, + ENABLE => 4011); + + -- Ring Oscillator control + type CTRL_Register is record + -- Controls the number of delay stages in the ROSC ring LOW uses stages + -- 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses + -- stages 6 to 7 and should not be used because its frequency exceeds + -- design specifications The clock output will not glitch when changing + -- the range up one step at a time The clock output will glitch when + -- changing the range down Note: the values here are gray coded which is + -- why HIGH comes before TOOHIGH + FREQ_RANGE : CTRL_FREQ_RANGE_Field := CTRL_FREQ_RANGE_Field_Reset; + -- On power-up this field is initialised to ENABLE The system clock must + -- be switched to another source before setting this field to DISABLE + -- otherwise the chip will lock up The 12-bit code is intended to give + -- some protection against accidental writes. An invalid setting will + -- enable the oscillator. + ENABLE : CTRL_ENABLE_Field := CTRL_ENABLE_Field_Reset; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + FREQ_RANGE at 0 range 0 .. 11; + ENABLE at 0 range 12 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype FREQA_DS0_Field is HAL.UInt3; + subtype FREQA_DS1_Field is HAL.UInt3; + subtype FREQA_DS2_Field is HAL.UInt3; + subtype FREQA_DS3_Field is HAL.UInt3; + + -- Set to 0x9696 to apply the settings Any other value in this field will + -- set all drive strengths to 0 + type FREQA_PASSWD_Field is + (-- Reset value for the field + FREQA_PASSWD_Field_Reset, + PASS) + with Size => 16; + for FREQA_PASSWD_Field use + (FREQA_PASSWD_Field_Reset => 0, + PASS => 38550); + + -- The FREQA & FREQB registers control the frequency by controlling the + -- drive strength of each stage The drive strength has 4 levels determined + -- by the number of bits set Increasing the number of bits set increases + -- the drive strength and increases the oscillation frequency 0 bits set is + -- the default drive strength 1 bit set doubles the drive strength 2 bits + -- set triples drive strength 3 bits set quadruples drive strength For + -- frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + type FREQA_Register is record + -- Stage 0 drive strength + DS0 : FREQA_DS0_Field := 16#0#; + -- Randomises the stage 0 drive strength + DS0_RANDOM : Boolean := False; + -- Stage 1 drive strength + DS1 : FREQA_DS1_Field := 16#0#; + -- Randomises the stage 1 drive strength + DS1_RANDOM : Boolean := False; + -- Stage 2 drive strength + DS2 : FREQA_DS2_Field := 16#0#; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Stage 3 drive strength + DS3 : FREQA_DS3_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Set to 0x9696 to apply the settings Any other value in this field + -- will set all drive strengths to 0 + PASSWD : FREQA_PASSWD_Field := FREQA_PASSWD_Field_Reset; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FREQA_Register use record + DS0 at 0 range 0 .. 2; + DS0_RANDOM at 0 range 3 .. 3; + DS1 at 0 range 4 .. 6; + DS1_RANDOM at 0 range 7 .. 7; + DS2 at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + DS3 at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PASSWD at 0 range 16 .. 31; + end record; + + subtype FREQB_DS4_Field is HAL.UInt3; + subtype FREQB_DS5_Field is HAL.UInt3; + subtype FREQB_DS6_Field is HAL.UInt3; + subtype FREQB_DS7_Field is HAL.UInt3; + + -- Set to 0x9696 to apply the settings Any other value in this field will + -- set all drive strengths to 0 + type FREQB_PASSWD_Field is + (-- Reset value for the field + FREQB_PASSWD_Field_Reset, + PASS) + with Size => 16; + for FREQB_PASSWD_Field use + (FREQB_PASSWD_Field_Reset => 0, + PASS => 38550); + + -- For a detailed description see freqa register + type FREQB_Register is record + -- Stage 4 drive strength + DS4 : FREQB_DS4_Field := 16#0#; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Stage 5 drive strength + DS5 : FREQB_DS5_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Stage 6 drive strength + DS6 : FREQB_DS6_Field := 16#0#; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Stage 7 drive strength + DS7 : FREQB_DS7_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Set to 0x9696 to apply the settings Any other value in this field + -- will set all drive strengths to 0 + PASSWD : FREQB_PASSWD_Field := FREQB_PASSWD_Field_Reset; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FREQB_Register use record + DS4 at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DS5 at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DS6 at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + DS7 at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PASSWD at 0 range 16 .. 31; + end record; + + -- set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by + -- div any other value sets div=128 this register resets to div=32 + type DIV_DIV_Field is + (-- Reset value for the field + DIV_DIV_Field_Reset, + PASS) + with Size => 16; + for DIV_DIV_Field use + (DIV_DIV_Field_Reset => 0, + PASS => 43520); + + -- Controls the output divider + type DIV_Register is record + -- set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides + -- by div any other value sets div=128 this register resets to div=32 + DIV : DIV_DIV_Field := DIV_DIV_Field_Reset; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DIV_Register use record + DIV at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype PHASE_SHIFT_Field is HAL.UInt2; + subtype PHASE_PASSWD_Field is HAL.UInt8; + + -- Controls the phase shifted output + type PHASE_Register is record + -- phase shift the phase-shifted output by SHIFT input clocks this can + -- be changed on-the-fly must be set to 0 before setting div=1 + SHIFT : PHASE_SHIFT_Field := 16#0#; + -- invert the phase-shifted output this is ignored when div=1 + FLIP : Boolean := False; + -- enable the phase-shifted output this can be changed on-the-fly + ENABLE : Boolean := True; + -- set to 0xaa any other value enables the output with shift=0 + PASSWD : PHASE_PASSWD_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PHASE_Register use record + SHIFT at 0 range 0 .. 1; + FLIP at 0 range 2 .. 2; + ENABLE at 0 range 3 .. 3; + PASSWD at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Ring Oscillator Status + type STATUS_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12 := 16#0#; + -- Read-only. Oscillator is enabled but not necessarily running and + -- stable this resets to 0 but transitions to 1 during chip startup + ENABLED : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Read-only. post-divider is running this resets to 0 but transitions + -- to 1 during chip startup + DIV_RUNNING : Boolean := False; + -- unspecified + Reserved_17_23 : HAL.UInt7 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. An invalid value has been written to CTRL_ENABLE or + -- CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + BADWRITE : Boolean := False; + -- unspecified + Reserved_25_30 : HAL.UInt6 := 16#0#; + -- Read-only. Oscillator is running and stable + STABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATUS_Register use record + Reserved_0_11 at 0 range 0 .. 11; + ENABLED at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + DIV_RUNNING at 0 range 16 .. 16; + Reserved_17_23 at 0 range 17 .. 23; + BADWRITE at 0 range 24 .. 24; + Reserved_25_30 at 0 range 25 .. 30; + STABLE at 0 range 31 .. 31; + end record; + + -- This just reads the state of the oscillator output so randomness is + -- compromised if the ring oscillator is stopped or run at a harmonic of + -- the bus frequency + type RANDOMBIT_Register is record + -- Read-only. + RANDOMBIT : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RANDOMBIT_Register use record + RANDOMBIT at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype COUNT_COUNT_Field is HAL.UInt16; + + -- A down counter running at the ROSC frequency which counts to zero and + -- stops. To start the counter write a non-zero value. Can be used for + -- short software pauses when setting up time sensitive hardware. + type COUNT_Register is record + COUNT : COUNT_COUNT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for COUNT_Register use record + COUNT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type ROSC_Peripheral is record + -- Ring Oscillator control + CTRL : aliased CTRL_Register; + -- The FREQA & FREQB registers control the frequency by controlling the + -- drive strength of each stage The drive strength has 4 levels + -- determined by the number of bits set Increasing the number of bits + -- set increases the drive strength and increases the oscillation + -- frequency 0 bits set is the default drive strength 1 bit set doubles + -- the drive strength 2 bits set triples drive strength 3 bits set + -- quadruples drive strength For frequency randomisation set both + -- DS0_RANDOM=1 & DS1_RANDOM=1 + FREQA : aliased FREQA_Register; + -- For a detailed description see freqa register + FREQB : aliased FREQB_Register; + -- Loads a value to the LFSR randomiser + RANDOM : aliased HAL.UInt32; + -- Ring Oscillator pause control + DORMANT : aliased HAL.UInt32; + -- Controls the output divider + DIV : aliased DIV_Register; + -- Controls the phase shifted output + PHASE : aliased PHASE_Register; + -- Ring Oscillator Status + STATUS : aliased STATUS_Register; + -- This just reads the state of the oscillator output so randomness is + -- compromised if the ring oscillator is stopped or run at a harmonic of + -- the bus frequency + RANDOMBIT : aliased RANDOMBIT_Register; + -- A down counter running at the ROSC frequency which counts to zero and + -- stops. To start the counter write a non-zero value. Can be used for + -- short software pauses when setting up time sensitive hardware. + COUNT : aliased COUNT_Register; + end record + with Volatile; + + for ROSC_Peripheral use record + CTRL at 16#0# range 0 .. 31; + FREQA at 16#4# range 0 .. 31; + FREQB at 16#8# range 0 .. 31; + RANDOM at 16#C# range 0 .. 31; + DORMANT at 16#10# range 0 .. 31; + DIV at 16#14# range 0 .. 31; + PHASE at 16#18# range 0 .. 31; + STATUS at 16#1C# range 0 .. 31; + RANDOMBIT at 16#20# range 0 .. 31; + COUNT at 16#24# range 0 .. 31; + end record; + + ROSC_Periph : aliased ROSC_Peripheral + with Import, Address => ROSC_Base; + +end RP2350_SVD.ROSC; diff --git a/src/svd/rp2350_svd-sha256.ads b/src/svd/rp2350_svd-sha256.ads new file mode 100644 index 0000000..c44d739 --- /dev/null +++ b/src/svd/rp2350_svd-sha256.ads @@ -0,0 +1,162 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- SHA-256 hash function implementation +package RP2350_SVD.SHA256 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Configure DREQ logic for the correct DMA data size. Must be configured + -- before the DMA channel is triggered. The SHA-256 core's DREQ logic + -- requests one entire block of data at once, since there is no FIFO, and + -- data goes straight into the core's message schedule and digest hardware. + -- Therefore, when transferring data with DMA, CSR_DMA_SIZE must be + -- configured in advance so that the correct number of transfers can be + -- requested per block. + type CSR_DMA_SIZE_Field is + (Val_8bit, + Val_16bit, + Val_32bit) + with Size => 2; + for CSR_DMA_SIZE_Field use + (Val_8bit => 0, + Val_16bit => 1, + Val_32bit => 2); + + -- Control and status register + type CSR_Register is record + -- Write-only. Write 1 to prepare the SHA-256 core for a new checksum. + -- The SUMx registers are initialised to the proper values (fractional + -- bits of square roots of first 8 primes) and internal counters are + -- cleared. This immediately forces WDATA_RDY and SUM_VLD high. START + -- must be written before initiating a DMA transfer to the SHA-256 core, + -- because the core will always request 16 transfers at a time (1 + -- 512-bit block). Additionally, the DMA channel should be configured + -- for a multiple of 16 32-bit transfers. + START : Boolean := False; + -- Read-only. If 1, the SHA-256 core is ready to accept more data + -- through the WDATA register. After writing 16 words, this flag will go + -- low for 57 cycles whilst the core completes its digest. + WDATA_RDY : Boolean := True; + -- Read-only. If 1, the SHA-256 checksum presented in registers SUM0 + -- through SUM7 is currently valid. Goes low when WDATA is first + -- written, then returns high once 16 words have been written and the + -- digest of the current 512-bit block has subsequently completed. + SUM_VLD : Boolean := True; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Set when a write occurs whilst the SHA-256 core is not + -- ready for data (WDATA_RDY is low). Write one to clear. + ERR_WDATA_NOT_RDY : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Configure DREQ logic for the correct DMA data size. Must be + -- configured before the DMA channel is triggered. The SHA-256 core's + -- DREQ logic requests one entire block of data at once, since there is + -- no FIFO, and data goes straight into the core's message schedule and + -- digest hardware. Therefore, when transferring data with DMA, + -- CSR_DMA_SIZE must be configured in advance so that the correct number + -- of transfers can be requested per block. + DMA_SIZE : CSR_DMA_SIZE_Field := RP2350_SVD.SHA256.Val_32bit; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Enable byte swapping of 32-bit values at the point they are committed + -- to the SHA message scheduler. This block's bus interface assembles + -- byte/halfword data into message words in little-endian order, so that + -- DMAing the same buffer with different transfer sizes always gives the + -- same result on a little-endian system like RP2350. However, when + -- marshalling bytes into blocks, SHA expects that the first byte is the + -- *most significant* in each message word. To resolve this, once the + -- bus interface has accumulated 32 bits of data (either a word write, + -- two halfword writes in little-endian order, or four byte writes in + -- little-endian order) the final value can be byte-swapped before + -- passing to the actual SHA core. This feature is enabled by default + -- because using the SHA core to checksum byte buffers is expected to be + -- more common than having preformatted SHA message words lying around. + BSWAP : Boolean := True; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CSR_Register use record + START at 0 range 0 .. 0; + WDATA_RDY at 0 range 1 .. 1; + SUM_VLD at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + ERR_WDATA_NOT_RDY at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + DMA_SIZE at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + BSWAP at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- SHA-256 hash function implementation + type SHA256_Peripheral is record + -- Control and status register + CSR : aliased CSR_Register; + -- Write data register + WDATA : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM0 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM1 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM2 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM3 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM4 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM5 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM6 : aliased HAL.UInt32; + -- 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is + -- 0. + SUM7 : aliased HAL.UInt32; + end record + with Volatile; + + for SHA256_Peripheral use record + CSR at 16#0# range 0 .. 31; + WDATA at 16#4# range 0 .. 31; + SUM0 at 16#8# range 0 .. 31; + SUM1 at 16#C# range 0 .. 31; + SUM2 at 16#10# range 0 .. 31; + SUM3 at 16#14# range 0 .. 31; + SUM4 at 16#18# range 0 .. 31; + SUM5 at 16#1C# range 0 .. 31; + SUM6 at 16#20# range 0 .. 31; + SUM7 at 16#24# range 0 .. 31; + end record; + + -- SHA-256 hash function implementation + SHA256_Periph : aliased SHA256_Peripheral + with Import, Address => SHA256_Base; + +end RP2350_SVD.SHA256; diff --git a/src/svd/rp2350_svd-sio.ads b/src/svd/rp2350_svd-sio.ads new file mode 100644 index 0000000..88499fb --- /dev/null +++ b/src/svd/rp2350_svd-sio.ads @@ -0,0 +1,1669 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Single-cycle IO block +-- Provides core-local and inter-core hardware for the two +-- processors, with single-cycle access. +package RP2350_SVD.SIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype GPIO_HI_IN_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_IN_QSPI_SD_Field is HAL.UInt4; + + -- Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + type GPIO_HI_IN_Register is record + -- Read-only. Input value on GPIO32...47 + GPIO : GPIO_HI_IN_GPIO_Field; + -- unspecified + Reserved_16_23 : HAL.UInt8; + -- Read-only. Input value on USB D+ pin + USB_DP : Boolean; + -- Read-only. Input value on USB D- pin + USB_DM : Boolean; + -- Read-only. Input value on QSPI SCK pin + QSPI_SCK : Boolean; + -- Read-only. Input value on QSPI CSn pin + QSPI_CSN : Boolean; + -- Read-only. Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 + -- pins + QSPI_SD : GPIO_HI_IN_QSPI_SD_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_IN_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_QSPI_SD_Field is HAL.UInt4; + + -- Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output + -- level (1/0 -> high/low). Reading back gives the last value written, NOT + -- the input value from the pins. If core 0 and core 1 both write to + -- GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as + -- though the write from core 0 took place first, and the write from core 1 + -- was then applied to that intermediate result. In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output + -- status reads back as zero. This is also true for SET/CLR/XOR aliases of + -- this register. + type GPIO_HI_OUT_Register is record + -- Output value for GPIO32...47 + GPIO : GPIO_HI_OUT_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Output value for USB D+ pin + USB_DP : Boolean := False; + -- Output value for USB D- pin + USB_DM : Boolean := False; + -- Output value for QSPI SCK pin + QSPI_SCK : Boolean := False; + -- Output value for QSPI CSn pin + QSPI_CSN : Boolean := False; + -- Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + QSPI_SD : GPIO_HI_OUT_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_SET_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_SET_QSPI_SD_Field is HAL.UInt4; + + -- Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + type GPIO_HI_OUT_SET_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_SET_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_SET_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_SET_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_CLR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_CLR_QSPI_SD_Field is HAL.UInt4; + + -- Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + type GPIO_HI_OUT_CLR_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_CLR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_CLR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_CLR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_XOR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_XOR_QSPI_SD_Field is HAL.UInt4; + + -- Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + type GPIO_HI_OUT_XOR_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_XOR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_XOR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_XOR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_QSPI_SD_Field is HAL.UInt4; + + -- Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output + -- enable (1/0 -> output/input). Reading back gives the last value written. + -- If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a + -- SET/CLR/XOR alias), the result is as though the write from core 0 took + -- place first, and the write from core 1 was then applied to that + -- intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per + -- ACCESSCTRL) ignore writes, and their output status reads back as zero. + -- This is also true for SET/CLR/XOR aliases of this register. + type GPIO_HI_OE_Register is record + -- Output enable value for GPIO32...47 + GPIO : GPIO_HI_OE_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Output enable value for USB D+ pin + USB_DP : Boolean := False; + -- Output enable value for USB D- pin + USB_DM : Boolean := False; + -- Output enable value for QSPI SCK pin + QSPI_SCK : Boolean := False; + -- Output enable value for QSPI CSn pin + QSPI_CSN : Boolean := False; + -- Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + QSPI_SD : GPIO_HI_OE_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_SET_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_SET_QSPI_SD_Field is HAL.UInt4; + + -- Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + type GPIO_HI_OE_SET_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_SET_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_SET_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_SET_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_CLR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_CLR_QSPI_SD_Field is HAL.UInt4; + + -- Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + type GPIO_HI_OE_CLR_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_CLR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_CLR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_CLR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_XOR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_XOR_QSPI_SD_Field is HAL.UInt4; + + -- Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + type GPIO_HI_OE_XOR_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_XOR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_XOR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_XOR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + -- Status register for inter-core FIFOs (mailboxes). There is one FIFO in + -- the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 + -- bits wide and 8 words deep. Core 0 can see the read side of the 1->0 + -- FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read + -- side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The + -- SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields + -- of its FIFO_ST register. + type FIFO_ST_Register is record + -- Read-only. Value is 1 if this core's RX FIFO is not empty (i.e. if + -- FIFO_RD is valid) + VLD : Boolean := False; + -- Read-only. Value is 1 if this core's TX FIFO is not full (i.e. if + -- FIFO_WR is ready for more data) + RDY : Boolean := True; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Sticky flag indicating the TX FIFO was written when + -- full. This write was ignored by the FIFO. + WOF : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Sticky flag indicating the RX FIFO was read when empty. + -- This read was ignored by the FIFO. + ROE : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIFO_ST_Register use record + VLD at 0 range 0 .. 0; + RDY at 0 range 1 .. 1; + WOF at 0 range 2 .. 2; + ROE at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype INTERP0_CTRL_LANE0_SHIFT_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2; + + -- INTERP0_CTRL_LANE0_OVERF array + type INTERP0_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for INTERP0_CTRL_LANE0_OVERF + type INTERP0_CTRL_LANE0_OVERF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OVERF as a value + Val : HAL.UInt3; + when True => + -- OVERF as an array + Arr : INTERP0_CTRL_LANE0_OVERF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for INTERP0_CTRL_LANE0_OVERF_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- Control register for lane 0 + type INTERP0_CTRL_LANE0_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP0_CTRL_LANE0_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP0_CTRL_LANE0_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP0_CTRL_LANE0_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE0 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP0_CTRL_LANE0_FORCE_MSB_Field := 16#0#; + -- Only present on INTERP0 on each core. If BLEND mode is enabled: - + -- LANE1 result is a linear interpolation between BASE0 and BASE1, + -- controlled by the 8 LSBs of lane 1 shift and mask value (a fractional + -- number between 0 and 255/256ths) - LANE0 result does not have BASE0 + -- added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL + -- result does not have lane 1 shift+mask value added (BASE2 + lane 0 + -- shift+mask) LANE1 SIGNED flag controls whether the interpolation is + -- signed or unsigned. + BLEND : Boolean := False; + -- unspecified + Reserved_22_22 : HAL.Bit := 16#0#; + -- Read-only. Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF : INTERP0_CTRL_LANE0_OVERF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_CTRL_LANE0_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + BLEND at 0 range 21 .. 21; + Reserved_22_22 at 0 range 22 .. 22; + OVERF at 0 range 23 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype INTERP0_CTRL_LANE1_SHIFT_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2; + + -- Control register for lane 1 + type INTERP0_CTRL_LANE1_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP0_CTRL_LANE1_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP0_CTRL_LANE1_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP0_CTRL_LANE1_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE1 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP0_CTRL_LANE1_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_CTRL_LANE1_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM0 Reading yields lane + -- 0's raw shift and mask value (BASE0 not added). + type INTERP0_ACCUM0_ADD_Register is record + INTERP0_ACCUM0_ADD : INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_ACCUM0_ADD_Register use record + INTERP0_ACCUM0_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM1 Reading yields lane + -- 1's raw shift and mask value (BASE1 not added). + type INTERP0_ACCUM1_ADD_Register is record + INTERP0_ACCUM1_ADD : INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_ACCUM1_ADD_Register use record + INTERP0_ACCUM1_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP1_CTRL_LANE0_SHIFT_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2; + + -- INTERP1_CTRL_LANE0_OVERF array + type INTERP1_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for INTERP1_CTRL_LANE0_OVERF + type INTERP1_CTRL_LANE0_OVERF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OVERF as a value + Val : HAL.UInt3; + when True => + -- OVERF as an array + Arr : INTERP1_CTRL_LANE0_OVERF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for INTERP1_CTRL_LANE0_OVERF_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- Control register for lane 0 + type INTERP1_CTRL_LANE0_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP1_CTRL_LANE0_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP1_CTRL_LANE0_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP1_CTRL_LANE0_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE0 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP1_CTRL_LANE0_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Only present on INTERP1 on each core. If CLAMP mode is enabled: - + -- LANE0 result is shifted and masked ACCUM0, clamped by a lower bound + -- of BASE0 and an upper bound of BASE1. - Signedness of these + -- comparisons is determined by LANE0_CTRL_SIGNED + CLAMP : Boolean := False; + -- Read-only. Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF : INTERP1_CTRL_LANE0_OVERF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_CTRL_LANE0_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + CLAMP at 0 range 22 .. 22; + OVERF at 0 range 23 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype INTERP1_CTRL_LANE1_SHIFT_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2; + + -- Control register for lane 1 + type INTERP1_CTRL_LANE1_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP1_CTRL_LANE1_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP1_CTRL_LANE1_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP1_CTRL_LANE1_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE1 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP1_CTRL_LANE1_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_CTRL_LANE1_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM0 Reading yields lane + -- 0's raw shift and mask value (BASE0 not added). + type INTERP1_ACCUM0_ADD_Register is record + INTERP1_ACCUM0_ADD : INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_ACCUM0_ADD_Register use record + INTERP1_ACCUM0_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM1 Reading yields lane + -- 1's raw shift and mask value (BASE1 not added). + type INTERP1_ACCUM1_ADD_Register is record + INTERP1_ACCUM1_ADD : INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_ACCUM1_ADD_Register use record + INTERP1_ACCUM1_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DOORBELL_OUT_SET_DOORBELL_OUT_SET_Field is HAL.UInt8; + + -- Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to + -- set the corresponding bit in DOORBELL_IN on the opposite core. This + -- raises the opposite core's doorbell interrupt. Read to get the status of + -- the doorbells currently asserted on the opposite core. This is + -- equivalent to that core reading its own DOORBELL_IN status. + type DOORBELL_OUT_SET_Register is record + DOORBELL_OUT_SET : DOORBELL_OUT_SET_DOORBELL_OUT_SET_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_OUT_SET_Register use record + DOORBELL_OUT_SET at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Field is HAL.UInt8; + + -- Clear doorbells which have been posted to the opposite core. This + -- register is intended for debugging and initialisation purposes. Writing + -- 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in + -- DOORBELL_IN on the opposite core. Clearing all bits will cause that + -- core's doorbell interrupt to deassert. Since the usual order of events + -- is for software to send events using DOORBELL_OUT_SET, and acknowledge + -- incoming events by writing to DOORBELL_IN_CLR, this register should be + -- used with caution to avoid race conditions. Reading returns the status + -- of the doorbells currently asserted on the other core, i.e. is + -- equivalent to that core reading its own DOORBELL_IN status. + type DOORBELL_OUT_CLR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + DOORBELL_OUT_CLR : DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_OUT_CLR_Register use record + DOORBELL_OUT_CLR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_IN_SET_DOORBELL_IN_SET_Field is HAL.UInt8; + + -- Write 1s to trigger doorbell interrupts on this core. Read to get status + -- of doorbells currently asserted on this core. + type DOORBELL_IN_SET_Register is record + DOORBELL_IN_SET : DOORBELL_IN_SET_DOORBELL_IN_SET_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_IN_SET_Register use record + DOORBELL_IN_SET at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_IN_CLR_DOORBELL_IN_CLR_Field is HAL.UInt8; + + -- Check and acknowledge doorbells posted to this core. This core's + -- doorbell interrupt is asserted when any bit in this register is 1. Write + -- 1 to each bit to clear that bit. The doorbell interrupt deasserts once + -- all bits are cleared. Read to get status of doorbells currently asserted + -- on this core. + type DOORBELL_IN_CLR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + DOORBELL_IN_CLR : DOORBELL_IN_CLR_DOORBELL_IN_CLR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_IN_CLR_Register use record + DOORBELL_IN_CLR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PERI_NONSEC_INTERP array + type PERI_NONSEC_INTERP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PERI_NONSEC_INTERP + type PERI_NONSEC_INTERP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- INTERP as a value + Val : HAL.UInt2; + when True => + -- INTERP as an array + Arr : PERI_NONSEC_INTERP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PERI_NONSEC_INTERP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Detach certain core-local peripherals from Secure SIO, and attach them + -- to Non-secure SIO, so that Non-secure software can use them. Attempting + -- to access one of these peripherals from the Secure SIO when it is + -- attached to the Non-secure SIO, or vice versa, will generate a bus + -- error. This register is per-core, and is only present on the Secure SIO. + -- Most SIO hardware is duplicated across the Secure and Non-secure SIO, so + -- is not listed in this register. + type PERI_NONSEC_Register is record + -- If 1, detach interpolator 0 (of this core) from the Secure SIO, and + -- attach to the Non-secure SIO. + INTERP : PERI_NONSEC_INTERP_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- IF 1, detach TMDS encoder (of this core) from the Secure SIO, and + -- attach to the Non-secure SIO. + TMDS : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERI_NONSEC_Register use record + INTERP at 0 range 0 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + TMDS at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Control the assertion of the standard software interrupt (MIP.MSIP) on + -- the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed + -- to a normal system-level interrupt line, so can not be used by the Arm + -- cores. It is safe for both cores to write to this register on the same + -- cycle. The set/clear effect is accumulated across both cores, and then + -- applied. If a flag is both set and cleared on the same cycle, only the + -- set takes effect. + type RISCV_SOFTIRQ_Register is record + -- Write 1 to atomically set the core 0 software interrupt flag. Read to + -- get the status of this flag. + CORE0_SET : Boolean := False; + -- Write 1 to atomically set the core 1 software interrupt flag. Read to + -- get the status of this flag. + CORE1_SET : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Write 1 to atomically clear the core 0 software interrupt flag. Read + -- to get the status of this flag. + CORE0_CLR : Boolean := False; + -- Write 1 to atomically clear the core 1 software interrupt flag. Read + -- to get the status of this flag. + CORE1_CLR : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RISCV_SOFTIRQ_Register use record + CORE0_SET at 0 range 0 .. 0; + CORE1_SET at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + CORE0_CLR at 0 range 8 .. 8; + CORE1_CLR at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- MTIME_CTRL_DBGPAUSE_CORE array + type MTIME_CTRL_DBGPAUSE_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for MTIME_CTRL_DBGPAUSE_CORE + type MTIME_CTRL_DBGPAUSE_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DBGPAUSE_CORE as a value + Val : HAL.UInt2; + when True => + -- DBGPAUSE_CORE as an array + Arr : MTIME_CTRL_DBGPAUSE_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for MTIME_CTRL_DBGPAUSE_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control register for the RISC-V 64-bit Machine-mode timer. This timer is + -- only present in the Secure SIO, so is only accessible to an Arm core in + -- Secure mode or a RISC-V core in Machine mode. Note whilst this timer + -- follows the RISC-V privileged specification, it is equally usable by the + -- Arm cores. The interrupts are routed to normal system-level interrupt + -- lines as well as to the MIP.MTIP inputs on the RISC-V cores. + type MTIME_CTRL_Register is record + -- Timer enable bit. When 0, the timer will not increment automatically. + EN : Boolean := True; + -- If 1, increment the timer every cycle (i.e. run directly from the + -- system clock), rather than incrementing on the system-level timer + -- tick input. + FULLSPEED : Boolean := False; + -- If 1, the timer pauses when core 0 is in the debug halt state. + DBGPAUSE_CORE : MTIME_CTRL_DBGPAUSE_CORE_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MTIME_CTRL_Register use record + EN at 0 range 0 .. 0; + FULLSPEED at 0 range 1 .. 1; + DBGPAUSE_CORE at 0 range 2 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TMDS_CTRL_L0_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L1_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L2_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L0_NBITS_Field is HAL.UInt3; + subtype TMDS_CTRL_L1_NBITS_Field is HAL.UInt3; + subtype TMDS_CTRL_L2_NBITS_Field is HAL.UInt3; + + -- Shift applied to the colour data register with each read of a POP alias + -- register. Reading from the POP_SINGLE register, or reading from the + -- POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts + -- by the indicated amount. Reading from a POP_DOUBLE register when + -- PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift + -- by 32 means no shift.) + type TMDS_CTRL_PIX_SHIFT_Field is + (-- Do not shift the colour data register. + Val_0, + -- Shift the colour data register by 1 bit + Val_1, + -- Shift the colour data register by 2 bits + Val_2, + -- Shift the colour data register by 4 bits + Val_4, + -- Shift the colour data register by 8 bits + Val_8, + -- Shift the colour data register by 16 bits + Val_16) + with Size => 3; + for TMDS_CTRL_PIX_SHIFT_Field use + (Val_0 => 0, + Val_1 => 1, + Val_2 => 2, + Val_4 => 3, + Val_8 => 4, + Val_16 => 5); + + -- Control register for TMDS encoder. + type TMDS_CTRL_Register is record + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 0 (blue) colour data aligned with + -- the MSB of the 8-bit encoder input. For example, for RGB565 (red most + -- significant), blue is bits 4:0, so should be right-rotated by 13 to + -- align with bits 7:3 of the encoder input. + L0_ROT : TMDS_CTRL_L0_ROT_Field := 16#0#; + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 1 (green) colour data aligned with + -- the MSB of the 8-bit encoder input. For example, for RGB565, green is + -- bits 10:5, so should be right-rotated by 3 bits to align with bits + -- 7:2 of the encoder input. + L1_ROT : TMDS_CTRL_L1_ROT_Field := 16#0#; + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 2 (red) colour data aligned with the + -- MSB of the 8-bit encoder input. For example, for RGB565 (red most + -- significant), red is bits 15:11, so should be right-rotated by 8 bits + -- to align with bits 7:3 of the encoder input. + L2_ROT : TMDS_CTRL_L2_ROT_Field := 16#0#; + -- Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L0_NBITS : TMDS_CTRL_L0_NBITS_Field := 16#0#; + -- Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L1_NBITS : TMDS_CTRL_L1_NBITS_Field := 16#0#; + -- Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L2_NBITS : TMDS_CTRL_L2_NBITS_Field := 16#0#; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When + -- interleaving is disabled, each of the 3 symbols appears as a + -- contiguous 10-bit field, with lane 0 being the least-significant and + -- starting at bit 0 of the register. When interleaving is enabled, the + -- symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits + -- total). Each chunk contains two bits of a TMDS symbol per lane, with + -- lane 0 being the least significant. + INTERLEAVE : Boolean := False; + -- Shift applied to the colour data register with each read of a POP + -- alias register. Reading from the POP_SINGLE register, or reading from + -- the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), + -- shifts by the indicated amount. Reading from a POP_DOUBLE register + -- when PIX2_NOSHIFT is clear will shift by double the indicated amount. + -- (Shift by 32 means no shift.) + PIX_SHIFT : TMDS_CTRL_PIX_SHIFT_Field := RP2350_SVD.SIO.Val_0; + -- When encoding two pixels's worth of symbols in one cycle (a read of a + -- PEEK/POP_DOUBLE register), the second encoder sees a shifted version + -- of the colour data register. This control disables that shift, so + -- that both encoder layers see the same pixel data. This is used for + -- pixel doubling. + PIX2_NOSHIFT : Boolean := False; + -- Write-only. Clear the running DC balance state of the TMDS encoders. + -- This bit should be written once at the beginning of each scanline. + CLEAR_BALANCE : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TMDS_CTRL_Register use record + L0_ROT at 0 range 0 .. 3; + L1_ROT at 0 range 4 .. 7; + L2_ROT at 0 range 8 .. 11; + L0_NBITS at 0 range 12 .. 14; + L1_NBITS at 0 range 15 .. 17; + L2_NBITS at 0 range 18 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + INTERLEAVE at 0 range 23 .. 23; + PIX_SHIFT at 0 range 24 .. 26; + PIX2_NOSHIFT at 0 range 27 .. 27; + CLEAR_BALANCE at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Single-cycle IO block Provides core-local and inter-core hardware for + -- the two processors, with single-cycle access. + type SIO_Peripheral is record + -- Processor core identifier + CPUID : aliased HAL.UInt32; + -- Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs + -- (as per ACCESSCTRL) appear as zero. + GPIO_IN : aliased HAL.UInt32; + -- Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure + -- SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + GPIO_HI_IN : aliased GPIO_HI_IN_Register; + -- GPIO0...31 output value + GPIO_OUT : aliased HAL.UInt32; + -- Output value for GPIO32...47, QSPI IOs and USB pins. Write to set + -- output level (1/0 -> high/low). Reading back gives the last value + -- written, NOT the input value from the pins. If core 0 and core 1 both + -- write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the + -- result is as though the write from core 0 took place first, and the + -- write from core 1 was then applied to that intermediate result. In + -- the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore + -- writes, and their output status reads back as zero. This is also true + -- for SET/CLR/XOR aliases of this register. + GPIO_HI_OUT : aliased GPIO_HI_OUT_Register; + -- GPIO0...31 output value set + GPIO_OUT_SET : aliased HAL.UInt32; + -- Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + GPIO_HI_OUT_SET : aliased GPIO_HI_OUT_SET_Register; + -- GPIO0...31 output value clear + GPIO_OUT_CLR : aliased HAL.UInt32; + -- Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + GPIO_HI_OUT_CLR : aliased GPIO_HI_OUT_CLR_Register; + -- GPIO0...31 output value XOR + GPIO_OUT_XOR : aliased HAL.UInt32; + -- Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + GPIO_HI_OUT_XOR : aliased GPIO_HI_OUT_XOR_Register; + -- GPIO0...31 output enable + GPIO_OE : aliased HAL.UInt32; + -- Output enable value for GPIO32...47, QSPI IOs and USB pins. Write + -- output enable (1/0 -> output/input). Reading back gives the last + -- value written. If core 0 and core 1 both write to GPIO_HI_OE + -- simultaneously (or to a SET/CLR/XOR alias), the result is as though + -- the write from core 0 took place first, and the write from core 1 was + -- then applied to that intermediate result. In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output + -- status reads back as zero. This is also true for SET/CLR/XOR aliases + -- of this register. + GPIO_HI_OE : aliased GPIO_HI_OE_Register; + -- GPIO0...31 output enable set + GPIO_OE_SET : aliased HAL.UInt32; + -- Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + GPIO_HI_OE_SET : aliased GPIO_HI_OE_SET_Register; + -- GPIO0...31 output enable clear + GPIO_OE_CLR : aliased HAL.UInt32; + -- Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform + -- an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + GPIO_HI_OE_CLR : aliased GPIO_HI_OE_CLR_Register; + -- GPIO0...31 output enable XOR + GPIO_OE_XOR : aliased HAL.UInt32; + -- Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + GPIO_HI_OE_XOR : aliased GPIO_HI_OE_XOR_Register; + -- Status register for inter-core FIFOs (mailboxes). There is one FIFO + -- in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are + -- 32 bits wide and 8 words deep. Core 0 can see the read side of the + -- 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see + -- the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + -- (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and + -- ROE fields of its FIFO_ST register. + FIFO_ST : aliased FIFO_ST_Register; + -- Write access to this core's TX FIFO + FIFO_WR : aliased HAL.UInt32; + -- Read access to this core's RX FIFO + FIFO_RD : aliased HAL.UInt32; + -- Spinlock state A bitmap containing the state of all 32 spinlocks + -- (1=locked). Mainly intended for debugging. + SPINLOCK_ST : aliased HAL.UInt32; + -- Read/write access to accumulator 0 + INTERP0_ACCUM0 : aliased HAL.UInt32; + -- Read/write access to accumulator 1 + INTERP0_ACCUM1 : aliased HAL.UInt32; + -- Read/write access to BASE0 register. + INTERP0_BASE0 : aliased HAL.UInt32; + -- Read/write access to BASE1 register. + INTERP0_BASE1 : aliased HAL.UInt32; + -- Read/write access to BASE2 register. + INTERP0_BASE2 : aliased HAL.UInt32; + -- Read LANE0 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_LANE1 : aliased HAL.UInt32; + -- Read FULL result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_FULL : aliased HAL.UInt32; + -- Read LANE0 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE1 : aliased HAL.UInt32; + -- Read FULL result, without altering any internal state (PEEK). + INTERP0_PEEK_FULL : aliased HAL.UInt32; + -- Control register for lane 0 + INTERP0_CTRL_LANE0 : aliased INTERP0_CTRL_LANE0_Register; + -- Control register for lane 1 + INTERP0_CTRL_LANE1 : aliased INTERP0_CTRL_LANE1_Register; + -- Values written here are atomically added to ACCUM0 Reading yields + -- lane 0's raw shift and mask value (BASE0 not added). + INTERP0_ACCUM0_ADD : aliased INTERP0_ACCUM0_ADD_Register; + -- Values written here are atomically added to ACCUM1 Reading yields + -- lane 1's raw shift and mask value (BASE1 not added). + INTERP0_ACCUM1_ADD : aliased INTERP0_ACCUM1_ADD_Register; + -- On write, the lower 16 bits go to BASE0, upper bits to BASE1 + -- simultaneously. Each half is sign-extended to 32 bits if that lane's + -- SIGNED flag is set. + INTERP0_BASE_1AND0 : aliased HAL.UInt32; + -- Read/write access to accumulator 0 + INTERP1_ACCUM0 : aliased HAL.UInt32; + -- Read/write access to accumulator 1 + INTERP1_ACCUM1 : aliased HAL.UInt32; + -- Read/write access to BASE0 register. + INTERP1_BASE0 : aliased HAL.UInt32; + -- Read/write access to BASE1 register. + INTERP1_BASE1 : aliased HAL.UInt32; + -- Read/write access to BASE2 register. + INTERP1_BASE2 : aliased HAL.UInt32; + -- Read LANE0 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_LANE1 : aliased HAL.UInt32; + -- Read FULL result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_FULL : aliased HAL.UInt32; + -- Read LANE0 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE1 : aliased HAL.UInt32; + -- Read FULL result, without altering any internal state (PEEK). + INTERP1_PEEK_FULL : aliased HAL.UInt32; + -- Control register for lane 0 + INTERP1_CTRL_LANE0 : aliased INTERP1_CTRL_LANE0_Register; + -- Control register for lane 1 + INTERP1_CTRL_LANE1 : aliased INTERP1_CTRL_LANE1_Register; + -- Values written here are atomically added to ACCUM0 Reading yields + -- lane 0's raw shift and mask value (BASE0 not added). + INTERP1_ACCUM0_ADD : aliased INTERP1_ACCUM0_ADD_Register; + -- Values written here are atomically added to ACCUM1 Reading yields + -- lane 1's raw shift and mask value (BASE1 not added). + INTERP1_ACCUM1_ADD : aliased INTERP1_ACCUM1_ADD_Register; + -- On write, the lower 16 bits go to BASE0, upper bits to BASE1 + -- simultaneously. Each half is sign-extended to 32 bits if that lane's + -- SIGNED flag is set. + INTERP1_BASE_1AND0 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK0 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK1 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK2 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK3 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK4 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK5 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK6 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK7 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK8 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK9 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK10 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK11 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK12 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK13 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK14 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK15 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK16 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK17 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK18 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK19 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK20 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK21 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK22 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK23 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK24 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK25 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK26 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK27 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK28 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK29 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK30 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK31 : aliased HAL.UInt32; + -- Trigger a doorbell interrupt on the opposite core. Write 1 to a bit + -- to set the corresponding bit in DOORBELL_IN on the opposite core. + -- This raises the opposite core's doorbell interrupt. Read to get the + -- status of the doorbells currently asserted on the opposite core. This + -- is equivalent to that core reading its own DOORBELL_IN status. + DOORBELL_OUT_SET : aliased DOORBELL_OUT_SET_Register; + -- Clear doorbells which have been posted to the opposite core. This + -- register is intended for debugging and initialisation purposes. + -- Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit + -- in DOORBELL_IN on the opposite core. Clearing all bits will cause + -- that core's doorbell interrupt to deassert. Since the usual order of + -- events is for software to send events using DOORBELL_OUT_SET, and + -- acknowledge incoming events by writing to DOORBELL_IN_CLR, this + -- register should be used with caution to avoid race conditions. + -- Reading returns the status of the doorbells currently asserted on the + -- other core, i.e. is equivalent to that core reading its own + -- DOORBELL_IN status. + DOORBELL_OUT_CLR : aliased DOORBELL_OUT_CLR_Register; + -- Write 1s to trigger doorbell interrupts on this core. Read to get + -- status of doorbells currently asserted on this core. + DOORBELL_IN_SET : aliased DOORBELL_IN_SET_Register; + -- Check and acknowledge doorbells posted to this core. This core's + -- doorbell interrupt is asserted when any bit in this register is 1. + -- Write 1 to each bit to clear that bit. The doorbell interrupt + -- deasserts once all bits are cleared. Read to get status of doorbells + -- currently asserted on this core. + DOORBELL_IN_CLR : aliased DOORBELL_IN_CLR_Register; + -- Detach certain core-local peripherals from Secure SIO, and attach + -- them to Non-secure SIO, so that Non-secure software can use them. + -- Attempting to access one of these peripherals from the Secure SIO + -- when it is attached to the Non-secure SIO, or vice versa, will + -- generate a bus error. This register is per-core, and is only present + -- on the Secure SIO. Most SIO hardware is duplicated across the Secure + -- and Non-secure SIO, so is not listed in this register. + PERI_NONSEC : aliased PERI_NONSEC_Register; + -- Control the assertion of the standard software interrupt (MIP.MSIP) + -- on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not + -- routed to a normal system-level interrupt line, so can not be used by + -- the Arm cores. It is safe for both cores to write to this register on + -- the same cycle. The set/clear effect is accumulated across both + -- cores, and then applied. If a flag is both set and cleared on the + -- same cycle, only the set takes effect. + RISCV_SOFTIRQ : aliased RISCV_SOFTIRQ_Register; + -- Control register for the RISC-V 64-bit Machine-mode timer. This timer + -- is only present in the Secure SIO, so is only accessible to an Arm + -- core in Secure mode or a RISC-V core in Machine mode. Note whilst + -- this timer follows the RISC-V privileged specification, it is equally + -- usable by the Arm cores. The interrupts are routed to normal + -- system-level interrupt lines as well as to the MIP.MTIP inputs on the + -- RISC-V cores. + MTIME_CTRL : aliased MTIME_CTRL_Register; + -- Read/write access to the high half of RISC-V Machine-mode timer. This + -- register is shared between both cores. If both cores write on the + -- same cycle, core 1 takes precedence. + MTIME : aliased HAL.UInt32; + -- Read/write access to the high half of RISC-V Machine-mode timer. This + -- register is shared between both cores. If both cores write on the + -- same cycle, core 1 takes precedence. + MTIMEH : aliased HAL.UInt32; + -- Low half of RISC-V Machine-mode timer comparator. This register is + -- core-local, i.e., each core gets a copy of this register, with the + -- comparison result routed to its own interrupt line. The timer + -- interrupt is asserted whenever MTIME is greater than or equal to + -- MTIMECMP. This comparison is unsigned, and performed on the full + -- 64-bit values. + MTIMECMP : aliased HAL.UInt32; + -- High half of RISC-V Machine-mode timer comparator. This register is + -- core-local. The timer interrupt is asserted whenever MTIME is greater + -- than or equal to MTIMECMP. This comparison is unsigned, and performed + -- on the full 64-bit values. + MTIMECMPH : aliased HAL.UInt32; + -- Control register for TMDS encoder. + TMDS_CTRL : aliased TMDS_CTRL_Register; + -- Write-only access to the TMDS colour data register. + TMDS_WDATA : aliased HAL.UInt32; + -- Get the encoding of one pixel's worth of colour data, packed into a + -- 32-bit value (3x10-bit symbols). The PEEK alias does not shift the + -- colour register when read, but still advances the running DC balance + -- state of each encoder. This is useful for pixel doubling. + TMDS_PEEK_SINGLE : aliased HAL.UInt32; + -- Get the encoding of one pixel's worth of colour data, packed into a + -- 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 + -- bits total). Each chunk contains two bits of a TMDS symbol per lane. + -- This format is intended for shifting out with the HSTX peripheral on + -- RP2350. The POP alias shifts the colour register when read, as well + -- as advancing the running DC balance state of each encoder. + TMDS_POP_SINGLE : aliased HAL.UInt32; + -- Get lane 0 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 0 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L0 : aliased HAL.UInt32; + -- Get lane 0 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L0 : aliased HAL.UInt32; + -- Get lane 1 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 1 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L1 : aliased HAL.UInt32; + -- Get lane 1 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L1 : aliased HAL.UInt32; + -- Get lane 2 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 2 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L2 : aliased HAL.UInt32; + -- Get lane 2 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L2 : aliased HAL.UInt32; + end record + with Volatile; + + for SIO_Peripheral use record + CPUID at 16#0# range 0 .. 31; + GPIO_IN at 16#4# range 0 .. 31; + GPIO_HI_IN at 16#8# range 0 .. 31; + GPIO_OUT at 16#10# range 0 .. 31; + GPIO_HI_OUT at 16#14# range 0 .. 31; + GPIO_OUT_SET at 16#18# range 0 .. 31; + GPIO_HI_OUT_SET at 16#1C# range 0 .. 31; + GPIO_OUT_CLR at 16#20# range 0 .. 31; + GPIO_HI_OUT_CLR at 16#24# range 0 .. 31; + GPIO_OUT_XOR at 16#28# range 0 .. 31; + GPIO_HI_OUT_XOR at 16#2C# range 0 .. 31; + GPIO_OE at 16#30# range 0 .. 31; + GPIO_HI_OE at 16#34# range 0 .. 31; + GPIO_OE_SET at 16#38# range 0 .. 31; + GPIO_HI_OE_SET at 16#3C# range 0 .. 31; + GPIO_OE_CLR at 16#40# range 0 .. 31; + GPIO_HI_OE_CLR at 16#44# range 0 .. 31; + GPIO_OE_XOR at 16#48# range 0 .. 31; + GPIO_HI_OE_XOR at 16#4C# range 0 .. 31; + FIFO_ST at 16#50# range 0 .. 31; + FIFO_WR at 16#54# range 0 .. 31; + FIFO_RD at 16#58# range 0 .. 31; + SPINLOCK_ST at 16#5C# range 0 .. 31; + INTERP0_ACCUM0 at 16#80# range 0 .. 31; + INTERP0_ACCUM1 at 16#84# range 0 .. 31; + INTERP0_BASE0 at 16#88# range 0 .. 31; + INTERP0_BASE1 at 16#8C# range 0 .. 31; + INTERP0_BASE2 at 16#90# range 0 .. 31; + INTERP0_POP_LANE0 at 16#94# range 0 .. 31; + INTERP0_POP_LANE1 at 16#98# range 0 .. 31; + INTERP0_POP_FULL at 16#9C# range 0 .. 31; + INTERP0_PEEK_LANE0 at 16#A0# range 0 .. 31; + INTERP0_PEEK_LANE1 at 16#A4# range 0 .. 31; + INTERP0_PEEK_FULL at 16#A8# range 0 .. 31; + INTERP0_CTRL_LANE0 at 16#AC# range 0 .. 31; + INTERP0_CTRL_LANE1 at 16#B0# range 0 .. 31; + INTERP0_ACCUM0_ADD at 16#B4# range 0 .. 31; + INTERP0_ACCUM1_ADD at 16#B8# range 0 .. 31; + INTERP0_BASE_1AND0 at 16#BC# range 0 .. 31; + INTERP1_ACCUM0 at 16#C0# range 0 .. 31; + INTERP1_ACCUM1 at 16#C4# range 0 .. 31; + INTERP1_BASE0 at 16#C8# range 0 .. 31; + INTERP1_BASE1 at 16#CC# range 0 .. 31; + INTERP1_BASE2 at 16#D0# range 0 .. 31; + INTERP1_POP_LANE0 at 16#D4# range 0 .. 31; + INTERP1_POP_LANE1 at 16#D8# range 0 .. 31; + INTERP1_POP_FULL at 16#DC# range 0 .. 31; + INTERP1_PEEK_LANE0 at 16#E0# range 0 .. 31; + INTERP1_PEEK_LANE1 at 16#E4# range 0 .. 31; + INTERP1_PEEK_FULL at 16#E8# range 0 .. 31; + INTERP1_CTRL_LANE0 at 16#EC# range 0 .. 31; + INTERP1_CTRL_LANE1 at 16#F0# range 0 .. 31; + INTERP1_ACCUM0_ADD at 16#F4# range 0 .. 31; + INTERP1_ACCUM1_ADD at 16#F8# range 0 .. 31; + INTERP1_BASE_1AND0 at 16#FC# range 0 .. 31; + SPINLOCK0 at 16#100# range 0 .. 31; + SPINLOCK1 at 16#104# range 0 .. 31; + SPINLOCK2 at 16#108# range 0 .. 31; + SPINLOCK3 at 16#10C# range 0 .. 31; + SPINLOCK4 at 16#110# range 0 .. 31; + SPINLOCK5 at 16#114# range 0 .. 31; + SPINLOCK6 at 16#118# range 0 .. 31; + SPINLOCK7 at 16#11C# range 0 .. 31; + SPINLOCK8 at 16#120# range 0 .. 31; + SPINLOCK9 at 16#124# range 0 .. 31; + SPINLOCK10 at 16#128# range 0 .. 31; + SPINLOCK11 at 16#12C# range 0 .. 31; + SPINLOCK12 at 16#130# range 0 .. 31; + SPINLOCK13 at 16#134# range 0 .. 31; + SPINLOCK14 at 16#138# range 0 .. 31; + SPINLOCK15 at 16#13C# range 0 .. 31; + SPINLOCK16 at 16#140# range 0 .. 31; + SPINLOCK17 at 16#144# range 0 .. 31; + SPINLOCK18 at 16#148# range 0 .. 31; + SPINLOCK19 at 16#14C# range 0 .. 31; + SPINLOCK20 at 16#150# range 0 .. 31; + SPINLOCK21 at 16#154# range 0 .. 31; + SPINLOCK22 at 16#158# range 0 .. 31; + SPINLOCK23 at 16#15C# range 0 .. 31; + SPINLOCK24 at 16#160# range 0 .. 31; + SPINLOCK25 at 16#164# range 0 .. 31; + SPINLOCK26 at 16#168# range 0 .. 31; + SPINLOCK27 at 16#16C# range 0 .. 31; + SPINLOCK28 at 16#170# range 0 .. 31; + SPINLOCK29 at 16#174# range 0 .. 31; + SPINLOCK30 at 16#178# range 0 .. 31; + SPINLOCK31 at 16#17C# range 0 .. 31; + DOORBELL_OUT_SET at 16#180# range 0 .. 31; + DOORBELL_OUT_CLR at 16#184# range 0 .. 31; + DOORBELL_IN_SET at 16#188# range 0 .. 31; + DOORBELL_IN_CLR at 16#18C# range 0 .. 31; + PERI_NONSEC at 16#190# range 0 .. 31; + RISCV_SOFTIRQ at 16#1A0# range 0 .. 31; + MTIME_CTRL at 16#1A4# range 0 .. 31; + MTIME at 16#1B0# range 0 .. 31; + MTIMEH at 16#1B4# range 0 .. 31; + MTIMECMP at 16#1B8# range 0 .. 31; + MTIMECMPH at 16#1BC# range 0 .. 31; + TMDS_CTRL at 16#1C0# range 0 .. 31; + TMDS_WDATA at 16#1C4# range 0 .. 31; + TMDS_PEEK_SINGLE at 16#1C8# range 0 .. 31; + TMDS_POP_SINGLE at 16#1CC# range 0 .. 31; + TMDS_PEEK_DOUBLE_L0 at 16#1D0# range 0 .. 31; + TMDS_POP_DOUBLE_L0 at 16#1D4# range 0 .. 31; + TMDS_PEEK_DOUBLE_L1 at 16#1D8# range 0 .. 31; + TMDS_POP_DOUBLE_L1 at 16#1DC# range 0 .. 31; + TMDS_PEEK_DOUBLE_L2 at 16#1E0# range 0 .. 31; + TMDS_POP_DOUBLE_L2 at 16#1E4# range 0 .. 31; + end record; + + -- Single-cycle IO block Provides core-local and inter-core hardware for + -- the two processors, with single-cycle access. + SIO_Periph : aliased SIO_Peripheral + with Import, Address => SIO_Base; + +end RP2350_SVD.SIO; diff --git a/src/svd/rp2350_svd-sio_ns.ads b/src/svd/rp2350_svd-sio_ns.ads new file mode 100644 index 0000000..091dbaa --- /dev/null +++ b/src/svd/rp2350_svd-sio_ns.ads @@ -0,0 +1,1669 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Single-cycle IO block +-- Provides core-local and inter-core hardware for the two +-- processors, with single-cycle access. +package RP2350_SVD.SIO_NS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype GPIO_HI_IN_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_IN_QSPI_SD_Field is HAL.UInt4; + + -- Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + type GPIO_HI_IN_Register is record + -- Read-only. Input value on GPIO32...47 + GPIO : GPIO_HI_IN_GPIO_Field; + -- unspecified + Reserved_16_23 : HAL.UInt8; + -- Read-only. Input value on USB D+ pin + USB_DP : Boolean; + -- Read-only. Input value on USB D- pin + USB_DM : Boolean; + -- Read-only. Input value on QSPI SCK pin + QSPI_SCK : Boolean; + -- Read-only. Input value on QSPI CSn pin + QSPI_CSN : Boolean; + -- Read-only. Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 + -- pins + QSPI_SD : GPIO_HI_IN_QSPI_SD_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_IN_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_QSPI_SD_Field is HAL.UInt4; + + -- Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output + -- level (1/0 -> high/low). Reading back gives the last value written, NOT + -- the input value from the pins. If core 0 and core 1 both write to + -- GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as + -- though the write from core 0 took place first, and the write from core 1 + -- was then applied to that intermediate result. In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output + -- status reads back as zero. This is also true for SET/CLR/XOR aliases of + -- this register. + type GPIO_HI_OUT_Register is record + -- Output value for GPIO32...47 + GPIO : GPIO_HI_OUT_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Output value for USB D+ pin + USB_DP : Boolean := False; + -- Output value for USB D- pin + USB_DM : Boolean := False; + -- Output value for QSPI SCK pin + QSPI_SCK : Boolean := False; + -- Output value for QSPI CSn pin + QSPI_CSN : Boolean := False; + -- Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + QSPI_SD : GPIO_HI_OUT_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_SET_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_SET_QSPI_SD_Field is HAL.UInt4; + + -- Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + type GPIO_HI_OUT_SET_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_SET_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_SET_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_SET_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_CLR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_CLR_QSPI_SD_Field is HAL.UInt4; + + -- Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + type GPIO_HI_OUT_CLR_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_CLR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_CLR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_CLR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OUT_XOR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OUT_XOR_QSPI_SD_Field is HAL.UInt4; + + -- Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + type GPIO_HI_OUT_XOR_Register is record + -- Write-only. + GPIO : GPIO_HI_OUT_XOR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OUT_XOR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OUT_XOR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_QSPI_SD_Field is HAL.UInt4; + + -- Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output + -- enable (1/0 -> output/input). Reading back gives the last value written. + -- If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a + -- SET/CLR/XOR alias), the result is as though the write from core 0 took + -- place first, and the write from core 1 was then applied to that + -- intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per + -- ACCESSCTRL) ignore writes, and their output status reads back as zero. + -- This is also true for SET/CLR/XOR aliases of this register. + type GPIO_HI_OE_Register is record + -- Output enable value for GPIO32...47 + GPIO : GPIO_HI_OE_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Output enable value for USB D+ pin + USB_DP : Boolean := False; + -- Output enable value for USB D- pin + USB_DM : Boolean := False; + -- Output enable value for QSPI SCK pin + QSPI_SCK : Boolean := False; + -- Output enable value for QSPI CSn pin + QSPI_CSN : Boolean := False; + -- Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + QSPI_SD : GPIO_HI_OE_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_SET_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_SET_QSPI_SD_Field is HAL.UInt4; + + -- Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + type GPIO_HI_OE_SET_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_SET_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_SET_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_SET_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_CLR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_CLR_QSPI_SD_Field is HAL.UInt4; + + -- Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + type GPIO_HI_OE_CLR_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_CLR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_CLR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_CLR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + subtype GPIO_HI_OE_XOR_GPIO_Field is HAL.UInt16; + subtype GPIO_HI_OE_XOR_QSPI_SD_Field is HAL.UInt4; + + -- Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + type GPIO_HI_OE_XOR_Register is record + -- Write-only. + GPIO : GPIO_HI_OE_XOR_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- Write-only. + USB_DP : Boolean := False; + -- Write-only. + USB_DM : Boolean := False; + -- Write-only. + QSPI_SCK : Boolean := False; + -- Write-only. + QSPI_CSN : Boolean := False; + -- Write-only. + QSPI_SD : GPIO_HI_OE_XOR_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for GPIO_HI_OE_XOR_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + -- Status register for inter-core FIFOs (mailboxes). There is one FIFO in + -- the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 + -- bits wide and 8 words deep. Core 0 can see the read side of the 1->0 + -- FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read + -- side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The + -- SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields + -- of its FIFO_ST register. + type FIFO_ST_Register is record + -- Read-only. Value is 1 if this core's RX FIFO is not empty (i.e. if + -- FIFO_RD is valid) + VLD : Boolean := False; + -- Read-only. Value is 1 if this core's TX FIFO is not full (i.e. if + -- FIFO_WR is ready for more data) + RDY : Boolean := True; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Sticky flag indicating the TX FIFO was written when + -- full. This write was ignored by the FIFO. + WOF : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Sticky flag indicating the RX FIFO was read when empty. + -- This read was ignored by the FIFO. + ROE : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for FIFO_ST_Register use record + VLD at 0 range 0 .. 0; + RDY at 0 range 1 .. 1; + WOF at 0 range 2 .. 2; + ROE at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype INTERP0_CTRL_LANE0_SHIFT_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2; + + -- INTERP0_CTRL_LANE0_OVERF array + type INTERP0_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for INTERP0_CTRL_LANE0_OVERF + type INTERP0_CTRL_LANE0_OVERF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OVERF as a value + Val : HAL.UInt3; + when True => + -- OVERF as an array + Arr : INTERP0_CTRL_LANE0_OVERF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for INTERP0_CTRL_LANE0_OVERF_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- Control register for lane 0 + type INTERP0_CTRL_LANE0_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP0_CTRL_LANE0_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP0_CTRL_LANE0_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP0_CTRL_LANE0_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE0 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP0_CTRL_LANE0_FORCE_MSB_Field := 16#0#; + -- Only present on INTERP0 on each core. If BLEND mode is enabled: - + -- LANE1 result is a linear interpolation between BASE0 and BASE1, + -- controlled by the 8 LSBs of lane 1 shift and mask value (a fractional + -- number between 0 and 255/256ths) - LANE0 result does not have BASE0 + -- added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL + -- result does not have lane 1 shift+mask value added (BASE2 + lane 0 + -- shift+mask) LANE1 SIGNED flag controls whether the interpolation is + -- signed or unsigned. + BLEND : Boolean := False; + -- unspecified + Reserved_22_22 : HAL.Bit := 16#0#; + -- Read-only. Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF : INTERP0_CTRL_LANE0_OVERF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_CTRL_LANE0_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + BLEND at 0 range 21 .. 21; + Reserved_22_22 at 0 range 22 .. 22; + OVERF at 0 range 23 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype INTERP0_CTRL_LANE1_SHIFT_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5; + subtype INTERP0_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2; + + -- Control register for lane 1 + type INTERP0_CTRL_LANE1_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP0_CTRL_LANE1_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP0_CTRL_LANE1_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP0_CTRL_LANE1_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE1 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP0_CTRL_LANE1_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_CTRL_LANE1_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM0 Reading yields lane + -- 0's raw shift and mask value (BASE0 not added). + type INTERP0_ACCUM0_ADD_Register is record + INTERP0_ACCUM0_ADD : INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_ACCUM0_ADD_Register use record + INTERP0_ACCUM0_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM1 Reading yields lane + -- 1's raw shift and mask value (BASE1 not added). + type INTERP0_ACCUM1_ADD_Register is record + INTERP0_ACCUM1_ADD : INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP0_ACCUM1_ADD_Register use record + INTERP0_ACCUM1_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP1_CTRL_LANE0_SHIFT_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_MASK_LSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_MASK_MSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE0_FORCE_MSB_Field is HAL.UInt2; + + -- INTERP1_CTRL_LANE0_OVERF array + type INTERP1_CTRL_LANE0_OVERF_Field_Array is array (0 .. 2) of Boolean + with Component_Size => 1, Size => 3; + + -- Type definition for INTERP1_CTRL_LANE0_OVERF + type INTERP1_CTRL_LANE0_OVERF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OVERF as a value + Val : HAL.UInt3; + when True => + -- OVERF as an array + Arr : INTERP1_CTRL_LANE0_OVERF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 3; + + for INTERP1_CTRL_LANE0_OVERF_Field use record + Val at 0 range 0 .. 2; + Arr at 0 range 0 .. 2; + end record; + + -- Control register for lane 0 + type INTERP1_CTRL_LANE0_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP1_CTRL_LANE0_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP1_CTRL_LANE0_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP1_CTRL_LANE0_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE0 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP1_CTRL_LANE0_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_21 : HAL.Bit := 16#0#; + -- Only present on INTERP1 on each core. If CLAMP mode is enabled: - + -- LANE0 result is shifted and masked ACCUM0, clamped by a lower bound + -- of BASE0 and an upper bound of BASE1. - Signedness of these + -- comparisons is determined by LANE0_CTRL_SIGNED + CLAMP : Boolean := False; + -- Read-only. Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF : INTERP1_CTRL_LANE0_OVERF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_CTRL_LANE0_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_21 at 0 range 21 .. 21; + CLAMP at 0 range 22 .. 22; + OVERF at 0 range 23 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype INTERP1_CTRL_LANE1_SHIFT_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_MASK_LSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_MASK_MSB_Field is HAL.UInt5; + subtype INTERP1_CTRL_LANE1_FORCE_MSB_Field is HAL.UInt2; + + -- Control register for lane 1 + type INTERP1_CTRL_LANE1_Register is record + -- Right-rotate applied to accumulator before masking. By appropriately + -- configuring the masks, left and right shifts can be synthesised. + SHIFT : INTERP1_CTRL_LANE1_SHIFT_Field := 16#0#; + -- The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB : INTERP1_CTRL_LANE1_MASK_LSB_Field := 16#0#; + -- The most-significant bit allowed to pass by the mask (inclusive) + -- Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB : INTERP1_CTRL_LANE1_MASK_MSB_Field := 16#0#; + -- If SIGNED is set, the shifted and masked accumulator value is + -- sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP + -- appear extended to 32 bits when read by processor. + SIGNED : Boolean := False; + -- If 1, feed the opposite lane's accumulator into this lane's shift + + -- mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT + -- mux is before the shift+mask bypass) + CROSS_INPUT : Boolean := False; + -- If 1, feed the opposite lane's result into this lane's accumulator on + -- POP. + CROSS_RESULT : Boolean := False; + -- If 1, mask + shift is bypassed for LANE1 result. This does not affect + -- FULL result. + ADD_RAW : Boolean := False; + -- ORed into bits 29:28 of the lane result presented to the processor on + -- the bus. No effect on the internal 32-bit datapath. Handy for using a + -- lane to generate sequence of pointers into flash or SRAM. + FORCE_MSB : INTERP1_CTRL_LANE1_FORCE_MSB_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_CTRL_LANE1_Register use record + SHIFT at 0 range 0 .. 4; + MASK_LSB at 0 range 5 .. 9; + MASK_MSB at 0 range 10 .. 14; + SIGNED at 0 range 15 .. 15; + CROSS_INPUT at 0 range 16 .. 16; + CROSS_RESULT at 0 range 17 .. 17; + ADD_RAW at 0 range 18 .. 18; + FORCE_MSB at 0 range 19 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM0 Reading yields lane + -- 0's raw shift and mask value (BASE0 not added). + type INTERP1_ACCUM0_ADD_Register is record + INTERP1_ACCUM0_ADD : INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_ACCUM0_ADD_Register use record + INTERP1_ACCUM0_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field is HAL.UInt24; + + -- Values written here are atomically added to ACCUM1 Reading yields lane + -- 1's raw shift and mask value (BASE1 not added). + type INTERP1_ACCUM1_ADD_Register is record + INTERP1_ACCUM1_ADD : INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Field := + 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTERP1_ACCUM1_ADD_Register use record + INTERP1_ACCUM1_ADD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype DOORBELL_OUT_SET_DOORBELL_OUT_SET_Field is HAL.UInt8; + + -- Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to + -- set the corresponding bit in DOORBELL_IN on the opposite core. This + -- raises the opposite core's doorbell interrupt. Read to get the status of + -- the doorbells currently asserted on the opposite core. This is + -- equivalent to that core reading its own DOORBELL_IN status. + type DOORBELL_OUT_SET_Register is record + DOORBELL_OUT_SET : DOORBELL_OUT_SET_DOORBELL_OUT_SET_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_OUT_SET_Register use record + DOORBELL_OUT_SET at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Field is HAL.UInt8; + + -- Clear doorbells which have been posted to the opposite core. This + -- register is intended for debugging and initialisation purposes. Writing + -- 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in + -- DOORBELL_IN on the opposite core. Clearing all bits will cause that + -- core's doorbell interrupt to deassert. Since the usual order of events + -- is for software to send events using DOORBELL_OUT_SET, and acknowledge + -- incoming events by writing to DOORBELL_IN_CLR, this register should be + -- used with caution to avoid race conditions. Reading returns the status + -- of the doorbells currently asserted on the other core, i.e. is + -- equivalent to that core reading its own DOORBELL_IN status. + type DOORBELL_OUT_CLR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + DOORBELL_OUT_CLR : DOORBELL_OUT_CLR_DOORBELL_OUT_CLR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_OUT_CLR_Register use record + DOORBELL_OUT_CLR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_IN_SET_DOORBELL_IN_SET_Field is HAL.UInt8; + + -- Write 1s to trigger doorbell interrupts on this core. Read to get status + -- of doorbells currently asserted on this core. + type DOORBELL_IN_SET_Register is record + DOORBELL_IN_SET : DOORBELL_IN_SET_DOORBELL_IN_SET_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_IN_SET_Register use record + DOORBELL_IN_SET at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype DOORBELL_IN_CLR_DOORBELL_IN_CLR_Field is HAL.UInt8; + + -- Check and acknowledge doorbells posted to this core. This core's + -- doorbell interrupt is asserted when any bit in this register is 1. Write + -- 1 to each bit to clear that bit. The doorbell interrupt deasserts once + -- all bits are cleared. Read to get status of doorbells currently asserted + -- on this core. + type DOORBELL_IN_CLR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + DOORBELL_IN_CLR : DOORBELL_IN_CLR_DOORBELL_IN_CLR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DOORBELL_IN_CLR_Register use record + DOORBELL_IN_CLR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PERI_NONSEC_INTERP array + type PERI_NONSEC_INTERP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PERI_NONSEC_INTERP + type PERI_NONSEC_INTERP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- INTERP as a value + Val : HAL.UInt2; + when True => + -- INTERP as an array + Arr : PERI_NONSEC_INTERP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PERI_NONSEC_INTERP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Detach certain core-local peripherals from Secure SIO, and attach them + -- to Non-secure SIO, so that Non-secure software can use them. Attempting + -- to access one of these peripherals from the Secure SIO when it is + -- attached to the Non-secure SIO, or vice versa, will generate a bus + -- error. This register is per-core, and is only present on the Secure SIO. + -- Most SIO hardware is duplicated across the Secure and Non-secure SIO, so + -- is not listed in this register. + type PERI_NONSEC_Register is record + -- If 1, detach interpolator 0 (of this core) from the Secure SIO, and + -- attach to the Non-secure SIO. + INTERP : PERI_NONSEC_INTERP_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- IF 1, detach TMDS encoder (of this core) from the Secure SIO, and + -- attach to the Non-secure SIO. + TMDS : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PERI_NONSEC_Register use record + INTERP at 0 range 0 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + TMDS at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Control the assertion of the standard software interrupt (MIP.MSIP) on + -- the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed + -- to a normal system-level interrupt line, so can not be used by the Arm + -- cores. It is safe for both cores to write to this register on the same + -- cycle. The set/clear effect is accumulated across both cores, and then + -- applied. If a flag is both set and cleared on the same cycle, only the + -- set takes effect. + type RISCV_SOFTIRQ_Register is record + -- Write 1 to atomically set the core 0 software interrupt flag. Read to + -- get the status of this flag. + CORE0_SET : Boolean := False; + -- Write 1 to atomically set the core 1 software interrupt flag. Read to + -- get the status of this flag. + CORE1_SET : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Write 1 to atomically clear the core 0 software interrupt flag. Read + -- to get the status of this flag. + CORE0_CLR : Boolean := False; + -- Write 1 to atomically clear the core 1 software interrupt flag. Read + -- to get the status of this flag. + CORE1_CLR : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RISCV_SOFTIRQ_Register use record + CORE0_SET at 0 range 0 .. 0; + CORE1_SET at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + CORE0_CLR at 0 range 8 .. 8; + CORE1_CLR at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- MTIME_CTRL_DBGPAUSE_CORE array + type MTIME_CTRL_DBGPAUSE_CORE_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for MTIME_CTRL_DBGPAUSE_CORE + type MTIME_CTRL_DBGPAUSE_CORE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DBGPAUSE_CORE as a value + Val : HAL.UInt2; + when True => + -- DBGPAUSE_CORE as an array + Arr : MTIME_CTRL_DBGPAUSE_CORE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for MTIME_CTRL_DBGPAUSE_CORE_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Control register for the RISC-V 64-bit Machine-mode timer. This timer is + -- only present in the Secure SIO, so is only accessible to an Arm core in + -- Secure mode or a RISC-V core in Machine mode. Note whilst this timer + -- follows the RISC-V privileged specification, it is equally usable by the + -- Arm cores. The interrupts are routed to normal system-level interrupt + -- lines as well as to the MIP.MTIP inputs on the RISC-V cores. + type MTIME_CTRL_Register is record + -- Timer enable bit. When 0, the timer will not increment automatically. + EN : Boolean := True; + -- If 1, increment the timer every cycle (i.e. run directly from the + -- system clock), rather than incrementing on the system-level timer + -- tick input. + FULLSPEED : Boolean := False; + -- If 1, the timer pauses when core 0 is in the debug halt state. + DBGPAUSE_CORE : MTIME_CTRL_DBGPAUSE_CORE_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MTIME_CTRL_Register use record + EN at 0 range 0 .. 0; + FULLSPEED at 0 range 1 .. 1; + DBGPAUSE_CORE at 0 range 2 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TMDS_CTRL_L0_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L1_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L2_ROT_Field is HAL.UInt4; + subtype TMDS_CTRL_L0_NBITS_Field is HAL.UInt3; + subtype TMDS_CTRL_L1_NBITS_Field is HAL.UInt3; + subtype TMDS_CTRL_L2_NBITS_Field is HAL.UInt3; + + -- Shift applied to the colour data register with each read of a POP alias + -- register. Reading from the POP_SINGLE register, or reading from the + -- POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts + -- by the indicated amount. Reading from a POP_DOUBLE register when + -- PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift + -- by 32 means no shift.) + type TMDS_CTRL_PIX_SHIFT_Field is + (-- Do not shift the colour data register. + Val_0, + -- Shift the colour data register by 1 bit + Val_1, + -- Shift the colour data register by 2 bits + Val_2, + -- Shift the colour data register by 4 bits + Val_4, + -- Shift the colour data register by 8 bits + Val_8, + -- Shift the colour data register by 16 bits + Val_16) + with Size => 3; + for TMDS_CTRL_PIX_SHIFT_Field use + (Val_0 => 0, + Val_1 => 1, + Val_2 => 2, + Val_4 => 3, + Val_8 => 4, + Val_16 => 5); + + -- Control register for TMDS encoder. + type TMDS_CTRL_Register is record + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 0 (blue) colour data aligned with + -- the MSB of the 8-bit encoder input. For example, for RGB565 (red most + -- significant), blue is bits 4:0, so should be right-rotated by 13 to + -- align with bits 7:3 of the encoder input. + L0_ROT : TMDS_CTRL_L0_ROT_Field := 16#0#; + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 1 (green) colour data aligned with + -- the MSB of the 8-bit encoder input. For example, for RGB565, green is + -- bits 10:5, so should be right-rotated by 3 bits to align with bits + -- 7:2 of the encoder input. + L1_ROT : TMDS_CTRL_L1_ROT_Field := 16#0#; + -- Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in + -- order to get the MSB of the lane 2 (red) colour data aligned with the + -- MSB of the 8-bit encoder input. For example, for RGB565 (red most + -- significant), red is bits 15:11, so should be right-rotated by 8 bits + -- to align with bits 7:3 of the encoder input. + L2_ROT : TMDS_CTRL_L2_ROT_Field := 16#0#; + -- Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L0_NBITS : TMDS_CTRL_L0_NBITS_Field := 16#0#; + -- Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L1_NBITS : TMDS_CTRL_L1_NBITS_Field := 16#0#; + -- Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 + -- through 7). Remaining LSBs are masked to 0 after the rotate. + L2_NBITS : TMDS_CTRL_L2_NBITS_Field := 16#0#; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When + -- interleaving is disabled, each of the 3 symbols appears as a + -- contiguous 10-bit field, with lane 0 being the least-significant and + -- starting at bit 0 of the register. When interleaving is enabled, the + -- symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits + -- total). Each chunk contains two bits of a TMDS symbol per lane, with + -- lane 0 being the least significant. + INTERLEAVE : Boolean := False; + -- Shift applied to the colour data register with each read of a POP + -- alias register. Reading from the POP_SINGLE register, or reading from + -- the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), + -- shifts by the indicated amount. Reading from a POP_DOUBLE register + -- when PIX2_NOSHIFT is clear will shift by double the indicated amount. + -- (Shift by 32 means no shift.) + PIX_SHIFT : TMDS_CTRL_PIX_SHIFT_Field := RP2350_SVD.SIO_NS.Val_0; + -- When encoding two pixels's worth of symbols in one cycle (a read of a + -- PEEK/POP_DOUBLE register), the second encoder sees a shifted version + -- of the colour data register. This control disables that shift, so + -- that both encoder layers see the same pixel data. This is used for + -- pixel doubling. + PIX2_NOSHIFT : Boolean := False; + -- Write-only. Clear the running DC balance state of the TMDS encoders. + -- This bit should be written once at the beginning of each scanline. + CLEAR_BALANCE : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TMDS_CTRL_Register use record + L0_ROT at 0 range 0 .. 3; + L1_ROT at 0 range 4 .. 7; + L2_ROT at 0 range 8 .. 11; + L0_NBITS at 0 range 12 .. 14; + L1_NBITS at 0 range 15 .. 17; + L2_NBITS at 0 range 18 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + INTERLEAVE at 0 range 23 .. 23; + PIX_SHIFT at 0 range 24 .. 26; + PIX2_NOSHIFT at 0 range 27 .. 27; + CLEAR_BALANCE at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Single-cycle IO block Provides core-local and inter-core hardware for + -- the two processors, with single-cycle access. + type SIO_NS_Peripheral is record + -- Processor core identifier + CPUID : aliased HAL.UInt32; + -- Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs + -- (as per ACCESSCTRL) appear as zero. + GPIO_IN : aliased HAL.UInt32; + -- Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure + -- SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + GPIO_HI_IN : aliased GPIO_HI_IN_Register; + -- GPIO0...31 output value + GPIO_OUT : aliased HAL.UInt32; + -- Output value for GPIO32...47, QSPI IOs and USB pins. Write to set + -- output level (1/0 -> high/low). Reading back gives the last value + -- written, NOT the input value from the pins. If core 0 and core 1 both + -- write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the + -- result is as though the write from core 0 took place first, and the + -- write from core 1 was then applied to that intermediate result. In + -- the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore + -- writes, and their output status reads back as zero. This is also true + -- for SET/CLR/XOR aliases of this register. + GPIO_HI_OUT : aliased GPIO_HI_OUT_Register; + -- GPIO0...31 output value set + GPIO_OUT_SET : aliased HAL.UInt32; + -- Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + GPIO_HI_OUT_SET : aliased GPIO_HI_OUT_SET_Register; + -- GPIO0...31 output value clear + GPIO_OUT_CLR : aliased HAL.UInt32; + -- Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + GPIO_HI_OUT_CLR : aliased GPIO_HI_OUT_CLR_Register; + -- GPIO0...31 output value XOR + GPIO_OUT_XOR : aliased HAL.UInt32; + -- Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + GPIO_HI_OUT_XOR : aliased GPIO_HI_OUT_XOR_Register; + -- GPIO0...31 output enable + GPIO_OE : aliased HAL.UInt32; + -- Output enable value for GPIO32...47, QSPI IOs and USB pins. Write + -- output enable (1/0 -> output/input). Reading back gives the last + -- value written. If core 0 and core 1 both write to GPIO_HI_OE + -- simultaneously (or to a SET/CLR/XOR alias), the result is as though + -- the write from core 0 took place first, and the write from core 1 was + -- then applied to that intermediate result. In the Non-secure SIO, + -- Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output + -- status reads back as zero. This is also true for SET/CLR/XOR aliases + -- of this register. + GPIO_HI_OE : aliased GPIO_HI_OE_Register; + -- GPIO0...31 output enable set + GPIO_OE_SET : aliased HAL.UInt32; + -- Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + GPIO_HI_OE_SET : aliased GPIO_HI_OE_SET_Register; + -- GPIO0...31 output enable clear + GPIO_OE_CLR : aliased HAL.UInt32; + -- Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform + -- an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + GPIO_HI_OE_CLR : aliased GPIO_HI_OE_CLR_Register; + -- GPIO0...31 output enable XOR + GPIO_OE_XOR : aliased HAL.UInt32; + -- Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an + -- atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + GPIO_HI_OE_XOR : aliased GPIO_HI_OE_XOR_Register; + -- Status register for inter-core FIFOs (mailboxes). There is one FIFO + -- in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are + -- 32 bits wide and 8 words deep. Core 0 can see the read side of the + -- 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see + -- the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + -- (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and + -- ROE fields of its FIFO_ST register. + FIFO_ST : aliased FIFO_ST_Register; + -- Write access to this core's TX FIFO + FIFO_WR : aliased HAL.UInt32; + -- Read access to this core's RX FIFO + FIFO_RD : aliased HAL.UInt32; + -- Spinlock state A bitmap containing the state of all 32 spinlocks + -- (1=locked). Mainly intended for debugging. + SPINLOCK_ST : aliased HAL.UInt32; + -- Read/write access to accumulator 0 + INTERP0_ACCUM0 : aliased HAL.UInt32; + -- Read/write access to accumulator 1 + INTERP0_ACCUM1 : aliased HAL.UInt32; + -- Read/write access to BASE0 register. + INTERP0_BASE0 : aliased HAL.UInt32; + -- Read/write access to BASE1 register. + INTERP0_BASE1 : aliased HAL.UInt32; + -- Read/write access to BASE2 register. + INTERP0_BASE2 : aliased HAL.UInt32; + -- Read LANE0 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_LANE1 : aliased HAL.UInt32; + -- Read FULL result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP0_POP_FULL : aliased HAL.UInt32; + -- Read LANE0 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, without altering any internal state (PEEK). + INTERP0_PEEK_LANE1 : aliased HAL.UInt32; + -- Read FULL result, without altering any internal state (PEEK). + INTERP0_PEEK_FULL : aliased HAL.UInt32; + -- Control register for lane 0 + INTERP0_CTRL_LANE0 : aliased INTERP0_CTRL_LANE0_Register; + -- Control register for lane 1 + INTERP0_CTRL_LANE1 : aliased INTERP0_CTRL_LANE1_Register; + -- Values written here are atomically added to ACCUM0 Reading yields + -- lane 0's raw shift and mask value (BASE0 not added). + INTERP0_ACCUM0_ADD : aliased INTERP0_ACCUM0_ADD_Register; + -- Values written here are atomically added to ACCUM1 Reading yields + -- lane 1's raw shift and mask value (BASE1 not added). + INTERP0_ACCUM1_ADD : aliased INTERP0_ACCUM1_ADD_Register; + -- On write, the lower 16 bits go to BASE0, upper bits to BASE1 + -- simultaneously. Each half is sign-extended to 32 bits if that lane's + -- SIGNED flag is set. + INTERP0_BASE_1AND0 : aliased HAL.UInt32; + -- Read/write access to accumulator 0 + INTERP1_ACCUM0 : aliased HAL.UInt32; + -- Read/write access to accumulator 1 + INTERP1_ACCUM1 : aliased HAL.UInt32; + -- Read/write access to BASE0 register. + INTERP1_BASE0 : aliased HAL.UInt32; + -- Read/write access to BASE1 register. + INTERP1_BASE1 : aliased HAL.UInt32; + -- Read/write access to BASE2 register. + INTERP1_BASE2 : aliased HAL.UInt32; + -- Read LANE0 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_LANE1 : aliased HAL.UInt32; + -- Read FULL result, and simultaneously write lane results to both + -- accumulators (POP). + INTERP1_POP_FULL : aliased HAL.UInt32; + -- Read LANE0 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE0 : aliased HAL.UInt32; + -- Read LANE1 result, without altering any internal state (PEEK). + INTERP1_PEEK_LANE1 : aliased HAL.UInt32; + -- Read FULL result, without altering any internal state (PEEK). + INTERP1_PEEK_FULL : aliased HAL.UInt32; + -- Control register for lane 0 + INTERP1_CTRL_LANE0 : aliased INTERP1_CTRL_LANE0_Register; + -- Control register for lane 1 + INTERP1_CTRL_LANE1 : aliased INTERP1_CTRL_LANE1_Register; + -- Values written here are atomically added to ACCUM0 Reading yields + -- lane 0's raw shift and mask value (BASE0 not added). + INTERP1_ACCUM0_ADD : aliased INTERP1_ACCUM0_ADD_Register; + -- Values written here are atomically added to ACCUM1 Reading yields + -- lane 1's raw shift and mask value (BASE1 not added). + INTERP1_ACCUM1_ADD : aliased INTERP1_ACCUM1_ADD_Register; + -- On write, the lower 16 bits go to BASE0, upper bits to BASE1 + -- simultaneously. Each half is sign-extended to 32 bits if that lane's + -- SIGNED flag is set. + INTERP1_BASE_1AND0 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK0 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK1 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK2 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK3 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK4 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK5 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK6 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK7 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK8 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK9 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK10 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK11 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK12 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK13 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK14 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK15 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK16 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK17 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK18 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK19 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK20 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK21 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK22 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK23 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK24 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK25 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK26 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK27 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK28 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK29 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK30 : aliased HAL.UInt32; + -- Reading from a spinlock address will: - Return 0 if lock is already + -- locked - Otherwise return nonzero, and simultaneously claim the lock + -- Writing (any value) releases the lock. If core 0 and core 1 attempt + -- to claim the same lock simultaneously, core 0 wins. The value + -- returned on success is 0x1 << lock number. + SPINLOCK31 : aliased HAL.UInt32; + -- Trigger a doorbell interrupt on the opposite core. Write 1 to a bit + -- to set the corresponding bit in DOORBELL_IN on the opposite core. + -- This raises the opposite core's doorbell interrupt. Read to get the + -- status of the doorbells currently asserted on the opposite core. This + -- is equivalent to that core reading its own DOORBELL_IN status. + DOORBELL_OUT_SET : aliased DOORBELL_OUT_SET_Register; + -- Clear doorbells which have been posted to the opposite core. This + -- register is intended for debugging and initialisation purposes. + -- Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit + -- in DOORBELL_IN on the opposite core. Clearing all bits will cause + -- that core's doorbell interrupt to deassert. Since the usual order of + -- events is for software to send events using DOORBELL_OUT_SET, and + -- acknowledge incoming events by writing to DOORBELL_IN_CLR, this + -- register should be used with caution to avoid race conditions. + -- Reading returns the status of the doorbells currently asserted on the + -- other core, i.e. is equivalent to that core reading its own + -- DOORBELL_IN status. + DOORBELL_OUT_CLR : aliased DOORBELL_OUT_CLR_Register; + -- Write 1s to trigger doorbell interrupts on this core. Read to get + -- status of doorbells currently asserted on this core. + DOORBELL_IN_SET : aliased DOORBELL_IN_SET_Register; + -- Check and acknowledge doorbells posted to this core. This core's + -- doorbell interrupt is asserted when any bit in this register is 1. + -- Write 1 to each bit to clear that bit. The doorbell interrupt + -- deasserts once all bits are cleared. Read to get status of doorbells + -- currently asserted on this core. + DOORBELL_IN_CLR : aliased DOORBELL_IN_CLR_Register; + -- Detach certain core-local peripherals from Secure SIO, and attach + -- them to Non-secure SIO, so that Non-secure software can use them. + -- Attempting to access one of these peripherals from the Secure SIO + -- when it is attached to the Non-secure SIO, or vice versa, will + -- generate a bus error. This register is per-core, and is only present + -- on the Secure SIO. Most SIO hardware is duplicated across the Secure + -- and Non-secure SIO, so is not listed in this register. + PERI_NONSEC : aliased PERI_NONSEC_Register; + -- Control the assertion of the standard software interrupt (MIP.MSIP) + -- on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not + -- routed to a normal system-level interrupt line, so can not be used by + -- the Arm cores. It is safe for both cores to write to this register on + -- the same cycle. The set/clear effect is accumulated across both + -- cores, and then applied. If a flag is both set and cleared on the + -- same cycle, only the set takes effect. + RISCV_SOFTIRQ : aliased RISCV_SOFTIRQ_Register; + -- Control register for the RISC-V 64-bit Machine-mode timer. This timer + -- is only present in the Secure SIO, so is only accessible to an Arm + -- core in Secure mode or a RISC-V core in Machine mode. Note whilst + -- this timer follows the RISC-V privileged specification, it is equally + -- usable by the Arm cores. The interrupts are routed to normal + -- system-level interrupt lines as well as to the MIP.MTIP inputs on the + -- RISC-V cores. + MTIME_CTRL : aliased MTIME_CTRL_Register; + -- Read/write access to the high half of RISC-V Machine-mode timer. This + -- register is shared between both cores. If both cores write on the + -- same cycle, core 1 takes precedence. + MTIME : aliased HAL.UInt32; + -- Read/write access to the high half of RISC-V Machine-mode timer. This + -- register is shared between both cores. If both cores write on the + -- same cycle, core 1 takes precedence. + MTIMEH : aliased HAL.UInt32; + -- Low half of RISC-V Machine-mode timer comparator. This register is + -- core-local, i.e., each core gets a copy of this register, with the + -- comparison result routed to its own interrupt line. The timer + -- interrupt is asserted whenever MTIME is greater than or equal to + -- MTIMECMP. This comparison is unsigned, and performed on the full + -- 64-bit values. + MTIMECMP : aliased HAL.UInt32; + -- High half of RISC-V Machine-mode timer comparator. This register is + -- core-local. The timer interrupt is asserted whenever MTIME is greater + -- than or equal to MTIMECMP. This comparison is unsigned, and performed + -- on the full 64-bit values. + MTIMECMPH : aliased HAL.UInt32; + -- Control register for TMDS encoder. + TMDS_CTRL : aliased TMDS_CTRL_Register; + -- Write-only access to the TMDS colour data register. + TMDS_WDATA : aliased HAL.UInt32; + -- Get the encoding of one pixel's worth of colour data, packed into a + -- 32-bit value (3x10-bit symbols). The PEEK alias does not shift the + -- colour register when read, but still advances the running DC balance + -- state of each encoder. This is useful for pixel doubling. + TMDS_PEEK_SINGLE : aliased HAL.UInt32; + -- Get the encoding of one pixel's worth of colour data, packed into a + -- 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 + -- bits total). Each chunk contains two bits of a TMDS symbol per lane. + -- This format is intended for shifting out with the HSTX peripheral on + -- RP2350. The POP alias shifts the colour register when read, as well + -- as advancing the running DC balance state of each encoder. + TMDS_POP_SINGLE : aliased HAL.UInt32; + -- Get lane 0 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 0 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L0 : aliased HAL.UInt32; + -- Get lane 0 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L0 : aliased HAL.UInt32; + -- Get lane 1 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 1 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L1 : aliased HAL.UInt32; + -- Get lane 1 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L1 : aliased HAL.UInt32; + -- Get lane 2 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- PEEK alias does not shift the colour register when read, but still + -- advances the lane 2 DC balance state. This is useful if all 3 lanes' + -- worth of encode are to be read at once, rather than processing the + -- entire scanline for one lane before moving to the next lane. + TMDS_PEEK_DOUBLE_L2 : aliased HAL.UInt32; + -- Get lane 2 of the encoding of two pixels' worth of colour data. Two + -- 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The + -- POP alias shifts the colour register when read, according to the + -- values of PIX_SHIFT and PIX2_NOSHIFT. + TMDS_POP_DOUBLE_L2 : aliased HAL.UInt32; + end record + with Volatile; + + for SIO_NS_Peripheral use record + CPUID at 16#0# range 0 .. 31; + GPIO_IN at 16#4# range 0 .. 31; + GPIO_HI_IN at 16#8# range 0 .. 31; + GPIO_OUT at 16#10# range 0 .. 31; + GPIO_HI_OUT at 16#14# range 0 .. 31; + GPIO_OUT_SET at 16#18# range 0 .. 31; + GPIO_HI_OUT_SET at 16#1C# range 0 .. 31; + GPIO_OUT_CLR at 16#20# range 0 .. 31; + GPIO_HI_OUT_CLR at 16#24# range 0 .. 31; + GPIO_OUT_XOR at 16#28# range 0 .. 31; + GPIO_HI_OUT_XOR at 16#2C# range 0 .. 31; + GPIO_OE at 16#30# range 0 .. 31; + GPIO_HI_OE at 16#34# range 0 .. 31; + GPIO_OE_SET at 16#38# range 0 .. 31; + GPIO_HI_OE_SET at 16#3C# range 0 .. 31; + GPIO_OE_CLR at 16#40# range 0 .. 31; + GPIO_HI_OE_CLR at 16#44# range 0 .. 31; + GPIO_OE_XOR at 16#48# range 0 .. 31; + GPIO_HI_OE_XOR at 16#4C# range 0 .. 31; + FIFO_ST at 16#50# range 0 .. 31; + FIFO_WR at 16#54# range 0 .. 31; + FIFO_RD at 16#58# range 0 .. 31; + SPINLOCK_ST at 16#5C# range 0 .. 31; + INTERP0_ACCUM0 at 16#80# range 0 .. 31; + INTERP0_ACCUM1 at 16#84# range 0 .. 31; + INTERP0_BASE0 at 16#88# range 0 .. 31; + INTERP0_BASE1 at 16#8C# range 0 .. 31; + INTERP0_BASE2 at 16#90# range 0 .. 31; + INTERP0_POP_LANE0 at 16#94# range 0 .. 31; + INTERP0_POP_LANE1 at 16#98# range 0 .. 31; + INTERP0_POP_FULL at 16#9C# range 0 .. 31; + INTERP0_PEEK_LANE0 at 16#A0# range 0 .. 31; + INTERP0_PEEK_LANE1 at 16#A4# range 0 .. 31; + INTERP0_PEEK_FULL at 16#A8# range 0 .. 31; + INTERP0_CTRL_LANE0 at 16#AC# range 0 .. 31; + INTERP0_CTRL_LANE1 at 16#B0# range 0 .. 31; + INTERP0_ACCUM0_ADD at 16#B4# range 0 .. 31; + INTERP0_ACCUM1_ADD at 16#B8# range 0 .. 31; + INTERP0_BASE_1AND0 at 16#BC# range 0 .. 31; + INTERP1_ACCUM0 at 16#C0# range 0 .. 31; + INTERP1_ACCUM1 at 16#C4# range 0 .. 31; + INTERP1_BASE0 at 16#C8# range 0 .. 31; + INTERP1_BASE1 at 16#CC# range 0 .. 31; + INTERP1_BASE2 at 16#D0# range 0 .. 31; + INTERP1_POP_LANE0 at 16#D4# range 0 .. 31; + INTERP1_POP_LANE1 at 16#D8# range 0 .. 31; + INTERP1_POP_FULL at 16#DC# range 0 .. 31; + INTERP1_PEEK_LANE0 at 16#E0# range 0 .. 31; + INTERP1_PEEK_LANE1 at 16#E4# range 0 .. 31; + INTERP1_PEEK_FULL at 16#E8# range 0 .. 31; + INTERP1_CTRL_LANE0 at 16#EC# range 0 .. 31; + INTERP1_CTRL_LANE1 at 16#F0# range 0 .. 31; + INTERP1_ACCUM0_ADD at 16#F4# range 0 .. 31; + INTERP1_ACCUM1_ADD at 16#F8# range 0 .. 31; + INTERP1_BASE_1AND0 at 16#FC# range 0 .. 31; + SPINLOCK0 at 16#100# range 0 .. 31; + SPINLOCK1 at 16#104# range 0 .. 31; + SPINLOCK2 at 16#108# range 0 .. 31; + SPINLOCK3 at 16#10C# range 0 .. 31; + SPINLOCK4 at 16#110# range 0 .. 31; + SPINLOCK5 at 16#114# range 0 .. 31; + SPINLOCK6 at 16#118# range 0 .. 31; + SPINLOCK7 at 16#11C# range 0 .. 31; + SPINLOCK8 at 16#120# range 0 .. 31; + SPINLOCK9 at 16#124# range 0 .. 31; + SPINLOCK10 at 16#128# range 0 .. 31; + SPINLOCK11 at 16#12C# range 0 .. 31; + SPINLOCK12 at 16#130# range 0 .. 31; + SPINLOCK13 at 16#134# range 0 .. 31; + SPINLOCK14 at 16#138# range 0 .. 31; + SPINLOCK15 at 16#13C# range 0 .. 31; + SPINLOCK16 at 16#140# range 0 .. 31; + SPINLOCK17 at 16#144# range 0 .. 31; + SPINLOCK18 at 16#148# range 0 .. 31; + SPINLOCK19 at 16#14C# range 0 .. 31; + SPINLOCK20 at 16#150# range 0 .. 31; + SPINLOCK21 at 16#154# range 0 .. 31; + SPINLOCK22 at 16#158# range 0 .. 31; + SPINLOCK23 at 16#15C# range 0 .. 31; + SPINLOCK24 at 16#160# range 0 .. 31; + SPINLOCK25 at 16#164# range 0 .. 31; + SPINLOCK26 at 16#168# range 0 .. 31; + SPINLOCK27 at 16#16C# range 0 .. 31; + SPINLOCK28 at 16#170# range 0 .. 31; + SPINLOCK29 at 16#174# range 0 .. 31; + SPINLOCK30 at 16#178# range 0 .. 31; + SPINLOCK31 at 16#17C# range 0 .. 31; + DOORBELL_OUT_SET at 16#180# range 0 .. 31; + DOORBELL_OUT_CLR at 16#184# range 0 .. 31; + DOORBELL_IN_SET at 16#188# range 0 .. 31; + DOORBELL_IN_CLR at 16#18C# range 0 .. 31; + PERI_NONSEC at 16#190# range 0 .. 31; + RISCV_SOFTIRQ at 16#1A0# range 0 .. 31; + MTIME_CTRL at 16#1A4# range 0 .. 31; + MTIME at 16#1B0# range 0 .. 31; + MTIMEH at 16#1B4# range 0 .. 31; + MTIMECMP at 16#1B8# range 0 .. 31; + MTIMECMPH at 16#1BC# range 0 .. 31; + TMDS_CTRL at 16#1C0# range 0 .. 31; + TMDS_WDATA at 16#1C4# range 0 .. 31; + TMDS_PEEK_SINGLE at 16#1C8# range 0 .. 31; + TMDS_POP_SINGLE at 16#1CC# range 0 .. 31; + TMDS_PEEK_DOUBLE_L0 at 16#1D0# range 0 .. 31; + TMDS_POP_DOUBLE_L0 at 16#1D4# range 0 .. 31; + TMDS_PEEK_DOUBLE_L1 at 16#1D8# range 0 .. 31; + TMDS_POP_DOUBLE_L1 at 16#1DC# range 0 .. 31; + TMDS_PEEK_DOUBLE_L2 at 16#1E0# range 0 .. 31; + TMDS_POP_DOUBLE_L2 at 16#1E4# range 0 .. 31; + end record; + + -- Single-cycle IO block Provides core-local and inter-core hardware for + -- the two processors, with single-cycle access. + SIO_NS_Periph : aliased SIO_NS_Peripheral + with Import, Address => SIO_NS_Base; + +end RP2350_SVD.SIO_NS; diff --git a/src/svd/rp2350_svd-syscfg.ads b/src/svd/rp2350_svd-syscfg.ads new file mode 100644 index 0000000..2c69b7a --- /dev/null +++ b/src/svd/rp2350_svd-syscfg.ads @@ -0,0 +1,212 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Register block for various chip control signals +package RP2350_SVD.SYSCFG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Configuration for processors + type PROC_CONFIG_Register is record + -- Read-only. Indication that proc0 has halted + PROC0_HALTED : Boolean; + -- Read-only. Indication that proc1 has halted + PROC1_HALTED : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC_CONFIG_Register use record + PROC0_HALTED at 0 range 0 .. 0; + PROC1_HALTED at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PROC_IN_SYNC_BYPASS_HI_GPIO_Field is HAL.UInt16; + subtype PROC_IN_SYNC_BYPASS_HI_QSPI_SD_Field is HAL.UInt4; + + -- For each bit, if 1, bypass the input synchronizer between that GPIO and + -- the GPIO input register in the SIO. The input synchronizers should + -- generally be unbypassed, to avoid injecting metastabilities into + -- processors. If you're feeling brave, you can bypass to save two cycles + -- of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 + -- QSPI GPIO 58..63 + type PROC_IN_SYNC_BYPASS_HI_Register is record + GPIO : PROC_IN_SYNC_BYPASS_HI_GPIO_Field := 16#0#; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + USB_DP : Boolean := False; + USB_DM : Boolean := False; + QSPI_SCK : Boolean := False; + QSPI_CSN : Boolean := False; + QSPI_SD : PROC_IN_SYNC_BYPASS_HI_QSPI_SD_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC_IN_SYNC_BYPASS_HI_Register use record + GPIO at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + USB_DP at 0 range 24 .. 24; + USB_DM at 0 range 25 .. 25; + QSPI_SCK at 0 range 26 .. 26; + QSPI_CSN at 0 range 27 .. 27; + QSPI_SD at 0 range 28 .. 31; + end record; + + -- Directly control the chip SWD debug port + type DBGFORCE_Register is record + -- Read-only. Observe the value of SWDIO output. + SWDO : Boolean := False; + -- Directly drive SWDIO input, if ATTACH is set + SWDI : Boolean := True; + -- Directly drive SWCLK, if ATTACH is set + SWCLK : Boolean := True; + -- Attach chip debug port to syscfg controls, and disconnect it from + -- external SWD pads. + ATTACH : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGFORCE_Register use record + SWDO at 0 range 0 .. 0; + SWDI at 0 range 1 .. 1; + SWCLK at 0 range 2 .. 2; + ATTACH at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- MEMPOWERDOWN_SRAM array + type MEMPOWERDOWN_SRAM_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for MEMPOWERDOWN_SRAM + type MEMPOWERDOWN_SRAM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SRAM as a value + Val : HAL.UInt10; + when True => + -- SRAM as an array + Arr : MEMPOWERDOWN_SRAM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for MEMPOWERDOWN_SRAM_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- Control PD pins to memories. Set high to put memories to a low power + -- state. In this state the memories will retain contents but not be + -- accessible Use with caution + type MEMPOWERDOWN_Register is record + SRAM : MEMPOWERDOWN_SRAM_Field := + (As_Array => False, Val => 16#0#); + USB : Boolean := False; + ROM : Boolean := False; + BOOTRAM : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MEMPOWERDOWN_Register use record + SRAM at 0 range 0 .. 9; + USB at 0 range 10 .. 10; + ROM at 0 range 11 .. 11; + BOOTRAM at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype AUXCTRL_AUXCTRL_Field is HAL.UInt8; + + -- Auxiliary system control register + type AUXCTRL_Register is record + -- * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed + -- into the TRNG ROSC output as an additional, uncorrelated entropy + -- source. When set, this behaviour is disabled. * Bit 0: Force POWMAN + -- clock to switch to LPOSC, by asserting its WDRESET input. This must + -- be set before initiating a watchdog reset of the RSM from a stage + -- that includes CLOCKS, if POWMAN is running from clk_ref at the point + -- that the watchdog reset takes place. Otherwise, the short pulse + -- generated on clk_ref by the reset of the CLOCKS block may affect + -- POWMAN register state. + AUXCTRL : AUXCTRL_AUXCTRL_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AUXCTRL_Register use record + AUXCTRL at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Register block for various chip control signals + type SYSCFG_Peripheral is record + -- Configuration for processors + PROC_CONFIG : aliased PROC_CONFIG_Register; + -- For each bit, if 1, bypass the input synchronizer between that GPIO + -- and the GPIO input register in the SIO. The input synchronizers + -- should generally be unbypassed, to avoid injecting metastabilities + -- into processors. If you're feeling brave, you can bypass to save two + -- cycles of input latency. This register applies to GPIO 0...31. + PROC_IN_SYNC_BYPASS : aliased HAL.UInt32; + -- For each bit, if 1, bypass the input synchronizer between that GPIO + -- and the GPIO input register in the SIO. The input synchronizers + -- should generally be unbypassed, to avoid injecting metastabilities + -- into processors. If you're feeling brave, you can bypass to save two + -- cycles of input latency. This register applies to GPIO 32...47. USB + -- GPIO 56..57 QSPI GPIO 58..63 + PROC_IN_SYNC_BYPASS_HI : aliased PROC_IN_SYNC_BYPASS_HI_Register; + -- Directly control the chip SWD debug port + DBGFORCE : aliased DBGFORCE_Register; + -- Control PD pins to memories. Set high to put memories to a low power + -- state. In this state the memories will retain contents but not be + -- accessible Use with caution + MEMPOWERDOWN : aliased MEMPOWERDOWN_Register; + -- Auxiliary system control register + AUXCTRL : aliased AUXCTRL_Register; + end record + with Volatile; + + for SYSCFG_Peripheral use record + PROC_CONFIG at 16#0# range 0 .. 31; + PROC_IN_SYNC_BYPASS at 16#4# range 0 .. 31; + PROC_IN_SYNC_BYPASS_HI at 16#8# range 0 .. 31; + DBGFORCE at 16#C# range 0 .. 31; + MEMPOWERDOWN at 16#10# range 0 .. 31; + AUXCTRL at 16#14# range 0 .. 31; + end record; + + -- Register block for various chip control signals + SYSCFG_Periph : aliased SYSCFG_Peripheral + with Import, Address => SYSCFG_Base; + +end RP2350_SVD.SYSCFG; diff --git a/src/svd/rp2350_svd-sysinfo.ads b/src/svd/rp2350_svd-sysinfo.ads new file mode 100644 index 0000000..79b9cae --- /dev/null +++ b/src/svd/rp2350_svd-sysinfo.ads @@ -0,0 +1,114 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.SYSINFO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CHIP_ID_MANUFACTURER_Field is HAL.UInt11; + subtype CHIP_ID_PART_Field is HAL.UInt16; + subtype CHIP_ID_REVISION_Field is HAL.UInt4; + + -- JEDEC JEP-106 compliant chip identifier. + type CHIP_ID_Register is record + -- Read-only. + STOP_BIT : Boolean; + -- Read-only. + MANUFACTURER : CHIP_ID_MANUFACTURER_Field; + -- Read-only. + PART : CHIP_ID_PART_Field; + -- Read-only. + REVISION : CHIP_ID_REVISION_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIP_ID_Register use record + STOP_BIT at 0 range 0 .. 0; + MANUFACTURER at 0 range 1 .. 11; + PART at 0 range 12 .. 27; + REVISION at 0 range 28 .. 31; + end record; + + type PACKAGE_SEL_Register is record + -- Read-only. + PACKAGE_SEL : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PACKAGE_SEL_Register use record + PACKAGE_SEL at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Platform register. Allows software to know what environment it is + -- running in during pre-production development. Post-production, the + -- PLATFORM is always ASIC, non-SIM. + type PLATFORM_Register is record + -- Read-only. + FPGA : Boolean; + -- Read-only. + ASIC : Boolean; + -- Read-only. + HDLSIM : Boolean; + -- Read-only. + BATCHSIM : Boolean; + -- Read-only. + GATESIM : Boolean; + -- unspecified + Reserved_5_31 : HAL.UInt27; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLATFORM_Register use record + FPGA at 0 range 0 .. 0; + ASIC at 0 range 1 .. 1; + HDLSIM at 0 range 2 .. 2; + BATCHSIM at 0 range 3 .. 3; + GATESIM at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type SYSINFO_Peripheral is record + -- JEDEC JEP-106 compliant chip identifier. + CHIP_ID : aliased CHIP_ID_Register; + PACKAGE_SEL : aliased PACKAGE_SEL_Register; + -- Platform register. Allows software to know what environment it is + -- running in during pre-production development. Post-production, the + -- PLATFORM is always ASIC, non-SIM. + PLATFORM : aliased PLATFORM_Register; + -- Git hash of the chip source. Used to identify chip version. + GITREF_RP2350 : aliased HAL.UInt32; + end record + with Volatile; + + for SYSINFO_Peripheral use record + CHIP_ID at 16#0# range 0 .. 31; + PACKAGE_SEL at 16#4# range 0 .. 31; + PLATFORM at 16#8# range 0 .. 31; + GITREF_RP2350 at 16#14# range 0 .. 31; + end record; + + SYSINFO_Periph : aliased SYSINFO_Peripheral + with Import, Address => SYSINFO_Base; + +end RP2350_SVD.SYSINFO; diff --git a/src/svd/rp2350_svd-tbman.ads b/src/svd/rp2350_svd-tbman.ads new file mode 100644 index 0000000..d22acc9 --- /dev/null +++ b/src/svd/rp2350_svd-tbman.ads @@ -0,0 +1,60 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- For managing simulation testbenches +package RP2350_SVD.TBMAN is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Indicates the type of platform in use + type PLATFORM_Register is record + -- Read-only. Indicates the platform is an ASIC + ASIC : Boolean; + -- Read-only. Indicates the platform is an FPGA + FPGA : Boolean; + -- Read-only. Indicates the platform is a simulation + HDLSIM : Boolean; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PLATFORM_Register use record + ASIC at 0 range 0 .. 0; + FPGA at 0 range 1 .. 1; + HDLSIM at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- For managing simulation testbenches + type TBMAN_Peripheral is record + -- Indicates the type of platform in use + PLATFORM : aliased PLATFORM_Register; + end record + with Volatile; + + for TBMAN_Peripheral use record + PLATFORM at 0 range 0 .. 31; + end record; + + -- For managing simulation testbenches + TBMAN_Periph : aliased TBMAN_Peripheral + with Import, Address => TBMAN_Base; + +end RP2350_SVD.TBMAN; diff --git a/src/svd/rp2350_svd-ticks.ads b/src/svd/rp2350_svd-ticks.ads new file mode 100644 index 0000000..a8208d9 --- /dev/null +++ b/src/svd/rp2350_svd-ticks.ads @@ -0,0 +1,381 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.TICKS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Controls the tick generator + type PROC0_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PROC0_CYCLES_PROC0_CYCLES_Field is HAL.UInt9; + + type PROC0_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + PROC0_CYCLES : PROC0_CYCLES_PROC0_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_CYCLES_Register use record + PROC0_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype PROC0_COUNT_PROC0_COUNT_Field is HAL.UInt9; + + type PROC0_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + PROC0_COUNT : PROC0_COUNT_PROC0_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC0_COUNT_Register use record + PROC0_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Controls the tick generator + type PROC1_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype PROC1_CYCLES_PROC1_CYCLES_Field is HAL.UInt9; + + type PROC1_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + PROC1_CYCLES : PROC1_CYCLES_PROC1_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_CYCLES_Register use record + PROC1_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype PROC1_COUNT_PROC1_COUNT_Field is HAL.UInt9; + + type PROC1_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + PROC1_COUNT : PROC1_COUNT_PROC1_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PROC1_COUNT_Register use record + PROC1_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Controls the tick generator + type TIMER0_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER0_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype TIMER0_CYCLES_TIMER0_CYCLES_Field is HAL.UInt9; + + type TIMER0_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + TIMER0_CYCLES : TIMER0_CYCLES_TIMER0_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER0_CYCLES_Register use record + TIMER0_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype TIMER0_COUNT_TIMER0_COUNT_Field is HAL.UInt9; + + type TIMER0_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + TIMER0_COUNT : TIMER0_COUNT_TIMER0_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER0_COUNT_Register use record + TIMER0_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Controls the tick generator + type TIMER1_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER1_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype TIMER1_CYCLES_TIMER1_CYCLES_Field is HAL.UInt9; + + type TIMER1_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + TIMER1_CYCLES : TIMER1_CYCLES_TIMER1_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER1_CYCLES_Register use record + TIMER1_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype TIMER1_COUNT_TIMER1_COUNT_Field is HAL.UInt9; + + type TIMER1_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + TIMER1_COUNT : TIMER1_COUNT_TIMER1_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TIMER1_COUNT_Register use record + TIMER1_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Controls the tick generator + type WATCHDOG_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WATCHDOG_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype WATCHDOG_CYCLES_WATCHDOG_CYCLES_Field is HAL.UInt9; + + type WATCHDOG_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + WATCHDOG_CYCLES : WATCHDOG_CYCLES_WATCHDOG_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WATCHDOG_CYCLES_Register use record + WATCHDOG_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype WATCHDOG_COUNT_WATCHDOG_COUNT_Field is HAL.UInt9; + + type WATCHDOG_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + WATCHDOG_COUNT : WATCHDOG_COUNT_WATCHDOG_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for WATCHDOG_COUNT_Register use record + WATCHDOG_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Controls the tick generator + type RISCV_CTRL_Register is record + -- start / stop tick generation + ENABLE : Boolean := False; + -- Read-only. Is the tick generator running? + RUNNING : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RISCV_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + RUNNING at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype RISCV_CYCLES_RISCV_CYCLES_Field is HAL.UInt9; + + type RISCV_CYCLES_Register is record + -- Total number of clk_tick cycles before the next tick. + RISCV_CYCLES : RISCV_CYCLES_RISCV_CYCLES_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RISCV_CYCLES_Register use record + RISCV_CYCLES at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype RISCV_COUNT_RISCV_COUNT_Field is HAL.UInt9; + + type RISCV_COUNT_Register is record + -- Read-only. Count down timer: the remaining number clk_tick cycles + -- before the next tick is generated. + RISCV_COUNT : RISCV_COUNT_RISCV_COUNT_Field; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RISCV_COUNT_Register use record + RISCV_COUNT at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type TICKS_Peripheral is record + -- Controls the tick generator + PROC0_CTRL : aliased PROC0_CTRL_Register; + PROC0_CYCLES : aliased PROC0_CYCLES_Register; + PROC0_COUNT : aliased PROC0_COUNT_Register; + -- Controls the tick generator + PROC1_CTRL : aliased PROC1_CTRL_Register; + PROC1_CYCLES : aliased PROC1_CYCLES_Register; + PROC1_COUNT : aliased PROC1_COUNT_Register; + -- Controls the tick generator + TIMER0_CTRL : aliased TIMER0_CTRL_Register; + TIMER0_CYCLES : aliased TIMER0_CYCLES_Register; + TIMER0_COUNT : aliased TIMER0_COUNT_Register; + -- Controls the tick generator + TIMER1_CTRL : aliased TIMER1_CTRL_Register; + TIMER1_CYCLES : aliased TIMER1_CYCLES_Register; + TIMER1_COUNT : aliased TIMER1_COUNT_Register; + -- Controls the tick generator + WATCHDOG_CTRL : aliased WATCHDOG_CTRL_Register; + WATCHDOG_CYCLES : aliased WATCHDOG_CYCLES_Register; + WATCHDOG_COUNT : aliased WATCHDOG_COUNT_Register; + -- Controls the tick generator + RISCV_CTRL : aliased RISCV_CTRL_Register; + RISCV_CYCLES : aliased RISCV_CYCLES_Register; + RISCV_COUNT : aliased RISCV_COUNT_Register; + end record + with Volatile; + + for TICKS_Peripheral use record + PROC0_CTRL at 16#0# range 0 .. 31; + PROC0_CYCLES at 16#4# range 0 .. 31; + PROC0_COUNT at 16#8# range 0 .. 31; + PROC1_CTRL at 16#C# range 0 .. 31; + PROC1_CYCLES at 16#10# range 0 .. 31; + PROC1_COUNT at 16#14# range 0 .. 31; + TIMER0_CTRL at 16#18# range 0 .. 31; + TIMER0_CYCLES at 16#1C# range 0 .. 31; + TIMER0_COUNT at 16#20# range 0 .. 31; + TIMER1_CTRL at 16#24# range 0 .. 31; + TIMER1_CYCLES at 16#28# range 0 .. 31; + TIMER1_COUNT at 16#2C# range 0 .. 31; + WATCHDOG_CTRL at 16#30# range 0 .. 31; + WATCHDOG_CYCLES at 16#34# range 0 .. 31; + WATCHDOG_COUNT at 16#38# range 0 .. 31; + RISCV_CTRL at 16#3C# range 0 .. 31; + RISCV_CYCLES at 16#40# range 0 .. 31; + RISCV_COUNT at 16#44# range 0 .. 31; + end record; + + TICKS_Periph : aliased TICKS_Peripheral + with Import, Address => TICKS_Base; + +end RP2350_SVD.TICKS; diff --git a/src/svd/rp2350_svd-timer0.ads b/src/svd/rp2350_svd-timer0.ads new file mode 100644 index 0000000..2e3670c --- /dev/null +++ b/src/svd/rp2350_svd-timer0.ads @@ -0,0 +1,355 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Controls time and alarms +-- +-- time is a 64 bit value indicating the time since power-on +-- +-- timeh is the top 32 bits of time & timel is the bottom 32 bits +-- to change time write to timelw before timehw to read time read from timelr +-- before timehr +-- +-- An alarm is set by setting alarm_enable and writing to the +-- corresponding alarm register When an alarm is pending, the corresponding +-- alarm_running signal will be high An alarm can be cancelled before it has +-- finished by clearing the alarm_enable When an alarm fires, the +-- corresponding alarm_irq is set and alarm_running is cleared To clear the +-- interrupt write a 1 to the corresponding alarm_irq The timer can be locked +-- to prevent writing +package RP2350_SVD.TIMER0 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ARMED_ARMED_Field is HAL.UInt4; + + -- Indicates the armed/disarmed status of each alarm. A write to the + -- corresponding ALARMx register arms the alarm. Alarms automatically + -- disarm upon firing, but writing ones here will disarm immediately + -- without waiting to fire. + type ARMED_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ARMED : ARMED_ARMED_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARMED_Register use record + ARMED at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- DBGPAUSE_DBG array + type DBGPAUSE_DBG_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DBGPAUSE_DBG + type DBGPAUSE_DBG_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DBG as a value + Val : HAL.UInt2; + when True => + -- DBG as an array + Arr : DBGPAUSE_DBG_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DBGPAUSE_DBG_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Set bits high to enable pause when the corresponding debug ports are + -- active + type DBGPAUSE_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#1#; + -- Pause when processor 0 is in debug mode + DBG : DBGPAUSE_DBG_Field := (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGPAUSE_Register use record + Reserved_0_0 at 0 range 0 .. 0; + DBG at 0 range 1 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Set high to pause the timer + type PAUSE_Register is record + PAUSE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAUSE_Register use record + PAUSE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Set locked bit to disable write access to timer Once set, cannot be + -- cleared (without a reset) + type LOCKED_Register is record + LOCKED : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKED_Register use record + LOCKED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + type SOURCE_CLK_SYS_Field is + (TICK, + CLK_SYS) + with Size => 1; + for SOURCE_CLK_SYS_Field use + (TICK => 0, + CLK_SYS => 1); + + -- Selects the source for the timer. Defaults to the normal tick configured + -- in the ticks block (typically configured to 1 microsecond). Writing to 1 + -- will ignore the tick and count clk_sys cycles instead. + type SOURCE_Register is record + CLK_SYS : SOURCE_CLK_SYS_Field := RP2350_SVD.TIMER0.TICK; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOURCE_Register use record + CLK_SYS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_0 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_1 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_2 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + ALARM_0 : Boolean := False; + ALARM_1 : Boolean := False; + ALARM_2 : Boolean := False; + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + ALARM_0 : Boolean := False; + ALARM_1 : Boolean := False; + ALARM_2 : Boolean := False; + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + ALARM_0 : Boolean; + -- Read-only. + ALARM_1 : Boolean; + -- Read-only. + ALARM_2 : Boolean; + -- Read-only. + ALARM_3 : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Controls time and alarms time is a 64 bit value indicating the time + -- since power-on timeh is the top 32 bits of time & timel is the bottom 32 + -- bits to change time write to timelw before timehw to read time read from + -- timelr before timehr An alarm is set by setting alarm_enable and writing + -- to the corresponding alarm register When an alarm is pending, the + -- corresponding alarm_running signal will be high An alarm can be + -- cancelled before it has finished by clearing the alarm_enable When an + -- alarm fires, the corresponding alarm_irq is set and alarm_running is + -- cleared To clear the interrupt write a 1 to the corresponding alarm_irq + -- The timer can be locked to prevent writing + type TIMER0_Peripheral is record + -- Write to bits 63:32 of time always write timelw before timehw + TIMEHW : aliased HAL.UInt32; + -- Write to bits 31:0 of time writes do not get copied to time until + -- timehw is written + TIMELW : aliased HAL.UInt32; + -- Read from bits 63:32 of time always read timelr before timehr + TIMEHR : aliased HAL.UInt32; + -- Read from bits 31:0 of time + TIMELR : aliased HAL.UInt32; + -- Arm alarm 0, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM0 : aliased HAL.UInt32; + -- Arm alarm 1, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM1 : aliased HAL.UInt32; + -- Arm alarm 2, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM2 : aliased HAL.UInt32; + -- Arm alarm 3, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM3 : aliased HAL.UInt32; + -- Indicates the armed/disarmed status of each alarm. A write to the + -- corresponding ALARMx register arms the alarm. Alarms automatically + -- disarm upon firing, but writing ones here will disarm immediately + -- without waiting to fire. + ARMED : aliased ARMED_Register; + -- Raw read from bits 63:32 of time (no side effects) + TIMERAWH : aliased HAL.UInt32; + -- Raw read from bits 31:0 of time (no side effects) + TIMERAWL : aliased HAL.UInt32; + -- Set bits high to enable pause when the corresponding debug ports are + -- active + DBGPAUSE : aliased DBGPAUSE_Register; + -- Set high to pause the timer + PAUSE : aliased PAUSE_Register; + -- Set locked bit to disable write access to timer Once set, cannot be + -- cleared (without a reset) + LOCKED : aliased LOCKED_Register; + -- Selects the source for the timer. Defaults to the normal tick + -- configured in the ticks block (typically configured to 1 + -- microsecond). Writing to 1 will ignore the tick and count clk_sys + -- cycles instead. + SOURCE : aliased SOURCE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for TIMER0_Peripheral use record + TIMEHW at 16#0# range 0 .. 31; + TIMELW at 16#4# range 0 .. 31; + TIMEHR at 16#8# range 0 .. 31; + TIMELR at 16#C# range 0 .. 31; + ALARM0 at 16#10# range 0 .. 31; + ALARM1 at 16#14# range 0 .. 31; + ALARM2 at 16#18# range 0 .. 31; + ALARM3 at 16#1C# range 0 .. 31; + ARMED at 16#20# range 0 .. 31; + TIMERAWH at 16#24# range 0 .. 31; + TIMERAWL at 16#28# range 0 .. 31; + DBGPAUSE at 16#2C# range 0 .. 31; + PAUSE at 16#30# range 0 .. 31; + LOCKED at 16#34# range 0 .. 31; + SOURCE at 16#38# range 0 .. 31; + INTR at 16#3C# range 0 .. 31; + INTE at 16#40# range 0 .. 31; + INTF at 16#44# range 0 .. 31; + INTS at 16#48# range 0 .. 31; + end record; + + -- Controls time and alarms time is a 64 bit value indicating the time + -- since power-on timeh is the top 32 bits of time & timel is the bottom 32 + -- bits to change time write to timelw before timehw to read time read from + -- timelr before timehr An alarm is set by setting alarm_enable and writing + -- to the corresponding alarm register When an alarm is pending, the + -- corresponding alarm_running signal will be high An alarm can be + -- cancelled before it has finished by clearing the alarm_enable When an + -- alarm fires, the corresponding alarm_irq is set and alarm_running is + -- cleared To clear the interrupt write a 1 to the corresponding alarm_irq + -- The timer can be locked to prevent writing + TIMER0_Periph : aliased TIMER0_Peripheral + with Import, Address => TIMER0_Base; + +end RP2350_SVD.TIMER0; diff --git a/src/svd/rp2350_svd-timer1.ads b/src/svd/rp2350_svd-timer1.ads new file mode 100644 index 0000000..25a2abb --- /dev/null +++ b/src/svd/rp2350_svd-timer1.ads @@ -0,0 +1,355 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Controls time and alarms +-- +-- time is a 64 bit value indicating the time since power-on +-- +-- timeh is the top 32 bits of time & timel is the bottom 32 bits +-- to change time write to timelw before timehw to read time read from timelr +-- before timehr +-- +-- An alarm is set by setting alarm_enable and writing to the +-- corresponding alarm register When an alarm is pending, the corresponding +-- alarm_running signal will be high An alarm can be cancelled before it has +-- finished by clearing the alarm_enable When an alarm fires, the +-- corresponding alarm_irq is set and alarm_running is cleared To clear the +-- interrupt write a 1 to the corresponding alarm_irq The timer can be locked +-- to prevent writing +package RP2350_SVD.TIMER1 is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ARMED_ARMED_Field is HAL.UInt4; + + -- Indicates the armed/disarmed status of each alarm. A write to the + -- corresponding ALARMx register arms the alarm. Alarms automatically + -- disarm upon firing, but writing ones here will disarm immediately + -- without waiting to fire. + type ARMED_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ARMED : ARMED_ARMED_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ARMED_Register use record + ARMED at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- DBGPAUSE_DBG array + type DBGPAUSE_DBG_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DBGPAUSE_DBG + type DBGPAUSE_DBG_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DBG as a value + Val : HAL.UInt2; + when True => + -- DBG as an array + Arr : DBGPAUSE_DBG_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DBGPAUSE_DBG_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Set bits high to enable pause when the corresponding debug ports are + -- active + type DBGPAUSE_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#1#; + -- Pause when processor 0 is in debug mode + DBG : DBGPAUSE_DBG_Field := (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DBGPAUSE_Register use record + Reserved_0_0 at 0 range 0 .. 0; + DBG at 0 range 1 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Set high to pause the timer + type PAUSE_Register is record + PAUSE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for PAUSE_Register use record + PAUSE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Set locked bit to disable write access to timer Once set, cannot be + -- cleared (without a reset) + type LOCKED_Register is record + LOCKED : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKED_Register use record + LOCKED at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + type SOURCE_CLK_SYS_Field is + (TICK, + CLK_SYS) + with Size => 1; + for SOURCE_CLK_SYS_Field use + (TICK => 0, + CLK_SYS => 1); + + -- Selects the source for the timer. Defaults to the normal tick configured + -- in the ticks block (typically configured to 1 microsecond). Writing to 1 + -- will ignore the tick and count clk_sys cycles instead. + type SOURCE_Register is record + CLK_SYS : SOURCE_CLK_SYS_Field := RP2350_SVD.TIMER1.TICK; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOURCE_Register use record + CLK_SYS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_0 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_1 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_2 : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + ALARM_0 : Boolean := False; + ALARM_1 : Boolean := False; + ALARM_2 : Boolean := False; + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + ALARM_0 : Boolean := False; + ALARM_1 : Boolean := False; + ALARM_2 : Boolean := False; + ALARM_3 : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. + ALARM_0 : Boolean; + -- Read-only. + ALARM_1 : Boolean; + -- Read-only. + ALARM_2 : Boolean; + -- Read-only. + ALARM_3 : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + ALARM_0 at 0 range 0 .. 0; + ALARM_1 at 0 range 1 .. 1; + ALARM_2 at 0 range 2 .. 2; + ALARM_3 at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Controls time and alarms time is a 64 bit value indicating the time + -- since power-on timeh is the top 32 bits of time & timel is the bottom 32 + -- bits to change time write to timelw before timehw to read time read from + -- timelr before timehr An alarm is set by setting alarm_enable and writing + -- to the corresponding alarm register When an alarm is pending, the + -- corresponding alarm_running signal will be high An alarm can be + -- cancelled before it has finished by clearing the alarm_enable When an + -- alarm fires, the corresponding alarm_irq is set and alarm_running is + -- cleared To clear the interrupt write a 1 to the corresponding alarm_irq + -- The timer can be locked to prevent writing + type TIMER1_Peripheral is record + -- Write to bits 63:32 of time always write timelw before timehw + TIMEHW : aliased HAL.UInt32; + -- Write to bits 31:0 of time writes do not get copied to time until + -- timehw is written + TIMELW : aliased HAL.UInt32; + -- Read from bits 63:32 of time always read timelr before timehr + TIMEHR : aliased HAL.UInt32; + -- Read from bits 31:0 of time + TIMELR : aliased HAL.UInt32; + -- Arm alarm 0, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM0 : aliased HAL.UInt32; + -- Arm alarm 1, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM1 : aliased HAL.UInt32; + -- Arm alarm 2, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM2 : aliased HAL.UInt32; + -- Arm alarm 3, and configure the time it will fire. Once armed, the + -- alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself + -- once it fires, and can be disarmed early using the ARMED status + -- register. + ALARM3 : aliased HAL.UInt32; + -- Indicates the armed/disarmed status of each alarm. A write to the + -- corresponding ALARMx register arms the alarm. Alarms automatically + -- disarm upon firing, but writing ones here will disarm immediately + -- without waiting to fire. + ARMED : aliased ARMED_Register; + -- Raw read from bits 63:32 of time (no side effects) + TIMERAWH : aliased HAL.UInt32; + -- Raw read from bits 31:0 of time (no side effects) + TIMERAWL : aliased HAL.UInt32; + -- Set bits high to enable pause when the corresponding debug ports are + -- active + DBGPAUSE : aliased DBGPAUSE_Register; + -- Set high to pause the timer + PAUSE : aliased PAUSE_Register; + -- Set locked bit to disable write access to timer Once set, cannot be + -- cleared (without a reset) + LOCKED : aliased LOCKED_Register; + -- Selects the source for the timer. Defaults to the normal tick + -- configured in the ticks block (typically configured to 1 + -- microsecond). Writing to 1 will ignore the tick and count clk_sys + -- cycles instead. + SOURCE : aliased SOURCE_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + end record + with Volatile; + + for TIMER1_Peripheral use record + TIMEHW at 16#0# range 0 .. 31; + TIMELW at 16#4# range 0 .. 31; + TIMEHR at 16#8# range 0 .. 31; + TIMELR at 16#C# range 0 .. 31; + ALARM0 at 16#10# range 0 .. 31; + ALARM1 at 16#14# range 0 .. 31; + ALARM2 at 16#18# range 0 .. 31; + ALARM3 at 16#1C# range 0 .. 31; + ARMED at 16#20# range 0 .. 31; + TIMERAWH at 16#24# range 0 .. 31; + TIMERAWL at 16#28# range 0 .. 31; + DBGPAUSE at 16#2C# range 0 .. 31; + PAUSE at 16#30# range 0 .. 31; + LOCKED at 16#34# range 0 .. 31; + SOURCE at 16#38# range 0 .. 31; + INTR at 16#3C# range 0 .. 31; + INTE at 16#40# range 0 .. 31; + INTF at 16#44# range 0 .. 31; + INTS at 16#48# range 0 .. 31; + end record; + + -- Controls time and alarms time is a 64 bit value indicating the time + -- since power-on timeh is the top 32 bits of time & timel is the bottom 32 + -- bits to change time write to timelw before timehw to read time read from + -- timelr before timehr An alarm is set by setting alarm_enable and writing + -- to the corresponding alarm register When an alarm is pending, the + -- corresponding alarm_running signal will be high An alarm can be + -- cancelled before it has finished by clearing the alarm_enable When an + -- alarm fires, the corresponding alarm_irq is set and alarm_running is + -- cleared To clear the interrupt write a 1 to the corresponding alarm_irq + -- The timer can be locked to prevent writing + TIMER1_Periph : aliased TIMER1_Peripheral + with Import, Address => TIMER1_Base; + +end RP2350_SVD.TIMER1; diff --git a/src/svd/rp2350_svd-trng.ads b/src/svd/rp2350_svd-trng.ads new file mode 100644 index 0000000..5d9d847 --- /dev/null +++ b/src/svd/rp2350_svd-trng.ads @@ -0,0 +1,461 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- ARM TrustZone RNG register block +package RP2350_SVD.TRNG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype RNG_IMR_RESERVED_Field is HAL.UInt28; + + -- Interrupt masking. + type RNG_IMR_Register is record + -- 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for + -- an explanation on this interrupt. + EHR_VALID_INT_MASK : Boolean := True; + -- 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for + -- an explanation on this interrupt. + AUTOCORR_ERR_INT_MASK : Boolean := True; + -- 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for + -- an explanation on this interrupt. + CRNGT_ERR_INT_MASK : Boolean := True; + -- 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for + -- an explanation on this interrupt. + VN_ERR_INT_MASK : Boolean := True; + -- Read-only. RESERVED + RESERVED : RNG_IMR_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_IMR_Register use record + EHR_VALID_INT_MASK at 0 range 0 .. 0; + AUTOCORR_ERR_INT_MASK at 0 range 1 .. 1; + CRNGT_ERR_INT_MASK at 0 range 2 .. 2; + VN_ERR_INT_MASK at 0 range 3 .. 3; + RESERVED at 0 range 4 .. 31; + end record; + + subtype RNG_ISR_RESERVED_Field is HAL.UInt28; + + -- RNG status register. If corresponding RNG_IMR bit is unmasked, an + -- interrupt will be generated. + type RNG_ISR_Register is record + -- Read-only. 1'b1 indicates that 192 bits have been collected in the + -- RNG, and are ready to be read. + EHR_VALID : Boolean; + -- Read-only. 1'b1 indicates Autocorrelation test failed four times in a + -- row. When set, RNG cease from functioning until next reset. + AUTOCORR_ERR : Boolean; + -- Read-only. 1'b1 indicates CRNGT in the RNG test failed. Failure + -- occurs when two consecutive blocks of 16 collected bits are equal. + CRNGT_ERR : Boolean; + -- Read-only. 1'b1 indicates Von Neuman error. Error in von Neuman + -- occurs if 32 consecutive collected bits are identical, ZERO or ONE. + VN_ERR : Boolean; + -- Read-only. RESERVED + RESERVED : RNG_ISR_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_ISR_Register use record + EHR_VALID at 0 range 0 .. 0; + AUTOCORR_ERR at 0 range 1 .. 1; + CRNGT_ERR at 0 range 2 .. 2; + VN_ERR at 0 range 3 .. 3; + RESERVED at 0 range 4 .. 31; + end record; + + subtype RNG_ICR_RESERVED_Field is HAL.UInt28; + + -- Interrupt/status bit clear Register. + type RNG_ICR_Register is record + -- Write 1'b1 - clear corresponding bit in RNG_ISR. + EHR_VALID : Boolean := False; + -- Cannot be cleared by SW! Only RNG reset clears this bit. + AUTOCORR_ERR : Boolean := False; + -- Write 1'b1 - clear corresponding bit in RNG_ISR. + CRNGT_ERR : Boolean := False; + -- Write 1'b1 - clear corresponding bit in RNG_ISR. + VN_ERR : Boolean := False; + -- Read-only. RESERVED + RESERVED : RNG_ICR_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_ICR_Register use record + EHR_VALID at 0 range 0 .. 0; + AUTOCORR_ERR at 0 range 1 .. 1; + CRNGT_ERR at 0 range 2 .. 2; + VN_ERR at 0 range 3 .. 3; + RESERVED at 0 range 4 .. 31; + end record; + + subtype TRNG_CONFIG_RND_SRC_SEL_Field is HAL.UInt2; + subtype TRNG_CONFIG_RESERVED_Field is HAL.UInt30; + + -- Selecting the inverter-chain length. + type TRNG_CONFIG_Register is record + -- Selects the number of inverters (out of four possible selections) in + -- the ring oscillator (the entropy source). + RND_SRC_SEL : TRNG_CONFIG_RND_SRC_SEL_Field := 16#0#; + -- Read-only. RESERVED + RESERVED : TRNG_CONFIG_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_CONFIG_Register use record + RND_SRC_SEL at 0 range 0 .. 1; + RESERVED at 0 range 2 .. 31; + end record; + + subtype TRNG_VALID_RESERVED_Field is HAL.UInt31; + + -- 192 bit collection indication. + type TRNG_VALID_Register is record + -- Read-only. 1'b1 indicates that collection of bits in the RNG is + -- completed, and data can be read from EHR_DATA register. + EHR_VALID : Boolean; + -- Read-only. RESERVED + RESERVED : TRNG_VALID_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_VALID_Register use record + EHR_VALID at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype RND_SOURCE_ENABLE_RESERVED_Field is HAL.UInt31; + + -- Enable signal for the random source. + type RND_SOURCE_ENABLE_Register is record + -- * 1'b1 - entropy source is enabled. *1'b0 - entropy source is + -- disabled + RND_SRC_EN : Boolean := False; + -- Read-only. RESERVED + RESERVED : RND_SOURCE_ENABLE_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RND_SOURCE_ENABLE_Register use record + RND_SRC_EN at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype AUTOCORR_STATISTIC_AUTOCORR_TRYS_Field is HAL.UInt14; + subtype AUTOCORR_STATISTIC_AUTOCORR_FAILS_Field is HAL.UInt8; + subtype AUTOCORR_STATISTIC_RESERVED_Field is HAL.UInt10; + + -- Statistic about Autocorrelation test activations. + type AUTOCORR_STATISTIC_Register is record + -- Count each time an autocorrelation test starts. Any write to the + -- register reset the counter. Stop collecting statistic if one of the + -- counters reached the limit. + AUTOCORR_TRYS : AUTOCORR_STATISTIC_AUTOCORR_TRYS_Field := 16#0#; + -- Count each time an autocorrelation test fails. Any write to the + -- register reset the counter. Stop collecting statistic if one of the + -- counters reached the limit. + AUTOCORR_FAILS : AUTOCORR_STATISTIC_AUTOCORR_FAILS_Field := 16#0#; + -- Read-only. RESERVED + RESERVED : AUTOCORR_STATISTIC_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for AUTOCORR_STATISTIC_Register use record + AUTOCORR_TRYS at 0 range 0 .. 13; + AUTOCORR_FAILS at 0 range 14 .. 21; + RESERVED at 0 range 22 .. 31; + end record; + + -- Debug register. + type TRNG_DEBUG_CONTROL_Register is record + -- Read-only. N/A + RESERVED : Boolean := False; + -- When set, the Von-Neuman balancer is bypassed (including the 32 + -- consecutive bits test). + VNC_BYPASS : Boolean := False; + -- When set, the CRNGT test in the RNG is bypassed. + TRNG_CRNGT_BYPASS : Boolean := False; + -- When set, the autocorrelation test in the TRNG module is bypassed. + AUTO_CORRELATE_BYPASS : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_DEBUG_CONTROL_Register use record + RESERVED at 0 range 0 .. 0; + VNC_BYPASS at 0 range 1 .. 1; + TRNG_CRNGT_BYPASS at 0 range 2 .. 2; + AUTO_CORRELATE_BYPASS at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype TRNG_SW_RESET_RESERVED_Field is HAL.UInt31; + + -- Generate internal SW reset within the RNG block. + type TRNG_SW_RESET_Register is record + -- Writing 1'b1 to this register causes an internal RNG reset. + TRNG_SW_RESET : Boolean := False; + -- Read-only. RESERVED + RESERVED : TRNG_SW_RESET_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_SW_RESET_Register use record + TRNG_SW_RESET at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype RNG_DEBUG_EN_INPUT_RESERVED_Field is HAL.UInt31; + + -- Enable the RNG debug mode + type RNG_DEBUG_EN_INPUT_Register is record + -- * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + RNG_DEBUG_EN : Boolean := False; + -- Read-only. RESERVED + RESERVED : RNG_DEBUG_EN_INPUT_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_DEBUG_EN_INPUT_Register use record + RNG_DEBUG_EN at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype TRNG_BUSY_RESERVED_Field is HAL.UInt31; + + -- RNG Busy indication. + type TRNG_BUSY_Register is record + -- Read-only. Reflects rng_busy status. + TRNG_BUSY : Boolean; + -- Read-only. RESERVED + RESERVED : TRNG_BUSY_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_BUSY_Register use record + TRNG_BUSY at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype RST_BITS_COUNTER_RESERVED_Field is HAL.UInt31; + + -- Reset the counter of collected bits in the RNG. + type RST_BITS_COUNTER_Register is record + -- Writing any value to this address will reset the bits counter and RNG + -- valid registers. RND_SORCE_ENABLE register must be unset in order for + -- the reset to take place. + RST_BITS_COUNTER : Boolean := False; + -- Read-only. RESERVED + RESERVED : RST_BITS_COUNTER_RESERVED_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RST_BITS_COUNTER_Register use record + RST_BITS_COUNTER at 0 range 0 .. 0; + RESERVED at 0 range 1 .. 31; + end record; + + subtype RNG_VERSION_RESERVED_Field is HAL.UInt24; + + -- Displays the version settings of the TRNG. + type RNG_VERSION_Register is record + -- Read-only. * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + EHR_WIDTH_192 : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + CRNGT_EXISTS : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + AUTOCORR_EXISTS : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + TRNG_TESTS_BYPASS_EN : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + PRNG_EXISTS : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + KAT_EXISTS : Boolean; + -- Read-only. * 1'b1 - Exists. *1'b0 - Does not exist + RESEEDING_EXISTS : Boolean; + -- Read-only. * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + RNG_USE_5_SBOXES : Boolean; + -- Read-only. RESERVED + RESERVED : RNG_VERSION_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_VERSION_Register use record + EHR_WIDTH_192 at 0 range 0 .. 0; + CRNGT_EXISTS at 0 range 1 .. 1; + AUTOCORR_EXISTS at 0 range 2 .. 2; + TRNG_TESTS_BYPASS_EN at 0 range 3 .. 3; + PRNG_EXISTS at 0 range 4 .. 4; + KAT_EXISTS at 0 range 5 .. 5; + RESEEDING_EXISTS at 0 range 6 .. 6; + RNG_USE_5_SBOXES at 0 range 7 .. 7; + RESERVED at 0 range 8 .. 31; + end record; + + subtype RNG_BIST_CNTR_0_ROSC_CNTR_VAL_Field is HAL.UInt22; + subtype RNG_BIST_CNTR_0_RESERVED_Field is HAL.UInt10; + + -- Collected BIST results. + type RNG_BIST_CNTR_0_Register is record + -- Read-only. Reflects the results of RNG BIST counter. + ROSC_CNTR_VAL : RNG_BIST_CNTR_0_ROSC_CNTR_VAL_Field; + -- Read-only. RESERVED + RESERVED : RNG_BIST_CNTR_0_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_BIST_CNTR_0_Register use record + ROSC_CNTR_VAL at 0 range 0 .. 21; + RESERVED at 0 range 22 .. 31; + end record; + + subtype RNG_BIST_CNTR_1_ROSC_CNTR_VAL_Field is HAL.UInt22; + subtype RNG_BIST_CNTR_1_RESERVED_Field is HAL.UInt10; + + -- Collected BIST results. + type RNG_BIST_CNTR_1_Register is record + -- Read-only. Reflects the results of RNG BIST counter. + ROSC_CNTR_VAL : RNG_BIST_CNTR_1_ROSC_CNTR_VAL_Field; + -- Read-only. RESERVED + RESERVED : RNG_BIST_CNTR_1_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_BIST_CNTR_1_Register use record + ROSC_CNTR_VAL at 0 range 0 .. 21; + RESERVED at 0 range 22 .. 31; + end record; + + subtype RNG_BIST_CNTR_2_ROSC_CNTR_VAL_Field is HAL.UInt22; + subtype RNG_BIST_CNTR_2_RESERVED_Field is HAL.UInt10; + + -- Collected BIST results. + type RNG_BIST_CNTR_2_Register is record + -- Read-only. Reflects the results of RNG BIST counter. + ROSC_CNTR_VAL : RNG_BIST_CNTR_2_ROSC_CNTR_VAL_Field; + -- Read-only. RESERVED + RESERVED : RNG_BIST_CNTR_2_RESERVED_Field; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for RNG_BIST_CNTR_2_Register use record + ROSC_CNTR_VAL at 0 range 0 .. 21; + RESERVED at 0 range 22 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- ARM TrustZone RNG register block + type TRNG_Peripheral is record + -- Interrupt masking. + RNG_IMR : aliased RNG_IMR_Register; + -- RNG status register. If corresponding RNG_IMR bit is unmasked, an + -- interrupt will be generated. + RNG_ISR : aliased RNG_ISR_Register; + -- Interrupt/status bit clear Register. + RNG_ICR : aliased RNG_ICR_Register; + -- Selecting the inverter-chain length. + TRNG_CONFIG : aliased TRNG_CONFIG_Register; + -- 192 bit collection indication. + TRNG_VALID : aliased TRNG_VALID_Register; + -- RNG collected bits. + EHR_DATA0 : aliased HAL.UInt32; + -- RNG collected bits. + EHR_DATA1 : aliased HAL.UInt32; + -- RNG collected bits. + EHR_DATA2 : aliased HAL.UInt32; + -- RNG collected bits. + EHR_DATA3 : aliased HAL.UInt32; + -- RNG collected bits. + EHR_DATA4 : aliased HAL.UInt32; + -- RNG collected bits. + EHR_DATA5 : aliased HAL.UInt32; + -- Enable signal for the random source. + RND_SOURCE_ENABLE : aliased RND_SOURCE_ENABLE_Register; + -- Counts clocks between sampling of random bit. + SAMPLE_CNT1 : aliased HAL.UInt32; + -- Statistic about Autocorrelation test activations. + AUTOCORR_STATISTIC : aliased AUTOCORR_STATISTIC_Register; + -- Debug register. + TRNG_DEBUG_CONTROL : aliased TRNG_DEBUG_CONTROL_Register; + -- Generate internal SW reset within the RNG block. + TRNG_SW_RESET : aliased TRNG_SW_RESET_Register; + -- Enable the RNG debug mode + RNG_DEBUG_EN_INPUT : aliased RNG_DEBUG_EN_INPUT_Register; + -- RNG Busy indication. + TRNG_BUSY : aliased TRNG_BUSY_Register; + -- Reset the counter of collected bits in the RNG. + RST_BITS_COUNTER : aliased RST_BITS_COUNTER_Register; + -- Displays the version settings of the TRNG. + RNG_VERSION : aliased RNG_VERSION_Register; + -- Collected BIST results. + RNG_BIST_CNTR_0 : aliased RNG_BIST_CNTR_0_Register; + -- Collected BIST results. + RNG_BIST_CNTR_1 : aliased RNG_BIST_CNTR_1_Register; + -- Collected BIST results. + RNG_BIST_CNTR_2 : aliased RNG_BIST_CNTR_2_Register; + end record + with Volatile; + + for TRNG_Peripheral use record + RNG_IMR at 16#100# range 0 .. 31; + RNG_ISR at 16#104# range 0 .. 31; + RNG_ICR at 16#108# range 0 .. 31; + TRNG_CONFIG at 16#10C# range 0 .. 31; + TRNG_VALID at 16#110# range 0 .. 31; + EHR_DATA0 at 16#114# range 0 .. 31; + EHR_DATA1 at 16#118# range 0 .. 31; + EHR_DATA2 at 16#11C# range 0 .. 31; + EHR_DATA3 at 16#120# range 0 .. 31; + EHR_DATA4 at 16#124# range 0 .. 31; + EHR_DATA5 at 16#128# range 0 .. 31; + RND_SOURCE_ENABLE at 16#12C# range 0 .. 31; + SAMPLE_CNT1 at 16#130# range 0 .. 31; + AUTOCORR_STATISTIC at 16#134# range 0 .. 31; + TRNG_DEBUG_CONTROL at 16#138# range 0 .. 31; + TRNG_SW_RESET at 16#140# range 0 .. 31; + RNG_DEBUG_EN_INPUT at 16#1B4# range 0 .. 31; + TRNG_BUSY at 16#1B8# range 0 .. 31; + RST_BITS_COUNTER at 16#1BC# range 0 .. 31; + RNG_VERSION at 16#1C0# range 0 .. 31; + RNG_BIST_CNTR_0 at 16#1E0# range 0 .. 31; + RNG_BIST_CNTR_1 at 16#1E4# range 0 .. 31; + RNG_BIST_CNTR_2 at 16#1E8# range 0 .. 31; + end record; + + -- ARM TrustZone RNG register block + TRNG_Periph : aliased TRNG_Peripheral + with Import, Address => TRNG_Base; + +end RP2350_SVD.TRNG; diff --git a/src/svd/rp2350_svd-usb.ads b/src/svd/rp2350_svd-usb.ads new file mode 100644 index 0000000..44715f4 --- /dev/null +++ b/src/svd/rp2350_svd-usb.ads @@ -0,0 +1,2140 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- USB FS/LS controller device registers +package RP2350_SVD.USB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ADDR_ENDP_ADDRESS_Field is HAL.UInt7; + subtype ADDR_ENDP_ENDPOINT_Field is HAL.UInt4; + + -- Device address and endpoint control + type ADDR_ENDP_Register is record + -- In device mode, the address that the device should respond to. Set in + -- response to a SET_ADDR setup packet from the host. In host mode set + -- to the address of the device to communicate with. + ADDRESS : ADDR_ENDP_ADDRESS_Field := 16#0#; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Device endpoint to send data to. Only valid for HOST mode. + ENDPOINT : ADDR_ENDP_ENDPOINT_Field := 16#0#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADDR_ENDP_Register use record + ADDRESS at 0 range 0 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + ENDPOINT at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Interrupt endpoint 1. Only valid for HOST mode. + type ADDR_ENDP_Register_1 is record + -- Device address + ADDRESS : ADDR_ENDP_ADDRESS_Field := 16#0#; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Endpoint number of the interrupt endpoint + ENDPOINT : ADDR_ENDP_ENDPOINT_Field := 16#0#; + -- unspecified + Reserved_20_24 : HAL.UInt5 := 16#0#; + -- Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR : Boolean := False; + -- Interrupt EP requires preamble (is a low speed device on a full speed + -- hub) + INTEP_PREAMBLE : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for ADDR_ENDP_Register_1 use record + ADDRESS at 0 range 0 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + ENDPOINT at 0 range 16 .. 19; + Reserved_20_24 at 0 range 20 .. 24; + INTEP_DIR at 0 range 25 .. 25; + INTEP_PREAMBLE at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- Main control register + type MAIN_CTRL_Register is record + -- Enable controller + CONTROLLER_EN : Boolean := False; + -- Device mode = 0, Host mode = 1 + HOST_NDEVICE : Boolean := False; + -- Isolates USB phy after controller power-up Remove isolation once + -- software has configured the controller Not isolated = 0, Isolated = 1 + PHY_ISO : Boolean := True; + -- unspecified + Reserved_3_30 : HAL.UInt28 := 16#0#; + -- Reduced timings for simulation + SIM_TIMING : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for MAIN_CTRL_Register use record + CONTROLLER_EN at 0 range 0 .. 0; + HOST_NDEVICE at 0 range 1 .. 1; + PHY_ISO at 0 range 2 .. 2; + Reserved_3_30 at 0 range 3 .. 30; + SIM_TIMING at 0 range 31 .. 31; + end record; + + subtype SOF_WR_COUNT_Field is HAL.UInt11; + + -- Set the SOF (Start of Frame) frame number in the host controller. The + -- SOF packet is sent every 1ms and the host will increment the frame + -- number by 1 each time. + type SOF_WR_Register is record + -- Write-only. + COUNT : SOF_WR_COUNT_Field := 16#0#; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOF_WR_Register use record + COUNT at 0 range 0 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype SOF_RD_COUNT_Field is HAL.UInt11; + + -- Read the last SOF (Start of Frame) frame number seen. In device mode the + -- last SOF received from the host. In host mode the last SOF sent by the + -- host. + type SOF_RD_Register is record + -- Read-only. + COUNT : SOF_RD_COUNT_Field; + -- unspecified + Reserved_11_31 : HAL.UInt21; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOF_RD_Register use record + COUNT at 0 range 0 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- SIE control register + type SIE_CTRL_Register is record + -- Write-only. Host: Start transaction + START_TRANS : Boolean := False; + -- Host: Send Setup packet + SEND_SETUP : Boolean := False; + -- Host: Send transaction (OUT from host) + SEND_DATA : Boolean := False; + -- Host: Receive transaction (IN to host) + RECEIVE_DATA : Boolean := False; + -- Write-only. Host: Stop transaction + STOP_TRANS : Boolean := False; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Host: Preable enable for LS device on FS hub + PREAMBLE_EN : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Host: Delay packet(s) until after SOF + SOF_SYNC : Boolean := False; + -- Host: Enable SOF generation (for full speed bus) + SOF_EN : Boolean := False; + -- Host: Enable keep alive packet (for low speed bus) + KEEP_ALIVE_EN : Boolean := False; + -- Host: Enable VBUS + VBUS_EN : Boolean := False; + -- Write-only. Device: Remote wakeup. Device can initiate its own resume + -- after suspend. + RESUME : Boolean := False; + -- Write-only. Host: Reset bus + RESET_BUS : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Host: Enable pull down resistors + PULLDOWN_EN : Boolean := True; + -- Device: Enable pull up resistor + PULLUP_EN : Boolean := False; + -- Device: Pull-up strength (0=1K2, 1=2k3) + RPU_OPT : Boolean := False; + -- Power down bus transceiver + TRANSCEIVER_PD : Boolean := False; + -- Device: Stop EP0 on a short packet. + EP0_STOP_ON_SHORT_PACKET : Boolean := False; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Direct control of DM + DIRECT_DM : Boolean := False; + -- Direct control of DP + DIRECT_DP : Boolean := False; + -- Direct bus drive enable + DIRECT_EN : Boolean := False; + -- Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + EP0_INT_NAK : Boolean := False; + -- Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + EP0_INT_2BUF : Boolean := False; + -- Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + EP0_INT_1BUF : Boolean := False; + -- Device: EP0 single buffered = 0, double buffered = 1 + EP0_DOUBLE_BUF : Boolean := False; + -- Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + EP0_INT_STALL : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SIE_CTRL_Register use record + START_TRANS at 0 range 0 .. 0; + SEND_SETUP at 0 range 1 .. 1; + SEND_DATA at 0 range 2 .. 2; + RECEIVE_DATA at 0 range 3 .. 3; + STOP_TRANS at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + PREAMBLE_EN at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SOF_SYNC at 0 range 8 .. 8; + SOF_EN at 0 range 9 .. 9; + KEEP_ALIVE_EN at 0 range 10 .. 10; + VBUS_EN at 0 range 11 .. 11; + RESUME at 0 range 12 .. 12; + RESET_BUS at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + PULLDOWN_EN at 0 range 15 .. 15; + PULLUP_EN at 0 range 16 .. 16; + RPU_OPT at 0 range 17 .. 17; + TRANSCEIVER_PD at 0 range 18 .. 18; + EP0_STOP_ON_SHORT_PACKET at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + DIRECT_DM at 0 range 24 .. 24; + DIRECT_DP at 0 range 25 .. 25; + DIRECT_EN at 0 range 26 .. 26; + EP0_INT_NAK at 0 range 27 .. 27; + EP0_INT_2BUF at 0 range 28 .. 28; + EP0_INT_1BUF at 0 range 29 .. 29; + EP0_DOUBLE_BUF at 0 range 30 .. 30; + EP0_INT_STALL at 0 range 31 .. 31; + end record; + + subtype SIE_STATUS_LINE_STATE_Field is HAL.UInt2; + subtype SIE_STATUS_SPEED_Field is HAL.UInt2; + + -- SIE status register + type SIE_STATUS_Register is record + -- Read-only. Device: VBUS Detected + VBUS_DETECTED : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Read-only. USB bus line state + LINE_STATE : SIE_STATUS_LINE_STATE_Field := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Bus in suspended state. Valid for device. Device will + -- go into suspend if neither Keep Alive / SOF frames are enabled. + SUSPENDED : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Read-only. Host: device speed. Disconnected = 00, LS = 01, FS = 10 + SPEED : SIE_STATUS_SPEED_Field := 16#0#; + -- Read-only. VBUS over current detected + VBUS_OVER_CURR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Host: Device has initiated a remote resume. Device: + -- host has initiated a resume. + RESUME : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Device or Host has received a short packet. This is + -- when the data received is less than configured in the buffer control + -- register. Device: If using double buffered mode on device the buffer + -- select will not be toggled after writing status back to the buffer + -- control register. This is to prevent any further transactions on that + -- endpoint until the user has reset the buffer control registers. Host: + -- the current transfer will be stopped early. + RX_SHORT_PACKET : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Read-only. Device: connected + CONNECTED : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Device: Setup packet received + SETUP_REC : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Transaction complete. Raised by device if: * An IN or + -- OUT packet is sent with the `LAST_BUFF` bit set in the buffer control + -- register Raised by host if: * A setup packet is sent when no data in + -- or data out transaction follows * An IN packet is received and the + -- `LAST_BUFF` bit is set in the buffer control register * An IN packet + -- is received with zero length * An OUT packet is sent and the + -- `LAST_BUFF` bit is set + TRANS_COMPLETE : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Device: bus reset received + BUS_RESET : Boolean := False; + -- unspecified + Reserved_20_22 : HAL.UInt3 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. An endpoint has encountered an error. Read the + -- ep_rx_error and ep_tx_error registers to find out which endpoint had + -- an error. + ENDPOINT_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. CRC Error. Raised by the Serial RX engine. + CRC_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Bit Stuff Error. Raised by the Serial RX engine. + BIT_STUFF_ERROR : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. RX overflow is raised by the Serial RX engine if the + -- incoming data is too fast. + RX_OVERFLOW : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. RX timeout is raised by both the host and device if an + -- ACK is not received in the maximum time specified by the USB spec. + RX_TIMEOUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Host: NAK received + NAK_REC : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Host: STALL received + STALL_REC : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. ACK received. Raised by both host and device. + ACK_REC : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. Data Sequence Error. The device can raise a sequence + -- error in the following conditions: * A SETUP packet is received + -- followed by a DATA1 packet (data phase should always be DATA0) * An + -- OUT packet is received from the host but doesn't match the data pid + -- in the buffer control register read from DPSRAM The host can raise a + -- data sequence error in the following conditions: * An IN packet from + -- the device has the wrong data PID + DATA_SEQ_ERROR : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SIE_STATUS_Register use record + VBUS_DETECTED at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + LINE_STATE at 0 range 2 .. 3; + SUSPENDED at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + SPEED at 0 range 8 .. 9; + VBUS_OVER_CURR at 0 range 10 .. 10; + RESUME at 0 range 11 .. 11; + RX_SHORT_PACKET at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + CONNECTED at 0 range 16 .. 16; + SETUP_REC at 0 range 17 .. 17; + TRANS_COMPLETE at 0 range 18 .. 18; + BUS_RESET at 0 range 19 .. 19; + Reserved_20_22 at 0 range 20 .. 22; + ENDPOINT_ERROR at 0 range 23 .. 23; + CRC_ERROR at 0 range 24 .. 24; + BIT_STUFF_ERROR at 0 range 25 .. 25; + RX_OVERFLOW at 0 range 26 .. 26; + RX_TIMEOUT at 0 range 27 .. 27; + NAK_REC at 0 range 28 .. 28; + STALL_REC at 0 range 29 .. 29; + ACK_REC at 0 range 30 .. 30; + DATA_SEQ_ERROR at 0 range 31 .. 31; + end record; + + subtype INT_EP_CTRL_INT_EP_ACTIVE_Field is HAL.UInt15; + + -- interrupt endpoint control register + type INT_EP_CTRL_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Host: Enable interrupt endpoint 1 -> 15 + INT_EP_ACTIVE : INT_EP_CTRL_INT_EP_ACTIVE_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INT_EP_CTRL_Register use record + Reserved_0_0 at 0 range 0 .. 0; + INT_EP_ACTIVE at 0 range 1 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Buffer status register. A bit set here indicates that a buffer has + -- completed on the endpoint (if the buffer interrupt is enabled). It is + -- possible for 2 buffers to be completed, so clearing the buffer status + -- bit may instantly re set it on the next clock cycle. + type BUFF_STATUS_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_OUT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BUFF_STATUS_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + EP1_IN at 0 range 2 .. 2; + EP1_OUT at 0 range 3 .. 3; + EP2_IN at 0 range 4 .. 4; + EP2_OUT at 0 range 5 .. 5; + EP3_IN at 0 range 6 .. 6; + EP3_OUT at 0 range 7 .. 7; + EP4_IN at 0 range 8 .. 8; + EP4_OUT at 0 range 9 .. 9; + EP5_IN at 0 range 10 .. 10; + EP5_OUT at 0 range 11 .. 11; + EP6_IN at 0 range 12 .. 12; + EP6_OUT at 0 range 13 .. 13; + EP7_IN at 0 range 14 .. 14; + EP7_OUT at 0 range 15 .. 15; + EP8_IN at 0 range 16 .. 16; + EP8_OUT at 0 range 17 .. 17; + EP9_IN at 0 range 18 .. 18; + EP9_OUT at 0 range 19 .. 19; + EP10_IN at 0 range 20 .. 20; + EP10_OUT at 0 range 21 .. 21; + EP11_IN at 0 range 22 .. 22; + EP11_OUT at 0 range 23 .. 23; + EP12_IN at 0 range 24 .. 24; + EP12_OUT at 0 range 25 .. 25; + EP13_IN at 0 range 26 .. 26; + EP13_OUT at 0 range 27 .. 27; + EP14_IN at 0 range 28 .. 28; + EP14_OUT at 0 range 29 .. 29; + EP15_IN at 0 range 30 .. 30; + EP15_OUT at 0 range 31 .. 31; + end record; + + -- Which of the double buffers should be handled. Only valid if using an + -- interrupt per buffer (i.e. not per 2 buffers). Not valid for host + -- interrupt endpoint polling because they are only single buffered. + type BUFF_CPU_SHOULD_HANDLE_Register is record + -- Read-only. + EP0_IN : Boolean; + -- Read-only. + EP0_OUT : Boolean; + -- Read-only. + EP1_IN : Boolean; + -- Read-only. + EP1_OUT : Boolean; + -- Read-only. + EP2_IN : Boolean; + -- Read-only. + EP2_OUT : Boolean; + -- Read-only. + EP3_IN : Boolean; + -- Read-only. + EP3_OUT : Boolean; + -- Read-only. + EP4_IN : Boolean; + -- Read-only. + EP4_OUT : Boolean; + -- Read-only. + EP5_IN : Boolean; + -- Read-only. + EP5_OUT : Boolean; + -- Read-only. + EP6_IN : Boolean; + -- Read-only. + EP6_OUT : Boolean; + -- Read-only. + EP7_IN : Boolean; + -- Read-only. + EP7_OUT : Boolean; + -- Read-only. + EP8_IN : Boolean; + -- Read-only. + EP8_OUT : Boolean; + -- Read-only. + EP9_IN : Boolean; + -- Read-only. + EP9_OUT : Boolean; + -- Read-only. + EP10_IN : Boolean; + -- Read-only. + EP10_OUT : Boolean; + -- Read-only. + EP11_IN : Boolean; + -- Read-only. + EP11_OUT : Boolean; + -- Read-only. + EP12_IN : Boolean; + -- Read-only. + EP12_OUT : Boolean; + -- Read-only. + EP13_IN : Boolean; + -- Read-only. + EP13_OUT : Boolean; + -- Read-only. + EP14_IN : Boolean; + -- Read-only. + EP14_OUT : Boolean; + -- Read-only. + EP15_IN : Boolean; + -- Read-only. + EP15_OUT : Boolean; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for BUFF_CPU_SHOULD_HANDLE_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + EP1_IN at 0 range 2 .. 2; + EP1_OUT at 0 range 3 .. 3; + EP2_IN at 0 range 4 .. 4; + EP2_OUT at 0 range 5 .. 5; + EP3_IN at 0 range 6 .. 6; + EP3_OUT at 0 range 7 .. 7; + EP4_IN at 0 range 8 .. 8; + EP4_OUT at 0 range 9 .. 9; + EP5_IN at 0 range 10 .. 10; + EP5_OUT at 0 range 11 .. 11; + EP6_IN at 0 range 12 .. 12; + EP6_OUT at 0 range 13 .. 13; + EP7_IN at 0 range 14 .. 14; + EP7_OUT at 0 range 15 .. 15; + EP8_IN at 0 range 16 .. 16; + EP8_OUT at 0 range 17 .. 17; + EP9_IN at 0 range 18 .. 18; + EP9_OUT at 0 range 19 .. 19; + EP10_IN at 0 range 20 .. 20; + EP10_OUT at 0 range 21 .. 21; + EP11_IN at 0 range 22 .. 22; + EP11_OUT at 0 range 23 .. 23; + EP12_IN at 0 range 24 .. 24; + EP12_OUT at 0 range 25 .. 25; + EP13_IN at 0 range 26 .. 26; + EP13_OUT at 0 range 27 .. 27; + EP14_IN at 0 range 28 .. 28; + EP14_OUT at 0 range 29 .. 29; + EP15_IN at 0 range 30 .. 30; + EP15_OUT at 0 range 31 .. 31; + end record; + + -- Device only: Can be set to ignore the buffer control register for this + -- endpoint in case you would like to revoke a buffer. A NAK will be sent + -- for every access to the endpoint until this bit is cleared. A + -- corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify + -- the buffer control register. + type EP_ABORT_Register is record + EP0_IN : Boolean := False; + EP0_OUT : Boolean := False; + EP1_IN : Boolean := False; + EP1_OUT : Boolean := False; + EP2_IN : Boolean := False; + EP2_OUT : Boolean := False; + EP3_IN : Boolean := False; + EP3_OUT : Boolean := False; + EP4_IN : Boolean := False; + EP4_OUT : Boolean := False; + EP5_IN : Boolean := False; + EP5_OUT : Boolean := False; + EP6_IN : Boolean := False; + EP6_OUT : Boolean := False; + EP7_IN : Boolean := False; + EP7_OUT : Boolean := False; + EP8_IN : Boolean := False; + EP8_OUT : Boolean := False; + EP9_IN : Boolean := False; + EP9_OUT : Boolean := False; + EP10_IN : Boolean := False; + EP10_OUT : Boolean := False; + EP11_IN : Boolean := False; + EP11_OUT : Boolean := False; + EP12_IN : Boolean := False; + EP12_OUT : Boolean := False; + EP13_IN : Boolean := False; + EP13_OUT : Boolean := False; + EP14_IN : Boolean := False; + EP14_OUT : Boolean := False; + EP15_IN : Boolean := False; + EP15_OUT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_ABORT_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + EP1_IN at 0 range 2 .. 2; + EP1_OUT at 0 range 3 .. 3; + EP2_IN at 0 range 4 .. 4; + EP2_OUT at 0 range 5 .. 5; + EP3_IN at 0 range 6 .. 6; + EP3_OUT at 0 range 7 .. 7; + EP4_IN at 0 range 8 .. 8; + EP4_OUT at 0 range 9 .. 9; + EP5_IN at 0 range 10 .. 10; + EP5_OUT at 0 range 11 .. 11; + EP6_IN at 0 range 12 .. 12; + EP6_OUT at 0 range 13 .. 13; + EP7_IN at 0 range 14 .. 14; + EP7_OUT at 0 range 15 .. 15; + EP8_IN at 0 range 16 .. 16; + EP8_OUT at 0 range 17 .. 17; + EP9_IN at 0 range 18 .. 18; + EP9_OUT at 0 range 19 .. 19; + EP10_IN at 0 range 20 .. 20; + EP10_OUT at 0 range 21 .. 21; + EP11_IN at 0 range 22 .. 22; + EP11_OUT at 0 range 23 .. 23; + EP12_IN at 0 range 24 .. 24; + EP12_OUT at 0 range 25 .. 25; + EP13_IN at 0 range 26 .. 26; + EP13_OUT at 0 range 27 .. 27; + EP14_IN at 0 range 28 .. 28; + EP14_OUT at 0 range 29 .. 29; + EP15_IN at 0 range 30 .. 30; + EP15_OUT at 0 range 31 .. 31; + end record; + + -- Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint + -- is idle so the programmer knows it is safe to modify the buffer control + -- register. + type EP_ABORT_DONE_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_OUT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_ABORT_DONE_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + EP1_IN at 0 range 2 .. 2; + EP1_OUT at 0 range 3 .. 3; + EP2_IN at 0 range 4 .. 4; + EP2_OUT at 0 range 5 .. 5; + EP3_IN at 0 range 6 .. 6; + EP3_OUT at 0 range 7 .. 7; + EP4_IN at 0 range 8 .. 8; + EP4_OUT at 0 range 9 .. 9; + EP5_IN at 0 range 10 .. 10; + EP5_OUT at 0 range 11 .. 11; + EP6_IN at 0 range 12 .. 12; + EP6_OUT at 0 range 13 .. 13; + EP7_IN at 0 range 14 .. 14; + EP7_OUT at 0 range 15 .. 15; + EP8_IN at 0 range 16 .. 16; + EP8_OUT at 0 range 17 .. 17; + EP9_IN at 0 range 18 .. 18; + EP9_OUT at 0 range 19 .. 19; + EP10_IN at 0 range 20 .. 20; + EP10_OUT at 0 range 21 .. 21; + EP11_IN at 0 range 22 .. 22; + EP11_OUT at 0 range 23 .. 23; + EP12_IN at 0 range 24 .. 24; + EP12_OUT at 0 range 25 .. 25; + EP13_IN at 0 range 26 .. 26; + EP13_OUT at 0 range 27 .. 27; + EP14_IN at 0 range 28 .. 28; + EP14_OUT at 0 range 29 .. 29; + EP15_IN at 0 range 30 .. 30; + EP15_OUT at 0 range 31 .. 31; + end record; + + -- Device: this bit must be set in conjunction with the `STALL` bit in the + -- buffer control register to send a STALL on EP0. The device controller + -- clears these bits when a SETUP packet is received because the USB spec + -- requires that a STALL condition is cleared when a SETUP packet is + -- received. + type EP_STALL_ARM_Register is record + EP0_IN : Boolean := False; + EP0_OUT : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_STALL_ARM_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype NAK_POLL_DELAY_LS_Field is HAL.UInt10; + subtype NAK_POLL_RETRY_COUNT_LO_Field is HAL.UInt6; + subtype NAK_POLL_DELAY_FS_Field is HAL.UInt10; + subtype NAK_POLL_RETRY_COUNT_HI_Field is HAL.UInt4; + + -- Used by the host controller. Sets the wait time in microseconds before + -- trying again if the device replies with a NAK. + type NAK_POLL_Register is record + -- NAK polling interval for a low speed device + DELAY_LS : NAK_POLL_DELAY_LS_Field := 16#10#; + -- Read-only. Bits 5:0 of nak_retry_count + RETRY_COUNT_LO : NAK_POLL_RETRY_COUNT_LO_Field := 16#0#; + -- NAK polling interval for a full speed device + DELAY_FS : NAK_POLL_DELAY_FS_Field := 16#10#; + -- Stop polling epx when a nak is received + STOP_EPX_ON_NAK : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. EPX polling has stopped because a nak was received + EPX_STOPPED_ON_NAK : Boolean := False; + -- Read-only. Bits 9:6 of nak_retry count + RETRY_COUNT_HI : NAK_POLL_RETRY_COUNT_HI_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for NAK_POLL_Register use record + DELAY_LS at 0 range 0 .. 9; + RETRY_COUNT_LO at 0 range 10 .. 15; + DELAY_FS at 0 range 16 .. 25; + STOP_EPX_ON_NAK at 0 range 26 .. 26; + EPX_STOPPED_ON_NAK at 0 range 27 .. 27; + RETRY_COUNT_HI at 0 range 28 .. 31; + end record; + + -- Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are + -- set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it + -- comes from the endpoint control register. + type EP_STATUS_STALL_NAK_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_OUT : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_IN : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_OUT : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_STATUS_STALL_NAK_Register use record + EP0_IN at 0 range 0 .. 0; + EP0_OUT at 0 range 1 .. 1; + EP1_IN at 0 range 2 .. 2; + EP1_OUT at 0 range 3 .. 3; + EP2_IN at 0 range 4 .. 4; + EP2_OUT at 0 range 5 .. 5; + EP3_IN at 0 range 6 .. 6; + EP3_OUT at 0 range 7 .. 7; + EP4_IN at 0 range 8 .. 8; + EP4_OUT at 0 range 9 .. 9; + EP5_IN at 0 range 10 .. 10; + EP5_OUT at 0 range 11 .. 11; + EP6_IN at 0 range 12 .. 12; + EP6_OUT at 0 range 13 .. 13; + EP7_IN at 0 range 14 .. 14; + EP7_OUT at 0 range 15 .. 15; + EP8_IN at 0 range 16 .. 16; + EP8_OUT at 0 range 17 .. 17; + EP9_IN at 0 range 18 .. 18; + EP9_OUT at 0 range 19 .. 19; + EP10_IN at 0 range 20 .. 20; + EP10_OUT at 0 range 21 .. 21; + EP11_IN at 0 range 22 .. 22; + EP11_OUT at 0 range 23 .. 23; + EP12_IN at 0 range 24 .. 24; + EP12_OUT at 0 range 25 .. 25; + EP13_IN at 0 range 26 .. 26; + EP13_OUT at 0 range 27 .. 27; + EP14_IN at 0 range 28 .. 28; + EP14_OUT at 0 range 29 .. 29; + EP15_IN at 0 range 30 .. 30; + EP15_OUT at 0 range 31 .. 31; + end record; + + -- Where to connect the USB controller. Should be to_phy by default. + type USB_MUXING_Register is record + TO_PHY : Boolean := True; + TO_EXTPHY : Boolean := False; + TO_DIGITAL_PAD : Boolean := False; + SOFTCON : Boolean := False; + -- Use the usb DP and DM pins as GPIO pins instead of connecting them to + -- the USB controller. + USBPHY_AS_GPIO : Boolean := False; + -- unspecified + Reserved_5_30 : HAL.UInt26 := 16#0#; + -- Swap the USB PHY DP and DM pins and all related controls and flip + -- receive differential data. Can be used to switch USB DP/DP on the + -- PCB. This is done at a low level so overrides all other controls. + SWAP_DPDM : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_MUXING_Register use record + TO_PHY at 0 range 0 .. 0; + TO_EXTPHY at 0 range 1 .. 1; + TO_DIGITAL_PAD at 0 range 2 .. 2; + SOFTCON at 0 range 3 .. 3; + USBPHY_AS_GPIO at 0 range 4 .. 4; + Reserved_5_30 at 0 range 5 .. 30; + SWAP_DPDM at 0 range 31 .. 31; + end record; + + -- Overrides for the power signals in the event that the VBUS signals are + -- not hooked up to GPIO. Set the value of the override and then the + -- override enable to switch over to the override value. + type USB_PWR_Register is record + VBUS_EN : Boolean := False; + VBUS_EN_OVERRIDE_EN : Boolean := False; + VBUS_DETECT : Boolean := False; + VBUS_DETECT_OVERRIDE_EN : Boolean := False; + OVERCURR_DETECT : Boolean := False; + OVERCURR_DETECT_EN : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USB_PWR_Register use record + VBUS_EN at 0 range 0 .. 0; + VBUS_EN_OVERRIDE_EN at 0 range 1 .. 1; + VBUS_DETECT at 0 range 2 .. 2; + VBUS_DETECT_OVERRIDE_EN at 0 range 3 .. 3; + OVERCURR_DETECT at 0 range 4 .. 4; + OVERCURR_DETECT_EN at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- This register allows for direct control of the USB phy. Use in + -- conjunction with usbphy_direct_override register to enable each override + -- bit. + type USBPHY_DIRECT_Register is record + -- Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = + -- Rpu1 + Rpu2 + DP_PULLUP_HISEL : Boolean := False; + -- DP pull up enable + DP_PULLUP_EN : Boolean := False; + -- DP pull down enable + DP_PULLDN_EN : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = + -- Rpu1 + Rpu2 + DM_PULLUP_HISEL : Boolean := False; + -- DM pull up enable + DM_PULLUP_EN : Boolean := False; + -- DM pull down enable + DM_PULLDN_EN : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - + -- DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for + -- DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + TX_DP_OE : Boolean := False; + -- Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for + -- DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + TX_DM_OE : Boolean := False; + -- Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 + -- to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP + -- only. TX_DP_OE=1 to enable drive. DPP=TX_DP + TX_DP : Boolean := False; + -- Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. + -- TX_DM_OE=1 to enable drive. DPM=TX_DM + TX_DM : Boolean := False; + -- RX power down override (if override enable is set). 1 = powered down. + RX_PD : Boolean := False; + -- TX power down override (if override enable is set). 1 = powered down. + TX_PD : Boolean := False; + -- TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate + TX_FSSLEW : Boolean := False; + -- TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive + -- mode (TX_DM, TX_DM_OE ignored) + TX_DIFFMODE : Boolean := False; + -- Read-only. Differential RX + RX_DD : Boolean := False; + -- Read-only. DPP pin state + RX_DP : Boolean := False; + -- Read-only. DPM pin state + RX_DM : Boolean := False; + -- Read-only. DP overcurrent + DP_OVCN : Boolean := False; + -- Read-only. DM overcurrent + DM_OVCN : Boolean := False; + -- Read-only. DP over voltage + DP_OVV : Boolean := False; + -- Read-only. DM over voltage + DM_OVV : Boolean := False; + -- Override rx_dd value into controller + RX_DD_OVERRIDE : Boolean := False; + -- Override rx_dp value into controller + RX_DP_OVERRIDE : Boolean := False; + -- Override rx_dm value into controller + RX_DM_OVERRIDE : Boolean := False; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DIRECT_Register use record + DP_PULLUP_HISEL at 0 range 0 .. 0; + DP_PULLUP_EN at 0 range 1 .. 1; + DP_PULLDN_EN at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DM_PULLUP_HISEL at 0 range 4 .. 4; + DM_PULLUP_EN at 0 range 5 .. 5; + DM_PULLDN_EN at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TX_DP_OE at 0 range 8 .. 8; + TX_DM_OE at 0 range 9 .. 9; + TX_DP at 0 range 10 .. 10; + TX_DM at 0 range 11 .. 11; + RX_PD at 0 range 12 .. 12; + TX_PD at 0 range 13 .. 13; + TX_FSSLEW at 0 range 14 .. 14; + TX_DIFFMODE at 0 range 15 .. 15; + RX_DD at 0 range 16 .. 16; + RX_DP at 0 range 17 .. 17; + RX_DM at 0 range 18 .. 18; + DP_OVCN at 0 range 19 .. 19; + DM_OVCN at 0 range 20 .. 20; + DP_OVV at 0 range 21 .. 21; + DM_OVV at 0 range 22 .. 22; + RX_DD_OVERRIDE at 0 range 23 .. 23; + RX_DP_OVERRIDE at 0 range 24 .. 24; + RX_DM_OVERRIDE at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Override enable for each control in usbphy_direct + type USBPHY_DIRECT_OVERRIDE_Register is record + DP_PULLUP_HISEL_OVERRIDE_EN : Boolean := False; + DM_PULLUP_HISEL_OVERRIDE_EN : Boolean := False; + DP_PULLUP_EN_OVERRIDE_EN : Boolean := False; + DP_PULLDN_EN_OVERRIDE_EN : Boolean := False; + DM_PULLDN_EN_OVERRIDE_EN : Boolean := False; + TX_DP_OE_OVERRIDE_EN : Boolean := False; + TX_DM_OE_OVERRIDE_EN : Boolean := False; + TX_DP_OVERRIDE_EN : Boolean := False; + TX_DM_OVERRIDE_EN : Boolean := False; + RX_PD_OVERRIDE_EN : Boolean := False; + TX_PD_OVERRIDE_EN : Boolean := False; + TX_FSSLEW_OVERRIDE_EN : Boolean := False; + DM_PULLUP_OVERRIDE_EN : Boolean := False; + -- unspecified + Reserved_13_14 : HAL.UInt2 := 16#0#; + TX_DIFFMODE_OVERRIDE_EN : Boolean := False; + RX_DD_OVERRIDE_EN : Boolean := False; + RX_DP_OVERRIDE_EN : Boolean := False; + RX_DM_OVERRIDE_EN : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_DIRECT_OVERRIDE_Register use record + DP_PULLUP_HISEL_OVERRIDE_EN at 0 range 0 .. 0; + DM_PULLUP_HISEL_OVERRIDE_EN at 0 range 1 .. 1; + DP_PULLUP_EN_OVERRIDE_EN at 0 range 2 .. 2; + DP_PULLDN_EN_OVERRIDE_EN at 0 range 3 .. 3; + DM_PULLDN_EN_OVERRIDE_EN at 0 range 4 .. 4; + TX_DP_OE_OVERRIDE_EN at 0 range 5 .. 5; + TX_DM_OE_OVERRIDE_EN at 0 range 6 .. 6; + TX_DP_OVERRIDE_EN at 0 range 7 .. 7; + TX_DM_OVERRIDE_EN at 0 range 8 .. 8; + RX_PD_OVERRIDE_EN at 0 range 9 .. 9; + TX_PD_OVERRIDE_EN at 0 range 10 .. 10; + TX_FSSLEW_OVERRIDE_EN at 0 range 11 .. 11; + DM_PULLUP_OVERRIDE_EN at 0 range 12 .. 12; + Reserved_13_14 at 0 range 13 .. 14; + TX_DIFFMODE_OVERRIDE_EN at 0 range 15 .. 15; + RX_DD_OVERRIDE_EN at 0 range 16 .. 16; + RX_DP_OVERRIDE_EN at 0 range 17 .. 17; + RX_DM_OVERRIDE_EN at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype USBPHY_TRIM_DP_PULLDN_TRIM_Field is HAL.UInt5; + subtype USBPHY_TRIM_DM_PULLDN_TRIM_Field is HAL.UInt5; + + -- Used to adjust trim values of USB phy pull down resistors. + type USBPHY_TRIM_Register is record + -- Value to drive to USB PHY DP pulldown resistor trim control + -- Experimental data suggests that the reset value will work, but this + -- register allows adjustment if required + DP_PULLDN_TRIM : USBPHY_TRIM_DP_PULLDN_TRIM_Field := 16#1F#; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Value to drive to USB PHY DM pulldown resistor trim control + -- Experimental data suggests that the reset value will work, but this + -- register allows adjustment if required + DM_PULLDN_TRIM : USBPHY_TRIM_DM_PULLDN_TRIM_Field := 16#1F#; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for USBPHY_TRIM_Register use record + DP_PULLDN_TRIM at 0 range 0 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + DM_PULLDN_TRIM at 0 range 8 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + subtype LINESTATE_TUNING_SPARE_FIX_Field is HAL.UInt4; + + -- Used for debug only. + type LINESTATE_TUNING_Register is record + -- Device - register the received data to account for hub bit dribble + -- before EOP. Only affects certain hubs. + RCV_DELAY : Boolean := False; + -- Device/Host - add an extra 1-bit debounce of linestate sampling. + LINESTATE_DELAY : Boolean := False; + -- Host - increase inter-packet and turnaround timeouts to accommodate + -- worst-case hub delays. + MULTI_HUB_FIX : Boolean := False; + -- Device - the controller FSM performs two reads of the buffer status + -- memory address to avoid sampling metastable data. An enabled buffer + -- is only used if both reads match. + DEV_BUFF_CONTROL_DOUBLE_READ_FIX : Boolean := True; + -- RX - when a bitstuff error is signalled by rx_dasm, unconditionally + -- terminate RX decode to avoid a hang during certain packet phases. + SIE_RX_BITSTUFF_FIX : Boolean := True; + -- RX - when recovering from line chatter or bitstuff errors, treat SE0 + -- as the end of chatter as well as 8 consecutive idle bits. + SIE_RX_CHATTER_SE0_FIX : Boolean := True; + -- Device - suppress repeated errors until the device FSM is next in the + -- process of decoding an inbound packet. + DEV_RX_ERR_QUIESCE : Boolean := True; + -- Device - exit suspend on any non-idle signalling, not qualified with + -- a 1ms timer + DEV_LS_WAKE_FIX : Boolean := True; + SPARE_FIX : LINESTATE_TUNING_SPARE_FIX_Field := + 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LINESTATE_TUNING_Register use record + RCV_DELAY at 0 range 0 .. 0; + LINESTATE_DELAY at 0 range 1 .. 1; + MULTI_HUB_FIX at 0 range 2 .. 2; + DEV_BUFF_CONTROL_DOUBLE_READ_FIX at 0 range 3 .. 3; + SIE_RX_BITSTUFF_FIX at 0 range 4 .. 4; + SIE_RX_CHATTER_SE0_FIX at 0 range 5 .. 5; + DEV_RX_ERR_QUIESCE at 0 range 6 .. 6; + DEV_LS_WAKE_FIX at 0 range 7 .. 7; + SPARE_FIX at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Raw Interrupts + type INTR_Register is record + -- Read-only. Host: raised when a device is connected or disconnected + -- (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to + -- SIE_STATUS.SPEED + HOST_CONN_DIS : Boolean; + -- Read-only. Host: raised when a device wakes up the host. Cleared by + -- writing to SIE_STATUS.RESUME + HOST_RESUME : Boolean; + -- Read-only. Host: raised every time the host sends a SOF (Start of + -- Frame). Cleared by reading SOF_RD + HOST_SOF : Boolean; + -- Read-only. Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear + -- by writing to this bit. + TRANS_COMPLETE : Boolean; + -- Read-only. Raised when any bit in BUFF_STATUS is set. Clear by + -- clearing all bits in BUFF_STATUS. + BUFF_STATUS : Boolean; + -- Read-only. Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ : Boolean; + -- Read-only. Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT : Boolean; + -- Read-only. Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW : Boolean; + -- Read-only. Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF : Boolean; + -- Read-only. Source: SIE_STATUS.CRC_ERROR + ERROR_CRC : Boolean; + -- Read-only. Source: SIE_STATUS.STALL_REC + STALL : Boolean; + -- Read-only. Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT : Boolean; + -- Read-only. Source: SIE_STATUS.BUS_RESET + BUS_RESET : Boolean; + -- Read-only. Set when the device connection state changes. Cleared by + -- writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS : Boolean; + -- Read-only. Set when the device suspend state changes. Cleared by + -- writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND : Boolean; + -- Read-only. Set when the device receives a resume from the host. + -- Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST : Boolean; + -- Read-only. Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ : Boolean; + -- Read-only. Set every time the device receives a SOF (Start of Frame) + -- packet. Cleared by reading SOF_RD + DEV_SOF : Boolean; + -- Read-only. Raised when any bit in ABORT_DONE is set. Clear by + -- clearing all bits in ABORT_DONE. + ABORT_DONE : Boolean; + -- Read-only. Raised when any bit in EP_STATUS_STALL_NAK is set. Clear + -- by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK : Boolean; + -- Read-only. Source: SIE_STATUS.RX_SHORT_PACKET + RX_SHORT_PACKET : Boolean; + -- Read-only. Source: SIE_STATUS.ENDPOINT_ERROR + ENDPOINT_ERROR : Boolean; + -- Read-only. Source: DEV_SM_WATCHDOG.FIRED + DEV_SM_WATCHDOG_FIRED : Boolean; + -- Read-only. Source: NAK_POLL.EPX_STOPPED_ON_NAK + EPX_STOPPED_ON_NAK : Boolean; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTR_Register use record + HOST_CONN_DIS at 0 range 0 .. 0; + HOST_RESUME at 0 range 1 .. 1; + HOST_SOF at 0 range 2 .. 2; + TRANS_COMPLETE at 0 range 3 .. 3; + BUFF_STATUS at 0 range 4 .. 4; + ERROR_DATA_SEQ at 0 range 5 .. 5; + ERROR_RX_TIMEOUT at 0 range 6 .. 6; + ERROR_RX_OVERFLOW at 0 range 7 .. 7; + ERROR_BIT_STUFF at 0 range 8 .. 8; + ERROR_CRC at 0 range 9 .. 9; + STALL at 0 range 10 .. 10; + VBUS_DETECT at 0 range 11 .. 11; + BUS_RESET at 0 range 12 .. 12; + DEV_CONN_DIS at 0 range 13 .. 13; + DEV_SUSPEND at 0 range 14 .. 14; + DEV_RESUME_FROM_HOST at 0 range 15 .. 15; + SETUP_REQ at 0 range 16 .. 16; + DEV_SOF at 0 range 17 .. 17; + ABORT_DONE at 0 range 18 .. 18; + EP_STALL_NAK at 0 range 19 .. 19; + RX_SHORT_PACKET at 0 range 20 .. 20; + ENDPOINT_ERROR at 0 range 21 .. 21; + DEV_SM_WATCHDOG_FIRED at 0 range 22 .. 22; + EPX_STOPPED_ON_NAK at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Interrupt Enable + type INTE_Register is record + -- Host: raised when a device is connected or disconnected (i.e. when + -- SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS : Boolean := False; + -- Host: raised when a device wakes up the host. Cleared by writing to + -- SIE_STATUS.RESUME + HOST_RESUME : Boolean := False; + -- Host: raised every time the host sends a SOF (Start of Frame). + -- Cleared by reading SOF_RD + HOST_SOF : Boolean := False; + -- Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing + -- to this bit. + TRANS_COMPLETE : Boolean := False; + -- Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits + -- in BUFF_STATUS. + BUFF_STATUS : Boolean := False; + -- Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ : Boolean := False; + -- Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT : Boolean := False; + -- Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW : Boolean := False; + -- Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF : Boolean := False; + -- Source: SIE_STATUS.CRC_ERROR + ERROR_CRC : Boolean := False; + -- Source: SIE_STATUS.STALL_REC + STALL : Boolean := False; + -- Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT : Boolean := False; + -- Source: SIE_STATUS.BUS_RESET + BUS_RESET : Boolean := False; + -- Set when the device connection state changes. Cleared by writing to + -- SIE_STATUS.CONNECTED + DEV_CONN_DIS : Boolean := False; + -- Set when the device suspend state changes. Cleared by writing to + -- SIE_STATUS.SUSPENDED + DEV_SUSPEND : Boolean := False; + -- Set when the device receives a resume from the host. Cleared by + -- writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST : Boolean := False; + -- Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ : Boolean := False; + -- Set every time the device receives a SOF (Start of Frame) packet. + -- Cleared by reading SOF_RD + DEV_SOF : Boolean := False; + -- Raised when any bit in ABORT_DONE is set. Clear by clearing all bits + -- in ABORT_DONE. + ABORT_DONE : Boolean := False; + -- Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing + -- all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK : Boolean := False; + -- Source: SIE_STATUS.RX_SHORT_PACKET + RX_SHORT_PACKET : Boolean := False; + -- Source: SIE_STATUS.ENDPOINT_ERROR + ENDPOINT_ERROR : Boolean := False; + -- Source: DEV_SM_WATCHDOG.FIRED + DEV_SM_WATCHDOG_FIRED : Boolean := False; + -- Source: NAK_POLL.EPX_STOPPED_ON_NAK + EPX_STOPPED_ON_NAK : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTE_Register use record + HOST_CONN_DIS at 0 range 0 .. 0; + HOST_RESUME at 0 range 1 .. 1; + HOST_SOF at 0 range 2 .. 2; + TRANS_COMPLETE at 0 range 3 .. 3; + BUFF_STATUS at 0 range 4 .. 4; + ERROR_DATA_SEQ at 0 range 5 .. 5; + ERROR_RX_TIMEOUT at 0 range 6 .. 6; + ERROR_RX_OVERFLOW at 0 range 7 .. 7; + ERROR_BIT_STUFF at 0 range 8 .. 8; + ERROR_CRC at 0 range 9 .. 9; + STALL at 0 range 10 .. 10; + VBUS_DETECT at 0 range 11 .. 11; + BUS_RESET at 0 range 12 .. 12; + DEV_CONN_DIS at 0 range 13 .. 13; + DEV_SUSPEND at 0 range 14 .. 14; + DEV_RESUME_FROM_HOST at 0 range 15 .. 15; + SETUP_REQ at 0 range 16 .. 16; + DEV_SOF at 0 range 17 .. 17; + ABORT_DONE at 0 range 18 .. 18; + EP_STALL_NAK at 0 range 19 .. 19; + RX_SHORT_PACKET at 0 range 20 .. 20; + ENDPOINT_ERROR at 0 range 21 .. 21; + DEV_SM_WATCHDOG_FIRED at 0 range 22 .. 22; + EPX_STOPPED_ON_NAK at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Interrupt Force + type INTF_Register is record + -- Host: raised when a device is connected or disconnected (i.e. when + -- SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS : Boolean := False; + -- Host: raised when a device wakes up the host. Cleared by writing to + -- SIE_STATUS.RESUME + HOST_RESUME : Boolean := False; + -- Host: raised every time the host sends a SOF (Start of Frame). + -- Cleared by reading SOF_RD + HOST_SOF : Boolean := False; + -- Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing + -- to this bit. + TRANS_COMPLETE : Boolean := False; + -- Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits + -- in BUFF_STATUS. + BUFF_STATUS : Boolean := False; + -- Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ : Boolean := False; + -- Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT : Boolean := False; + -- Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW : Boolean := False; + -- Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF : Boolean := False; + -- Source: SIE_STATUS.CRC_ERROR + ERROR_CRC : Boolean := False; + -- Source: SIE_STATUS.STALL_REC + STALL : Boolean := False; + -- Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT : Boolean := False; + -- Source: SIE_STATUS.BUS_RESET + BUS_RESET : Boolean := False; + -- Set when the device connection state changes. Cleared by writing to + -- SIE_STATUS.CONNECTED + DEV_CONN_DIS : Boolean := False; + -- Set when the device suspend state changes. Cleared by writing to + -- SIE_STATUS.SUSPENDED + DEV_SUSPEND : Boolean := False; + -- Set when the device receives a resume from the host. Cleared by + -- writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST : Boolean := False; + -- Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ : Boolean := False; + -- Set every time the device receives a SOF (Start of Frame) packet. + -- Cleared by reading SOF_RD + DEV_SOF : Boolean := False; + -- Raised when any bit in ABORT_DONE is set. Clear by clearing all bits + -- in ABORT_DONE. + ABORT_DONE : Boolean := False; + -- Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing + -- all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK : Boolean := False; + -- Source: SIE_STATUS.RX_SHORT_PACKET + RX_SHORT_PACKET : Boolean := False; + -- Source: SIE_STATUS.ENDPOINT_ERROR + ENDPOINT_ERROR : Boolean := False; + -- Source: DEV_SM_WATCHDOG.FIRED + DEV_SM_WATCHDOG_FIRED : Boolean := False; + -- Source: NAK_POLL.EPX_STOPPED_ON_NAK + EPX_STOPPED_ON_NAK : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTF_Register use record + HOST_CONN_DIS at 0 range 0 .. 0; + HOST_RESUME at 0 range 1 .. 1; + HOST_SOF at 0 range 2 .. 2; + TRANS_COMPLETE at 0 range 3 .. 3; + BUFF_STATUS at 0 range 4 .. 4; + ERROR_DATA_SEQ at 0 range 5 .. 5; + ERROR_RX_TIMEOUT at 0 range 6 .. 6; + ERROR_RX_OVERFLOW at 0 range 7 .. 7; + ERROR_BIT_STUFF at 0 range 8 .. 8; + ERROR_CRC at 0 range 9 .. 9; + STALL at 0 range 10 .. 10; + VBUS_DETECT at 0 range 11 .. 11; + BUS_RESET at 0 range 12 .. 12; + DEV_CONN_DIS at 0 range 13 .. 13; + DEV_SUSPEND at 0 range 14 .. 14; + DEV_RESUME_FROM_HOST at 0 range 15 .. 15; + SETUP_REQ at 0 range 16 .. 16; + DEV_SOF at 0 range 17 .. 17; + ABORT_DONE at 0 range 18 .. 18; + EP_STALL_NAK at 0 range 19 .. 19; + RX_SHORT_PACKET at 0 range 20 .. 20; + ENDPOINT_ERROR at 0 range 21 .. 21; + DEV_SM_WATCHDOG_FIRED at 0 range 22 .. 22; + EPX_STOPPED_ON_NAK at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Interrupt status after masking & forcing + type INTS_Register is record + -- Read-only. Host: raised when a device is connected or disconnected + -- (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to + -- SIE_STATUS.SPEED + HOST_CONN_DIS : Boolean; + -- Read-only. Host: raised when a device wakes up the host. Cleared by + -- writing to SIE_STATUS.RESUME + HOST_RESUME : Boolean; + -- Read-only. Host: raised every time the host sends a SOF (Start of + -- Frame). Cleared by reading SOF_RD + HOST_SOF : Boolean; + -- Read-only. Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear + -- by writing to this bit. + TRANS_COMPLETE : Boolean; + -- Read-only. Raised when any bit in BUFF_STATUS is set. Clear by + -- clearing all bits in BUFF_STATUS. + BUFF_STATUS : Boolean; + -- Read-only. Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ : Boolean; + -- Read-only. Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT : Boolean; + -- Read-only. Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW : Boolean; + -- Read-only. Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF : Boolean; + -- Read-only. Source: SIE_STATUS.CRC_ERROR + ERROR_CRC : Boolean; + -- Read-only. Source: SIE_STATUS.STALL_REC + STALL : Boolean; + -- Read-only. Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT : Boolean; + -- Read-only. Source: SIE_STATUS.BUS_RESET + BUS_RESET : Boolean; + -- Read-only. Set when the device connection state changes. Cleared by + -- writing to SIE_STATUS.CONNECTED + DEV_CONN_DIS : Boolean; + -- Read-only. Set when the device suspend state changes. Cleared by + -- writing to SIE_STATUS.SUSPENDED + DEV_SUSPEND : Boolean; + -- Read-only. Set when the device receives a resume from the host. + -- Cleared by writing to SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST : Boolean; + -- Read-only. Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ : Boolean; + -- Read-only. Set every time the device receives a SOF (Start of Frame) + -- packet. Cleared by reading SOF_RD + DEV_SOF : Boolean; + -- Read-only. Raised when any bit in ABORT_DONE is set. Clear by + -- clearing all bits in ABORT_DONE. + ABORT_DONE : Boolean; + -- Read-only. Raised when any bit in EP_STATUS_STALL_NAK is set. Clear + -- by clearing all bits in EP_STATUS_STALL_NAK. + EP_STALL_NAK : Boolean; + -- Read-only. Source: SIE_STATUS.RX_SHORT_PACKET + RX_SHORT_PACKET : Boolean; + -- Read-only. Source: SIE_STATUS.ENDPOINT_ERROR + ENDPOINT_ERROR : Boolean; + -- Read-only. Source: DEV_SM_WATCHDOG.FIRED + DEV_SM_WATCHDOG_FIRED : Boolean; + -- Read-only. Source: NAK_POLL.EPX_STOPPED_ON_NAK + EPX_STOPPED_ON_NAK : Boolean; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for INTS_Register use record + HOST_CONN_DIS at 0 range 0 .. 0; + HOST_RESUME at 0 range 1 .. 1; + HOST_SOF at 0 range 2 .. 2; + TRANS_COMPLETE at 0 range 3 .. 3; + BUFF_STATUS at 0 range 4 .. 4; + ERROR_DATA_SEQ at 0 range 5 .. 5; + ERROR_RX_TIMEOUT at 0 range 6 .. 6; + ERROR_RX_OVERFLOW at 0 range 7 .. 7; + ERROR_BIT_STUFF at 0 range 8 .. 8; + ERROR_CRC at 0 range 9 .. 9; + STALL at 0 range 10 .. 10; + VBUS_DETECT at 0 range 11 .. 11; + BUS_RESET at 0 range 12 .. 12; + DEV_CONN_DIS at 0 range 13 .. 13; + DEV_SUSPEND at 0 range 14 .. 14; + DEV_RESUME_FROM_HOST at 0 range 15 .. 15; + SETUP_REQ at 0 range 16 .. 16; + DEV_SOF at 0 range 17 .. 17; + ABORT_DONE at 0 range 18 .. 18; + EP_STALL_NAK at 0 range 19 .. 19; + RX_SHORT_PACKET at 0 range 20 .. 20; + ENDPOINT_ERROR at 0 range 21 .. 21; + DEV_SM_WATCHDOG_FIRED at 0 range 22 .. 22; + EPX_STOPPED_ON_NAK at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SOF_TIMESTAMP_RAW_SOF_TIMESTAMP_RAW_Field is HAL.UInt21; + + -- Device only. Raw value of free-running PHY clock counter @48MHz. Used to + -- calculate time between SOF events. + type SOF_TIMESTAMP_RAW_Register is record + -- Read-only. + SOF_TIMESTAMP_RAW : SOF_TIMESTAMP_RAW_SOF_TIMESTAMP_RAW_Field; + -- unspecified + Reserved_21_31 : HAL.UInt11; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOF_TIMESTAMP_RAW_Register use record + SOF_TIMESTAMP_RAW at 0 range 0 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype SOF_TIMESTAMP_LAST_SOF_TIMESTAMP_LAST_Field is HAL.UInt21; + + -- Device only. Value of free-running PHY clock counter @48MHz when last + -- SOF event occurred. + type SOF_TIMESTAMP_LAST_Register is record + -- Read-only. + SOF_TIMESTAMP_LAST : SOF_TIMESTAMP_LAST_SOF_TIMESTAMP_LAST_Field; + -- unspecified + Reserved_21_31 : HAL.UInt11; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SOF_TIMESTAMP_LAST_Register use record + SOF_TIMESTAMP_LAST at 0 range 0 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype SM_STATE_STATE_Field is HAL.UInt5; + subtype SM_STATE_BC_STATE_Field is HAL.UInt3; + subtype SM_STATE_RX_DASM_Field is HAL.UInt4; + + type SM_STATE_Register is record + -- Read-only. + STATE : SM_STATE_STATE_Field; + -- Read-only. + BC_STATE : SM_STATE_BC_STATE_Field; + -- Read-only. + RX_DASM : SM_STATE_RX_DASM_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SM_STATE_Register use record + STATE at 0 range 0 .. 4; + BC_STATE at 0 range 5 .. 7; + RX_DASM at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- EP_TX_ERROR_EP array element + subtype EP_TX_ERROR_EP_Element is HAL.UInt2; + + -- EP_TX_ERROR_EP array + type EP_TX_ERROR_EP_Field_Array is array (0 .. 15) + of EP_TX_ERROR_EP_Element + with Component_Size => 2, Size => 32; + + -- TX error count for each endpoint. Write to each field to reset the + -- counter to 0. + type EP_TX_ERROR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EP as a value + Val : HAL.UInt32; + when True => + -- EP as an array + Arr : EP_TX_ERROR_EP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_TX_ERROR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- RX error count for each endpoint. Write to each field to reset the + -- counter to 0. + type EP_RX_ERROR_Register is record + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP0_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP1_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP2_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP3_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP4_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP5_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP6_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP7_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP8_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP9_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP10_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP11_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP12_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP13_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP14_SEQ : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_TRANSACTION : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + EP15_SEQ : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP_RX_ERROR_Register use record + EP0_TRANSACTION at 0 range 0 .. 0; + EP0_SEQ at 0 range 1 .. 1; + EP1_TRANSACTION at 0 range 2 .. 2; + EP1_SEQ at 0 range 3 .. 3; + EP2_TRANSACTION at 0 range 4 .. 4; + EP2_SEQ at 0 range 5 .. 5; + EP3_TRANSACTION at 0 range 6 .. 6; + EP3_SEQ at 0 range 7 .. 7; + EP4_TRANSACTION at 0 range 8 .. 8; + EP4_SEQ at 0 range 9 .. 9; + EP5_TRANSACTION at 0 range 10 .. 10; + EP5_SEQ at 0 range 11 .. 11; + EP6_TRANSACTION at 0 range 12 .. 12; + EP6_SEQ at 0 range 13 .. 13; + EP7_TRANSACTION at 0 range 14 .. 14; + EP7_SEQ at 0 range 15 .. 15; + EP8_TRANSACTION at 0 range 16 .. 16; + EP8_SEQ at 0 range 17 .. 17; + EP9_TRANSACTION at 0 range 18 .. 18; + EP9_SEQ at 0 range 19 .. 19; + EP10_TRANSACTION at 0 range 20 .. 20; + EP10_SEQ at 0 range 21 .. 21; + EP11_TRANSACTION at 0 range 22 .. 22; + EP11_SEQ at 0 range 23 .. 23; + EP12_TRANSACTION at 0 range 24 .. 24; + EP12_SEQ at 0 range 25 .. 25; + EP13_TRANSACTION at 0 range 26 .. 26; + EP13_SEQ at 0 range 27 .. 27; + EP14_TRANSACTION at 0 range 28 .. 28; + EP14_SEQ at 0 range 29 .. 29; + EP15_TRANSACTION at 0 range 30 .. 30; + EP15_SEQ at 0 range 31 .. 31; + end record; + + subtype DEV_SM_WATCHDOG_LIMIT_Field is HAL.UInt18; + + -- Watchdog that forces the device state machine to idle and raises an + -- interrupt if the device stays in a state that isn't idle for the + -- configured limit. The counter is reset on every state transition. Set + -- limit while enable is low and then set the enable. + type DEV_SM_WATCHDOG_Register is record + LIMIT : DEV_SM_WATCHDOG_LIMIT_Field := 16#0#; + ENABLE : Boolean := False; + -- Set to 1 to forcibly reset the device state machine on watchdog + -- expiry + RESET : Boolean := False; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. + FIRED : Boolean := False; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for DEV_SM_WATCHDOG_Register use record + LIMIT at 0 range 0 .. 17; + ENABLE at 0 range 18 .. 18; + RESET at 0 range 19 .. 19; + FIRED at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- USB FS/LS controller device registers + type USB_Peripheral is record + -- Device address and endpoint control + ADDR_ENDP : aliased ADDR_ENDP_Register; + -- Interrupt endpoint 1. Only valid for HOST mode. + ADDR_ENDP1 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 2. Only valid for HOST mode. + ADDR_ENDP2 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 3. Only valid for HOST mode. + ADDR_ENDP3 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 4. Only valid for HOST mode. + ADDR_ENDP4 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 5. Only valid for HOST mode. + ADDR_ENDP5 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 6. Only valid for HOST mode. + ADDR_ENDP6 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 7. Only valid for HOST mode. + ADDR_ENDP7 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 8. Only valid for HOST mode. + ADDR_ENDP8 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 9. Only valid for HOST mode. + ADDR_ENDP9 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 10. Only valid for HOST mode. + ADDR_ENDP10 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 11. Only valid for HOST mode. + ADDR_ENDP11 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 12. Only valid for HOST mode. + ADDR_ENDP12 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 13. Only valid for HOST mode. + ADDR_ENDP13 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 14. Only valid for HOST mode. + ADDR_ENDP14 : aliased ADDR_ENDP_Register_1; + -- Interrupt endpoint 15. Only valid for HOST mode. + ADDR_ENDP15 : aliased ADDR_ENDP_Register_1; + -- Main control register + MAIN_CTRL : aliased MAIN_CTRL_Register; + -- Set the SOF (Start of Frame) frame number in the host controller. The + -- SOF packet is sent every 1ms and the host will increment the frame + -- number by 1 each time. + SOF_WR : aliased SOF_WR_Register; + -- Read the last SOF (Start of Frame) frame number seen. In device mode + -- the last SOF received from the host. In host mode the last SOF sent + -- by the host. + SOF_RD : aliased SOF_RD_Register; + -- SIE control register + SIE_CTRL : aliased SIE_CTRL_Register; + -- SIE status register + SIE_STATUS : aliased SIE_STATUS_Register; + -- interrupt endpoint control register + INT_EP_CTRL : aliased INT_EP_CTRL_Register; + -- Buffer status register. A bit set here indicates that a buffer has + -- completed on the endpoint (if the buffer interrupt is enabled). It is + -- possible for 2 buffers to be completed, so clearing the buffer status + -- bit may instantly re set it on the next clock cycle. + BUFF_STATUS : aliased BUFF_STATUS_Register; + -- Which of the double buffers should be handled. Only valid if using an + -- interrupt per buffer (i.e. not per 2 buffers). Not valid for host + -- interrupt endpoint polling because they are only single buffered. + BUFF_CPU_SHOULD_HANDLE : aliased BUFF_CPU_SHOULD_HANDLE_Register; + -- Device only: Can be set to ignore the buffer control register for + -- this endpoint in case you would like to revoke a buffer. A NAK will + -- be sent for every access to the endpoint until this bit is cleared. A + -- corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify + -- the buffer control register. + EP_ABORT : aliased EP_ABORT_Register; + -- Device only: Used in conjunction with `EP_ABORT`. Set once an + -- endpoint is idle so the programmer knows it is safe to modify the + -- buffer control register. + EP_ABORT_DONE : aliased EP_ABORT_DONE_Register; + -- Device: this bit must be set in conjunction with the `STALL` bit in + -- the buffer control register to send a STALL on EP0. The device + -- controller clears these bits when a SETUP packet is received because + -- the USB spec requires that a STALL condition is cleared when a SETUP + -- packet is received. + EP_STALL_ARM : aliased EP_STALL_ARM_Register; + -- Used by the host controller. Sets the wait time in microseconds + -- before trying again if the device replies with a NAK. + NAK_POLL : aliased NAK_POLL_Register; + -- Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are + -- set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it + -- comes from the endpoint control register. + EP_STATUS_STALL_NAK : aliased EP_STATUS_STALL_NAK_Register; + -- Where to connect the USB controller. Should be to_phy by default. + USB_MUXING : aliased USB_MUXING_Register; + -- Overrides for the power signals in the event that the VBUS signals + -- are not hooked up to GPIO. Set the value of the override and then the + -- override enable to switch over to the override value. + USB_PWR : aliased USB_PWR_Register; + -- This register allows for direct control of the USB phy. Use in + -- conjunction with usbphy_direct_override register to enable each + -- override bit. + USBPHY_DIRECT : aliased USBPHY_DIRECT_Register; + -- Override enable for each control in usbphy_direct + USBPHY_DIRECT_OVERRIDE : aliased USBPHY_DIRECT_OVERRIDE_Register; + -- Used to adjust trim values of USB phy pull down resistors. + USBPHY_TRIM : aliased USBPHY_TRIM_Register; + -- Used for debug only. + LINESTATE_TUNING : aliased LINESTATE_TUNING_Register; + -- Raw Interrupts + INTR : aliased INTR_Register; + -- Interrupt Enable + INTE : aliased INTE_Register; + -- Interrupt Force + INTF : aliased INTF_Register; + -- Interrupt status after masking & forcing + INTS : aliased INTS_Register; + -- Device only. Raw value of free-running PHY clock counter @48MHz. Used + -- to calculate time between SOF events. + SOF_TIMESTAMP_RAW : aliased SOF_TIMESTAMP_RAW_Register; + -- Device only. Value of free-running PHY clock counter @48MHz when last + -- SOF event occurred. + SOF_TIMESTAMP_LAST : aliased SOF_TIMESTAMP_LAST_Register; + SM_STATE : aliased SM_STATE_Register; + -- TX error count for each endpoint. Write to each field to reset the + -- counter to 0. + EP_TX_ERROR : aliased EP_TX_ERROR_Register; + -- RX error count for each endpoint. Write to each field to reset the + -- counter to 0. + EP_RX_ERROR : aliased EP_RX_ERROR_Register; + -- Watchdog that forces the device state machine to idle and raises an + -- interrupt if the device stays in a state that isn't idle for the + -- configured limit. The counter is reset on every state transition. Set + -- limit while enable is low and then set the enable. + DEV_SM_WATCHDOG : aliased DEV_SM_WATCHDOG_Register; + end record + with Volatile; + + for USB_Peripheral use record + ADDR_ENDP at 16#0# range 0 .. 31; + ADDR_ENDP1 at 16#4# range 0 .. 31; + ADDR_ENDP2 at 16#8# range 0 .. 31; + ADDR_ENDP3 at 16#C# range 0 .. 31; + ADDR_ENDP4 at 16#10# range 0 .. 31; + ADDR_ENDP5 at 16#14# range 0 .. 31; + ADDR_ENDP6 at 16#18# range 0 .. 31; + ADDR_ENDP7 at 16#1C# range 0 .. 31; + ADDR_ENDP8 at 16#20# range 0 .. 31; + ADDR_ENDP9 at 16#24# range 0 .. 31; + ADDR_ENDP10 at 16#28# range 0 .. 31; + ADDR_ENDP11 at 16#2C# range 0 .. 31; + ADDR_ENDP12 at 16#30# range 0 .. 31; + ADDR_ENDP13 at 16#34# range 0 .. 31; + ADDR_ENDP14 at 16#38# range 0 .. 31; + ADDR_ENDP15 at 16#3C# range 0 .. 31; + MAIN_CTRL at 16#40# range 0 .. 31; + SOF_WR at 16#44# range 0 .. 31; + SOF_RD at 16#48# range 0 .. 31; + SIE_CTRL at 16#4C# range 0 .. 31; + SIE_STATUS at 16#50# range 0 .. 31; + INT_EP_CTRL at 16#54# range 0 .. 31; + BUFF_STATUS at 16#58# range 0 .. 31; + BUFF_CPU_SHOULD_HANDLE at 16#5C# range 0 .. 31; + EP_ABORT at 16#60# range 0 .. 31; + EP_ABORT_DONE at 16#64# range 0 .. 31; + EP_STALL_ARM at 16#68# range 0 .. 31; + NAK_POLL at 16#6C# range 0 .. 31; + EP_STATUS_STALL_NAK at 16#70# range 0 .. 31; + USB_MUXING at 16#74# range 0 .. 31; + USB_PWR at 16#78# range 0 .. 31; + USBPHY_DIRECT at 16#7C# range 0 .. 31; + USBPHY_DIRECT_OVERRIDE at 16#80# range 0 .. 31; + USBPHY_TRIM at 16#84# range 0 .. 31; + LINESTATE_TUNING at 16#88# range 0 .. 31; + INTR at 16#8C# range 0 .. 31; + INTE at 16#90# range 0 .. 31; + INTF at 16#94# range 0 .. 31; + INTS at 16#98# range 0 .. 31; + SOF_TIMESTAMP_RAW at 16#100# range 0 .. 31; + SOF_TIMESTAMP_LAST at 16#104# range 0 .. 31; + SM_STATE at 16#108# range 0 .. 31; + EP_TX_ERROR at 16#10C# range 0 .. 31; + EP_RX_ERROR at 16#110# range 0 .. 31; + DEV_SM_WATCHDOG at 16#114# range 0 .. 31; + end record; + + -- USB FS/LS controller device registers + USB_Periph : aliased USB_Peripheral + with Import, Address => USB_Base; + +end RP2350_SVD.USB; diff --git a/src/svd/rp2350_svd-usb_dpram.ads b/src/svd/rp2350_svd-usb_dpram.ads new file mode 100644 index 0000000..a6fc5de --- /dev/null +++ b/src/svd/rp2350_svd-usb_dpram.ads @@ -0,0 +1,4543 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- DPRAM layout for USB device. +package RP2350_SVD.USB_DPRAM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype SETUP_PACKET_LOW_BMREQUESTTYPE_Field is HAL.UInt8; + subtype SETUP_PACKET_LOW_BREQUEST_Field is HAL.UInt8; + subtype SETUP_PACKET_LOW_WVALUE_Field is HAL.UInt16; + + -- Bytes 0-3 of the SETUP packet from the host. + type SETUP_PACKET_LOW_Register is record + BMREQUESTTYPE : SETUP_PACKET_LOW_BMREQUESTTYPE_Field := 16#0#; + BREQUEST : SETUP_PACKET_LOW_BREQUEST_Field := 16#0#; + WVALUE : SETUP_PACKET_LOW_WVALUE_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SETUP_PACKET_LOW_Register use record + BMREQUESTTYPE at 0 range 0 .. 7; + BREQUEST at 0 range 8 .. 15; + WVALUE at 0 range 16 .. 31; + end record; + + subtype SETUP_PACKET_HIGH_WINDEX_Field is HAL.UInt16; + subtype SETUP_PACKET_HIGH_WLENGTH_Field is HAL.UInt16; + + -- Bytes 4-7 of the setup packet from the host. + type SETUP_PACKET_HIGH_Register is record + WINDEX : SETUP_PACKET_HIGH_WINDEX_Field := 16#0#; + WLENGTH : SETUP_PACKET_HIGH_WLENGTH_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for SETUP_PACKET_HIGH_Register use record + WINDEX at 0 range 0 .. 15; + WLENGTH at 0 range 16 .. 31; + end record; + + subtype EP1_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP1_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP1_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP1_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP1_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP1_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP1_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP1_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP1_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP1_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP1_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP1_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP1_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP1_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP2_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP2_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP2_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP2_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP2_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP2_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP2_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP2_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP2_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP2_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP2_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP2_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP2_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP2_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP3_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP3_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP3_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP3_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP3_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP3_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP3_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP3_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP3_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP3_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP3_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP3_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP3_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP3_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP4_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP4_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP4_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP4_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP4_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP4_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP4_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP4_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP4_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP4_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP4_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP4_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP4_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP4_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP5_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP5_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP5_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP5_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP5_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP5_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP5_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP5_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP5_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP5_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP5_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP5_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP5_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP5_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP6_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP6_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP6_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP6_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP6_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP6_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP6_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP6_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP6_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP6_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP6_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP6_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP6_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP6_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP7_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP7_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP7_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP7_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP7_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP7_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP7_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP7_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP7_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP7_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP7_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP7_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP7_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP7_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP8_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP8_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP8_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP8_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP8_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP8_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP8_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP8_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP8_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP8_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP8_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP8_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP8_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP8_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP9_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP9_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP9_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP9_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP9_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP9_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP9_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP9_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP9_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP9_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP9_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP9_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP9_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP9_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP10_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP10_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP10_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP10_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP10_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP10_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP10_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP10_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP10_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP10_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP10_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP10_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP10_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP10_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP11_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP11_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP11_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP11_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP11_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP11_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP11_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP11_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP11_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP11_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP11_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP11_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP11_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP11_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP12_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP12_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP12_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP12_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP12_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP12_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP12_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP12_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP12_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP12_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP12_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP12_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP12_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP12_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP13_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP13_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP13_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP13_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP13_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP13_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP13_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP13_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP13_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP13_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP13_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP13_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP13_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP13_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP14_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP14_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP14_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP14_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP14_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP14_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP14_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP14_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP14_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP14_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP14_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP14_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP14_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP14_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP15_IN_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP15_IN_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP15_IN_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP15_IN_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP15_IN_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP15_IN_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP15_IN_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP15_OUT_CONTROL_BUFFER_ADDRESS_Field is HAL.UInt16; + + type EP15_OUT_CONTROL_ENDPOINT_TYPE_Field is + (Control, + Isochronous, + Bulk, + Interrupt) + with Size => 2; + for EP15_OUT_CONTROL_ENDPOINT_TYPE_Field use + (Control => 0, + Isochronous => 1, + Bulk => 2, + Interrupt => 3); + + type EP15_OUT_CONTROL_Register is record + -- 64 byte aligned buffer address for this EP (bits 0-5 are ignored). + -- Relative to the start of the DPRAM. + BUFFER_ADDRESS : EP15_OUT_CONTROL_BUFFER_ADDRESS_Field := + 16#0#; + -- Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK : Boolean := False; + -- Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL : Boolean := False; + -- unspecified + Reserved_18_25 : HAL.UInt8 := 16#0#; + ENDPOINT_TYPE : EP15_OUT_CONTROL_ENDPOINT_TYPE_Field := + RP2350_SVD.USB_DPRAM.Control; + -- Trigger an interrupt each time both buffers are done. Only valid in + -- double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF : Boolean := False; + -- Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF : Boolean := False; + -- This endpoint is double buffered. + DOUBLE_BUFFERED : Boolean := False; + -- Enable this endpoint. The device will not reply to any packets for + -- this endpoint if this bit is not set. + ENABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP15_OUT_CONTROL_Register use record + BUFFER_ADDRESS at 0 range 0 .. 15; + INTERRUPT_ON_NAK at 0 range 16 .. 16; + INTERRUPT_ON_STALL at 0 range 17 .. 17; + Reserved_18_25 at 0 range 18 .. 25; + ENDPOINT_TYPE at 0 range 26 .. 27; + INTERRUPT_PER_DOUBLE_BUFF at 0 range 28 .. 28; + INTERRUPT_PER_BUFF at 0 range 29 .. 29; + DOUBLE_BUFFERED at 0 range 30 .. 30; + ENABLE at 0 range 31 .. 31; + end record; + + subtype EP0_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP0_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP0_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP0_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP0_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP0_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP0_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP0_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP0_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP0_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP0_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP0_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP1_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP1_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP1_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP1_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP1_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP1_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP1_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP1_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP1_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP1_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP1_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP1_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP2_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP2_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP2_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP2_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP2_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP2_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP2_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP2_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP2_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP2_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP2_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP2_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP3_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP3_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP3_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP3_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP3_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP3_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP3_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP3_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP3_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP3_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP3_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP3_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP4_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP4_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP4_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP4_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP4_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP4_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP4_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP4_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP4_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP4_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP4_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP4_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP5_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP5_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP5_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP5_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP5_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP5_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP5_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP5_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP5_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP5_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP5_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP5_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP6_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP6_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP6_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP6_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP6_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP6_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP6_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP6_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP6_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP6_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP6_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP6_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP7_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP7_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP7_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP7_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP7_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP7_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP7_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP7_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP7_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP7_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP7_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP7_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP8_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP8_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP8_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP8_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP8_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP8_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP8_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP8_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP8_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP8_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP8_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP8_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP9_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP9_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP9_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP9_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP9_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP9_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP9_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP9_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP9_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP9_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP9_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP9_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP10_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP10_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP10_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP10_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP10_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP10_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP10_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP10_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP10_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP10_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP10_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP10_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP11_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP11_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP11_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP11_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP11_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP11_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP11_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP11_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP11_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP11_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP11_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP11_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP12_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP12_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP12_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP12_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP12_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP12_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP12_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP12_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP12_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP12_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP12_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP12_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP13_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP13_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP13_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP13_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP13_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP13_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP13_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP13_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP13_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP13_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP13_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP13_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP14_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP14_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP14_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP14_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP14_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP14_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP14_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP14_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP14_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP14_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP14_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP14_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP15_IN_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP15_IN_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP15_IN_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP15_IN_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP15_IN_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP15_IN_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + subtype EP15_OUT_BUFFER_CONTROL_LENGTH_0_Field is HAL.UInt10; + subtype EP15_OUT_BUFFER_CONTROL_LENGTH_1_Field is HAL.UInt10; + + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + type EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field is + (Val_128, + Val_256, + Val_512, + Val_1024) + with Size => 2; + for EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field use + (Val_128 => 0, + Val_256 => 1, + Val_512 => 2, + Val_1024 => 3); + + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + type EP15_OUT_BUFFER_CONTROL_Register is record + -- The length of the data in buffer 1. + LENGTH_0 : EP15_OUT_BUFFER_CONTROL_LENGTH_0_Field := + 16#0#; + -- Buffer 0 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_0 : Boolean := False; + -- Reply with a stall (valid for both buffers). + STALL : Boolean := False; + -- Reset the buffer selector to buffer 0. + RESET : Boolean := False; + -- The data pid of buffer 0. + PID_0 : Boolean := False; + -- Buffer 0 is the last buffer of the transfer. + LAST_0 : Boolean := False; + -- Buffer 0 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_0 : Boolean := False; + -- The length of the data in buffer 1. + LENGTH_1 : EP15_OUT_BUFFER_CONTROL_LENGTH_1_Field := + 16#0#; + -- Buffer 1 is available. This bit is set to indicate the buffer can be + -- used by the controller. The controller clears the available bit when + -- writing the status back. + AVAILABLE_1 : Boolean := False; + -- The number of bytes buffer 1 is offset from buffer 0 in Isochronous + -- mode. Only valid in double buffered mode for an Isochronous endpoint. + -- For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET : EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Field := + RP2350_SVD.USB_DPRAM.Val_128; + -- The data pid of buffer 1. + PID_1 : Boolean := False; + -- Buffer 1 is the last buffer of the transfer. + LAST_1 : Boolean := False; + -- Buffer 1 is full. For an IN transfer (TX to the host) the bit is set + -- to indicate the data is valid. For an OUT transfer (RX from the host) + -- this bit should be left as a 0. The host will set it when it has + -- filled the buffer with data. + FULL_1 : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for EP15_OUT_BUFFER_CONTROL_Register use record + LENGTH_0 at 0 range 0 .. 9; + AVAILABLE_0 at 0 range 10 .. 10; + STALL at 0 range 11 .. 11; + RESET at 0 range 12 .. 12; + PID_0 at 0 range 13 .. 13; + LAST_0 at 0 range 14 .. 14; + FULL_0 at 0 range 15 .. 15; + LENGTH_1 at 0 range 16 .. 25; + AVAILABLE_1 at 0 range 26 .. 26; + DOUBLE_BUFFER_ISO_OFFSET at 0 range 27 .. 28; + PID_1 at 0 range 29 .. 29; + LAST_1 at 0 range 30 .. 30; + FULL_1 at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- DPRAM layout for USB device. + type USB_DPRAM_Peripheral is record + -- Bytes 0-3 of the SETUP packet from the host. + SETUP_PACKET_LOW : aliased SETUP_PACKET_LOW_Register; + -- Bytes 4-7 of the setup packet from the host. + SETUP_PACKET_HIGH : aliased SETUP_PACKET_HIGH_Register; + EP1_IN_CONTROL : aliased EP1_IN_CONTROL_Register; + EP1_OUT_CONTROL : aliased EP1_OUT_CONTROL_Register; + EP2_IN_CONTROL : aliased EP2_IN_CONTROL_Register; + EP2_OUT_CONTROL : aliased EP2_OUT_CONTROL_Register; + EP3_IN_CONTROL : aliased EP3_IN_CONTROL_Register; + EP3_OUT_CONTROL : aliased EP3_OUT_CONTROL_Register; + EP4_IN_CONTROL : aliased EP4_IN_CONTROL_Register; + EP4_OUT_CONTROL : aliased EP4_OUT_CONTROL_Register; + EP5_IN_CONTROL : aliased EP5_IN_CONTROL_Register; + EP5_OUT_CONTROL : aliased EP5_OUT_CONTROL_Register; + EP6_IN_CONTROL : aliased EP6_IN_CONTROL_Register; + EP6_OUT_CONTROL : aliased EP6_OUT_CONTROL_Register; + EP7_IN_CONTROL : aliased EP7_IN_CONTROL_Register; + EP7_OUT_CONTROL : aliased EP7_OUT_CONTROL_Register; + EP8_IN_CONTROL : aliased EP8_IN_CONTROL_Register; + EP8_OUT_CONTROL : aliased EP8_OUT_CONTROL_Register; + EP9_IN_CONTROL : aliased EP9_IN_CONTROL_Register; + EP9_OUT_CONTROL : aliased EP9_OUT_CONTROL_Register; + EP10_IN_CONTROL : aliased EP10_IN_CONTROL_Register; + EP10_OUT_CONTROL : aliased EP10_OUT_CONTROL_Register; + EP11_IN_CONTROL : aliased EP11_IN_CONTROL_Register; + EP11_OUT_CONTROL : aliased EP11_OUT_CONTROL_Register; + EP12_IN_CONTROL : aliased EP12_IN_CONTROL_Register; + EP12_OUT_CONTROL : aliased EP12_OUT_CONTROL_Register; + EP13_IN_CONTROL : aliased EP13_IN_CONTROL_Register; + EP13_OUT_CONTROL : aliased EP13_OUT_CONTROL_Register; + EP14_IN_CONTROL : aliased EP14_IN_CONTROL_Register; + EP14_OUT_CONTROL : aliased EP14_OUT_CONTROL_Register; + EP15_IN_CONTROL : aliased EP15_IN_CONTROL_Register; + EP15_OUT_CONTROL : aliased EP15_OUT_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP0_IN_BUFFER_CONTROL : aliased EP0_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP0_OUT_BUFFER_CONTROL : aliased EP0_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP1_IN_BUFFER_CONTROL : aliased EP1_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP1_OUT_BUFFER_CONTROL : aliased EP1_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP2_IN_BUFFER_CONTROL : aliased EP2_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP2_OUT_BUFFER_CONTROL : aliased EP2_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP3_IN_BUFFER_CONTROL : aliased EP3_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP3_OUT_BUFFER_CONTROL : aliased EP3_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP4_IN_BUFFER_CONTROL : aliased EP4_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP4_OUT_BUFFER_CONTROL : aliased EP4_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP5_IN_BUFFER_CONTROL : aliased EP5_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP5_OUT_BUFFER_CONTROL : aliased EP5_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP6_IN_BUFFER_CONTROL : aliased EP6_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP6_OUT_BUFFER_CONTROL : aliased EP6_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP7_IN_BUFFER_CONTROL : aliased EP7_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP7_OUT_BUFFER_CONTROL : aliased EP7_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP8_IN_BUFFER_CONTROL : aliased EP8_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP8_OUT_BUFFER_CONTROL : aliased EP8_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP9_IN_BUFFER_CONTROL : aliased EP9_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP9_OUT_BUFFER_CONTROL : aliased EP9_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP10_IN_BUFFER_CONTROL : aliased EP10_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP10_OUT_BUFFER_CONTROL : aliased EP10_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP11_IN_BUFFER_CONTROL : aliased EP11_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP11_OUT_BUFFER_CONTROL : aliased EP11_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP12_IN_BUFFER_CONTROL : aliased EP12_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP12_OUT_BUFFER_CONTROL : aliased EP12_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP13_IN_BUFFER_CONTROL : aliased EP13_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP13_OUT_BUFFER_CONTROL : aliased EP13_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP14_IN_BUFFER_CONTROL : aliased EP14_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP14_OUT_BUFFER_CONTROL : aliased EP14_OUT_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP15_IN_BUFFER_CONTROL : aliased EP15_IN_BUFFER_CONTROL_Register; + -- Buffer control for both buffers of an endpoint. Fields ending in a _1 + -- are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 + -- controls are only valid if the endpoint is in double buffered mode. + EP15_OUT_BUFFER_CONTROL : aliased EP15_OUT_BUFFER_CONTROL_Register; + end record + with Volatile; + + for USB_DPRAM_Peripheral use record + SETUP_PACKET_LOW at 16#0# range 0 .. 31; + SETUP_PACKET_HIGH at 16#4# range 0 .. 31; + EP1_IN_CONTROL at 16#8# range 0 .. 31; + EP1_OUT_CONTROL at 16#C# range 0 .. 31; + EP2_IN_CONTROL at 16#10# range 0 .. 31; + EP2_OUT_CONTROL at 16#14# range 0 .. 31; + EP3_IN_CONTROL at 16#18# range 0 .. 31; + EP3_OUT_CONTROL at 16#1C# range 0 .. 31; + EP4_IN_CONTROL at 16#20# range 0 .. 31; + EP4_OUT_CONTROL at 16#24# range 0 .. 31; + EP5_IN_CONTROL at 16#28# range 0 .. 31; + EP5_OUT_CONTROL at 16#2C# range 0 .. 31; + EP6_IN_CONTROL at 16#30# range 0 .. 31; + EP6_OUT_CONTROL at 16#34# range 0 .. 31; + EP7_IN_CONTROL at 16#38# range 0 .. 31; + EP7_OUT_CONTROL at 16#3C# range 0 .. 31; + EP8_IN_CONTROL at 16#40# range 0 .. 31; + EP8_OUT_CONTROL at 16#44# range 0 .. 31; + EP9_IN_CONTROL at 16#48# range 0 .. 31; + EP9_OUT_CONTROL at 16#4C# range 0 .. 31; + EP10_IN_CONTROL at 16#50# range 0 .. 31; + EP10_OUT_CONTROL at 16#54# range 0 .. 31; + EP11_IN_CONTROL at 16#58# range 0 .. 31; + EP11_OUT_CONTROL at 16#5C# range 0 .. 31; + EP12_IN_CONTROL at 16#60# range 0 .. 31; + EP12_OUT_CONTROL at 16#64# range 0 .. 31; + EP13_IN_CONTROL at 16#68# range 0 .. 31; + EP13_OUT_CONTROL at 16#6C# range 0 .. 31; + EP14_IN_CONTROL at 16#70# range 0 .. 31; + EP14_OUT_CONTROL at 16#74# range 0 .. 31; + EP15_IN_CONTROL at 16#78# range 0 .. 31; + EP15_OUT_CONTROL at 16#7C# range 0 .. 31; + EP0_IN_BUFFER_CONTROL at 16#80# range 0 .. 31; + EP0_OUT_BUFFER_CONTROL at 16#84# range 0 .. 31; + EP1_IN_BUFFER_CONTROL at 16#88# range 0 .. 31; + EP1_OUT_BUFFER_CONTROL at 16#8C# range 0 .. 31; + EP2_IN_BUFFER_CONTROL at 16#90# range 0 .. 31; + EP2_OUT_BUFFER_CONTROL at 16#94# range 0 .. 31; + EP3_IN_BUFFER_CONTROL at 16#98# range 0 .. 31; + EP3_OUT_BUFFER_CONTROL at 16#9C# range 0 .. 31; + EP4_IN_BUFFER_CONTROL at 16#A0# range 0 .. 31; + EP4_OUT_BUFFER_CONTROL at 16#A4# range 0 .. 31; + EP5_IN_BUFFER_CONTROL at 16#A8# range 0 .. 31; + EP5_OUT_BUFFER_CONTROL at 16#AC# range 0 .. 31; + EP6_IN_BUFFER_CONTROL at 16#B0# range 0 .. 31; + EP6_OUT_BUFFER_CONTROL at 16#B4# range 0 .. 31; + EP7_IN_BUFFER_CONTROL at 16#B8# range 0 .. 31; + EP7_OUT_BUFFER_CONTROL at 16#BC# range 0 .. 31; + EP8_IN_BUFFER_CONTROL at 16#C0# range 0 .. 31; + EP8_OUT_BUFFER_CONTROL at 16#C4# range 0 .. 31; + EP9_IN_BUFFER_CONTROL at 16#C8# range 0 .. 31; + EP9_OUT_BUFFER_CONTROL at 16#CC# range 0 .. 31; + EP10_IN_BUFFER_CONTROL at 16#D0# range 0 .. 31; + EP10_OUT_BUFFER_CONTROL at 16#D4# range 0 .. 31; + EP11_IN_BUFFER_CONTROL at 16#D8# range 0 .. 31; + EP11_OUT_BUFFER_CONTROL at 16#DC# range 0 .. 31; + EP12_IN_BUFFER_CONTROL at 16#E0# range 0 .. 31; + EP12_OUT_BUFFER_CONTROL at 16#E4# range 0 .. 31; + EP13_IN_BUFFER_CONTROL at 16#E8# range 0 .. 31; + EP13_OUT_BUFFER_CONTROL at 16#EC# range 0 .. 31; + EP14_IN_BUFFER_CONTROL at 16#F0# range 0 .. 31; + EP14_OUT_BUFFER_CONTROL at 16#F4# range 0 .. 31; + EP15_IN_BUFFER_CONTROL at 16#F8# range 0 .. 31; + EP15_OUT_BUFFER_CONTROL at 16#FC# range 0 .. 31; + end record; + + -- DPRAM layout for USB device. + USB_DPRAM_Periph : aliased USB_DPRAM_Peripheral + with Import, Address => USB_DPRAM_Base; + +end RP2350_SVD.USB_DPRAM; diff --git a/src/svd/rp2350_svd-watchdog.ads b/src/svd/rp2350_svd-watchdog.ads new file mode 100644 index 0000000..8b674f0 --- /dev/null +++ b/src/svd/rp2350_svd-watchdog.ads @@ -0,0 +1,179 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +package RP2350_SVD.WATCHDOG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CTRL_TIME_Field is HAL.UInt24; + + -- CTRL_PAUSE_DBG array + type CTRL_PAUSE_DBG_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CTRL_PAUSE_DBG + type CTRL_PAUSE_DBG_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PAUSE_DBG as a value + Val : HAL.UInt2; + when True => + -- PAUSE_DBG as an array + Arr : CTRL_PAUSE_DBG_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CTRL_PAUSE_DBG_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Watchdog control The rst_wdsel register determines which subsystems are + -- reset when the watchdog is triggered. The watchdog can be triggered in + -- software. + type CTRL_Register is record + -- Read-only. Indicates the time in usec before a watchdog reset will be + -- triggered + TIME : CTRL_TIME_Field := 16#0#; + -- Pause the watchdog timer when JTAG is accessing the bus fabric + PAUSE_JTAG : Boolean := True; + -- Pause the watchdog timer when processor 0 is in debug mode + PAUSE_DBG : CTRL_PAUSE_DBG_Field := + (As_Array => False, Val => 16#1#); + -- unspecified + Reserved_27_29 : HAL.UInt3 := 16#0#; + -- When not enabled the watchdog timer is paused + ENABLE : Boolean := False; + -- Write-only. Trigger a watchdog reset + TRIGGER : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + TIME at 0 range 0 .. 23; + PAUSE_JTAG at 0 range 24 .. 24; + PAUSE_DBG at 0 range 25 .. 26; + Reserved_27_29 at 0 range 27 .. 29; + ENABLE at 0 range 30 .. 30; + TRIGGER at 0 range 31 .. 31; + end record; + + subtype LOAD_LOAD_Field is HAL.UInt24; + + -- Load the watchdog timer. The maximum setting is 0xffffff which + -- corresponds to approximately 16 seconds. + type LOAD_Register is record + -- Write-only. + LOAD : LOAD_LOAD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for LOAD_Register use record + LOAD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Logs the reason for the last reset. Both bits are zero for the case of a + -- hardware reset. Additionally, as of RP2350, a debugger warm reset of + -- either core (SYSRESETREQ or hartreset) will also clear the watchdog + -- reason register, so that software loaded under the debugger following a + -- watchdog timeout will not continue to see the timeout condition. + type REASON_Register is record + -- Read-only. + TIMER : Boolean; + -- Read-only. + FORCE : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for REASON_Register use record + TIMER at 0 range 0 .. 0; + FORCE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type WATCHDOG_Peripheral is record + -- Watchdog control The rst_wdsel register determines which subsystems + -- are reset when the watchdog is triggered. The watchdog can be + -- triggered in software. + CTRL : aliased CTRL_Register; + -- Load the watchdog timer. The maximum setting is 0xffffff which + -- corresponds to approximately 16 seconds. + LOAD : aliased LOAD_Register; + -- Logs the reason for the last reset. Both bits are zero for the case + -- of a hardware reset. Additionally, as of RP2350, a debugger warm + -- reset of either core (SYSRESETREQ or hartreset) will also clear the + -- watchdog reason register, so that software loaded under the debugger + -- following a watchdog timeout will not continue to see the timeout + -- condition. + REASON : aliased REASON_Register; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH0 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH1 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH2 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH3 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH4 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH5 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH6 : aliased HAL.UInt32; + -- Scratch register. Information persists through soft reset of the + -- chip. + SCRATCH7 : aliased HAL.UInt32; + end record + with Volatile; + + for WATCHDOG_Peripheral use record + CTRL at 16#0# range 0 .. 31; + LOAD at 16#4# range 0 .. 31; + REASON at 16#8# range 0 .. 31; + SCRATCH0 at 16#C# range 0 .. 31; + SCRATCH1 at 16#10# range 0 .. 31; + SCRATCH2 at 16#14# range 0 .. 31; + SCRATCH3 at 16#18# range 0 .. 31; + SCRATCH4 at 16#1C# range 0 .. 31; + SCRATCH5 at 16#20# range 0 .. 31; + SCRATCH6 at 16#24# range 0 .. 31; + SCRATCH7 at 16#28# range 0 .. 31; + end record; + + WATCHDOG_Periph : aliased WATCHDOG_Peripheral + with Import, Address => WATCHDOG_Base; + +end RP2350_SVD.WATCHDOG; diff --git a/src/svd/rp2350_svd-xip_aux.ads b/src/svd/rp2350_svd-xip_aux.ads new file mode 100644 index 0000000..ae73f47 --- /dev/null +++ b/src/svd/rp2350_svd-xip_aux.ads @@ -0,0 +1,132 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Auxiliary DMA access to XIP FIFOs, via fast AHB bus access +package RP2350_SVD.XIP_AUX is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype QMI_DIRECT_TX_DATA_Field is HAL.UInt16; + + -- Configure whether this FIFO record is transferred with single/dual/quad + -- interface width (0/1/2). Different widths can be mixed freely. + type QMI_DIRECT_TX_IWIDTH_Field is + (-- Single width + S, + -- Dual width + D, + -- Quad width + Q) + with Size => 2; + for QMI_DIRECT_TX_IWIDTH_Field use + (S => 0, + D => 1, + Q => 2); + + -- Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + type QMI_DIRECT_TX_Register is record + -- Write-only. Data pushed here will be clocked out falling edges of SCK + -- (or before the very first rising edge of SCK, if this is the first + -- pulse). For each byte clocked out, the interface will simultaneously + -- sample one byte, on rising edges of SCK, and push this to the + -- DIRECT_RX FIFO. For 16-bit data, the least-significant byte is + -- transmitted first. + DATA : QMI_DIRECT_TX_DATA_Field := 16#0#; + -- Write-only. Configure whether this FIFO record is transferred with + -- single/dual/quad interface width (0/1/2). Different widths can be + -- mixed freely. + IWIDTH : QMI_DIRECT_TX_IWIDTH_Field := RP2350_SVD.XIP_AUX.S; + -- Write-only. Data width. If 0, hardware will transmit the 8 LSBs of + -- the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of + -- DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit + -- transfers can be mixed freely. + DWIDTH : Boolean := False; + -- Write-only. Output enable (active-high). For single width (SPI), this + -- field is ignored, and SD0 is always set to output, with SD1 always + -- set to input. For dual and quad width (DSPI/QSPI), this sets whether + -- the relevant SDx pads are set to output whilst transferring this FIFO + -- record. In this case the command/address should have OE set, and the + -- data transfer should have OE set or clear depending on the direction + -- of the transfer. + OE : Boolean := False; + -- Write-only. Inhibit the RX FIFO push that would correspond to this TX + -- FIFO entry. Useful to avoid garbage appearing in the RX FIFO when + -- pushing the command at the beginning of a SPI transfer. + NOPUSH : Boolean := False; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for QMI_DIRECT_TX_Register use record + DATA at 0 range 0 .. 15; + IWIDTH at 0 range 16 .. 17; + DWIDTH at 0 range 18 .. 18; + OE at 0 range 19 .. 19; + NOPUSH at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype QMI_DIRECT_RX_QMI_DIRECT_RX_Field is HAL.UInt16; + + -- Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + type QMI_DIRECT_RX_Register is record + -- Read-only. *** This field is modified following a read operation ***. + -- With each byte clocked out on the serial interface, one byte will + -- simultaneously be clocked in, and will appear in this FIFO. The + -- serial interface will stall when this FIFO is full, to avoid dropping + -- data. When 16-bit data is pushed into the TX FIFO, the corresponding + -- RX FIFO push will also contain 16 bits of data. The least-significant + -- byte is the first one received. + QMI_DIRECT_RX : QMI_DIRECT_RX_QMI_DIRECT_RX_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for QMI_DIRECT_RX_Register use record + QMI_DIRECT_RX at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + type XIP_AUX_Peripheral is record + -- Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + STREAM : aliased HAL.UInt32; + -- Write to the QMI direct-mode TX FIFO (fast bus access to + -- QMI_DIRECT_TX) + QMI_DIRECT_TX : aliased QMI_DIRECT_TX_Register; + -- Read from the QMI direct-mode RX FIFO (fast bus access to + -- QMI_DIRECT_RX) + QMI_DIRECT_RX : aliased QMI_DIRECT_RX_Register; + end record + with Volatile; + + for XIP_AUX_Peripheral use record + STREAM at 16#0# range 0 .. 31; + QMI_DIRECT_TX at 16#4# range 0 .. 31; + QMI_DIRECT_RX at 16#8# range 0 .. 31; + end record; + + -- Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + XIP_AUX_Periph : aliased XIP_AUX_Peripheral + with Import, Address => XIP_AUX_Base; + +end RP2350_SVD.XIP_AUX; diff --git a/src/svd/rp2350_svd-xip_ctrl.ads b/src/svd/rp2350_svd-xip_ctrl.ads new file mode 100644 index 0000000..dc5a65a --- /dev/null +++ b/src/svd/rp2350_svd-xip_ctrl.ads @@ -0,0 +1,249 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- QSPI flash execute-in-place block +package RP2350_SVD.XIP_CTRL is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- CTRL_WRITABLE_M array + type CTRL_WRITABLE_M_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for CTRL_WRITABLE_M + type CTRL_WRITABLE_M_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WRITABLE_M as a value + Val : HAL.UInt2; + when True => + -- WRITABLE_M as an array + Arr : CTRL_WRITABLE_M_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for CTRL_WRITABLE_M_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Cache control register. Read-only from a Non-secure context. + type CTRL_Register is record + -- When 1, enable the cache for Secure accesses. When enabled, Secure + -- XIP accesses to the cached (addr[26] == 0) window will query the + -- cache, and QSPI accesses are performed only if the requested data is + -- not present. When disabled, Secure access ignore the cache contents, + -- and always access the QSPI interface. Accesses to the uncached + -- (addr[26] == 1) window will never query the cache, irrespective of + -- this bit. There is no cache-as-SRAM address window. Cache lines are + -- allocated for SRAM-like use by individually pinning them, and keeping + -- the cache enabled. + EN_SECURE : Boolean := True; + -- When 1, enable the cache for Non-secure accesses. When enabled, + -- Non-secure XIP accesses to the cached (addr[26] == 0) window will + -- query the cache, and QSPI accesses are performed only if the + -- requested data is not present. When disabled, Secure access ignore + -- the cache contents, and always access the QSPI interface. Accesses to + -- the uncached (addr[26] == 1) window will never query the cache, + -- irrespective of this bit. + EN_NONSECURE : Boolean := True; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- When 1, the cache memories are powered down. They retain state, but + -- can not be accessed. This reduces static power dissipation. Writing 1 + -- to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. + -- the cache cannot be enabled when powered down. + POWER_DOWN : Boolean := False; + -- When 1, Secure accesses to the uncached window (addr[27:26] == 1) + -- will generate a bus error. This may reduce the number of SAU/MPU/PMP + -- regions required to protect flash contents. Note this does not + -- disable access to the uncached, untranslated window -- see + -- NO_UNTRANSLATED_SEC. + NO_UNCACHED_SEC : Boolean := False; + -- When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) + -- will generate a bus error. This may reduce the number of SAU/MPU/PMP + -- regions required to protect flash contents. Note this does not + -- disable access to the uncached, untranslated window -- see + -- NO_UNTRANSLATED_SEC. + NO_UNCACHED_NONSEC : Boolean := False; + -- When 1, Secure accesses to the uncached, untranslated window + -- (addr[27:26] == 3) will generate a bus error. + NO_UNTRANSLATED_SEC : Boolean := False; + -- When 1, Non-secure accesses to the uncached, untranslated window + -- (addr[27:26] == 3) will generate a bus error. + NO_UNTRANSLATED_NONSEC : Boolean := True; + -- When 0, Non-secure accesses to the cache maintenance address window + -- (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, + -- Non-secure accesses can perform cache maintenance operations by + -- writing to the cache maintenance address window. Cache maintenance + -- operations may be used to corrupt Secure data by invalidating cache + -- lines inappropriately, or map Secure content into a Non-secure region + -- by pinning cache lines. Therefore this bit should generally be set to + -- 0, unless Secure code is not using the cache. Care should also be + -- taken to clear the cache data memory and tag memory before granting + -- maintenance operations to Non-secure code. + MAINT_NONSEC : Boolean := False; + -- When 1, route all cached+Secure accesses to way 0 of the cache, and + -- route all cached+Non-secure accesses to way 1 of the cache. This + -- partitions the cache into two half-sized direct-mapped regions, such + -- that Non-secure code can not observe cache line state changes caused + -- by Secure execution. A full cache flush is required when changing the + -- value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS + -- is 0, so that both cache ways are accessible for invalidation. + SPLIT_WAYS : Boolean := False; + -- If 1, enable writes to XIP memory window 0 (addresses 0x10000000 + -- through 0x10ffffff, and their uncached mirrors). If 0, this region is + -- read-only. XIP memory is *read-only by default*. This bit must be set + -- to enable writes if a RAM device is attached on QSPI chip select 0. + -- The default read-only behaviour avoids two issues with writing to a + -- read-only QSPI device (e.g. flash). First, a write will initially + -- appear to succeed due to caching, but the data will eventually be + -- lost when the written line is evicted, causing unpredictable + -- behaviour. Second, when a written line is evicted, it will cause a + -- write command to be issued to the flash, which can break the flash + -- out of its continuous read mode. After this point, flash reads will + -- return garbage. This is a security concern, as it allows Non-secure + -- software to break Secure flash reads if it has permission to write to + -- any flash address. Note the read-only behaviour is implemented by + -- downgrading writes to reads, so writes will still cause allocation of + -- an address, but have no other effect. + WRITABLE_M : CTRL_WRITABLE_M_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + EN_SECURE at 0 range 0 .. 0; + EN_NONSECURE at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + POWER_DOWN at 0 range 3 .. 3; + NO_UNCACHED_SEC at 0 range 4 .. 4; + NO_UNCACHED_NONSEC at 0 range 5 .. 5; + NO_UNTRANSLATED_SEC at 0 range 6 .. 6; + NO_UNTRANSLATED_NONSEC at 0 range 7 .. 7; + MAINT_NONSEC at 0 range 8 .. 8; + SPLIT_WAYS at 0 range 9 .. 9; + WRITABLE_M at 0 range 10 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + type STAT_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit; + -- Read-only. When 1, indicates the XIP streaming FIFO is completely + -- empty. + FIFO_EMPTY : Boolean; + -- Read-only. When 1, indicates the XIP streaming FIFO is completely + -- full. The streaming FIFO is 2 entries deep, so the full and empty + -- flag allow its level to be ascertained. + FIFO_FULL : Boolean; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STAT_Register use record + Reserved_0_0 at 0 range 0 .. 0; + FIFO_EMPTY at 0 range 1 .. 1; + FIFO_FULL at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype STREAM_ADDR_STREAM_ADDR_Field is HAL.UInt30; + + -- FIFO stream address + type STREAM_ADDR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- The address of the next word to be streamed from flash to the + -- streaming FIFO. Increments automatically after each flash access. + -- Write the initial access address here before starting a streaming + -- read. + STREAM_ADDR : STREAM_ADDR_STREAM_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STREAM_ADDR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + STREAM_ADDR at 0 range 2 .. 31; + end record; + + subtype STREAM_CTR_STREAM_CTR_Field is HAL.UInt22; + + -- FIFO stream control + type STREAM_CTR_Register is record + -- Write a nonzero value to start a streaming read. This will then + -- progress in the background, using flash idle cycles to transfer a + -- linear data block from flash to the streaming FIFO. Decrements + -- automatically (1 at a time) as the stream progresses, and halts on + -- reaching 0. Write 0 to halt an in-progress stream, and discard any + -- in-flight read, so that a new stream can immediately be started + -- (after draining the FIFO and reinitialising STREAM_ADDR) + STREAM_CTR : STREAM_CTR_STREAM_CTR_Field := 16#0#; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STREAM_CTR_Register use record + STREAM_CTR at 0 range 0 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- QSPI flash execute-in-place block + type XIP_CTRL_Peripheral is record + -- Cache control register. Read-only from a Non-secure context. + CTRL : aliased CTRL_Register; + STAT : aliased STAT_Register; + -- Cache Hit counter + CTR_HIT : aliased HAL.UInt32; + -- Cache Access counter + CTR_ACC : aliased HAL.UInt32; + -- FIFO stream address + STREAM_ADDR : aliased STREAM_ADDR_Register; + -- FIFO stream control + STREAM_CTR : aliased STREAM_CTR_Register; + -- FIFO stream data + STREAM_FIFO : aliased HAL.UInt32; + end record + with Volatile; + + for XIP_CTRL_Peripheral use record + CTRL at 16#0# range 0 .. 31; + STAT at 16#8# range 0 .. 31; + CTR_HIT at 16#C# range 0 .. 31; + CTR_ACC at 16#10# range 0 .. 31; + STREAM_ADDR at 16#14# range 0 .. 31; + STREAM_CTR at 16#18# range 0 .. 31; + STREAM_FIFO at 16#1C# range 0 .. 31; + end record; + + -- QSPI flash execute-in-place block + XIP_CTRL_Periph : aliased XIP_CTRL_Peripheral + with Import, Address => XIP_CTRL_Base; + +end RP2350_SVD.XIP_CTRL; diff --git a/src/svd/rp2350_svd-xosc.ads b/src/svd/rp2350_svd-xosc.ads new file mode 100644 index 0000000..defbe56 --- /dev/null +++ b/src/svd/rp2350_svd-xosc.ads @@ -0,0 +1,216 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with HAL; +with System; + +-- Controls the crystal oscillator +package RP2350_SVD.XOSC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- The 12-bit code is intended to give some protection against accidental + -- writes. An invalid setting will retain the previous value. The actual + -- value being used can be read from STATUS_FREQ_RANGE + type CTRL_FREQ_RANGE_Field is + (-- Reset value for the field + CTRL_FREQ_RANGE_Field_Reset, + Val_1_15MHZ, + Val_10_30MHZ, + Val_25_60MHZ, + Val_40_100MHZ) + with Size => 12; + for CTRL_FREQ_RANGE_Field use + (CTRL_FREQ_RANGE_Field_Reset => 0, + Val_1_15MHZ => 2720, + Val_10_30MHZ => 2721, + Val_25_60MHZ => 2722, + Val_40_100MHZ => 2723); + + -- On power-up this field is initialised to DISABLE and the chip runs from + -- the ROSC. If the chip has subsequently been programmed to run from the + -- XOSC then setting this field to DISABLE may lock-up the chip. If this is + -- a concern then run the clk_ref from the ROSC and enable the clk_sys + -- RESUS feature. The 12-bit code is intended to give some protection + -- against accidental writes. An invalid setting will retain the previous + -- value. The actual value being used can be read from STATUS_ENABLED + type CTRL_ENABLE_Field is + (-- Reset value for the field + CTRL_ENABLE_Field_Reset, + DISABLE, + ENABLE) + with Size => 12; + for CTRL_ENABLE_Field use + (CTRL_ENABLE_Field_Reset => 0, + DISABLE => 3358, + ENABLE => 4011); + + -- Crystal Oscillator Control + type CTRL_Register is record + -- The 12-bit code is intended to give some protection against + -- accidental writes. An invalid setting will retain the previous value. + -- The actual value being used can be read from STATUS_FREQ_RANGE + FREQ_RANGE : CTRL_FREQ_RANGE_Field := CTRL_FREQ_RANGE_Field_Reset; + -- On power-up this field is initialised to DISABLE and the chip runs + -- from the ROSC. If the chip has subsequently been programmed to run + -- from the XOSC then setting this field to DISABLE may lock-up the + -- chip. If this is a concern then run the clk_ref from the ROSC and + -- enable the clk_sys RESUS feature. The 12-bit code is intended to give + -- some protection against accidental writes. An invalid setting will + -- retain the previous value. The actual value being used can be read + -- from STATUS_ENABLED + ENABLE : CTRL_ENABLE_Field := CTRL_ENABLE_Field_Reset; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for CTRL_Register use record + FREQ_RANGE at 0 range 0 .. 11; + ENABLE at 0 range 12 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- The current frequency range setting + type STATUS_FREQ_RANGE_Field is + (Val_1_15MHZ, + Val_10_30MHZ, + Val_25_60MHZ, + Val_40_100MHZ) + with Size => 2; + for STATUS_FREQ_RANGE_Field use + (Val_1_15MHZ => 0, + Val_10_30MHZ => 1, + Val_25_60MHZ => 2, + Val_40_100MHZ => 3); + + -- Crystal Oscillator Status + type STATUS_Register is record + -- Read-only. The current frequency range setting + FREQ_RANGE : STATUS_FREQ_RANGE_Field := RP2350_SVD.XOSC.Val_1_15MHZ; + -- unspecified + Reserved_2_11 : HAL.UInt10 := 16#0#; + -- Read-only. Oscillator is enabled but not necessarily running and + -- stable, resets to 0 + ENABLED : Boolean := False; + -- unspecified + Reserved_13_23 : HAL.UInt11 := 16#0#; + -- Write data bit of one shall clear (set to zero) the corresponding bit + -- in the field. An invalid value has been written to CTRL_ENABLE or + -- CTRL_FREQ_RANGE or DORMANT + BADWRITE : Boolean := False; + -- unspecified + Reserved_25_30 : HAL.UInt6 := 16#0#; + -- Read-only. Oscillator is running and stable + STABLE : Boolean := False; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STATUS_Register use record + FREQ_RANGE at 0 range 0 .. 1; + Reserved_2_11 at 0 range 2 .. 11; + ENABLED at 0 range 12 .. 12; + Reserved_13_23 at 0 range 13 .. 23; + BADWRITE at 0 range 24 .. 24; + Reserved_25_30 at 0 range 25 .. 30; + STABLE at 0 range 31 .. 31; + end record; + + subtype STARTUP_DELAY_Field is HAL.UInt14; + + -- Controls the startup delay + type STARTUP_Register is record + -- in multiples of 256*xtal_period. The reset value of 0xc4 corresponds + -- to approx 50 000 cycles. + DELAY_k : STARTUP_DELAY_Field := 16#0#; + -- unspecified + Reserved_14_19 : HAL.UInt6 := 16#0#; + -- Multiplies the startup_delay by 4, just in case. The reset value is + -- controlled by a mask-programmable tiecell and is provided in case we + -- are booting from XOSC and the default startup delay is insufficient. + -- The reset value is 0x0. + X4 : Boolean := False; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for STARTUP_Register use record + DELAY_k at 0 range 0 .. 13; + Reserved_14_19 at 0 range 14 .. 19; + X4 at 0 range 20 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + subtype COUNT_COUNT_Field is HAL.UInt16; + + -- A down counter running at the xosc frequency which counts to zero and + -- stops. Can be used for short software pauses when setting up time + -- sensitive hardware. To start the counter, write a non-zero value. Reads + -- will return 1 while the count is running and 0 when it has finished. + -- Minimum count value is 4. Count values <4 will be treated as count value + -- =4. Note that synchronisation to the register clock domain costs 2 + -- register clock cycles and the counter cannot compensate for that. + type COUNT_Register is record + COUNT : COUNT_COUNT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Object_Size => 32, + Bit_Order => System.Low_Order_First; + + for COUNT_Register use record + COUNT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Controls the crystal oscillator + type XOSC_Peripheral is record + -- Crystal Oscillator Control + CTRL : aliased CTRL_Register; + -- Crystal Oscillator Status + STATUS : aliased STATUS_Register; + -- Crystal Oscillator pause control + DORMANT : aliased HAL.UInt32; + -- Controls the startup delay + STARTUP : aliased STARTUP_Register; + -- A down counter running at the xosc frequency which counts to zero and + -- stops. Can be used for short software pauses when setting up time + -- sensitive hardware. To start the counter, write a non-zero value. + -- Reads will return 1 while the count is running and 0 when it has + -- finished. Minimum count value is 4. Count values <4 will be treated + -- as count value =4. Note that synchronisation to the register clock + -- domain costs 2 register clock cycles and the counter cannot + -- compensate for that. + COUNT : aliased COUNT_Register; + end record + with Volatile; + + for XOSC_Peripheral use record + CTRL at 16#0# range 0 .. 31; + STATUS at 16#4# range 0 .. 31; + DORMANT at 16#8# range 0 .. 31; + STARTUP at 16#C# range 0 .. 31; + COUNT at 16#10# range 0 .. 31; + end record; + + -- Controls the crystal oscillator + XOSC_Periph : aliased XOSC_Peripheral + with Import, Address => XOSC_Base; + +end RP2350_SVD.XOSC; diff --git a/src/svd/rp2350_svd.ads b/src/svd/rp2350_svd.ads new file mode 100644 index 0000000..59c8a2c --- /dev/null +++ b/src/svd/rp2350_svd.ads @@ -0,0 +1,104 @@ +pragma Style_Checks (Off); + +-- Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + +-- This spec has been automatically generated from rp2350.svd + +pragma Restrictions (No_Elaboration_Code); + +with System; + +-- +-- Dual Cortex-M33 or Hazard3 processors at 150MHz +-- 520kB on-chip SRAM, in 10 independent banks +-- Extended low-power sleep states with optional SRAM retention: as +-- low as 10uA DVDD +-- 8kB of one-time-programmable storage (OTP) +-- Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus +-- Additional 16MB flash/PSRAM accessible via optional second +-- chip-select +-- On-chip switched-mode power supply to generate core voltage +-- Low-quiescent-current LDO mode can be enabled for sleep states +-- 2x on-chip PLLs for internal or external clock generation +-- GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) +-- Security features: +-- Optional boot signing, enforced by on-chip mask ROM, with key +-- fingerprint in OTP +-- Protected OTP storage for optional boot decryption key +-- Global bus filtering based on Arm or RISC-V security/privilege +-- levels +-- Peripherals, GPIOs and DMA channels individually assignable to +-- security domains +-- Hardware mitigations for fault injection attacks +-- Hardware SHA-256 accelerator +-- Peripherals: +-- 2x UARTs +-- 2x SPI controllers +-- 2x I2C controllers +-- 24x PWM channels +-- USB 1.1 controller and PHY, with host and device support +-- 12x PIO state machines +-- 1x HSTX peripheral +-- +package RP2350_SVD is + pragma Preelaborate; + + -------------------- + -- Base addresses -- + -------------------- + + RESETS_Base : constant System.Address := System'To_Address (16#40020000#); + PSM_Base : constant System.Address := System'To_Address (16#40018000#); + CLOCKS_Base : constant System.Address := System'To_Address (16#40010000#); + TICKS_Base : constant System.Address := System'To_Address (16#40108000#); + PADS_BANK0_Base : constant System.Address := System'To_Address (16#40038000#); + PADS_QSPI_Base : constant System.Address := System'To_Address (16#40040000#); + IO_QSPI_Base : constant System.Address := System'To_Address (16#40030000#); + IO_BANK0_Base : constant System.Address := System'To_Address (16#40028000#); + SYSINFO_Base : constant System.Address := System'To_Address (16#40000000#); + SHA256_Base : constant System.Address := System'To_Address (16#400F8000#); + HSTX_FIFO_Base : constant System.Address := System'To_Address (16#50600000#); + HSTX_CTRL_Base : constant System.Address := System'To_Address (16#400C0000#); + EPPB_Base : constant System.Address := System'To_Address (16#E0080000#); + PPB_Base : constant System.Address := System'To_Address (16#E0000000#); + PPB_NS_Base : constant System.Address := System'To_Address (16#E0020000#); + QMI_Base : constant System.Address := System'To_Address (16#400D0000#); + XIP_CTRL_Base : constant System.Address := System'To_Address (16#400C8000#); + XIP_AUX_Base : constant System.Address := System'To_Address (16#50500000#); + SYSCFG_Base : constant System.Address := System'To_Address (16#40008000#); + XOSC_Base : constant System.Address := System'To_Address (16#40048000#); + PLL_SYS_Base : constant System.Address := System'To_Address (16#40050000#); + PLL_USB_Base : constant System.Address := System'To_Address (16#40058000#); + ACCESSCTRL_Base : constant System.Address := System'To_Address (16#40060000#); + UART0_Base : constant System.Address := System'To_Address (16#40070000#); + UART1_Base : constant System.Address := System'To_Address (16#40078000#); + ROSC_Base : constant System.Address := System'To_Address (16#400E8000#); + POWMAN_Base : constant System.Address := System'To_Address (16#40100000#); + WATCHDOG_Base : constant System.Address := System'To_Address (16#400D8000#); + DMA_Base : constant System.Address := System'To_Address (16#50000000#); + TIMER0_Base : constant System.Address := System'To_Address (16#400B0000#); + TIMER1_Base : constant System.Address := System'To_Address (16#400B8000#); + PWM_Base : constant System.Address := System'To_Address (16#400A8000#); + ADC_Base : constant System.Address := System'To_Address (16#400A0000#); + I2C0_Base : constant System.Address := System'To_Address (16#40090000#); + I2C1_Base : constant System.Address := System'To_Address (16#40098000#); + SPI0_Base : constant System.Address := System'To_Address (16#40080000#); + SPI1_Base : constant System.Address := System'To_Address (16#40088000#); + PIO0_Base : constant System.Address := System'To_Address (16#50200000#); + PIO1_Base : constant System.Address := System'To_Address (16#50300000#); + PIO2_Base : constant System.Address := System'To_Address (16#50400000#); + BUSCTRL_Base : constant System.Address := System'To_Address (16#40068000#); + SIO_Base : constant System.Address := System'To_Address (16#D0000000#); + SIO_NS_Base : constant System.Address := System'To_Address (16#D0020000#); + BOOTRAM_Base : constant System.Address := System'To_Address (16#400E0000#); + CORESIGHT_TRACE_Base : constant System.Address := System'To_Address (16#50700000#); + USB_Base : constant System.Address := System'To_Address (16#50110000#); + TRNG_Base : constant System.Address := System'To_Address (16#400F0000#); + GLITCH_DETECTOR_Base : constant System.Address := System'To_Address (16#40158000#); + OTP_Base : constant System.Address := System'To_Address (16#40120000#); + OTP_DATA_Base : constant System.Address := System'To_Address (16#40130000#); + OTP_DATA_RAW_Base : constant System.Address := System'To_Address (16#40134000#); + TBMAN_Base : constant System.Address := System'To_Address (16#40160000#); + USB_DPRAM_Base : constant System.Address := System'To_Address (16#50100000#); + +end RP2350_SVD; diff --git a/tests/src/test_suite.adb b/tests/src/test_suite.adb index 122f871..80ce104 100644 --- a/tests/src/test_suite.adb +++ b/tests/src/test_suite.adb @@ -10,8 +10,8 @@ with UART_Tests; with PWM_Tests; with DMA_Tests; with ADC_Tests; -with ROM_Tests; -with RTC_Tests; +-- with ROM_Tests; +-- with RTC_Tests; with SPI_Tests; with I2C_Tests; -- with Flash_Tests; @@ -28,8 +28,8 @@ package body Test_Suite is PWM_Case : aliased PWM_Tests.PWM_Test; DMA_Case : aliased DMA_Tests.DMA_Test; ADC_Case : aliased ADC_Tests.ADC_Test; - ROM_Case : aliased ROM_Tests.ROM_Test; - RTC_Case : aliased RTC_Tests.RTC_Test; + -- ROM_Case : aliased ROM_Tests.ROM_Test; + -- RTC_Case : aliased RTC_Tests.RTC_Test; SPI_Case : aliased SPI_Tests.SPI_Test; I2C_Case : aliased I2C_Tests.I2C_Test; -- Flash_Case : aliased Flash_Tests.Flash_Test; @@ -48,8 +48,8 @@ package body Test_Suite is Add_Test (Result'Access, PWM_Case'Access); Add_Test (Result'Access, DMA_Case'Access); Add_Test (Result'Access, ADC_Case'Access); - Add_Test (Result'Access, ROM_Case'Access); - Add_Test (Result'Access, RTC_Case'Access); + -- Add_Test (Result'Access, ROM_Case'Access); + -- Add_Test (Result'Access, RTC_Case'Access); Add_Test (Result'Access, SPI_Case'Access); Add_Test (Result'Access, I2C_Case'Access); Add_Test (Result'Access, PIO_Case'Access);