From 1b3e3f1aa64183f5eaef34a244cc39b1ec62a23a Mon Sep 17 00:00:00 2001
From: GuillaumeG <48102745+JonathSpirit@users.noreply.github.com>
Date: Mon, 9 Mar 2020 19:31:54 +0100
Subject: [PATCH] Adding copyright and license notice

---
 AddressCounter.sch    |   6 +-
 AddressExchanger.sch  |   6 +-
 ClockGenerator.sch    |   6 +-
 Connector.sch         |   6 +-
 MemoryController.sch  |   6 +-
 MemorySlot1.sch       |   6 +-
 MemorySlot2.sch       |   6 +-
 Peripherals.sch       |   8 +-
 Project_GCM.kicad_pcb |   2 +
 Project_GCM.sch       | 392 +++++++++++++++++++++---------------------
 10 files changed, 224 insertions(+), 220 deletions(-)

diff --git a/AddressCounter.sch b/AddressCounter.sch
index c18d41a..d41b52e 100644
--- a/AddressCounter.sch
+++ b/AddressCounter.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/AddressExchanger.sch b/AddressExchanger.sch
index 41dae97..e8dcc95 100644
--- a/AddressExchanger.sch
+++ b/AddressExchanger.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/ClockGenerator.sch b/ClockGenerator.sch
index 74f556a..b194475 100644
--- a/ClockGenerator.sch
+++ b/ClockGenerator.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/Connector.sch b/Connector.sch
index b9a2971..f433a61 100644
--- a/Connector.sch
+++ b/Connector.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/MemoryController.sch b/MemoryController.sch
index e2b74f4..2589ea1 100644
--- a/MemoryController.sch
+++ b/MemoryController.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/MemorySlot1.sch b/MemorySlot1.sch
index 3506e8c..6065aa6 100644
--- a/MemorySlot1.sch
+++ b/MemorySlot1.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/MemorySlot2.sch b/MemorySlot2.sch
index 7a88ecd..6dee279 100644
--- a/MemorySlot2.sch
+++ b/MemorySlot2.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
diff --git a/Peripherals.sch b/Peripherals.sch
index e278ac2..eabce84 100644
--- a/Peripherals.sch
+++ b/Peripherals.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
@@ -1511,6 +1511,7 @@ F 3 "" H 4700 7500 50  0001 C CNN
 $EndComp
 Wire Wire Line
 	4700 7500 4700 7450
+Connection ~ 4700 7450
 Wire Bus Line
 	1600 3800 1600 4400
 Wire Bus Line
@@ -1521,5 +1522,4 @@ Wire Bus Line
 	10250 800  10250 1600
 Wire Bus Line
 	10250 2200 10250 3000
-Connection ~ 4700 7450
 $EndSCHEMATC
diff --git a/Project_GCM.kicad_pcb b/Project_GCM.kicad_pcb
index 1082ca4..751cbdc 100644
--- a/Project_GCM.kicad_pcb
+++ b/Project_GCM.kicad_pcb
@@ -15,6 +15,8 @@
     (date 2019-07-19)
     (rev V4)
     (company "Guillaume Guillet")
+    (comment 1 "Copyright Guillaume Guillet 2020")
+    (comment 2 "Licensed under CERN OHL v.1.2")
   )
 
   (layers
diff --git a/Project_GCM.sch b/Project_GCM.sch
index 59f928a..96836b9 100644
--- a/Project_GCM.sch
+++ b/Project_GCM.sch
@@ -1,6 +1,6 @@
 EESchema Schematic File Version 4
 LIBS:Project_GCM-cache
-EELAYER 29 0
+EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -9,8 +9,8 @@ Title "GCM"
 Date "2019-07-07"
 Rev "V4"
 Comp "Guillaume Guillet"
-Comment1 ""
-Comment2 ""
+Comment1 "Copyright Guillaume Guillet 2020"
+Comment2 "Licensed under CERN OHL v.1.2"
 Comment3 ""
 Comment4 ""
 $EndDescr
@@ -433,42 +433,42 @@ Wire Wire Line
 Wire Wire Line
 	8100 1050 8050 1050
 $Sheet
-S 4850 4050 2100 550 
+S 4850 3950 2100 550 
 U 5B94DD6C
 F0 "MemorySlot1" 60
 F1 "MemorySlot1.sch" 60
-F2 "MEM_ADD_[0..23]" I L 4850 4150 60 
-F3 "MEM_~OE" I L 4850 4300 60 
-F4 "MEM_~CE" I L 4850 4400 60 
-F5 "MEM_~WE" I L 4850 4500 60 
-F6 "MEMDATA_[0..7]" B R 6950 4150 60 
+F2 "MEM_ADD_[0..23]" I L 4850 4050 60 
+F3 "MEM_~OE" I L 4850 4200 60 
+F4 "MEM_~CE" I L 4850 4300 60 
+F5 "MEM_~WE" I L 4850 4400 60 
+F6 "MEMDATA_[0..7]" B R 6950 4050 60 
 $EndSheet
 $Sheet
-S 4850 2350 2100 1450
+S 4850 2250 2100 1450
 U 5B965978
 F0 "MemoryController" 60
 F1 "MemoryController.sch" 60
-F2 "BWRITE1_[0..7]" I L 4850 2500 60 
-F3 "~RESET_CLK" I L 4850 2900 60 
-F4 "MEM2DATA_[0..7]" B R 6950 2500 60 
-F5 "MEM1DATA_[0..7]" B R 6950 2400 60 
-F6 "BREAD1_[0..7]" T L 4850 2400 60 
-F7 "BJMPSRC_[0..23]" I L 4850 2650 60 
-F8 "SRCADD_[0..23]" I L 4850 2750 60 
-F9 "MEM2ADD_[0..23]" O R 6950 2750 60 
-F10 "MEM1ADD_[0..23]" O R 6950 2650 60 
-F11 "MEM1_~WE" O R 6950 2900 60 
-F12 "MEM1_~CE" O R 6950 3000 60 
-F13 "MEM1_~OE" O R 6950 3100 60 
-F14 "MEM2_~WE" O R 6950 3200 60 
-F15 "MEM2_~CE" O R 6950 3300 60 
-F16 "MEM2_~OE" O R 6950 3400 60 
-F17 "BDATASRC_[0..7]" O R 6950 3550 60 
-F18 "SRC_SWITCH_SIGNAL" O R 6950 3700 60 
-F19 "~CS~_READ_MODE" I L 4850 3050 60 
-F20 "~CS~_WRITE_MODE" I L 4850 3150 60 
-F21 "SRCSET_CLK" I L 4850 3300 60 
-F22 "MEMWRITE_CLK" I L 4850 3400 60 
+F2 "BWRITE1_[0..7]" I L 4850 2400 60 
+F3 "~RESET_CLK" I L 4850 2800 60 
+F4 "MEM2DATA_[0..7]" B R 6950 2400 60 
+F5 "MEM1DATA_[0..7]" B R 6950 2300 60 
+F6 "BREAD1_[0..7]" T L 4850 2300 60 
+F7 "BJMPSRC_[0..23]" I L 4850 2550 60 
+F8 "SRCADD_[0..23]" I L 4850 2650 60 
+F9 "MEM2ADD_[0..23]" O R 6950 2650 60 
+F10 "MEM1ADD_[0..23]" O R 6950 2550 60 
+F11 "MEM1_~WE" O R 6950 2800 60 
+F12 "MEM1_~CE" O R 6950 2900 60 
+F13 "MEM1_~OE" O R 6950 3000 60 
+F14 "MEM2_~WE" O R 6950 3100 60 
+F15 "MEM2_~CE" O R 6950 3200 60 
+F16 "MEM2_~OE" O R 6950 3300 60 
+F17 "BDATASRC_[0..7]" O R 6950 3450 60 
+F18 "SRC_SWITCH_SIGNAL" O R 6950 3600 60 
+F19 "~CS~_READ_MODE" I L 4850 2950 60 
+F20 "~CS~_WRITE_MODE" I L 4850 3050 60 
+F21 "SRCSET_CLK" I L 4850 3200 60 
+F22 "MEMWRITE_CLK" I L 4850 3300 60 
 $EndSheet
 Text Label 6500 1200 0    60   ~ 0
 CLK_MODULE_5
@@ -496,14 +496,14 @@ Wire Wire Line
 	6450 1900 6500 1900
 Text Label 1500 5300 0    60   ~ 0
 MAIN_RESET
-Text Label 7000 3700 0    60   ~ 0
+Text Label 7000 3600 0    60   ~ 0
 SRC_SWITCH_SIGNAL
 Text Label 2850 5050 2    60   ~ 0
 MAIN_RESET
 Text Label 2850 5150 2    60   ~ 0
 SOURCE_RESET
 Wire Wire Line
-	4800 2900 4850 2900
+	4800 2800 4850 2800
 $Comp
 L power:+5V #PWR011
 U 1 1 5B9F5086
@@ -657,49 +657,49 @@ F 3 "" H 3100 6400 50  0001 C CNN
 	1    3100 6400
 	1    0    0    -1  
 $EndComp
-Text Label 4800 3300 2    60   ~ 0
+Text Label 4800 3200 2    60   ~ 0
 CLK_MODULE_5
 Wire Wire Line
-	4800 3300 4850 3300
+	4800 3200 4850 3200
 Wire Bus Line
-	4850 2500 4800 2500
-Text Label 4800 2500 2    60   ~ 0
+	4850 2400 4800 2400
+Text Label 4800 2400 2    60   ~ 0
 BWRITE1_[0..7]
-Text Label 7000 3550 0    60   ~ 0
+Text Label 7000 3450 0    60   ~ 0
 BDATASRC_[0..7]
 Wire Bus Line
-	7000 3550 6950 3550
+	7000 3450 6950 3450
 Wire Wire Line
-	7000 3700 6950 3700
+	7000 3600 6950 3600
 $Comp
 L power:+5V #PWR018
 U 1 1 5BB2F48B
-P 4550 6000
-F 0 "#PWR018" H 4550 5850 50  0001 C CNN
-F 1 "+5V" H 4550 6140 50  0000 C CNN
-F 2 "" H 4550 6000 50  0001 C CNN
-F 3 "" H 4550 6000 50  0001 C CNN
-	1    4550 6000
+P 3950 5700
+F 0 "#PWR018" H 3950 5550 50  0001 C CNN
+F 1 "+5V" H 3950 5840 50  0000 C CNN
+F 2 "" H 3950 5700 50  0001 C CNN
+F 3 "" H 3950 5700 50  0001 C CNN
+	1    3950 5700
 	1    0    0    -1  
 $EndComp
 $Comp
 L power:GND #PWR019
 U 1 1 5BB2F491
-P 4550 6400
-F 0 "#PWR019" H 4550 6150 50  0001 C CNN
-F 1 "GND" H 4550 6250 50  0000 C CNN
-F 2 "" H 4550 6400 50  0001 C CNN
-F 3 "" H 4550 6400 50  0001 C CNN
-	1    4550 6400
+P 3950 6100
+F 0 "#PWR019" H 3950 5850 50  0001 C CNN
+F 1 "GND" H 3950 5950 50  0000 C CNN
+F 2 "" H 3950 6100 50  0001 C CNN
+F 3 "" H 3950 6100 50  0001 C CNN
+	1    3950 6100
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	4550 6400 4550 6300
+	3950 6100 3950 6000
 Wire Wire Line
-	4550 6100 4550 6000
-Text Label 4250 6200 2    60   ~ 0
+	3950 5800 3950 5700
+Text Label 3650 5900 2    60   ~ 0
 RESET_CLK
-Text Label 4800 6200 0    60   ~ 0
+Text Label 4200 5900 0    60   ~ 0
 ~RESET_CLK
 Text Label 2850 2750 0    60   ~ 0
 GLOBAL_CLK
@@ -710,15 +710,15 @@ GLOBAL_CLK
 Wire Wire Line
 	8050 1150 8100 1150
 Wire Wire Line
-	6950 2900 7000 2900
+	6950 2800 7000 2800
 Wire Wire Line
-	7000 3000 6950 3000
-Text Label 7000 3000 0    60   ~ 0
-MEM1_~CE
+	7000 2900 6950 2900
 Text Label 7000 2900 0    60   ~ 0
+MEM1_~CE
+Text Label 7000 2800 0    60   ~ 0
 MEM1_~WE
 Wire Bus Line
-	4800 4150 4850 4150
+	4800 4050 4850 4050
 Wire Wire Line
 	1400 2750 1350 2750
 Wire Wire Line
@@ -851,11 +851,11 @@ Text Label 8950 2500 2    60   ~ 0
 NUMBER_[0..7]
 Wire Bus Line
 	9000 2500 8950 2500
-Text Label 4250 7050 2    60   ~ 0
+Text Label 5300 5900 2    60   ~ 0
 MAIN_RESET
-Text Label 4800 7050 0    60   ~ 0
+Text Label 5850 5900 0    60   ~ 0
 ~MAIN_RESET
-Text Label 4800 2900 2    60   ~ 0
+Text Label 4800 2800 2    60   ~ 0
 ~MAIN_RESET
 NoConn ~ 6500 1900
 NoConn ~ 6500 1500
@@ -901,49 +901,49 @@ Wire Wire Line
 $Comp
 L 74xGxx:74AHC1G04 U5
 U 1 1 5D0027AA
-P 4550 6200
-F 0 "U5" H 4700 6450 50  0000 C CNN
-F 1 "74AHC1G04" H 4850 6350 50  0000 C CNN
-F 2 "Package_TO_SOT_SMD:SOT-23-5" H 4550 6200 50  0001 C CNN
-F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 4550 6200 50  0001 C CNN
-	1    4550 6200
+P 3950 5900
+F 0 "U5" H 4100 6150 50  0000 C CNN
+F 1 "74AHC1G04" H 4250 6050 50  0000 C CNN
+F 2 "Package_TO_SOT_SMD:SOT-23-5" H 3950 5900 50  0001 C CNN
+F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 3950 5900 50  0001 C CNN
+	1    3950 5900
 	1    0    0    -1  
 $EndComp
 $Comp
 L power:+5V #PWR0107
 U 1 1 5D028BEC
-P 4550 6850
-F 0 "#PWR0107" H 4550 6700 50  0001 C CNN
-F 1 "+5V" H 4550 6990 50  0000 C CNN
-F 2 "" H 4550 6850 50  0001 C CNN
-F 3 "" H 4550 6850 50  0001 C CNN
-	1    4550 6850
+P 5600 5700
+F 0 "#PWR0107" H 5600 5550 50  0001 C CNN
+F 1 "+5V" H 5600 5840 50  0000 C CNN
+F 2 "" H 5600 5700 50  0001 C CNN
+F 3 "" H 5600 5700 50  0001 C CNN
+	1    5600 5700
 	1    0    0    -1  
 $EndComp
 $Comp
 L power:GND #PWR0108
 U 1 1 5D028BF2
-P 4550 7250
-F 0 "#PWR0108" H 4550 7000 50  0001 C CNN
-F 1 "GND" H 4550 7100 50  0000 C CNN
-F 2 "" H 4550 7250 50  0001 C CNN
-F 3 "" H 4550 7250 50  0001 C CNN
-	1    4550 7250
+P 5600 6100
+F 0 "#PWR0108" H 5600 5850 50  0001 C CNN
+F 1 "GND" H 5600 5950 50  0000 C CNN
+F 2 "" H 5600 6100 50  0001 C CNN
+F 3 "" H 5600 6100 50  0001 C CNN
+	1    5600 6100
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	4550 7250 4550 7150
+	5600 6100 5600 6000
 Wire Wire Line
-	4550 6950 4550 6850
+	5600 5800 5600 5700
 $Comp
 L 74xGxx:74AHC1G04 U11
 U 1 1 5D028BFA
-P 4550 7050
-F 0 "U11" H 4700 7300 50  0000 C CNN
-F 1 "74AHC1G04" H 4850 7200 50  0000 C CNN
-F 2 "Package_TO_SOT_SMD:SOT-23-5" H 4550 7050 50  0001 C CNN
-F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 4550 7050 50  0001 C CNN
-	1    4550 7050
+P 5600 5900
+F 0 "U11" H 5750 6150 50  0000 C CNN
+F 1 "74AHC1G04" H 5900 6050 50  0000 C CNN
+F 2 "Package_TO_SOT_SMD:SOT-23-5" H 5600 5900 50  0001 C CNN
+F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 5600 5900 50  0001 C CNN
+	1    5600 5900
 	1    0    0    -1  
 $EndComp
 $Comp
@@ -995,109 +995,109 @@ SPI_MISO
 Wire Wire Line
 	1350 2000 1400 2000
 Wire Wire Line
-	6950 3100 7000 3100
+	6950 3000 7000 3000
 Wire Wire Line
-	7000 3200 6950 3200
-Text Label 7000 3200 0    60   ~ 0
-MEM2_~WE
+	7000 3100 6950 3100
 Text Label 7000 3100 0    60   ~ 0
+MEM2_~WE
+Text Label 7000 3000 0    60   ~ 0
 MEM1_~OE
 Wire Wire Line
-	6950 3300 7000 3300
+	6950 3200 7000 3200
 Wire Wire Line
-	7000 3400 6950 3400
-Text Label 7000 3400 0    60   ~ 0
-MEM2_~OE
+	7000 3300 6950 3300
 Text Label 7000 3300 0    60   ~ 0
+MEM2_~OE
+Text Label 7000 3200 0    60   ~ 0
 MEM2_~CE
-Text Label 4800 2400 2    60   ~ 0
+Text Label 4800 2300 2    60   ~ 0
 BREAD1_[0..7]
 Wire Bus Line
-	4850 2400 4800 2400
-Text Label 4800 2650 2    60   ~ 0
+	4850 2300 4800 2300
+Text Label 4800 2550 2    60   ~ 0
 BJMPSRC_[0..23]
-Text Label 4800 2750 2    60   ~ 0
+Text Label 4800 2650 2    60   ~ 0
 SRCADD_[0..23]
 Wire Bus Line
-	4800 2650 4850 2650
+	4800 2550 4850 2550
 Wire Bus Line
-	4800 2750 4850 2750
-Text Label 7000 2650 0    60   ~ 0
+	4800 2650 4850 2650
+Text Label 7000 2550 0    60   ~ 0
 MEM1ADD_[0..23]
-Text Label 7000 2750 0    60   ~ 0
+Text Label 7000 2650 0    60   ~ 0
 MEM2ADD_[0..23]
 Wire Bus Line
-	6950 2650 7000 2650
+	6950 2550 7000 2550
 Wire Bus Line
-	6950 2750 7000 2750
-Text Label 7000 2400 0    60   ~ 0
+	6950 2650 7000 2650
+Text Label 7000 2300 0    60   ~ 0
 MEM1DATA_[0..7]
-Text Label 7000 2500 0    60   ~ 0
+Text Label 7000 2400 0    60   ~ 0
 MEM2DATA_[0..7]
 Wire Bus Line
-	6950 2400 7000 2400
+	6950 2300 7000 2300
 Wire Bus Line
-	6950 2500 7000 2500
-Text Label 4800 3050 2    60   ~ 0
+	6950 2400 7000 2400
+Text Label 4800 2950 2    60   ~ 0
 ~CS_MODULE_5
-Text Label 4800 3150 2    60   ~ 0
+Text Label 4800 3050 2    60   ~ 0
 ~CS_MODULE_6
-Text Label 4800 3400 2    60   ~ 0
+Text Label 4800 3300 2    60   ~ 0
 CLK_MODULE_6
 Wire Wire Line
-	4800 3400 4850 3400
+	4800 3300 4850 3300
+Wire Wire Line
+	4800 2950 4850 2950
 Wire Wire Line
 	4800 3050 4850 3050
-Wire Wire Line
-	4800 3150 4850 3150
-Text Label 7000 4150 0    60   ~ 0
+Text Label 7000 4050 0    60   ~ 0
 MEM1DATA_[0..7]
-Text Label 4800 4400 2    60   ~ 0
+Text Label 4800 4300 2    60   ~ 0
 MEM1_~CE
-Text Label 4800 4500 2    60   ~ 0
+Text Label 4800 4400 2    60   ~ 0
 MEM1_~WE
-Text Label 4800 4300 2    60   ~ 0
+Text Label 4800 4200 2    60   ~ 0
 MEM1_~OE
+Wire Wire Line
+	4800 4200 4850 4200
 Wire Wire Line
 	4800 4300 4850 4300
 Wire Wire Line
 	4800 4400 4850 4400
-Wire Wire Line
-	4800 4500 4850 4500
-Text Label 4800 4150 2    60   ~ 0
+Text Label 4800 4050 2    60   ~ 0
 MEM1ADD_[0..23]
 Wire Bus Line
-	6950 4150 7000 4150
+	6950 4050 7000 4050
 $Sheet
-S 4850 4850 2100 550 
+S 4850 4750 2100 550 
 U 5E0692F0
 F0 "MemorySlot2" 60
 F1 "MemorySlot2.sch" 60
-F2 "MEM_ADD_[0..23]" I L 4850 4950 60 
-F3 "MEM_~OE" I L 4850 5100 60 
-F4 "MEM_~CE" I L 4850 5200 60 
-F5 "MEM_~WE" I L 4850 5300 60 
-F6 "MEMDATA_[0..7]" B R 6950 4950 60 
+F2 "MEM_ADD_[0..23]" I L 4850 4850 60 
+F3 "MEM_~OE" I L 4850 5000 60 
+F4 "MEM_~CE" I L 4850 5100 60 
+F5 "MEM_~WE" I L 4850 5200 60 
+F6 "MEMDATA_[0..7]" B R 6950 4850 60 
 $EndSheet
 Wire Bus Line
-	4800 4950 4850 4950
+	4800 4850 4850 4850
+Wire Wire Line
+	4800 5000 4850 5000
 Wire Wire Line
 	4800 5100 4850 5100
 Wire Wire Line
 	4800 5200 4850 5200
-Wire Wire Line
-	4800 5300 4850 5300
 Wire Bus Line
-	6950 4950 7000 4950
-Text Label 4800 4950 2    60   ~ 0
+	6950 4850 7000 4850
+Text Label 4800 4850 2    60   ~ 0
 MEM2ADD_[0..23]
-Text Label 4800 5300 2    60   ~ 0
+Text Label 4800 5200 2    60   ~ 0
 MEM2_~WE
-Text Label 4800 5100 2    60   ~ 0
+Text Label 4800 5000 2    60   ~ 0
 MEM2_~OE
-Text Label 4800 5200 2    60   ~ 0
+Text Label 4800 5100 2    60   ~ 0
 MEM2_~CE
-Text Label 7000 4950 0    60   ~ 0
+Text Label 7000 4850 0    60   ~ 0
 MEM2DATA_[0..7]
 Text Notes 1650 6050 0    60   ~ 0
 LTC6994IS6-1
@@ -1445,108 +1445,110 @@ Wire Wire Line
 Connection ~ 9550 4100
 Wire Wire Line
 	9550 4100 9600 4100
-Text Label 7900 5650 2    60   ~ 0
+Text Label 8100 5650 2    60   ~ 0
 SPI_MISO
-Text Label 7900 5950 2    60   ~ 0
+Text Label 8100 5950 2    60   ~ 0
 SPI_CS
-Text Label 7900 5850 2    60   ~ 0
+Text Label 8100 5850 2    60   ~ 0
 SPI_SCLK
-Text Label 7900 5750 2    60   ~ 0
+Text Label 8100 5750 2    60   ~ 0
 SPI_MOSI
 $Comp
 L power:GND #PWR0103
 U 1 1 5D554816
-P 7800 6150
-F 0 "#PWR0103" H 7800 5900 50  0001 C CNN
-F 1 "GND" H 7800 6000 50  0000 C CNN
-F 2 "" H 7800 6150 50  0001 C CNN
-F 3 "" H 7800 6150 50  0001 C CNN
-	1    7800 6150
+P 8000 6150
+F 0 "#PWR0103" H 8000 5900 50  0001 C CNN
+F 1 "GND" H 8000 6000 50  0000 C CNN
+F 2 "" H 8000 6150 50  0001 C CNN
+F 3 "" H 8000 6150 50  0001 C CNN
+	1    8000 6150
 	1    0    0    -1  
 $EndComp
 $Comp
 L power:+5V #PWR0104
 U 1 1 5D554F66
-P 7800 5450
-F 0 "#PWR0104" H 7800 5300 50  0001 C CNN
-F 1 "+5V" H 7800 5590 50  0000 C CNN
-F 2 "" H 7800 5450 50  0001 C CNN
-F 3 "" H 7800 5450 50  0001 C CNN
-	1    7800 5450
+P 8000 5450
+F 0 "#PWR0104" H 8000 5300 50  0001 C CNN
+F 1 "+5V" H 8000 5590 50  0000 C CNN
+F 2 "" H 8000 5450 50  0001 C CNN
+F 3 "" H 8000 5450 50  0001 C CNN
+	1    8000 5450
 	1    0    0    -1  
 $EndComp
 $Comp
 L Connector_Generic:Conn_01x06 J7
 U 1 1 5D56C164
-P 8100 5850
-F 0 "J7" H 8000 5350 50  0000 C CNN
-F 1 " 3-641124-6" H 8150 5450 50  0000 C CNN
-F 2 "Connector_PinSocket_2.54mm:PinSocket_1x06_P2.54mm_Vertical" H 8100 5850 50  0001 C CNN
-F 3 "~" H 8100 5850 50  0001 C CNN
-	1    8100 5850
+P 8300 5850
+F 0 "J7" H 8200 5350 50  0000 C CNN
+F 1 " 3-641124-6" H 8350 5450 50  0000 C CNN
+F 2 "Connector_PinSocket_2.54mm:PinSocket_1x06_P2.54mm_Vertical" H 8300 5850 50  0001 C CNN
+F 3 "~" H 8300 5850 50  0001 C CNN
+	1    8300 5850
 	1    0    0    1   
 $EndComp
 Wire Wire Line
-	7800 6150 7800 6050
+	8000 6150 8000 6050
 Wire Wire Line
-	7800 6050 7900 6050
+	8000 6050 8100 6050
 Wire Wire Line
-	7900 5550 7800 5550
+	8100 5550 8000 5550
 Wire Wire Line
-	7800 5550 7800 5450
+	8000 5550 8000 5450
 $Comp
 L Device:C C14
 U 1 1 5D589005
-P 7350 5800
-F 0 "C14" H 7375 5900 50  0000 L CNN
-F 1 "10nF" H 7375 5700 50  0000 L CNN
-F 2 "Capacitor_SMD:C_0805_2012Metric" H 7388 5650 50  0001 C CNN
-F 3 "" H 7350 5800 50  0001 C CNN
-	1    7350 5800
+P 7550 5800
+F 0 "C14" H 7575 5900 50  0000 L CNN
+F 1 "10nF" H 7575 5700 50  0000 L CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 7588 5650 50  0001 C CNN
+F 3 "" H 7550 5800 50  0001 C CNN
+	1    7550 5800
 	-1   0    0    1   
 $EndComp
 Wire Wire Line
-	7350 5650 7350 5550
+	7550 5650 7550 5550
 Wire Wire Line
-	7350 5550 7800 5550
-Connection ~ 7800 5550
+	7550 5550 8000 5550
+Connection ~ 8000 5550
 Wire Wire Line
-	7800 6050 7350 6050
+	8000 6050 7550 6050
 Wire Wire Line
-	7350 6050 7350 5950
-Connection ~ 7800 6050
-Text Label 6250 6100 2    60   ~ 0
+	7550 6050 7550 5950
+Connection ~ 8000 6050
+Text Label 6850 5600 2    60   ~ 0
 SPI_MISO
 $Comp
 L power:GND #PWR0137
 U 1 1 5D32F7C5
-P 6350 6600
-F 0 "#PWR0137" H 6350 6350 50  0001 C CNN
-F 1 "GND" H 6350 6450 50  0000 C CNN
-F 2 "" H 6350 6600 50  0001 C CNN
-F 3 "" H 6350 6600 50  0001 C CNN
-	1    6350 6600
+P 6950 6100
+F 0 "#PWR0137" H 6950 5850 50  0001 C CNN
+F 1 "GND" H 6950 5950 50  0000 C CNN
+F 2 "" H 6950 6100 50  0001 C CNN
+F 3 "" H 6950 6100 50  0001 C CNN
+	1    6950 6100
 	1    0    0    -1  
 $EndComp
 $Comp
 L Device:R R5
 U 1 1 5D33001E
-P 6350 6350
-F 0 "R5" H 6420 6396 50  0000 L CNN
-F 1 "10k" H 6420 6305 50  0000 L CNN
-F 2 "Resistor_SMD:R_0805_2012Metric" V 6280 6350 50  0001 C CNN
-F 3 "~" H 6350 6350 50  0001 C CNN
-	1    6350 6350
+P 6950 5850
+F 0 "R5" H 7020 5896 50  0000 L CNN
+F 1 "10k" H 7020 5805 50  0000 L CNN
+F 2 "Resistor_SMD:R_0805_2012Metric" V 6880 5850 50  0001 C CNN
+F 3 "~" H 6950 5850 50  0001 C CNN
+	1    6950 5850
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
-	6250 6100 6350 6100
+	6850 5600 6950 5600
 Wire Wire Line
-	6350 6100 6350 6200
+	6950 5600 6950 5700
 Wire Wire Line
-	6350 6500 6350 6600
+	6950 6000 6950 6100
 Text Label 1950 6650 2    60   ~ 0
 SRC_SWITCH_SIGNAL
+Text Notes 3300 7750 0    60   ~ 0
+This documentation describes Open Hardware and is licensed under the\nCERN OHL v. 1.2.\n\nYou may redistribute and modify this documentation under the terms of the\nCERN OHL v.1.2. (http://ohwr.org/cernohl). This documentation is distributed\nWITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF\nMERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A\nPARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable\nconditions
 Wire Bus Line
 	9000 1750 9000 2500
 Wire Bus Line