From ccbab1e4072cd64b41e7e28de57c891cbbb5febb Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Mon, 7 Sep 2020 11:36:54 +0200 Subject: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX Popular tools, like intel-undervolt, use MSR 0x150 to control the CPU voltage offset. In fact, evidently the intel_turbo_max_3 driver in-tree also uses this MSR. So, teach the kernel's MSR list about this, so that intel-undervolt and other such tools don't spew warnings to dmesg, while unifying the constant used throughout the kernel. Fixes: a7e1f67ed29f ("x86/msr: Filter MSR writes") Cc: Borislav Petkov Signed-off-by: Jason A. Donenfeld --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 356b37b311d277..f21950f371ebee 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -175,6 +175,8 @@ #define MSR_IA32_OC_MAILBOX 0x00000150 +#define MSR_IA32_OC_MAILBOX 0x00000150 + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176