From f070ae182aebbe028fea13faaade17dfbcd729ca Mon Sep 17 00:00:00 2001 From: FanXinhao <1023405741@qq.com> Date: Fri, 15 May 2020 13:53:18 +0800 Subject: [PATCH] add NB476 support. --- targets/STM32L476RG_NB476/.config | 44 + targets/STM32L476RG_NB476/Demos/Kconfig | 13 + .../Demos/use_coap_demo/defaults.sdkconfig | 44 + .../use_coap_demo/defaults.sdkconfig.back | 47 + .../Demos/use_coap_demo/use_coap_demo.c | 149 + targets/STM32L476RG_NB476/Demos/user_demo.mk | 19 + targets/STM32L476RG_NB476/GCC/LOG | 135 + targets/STM32L476RG_NB476/GCC/Makefile | 170 + targets/STM32L476RG_NB476/GCC/Makefile_Sota | 187 + targets/STM32L476RG_NB476/GCC/os.ld | 217 + targets/STM32L476RG_NB476/GCC/os_app.ld | 203 + targets/STM32L476RG_NB476/GCC/os_loader.ld | 198 + targets/STM32L476RG_NB476/GCC/project.mk | 76 + .../STM32L476RG_NB476/Hardware/DHT11/dht11.c | 183 + .../STM32L476RG_NB476/Hardware/DHT11/dht11.h | 29 + .../STM32L476RG_NB476/Hardware/Inc/hal_iwdg.h | 87 + .../Hardware/Inc/hal_qspi_flash.h | 190 + .../STM32L476RG_NB476/Hardware/Inc/hal_rng.h | 102 + targets/STM32L476RG_NB476/Hardware/OLED/bmp.h | 80 + .../STM32L476RG_NB476/Hardware/OLED/oled.c | 240 + .../STM32L476RG_NB476/Hardware/OLED/oled.h | 39 + .../Hardware/OLED/oledfont.h | 253 + .../STM32L476RG_NB476/Hardware/Src/hal_iwdg.c | 61 + .../Hardware/Src/hal_qspi_flash.c | 426 + .../STM32L476RG_NB476/Hardware/Src/hal_rng.c | 89 + targets/STM32L476RG_NB476/Inc/at_hal.h | 49 + targets/STM32L476RG_NB476/Inc/board.h | 81 + targets/STM32L476RG_NB476/Inc/common.h | 54 + targets/STM32L476RG_NB476/Inc/dwt.h | 54 + targets/STM32L476RG_NB476/Inc/gpio.h | 57 + targets/STM32L476RG_NB476/Inc/i2c.h | 58 + targets/STM32L476RG_NB476/Inc/main.h | 101 + targets/STM32L476RG_NB476/Inc/rtc.h | 58 + targets/STM32L476RG_NB476/Inc/stm32l476xx.h | 18481 ++++++++++++++++ targets/STM32L476RG_NB476/Inc/stm32l4xx.h | 248 + .../Inc/stm32l4xx_hal_conf.h | 440 + targets/STM32L476RG_NB476/Inc/stm32l4xx_it.h | 68 + targets/STM32L476RG_NB476/Inc/sys.h | 56 + targets/STM32L476RG_NB476/Inc/sys_init.h | 83 + .../STM32L476RG_NB476/Inc/system_stm32l4xx.h | 107 + targets/STM32L476RG_NB476/Inc/usart.h | 62 + targets/STM32L476RG_NB476/Kconfig | 58 + targets/STM32L476RG_NB476/Lib/hwpatch.lib | Bin 0 -> 118352 bytes targets/STM32L476RG_NB476/Lib/hwpatch_iar.a | Bin 0 -> 84644 bytes targets/STM32L476RG_NB476/Lib/libhwpatch.a | Bin 0 -> 100860 bytes .../OS_CONFIG/iot_link_config.h | 45 + .../OS_CONFIG/los_builddef.h | 239 + .../STM32L476RG_NB476/OS_CONFIG/los_printf.h | 115 + .../OS_CONFIG/target_config.h | 399 + targets/STM32L476RG_NB476/Src/LWM2M_Task.c | 93 + targets/STM32L476RG_NB476/Src/dwt.c | 72 + targets/STM32L476RG_NB476/Src/flash_adaptor.c | 122 + targets/STM32L476RG_NB476/Src/gpio.c | 91 + targets/STM32L476RG_NB476/Src/i2c.c | 118 + targets/STM32L476RG_NB476/Src/main.c | 143 + targets/STM32L476RG_NB476/Src/main.c.back.c | 429 + targets/STM32L476RG_NB476/Src/ota_port.c | 107 + targets/STM32L476RG_NB476/Src/rtc.c | 86 + .../STM32L476RG_NB476/Src/stm32l4xx_hal_msp.c | 84 + targets/STM32L476RG_NB476/Src/stm32l4xx_it.c | 190 + targets/STM32L476RG_NB476/Src/sys.c | 37 + targets/STM32L476RG_NB476/Src/sys_init.c | 160 + .../STM32L476RG_NB476/Src/system_stm32l4xx.c | 337 + targets/STM32L476RG_NB476/Src/uart_debug.c | 150 + targets/STM32L476RG_NB476/Src/usart.c | 237 + targets/STM32L476RG_NB476/iot_config.h | 26 + targets/STM32L476RG_NB476/uart_at/uart_at.c | 270 + 67 files changed, 26946 insertions(+) create mode 100644 targets/STM32L476RG_NB476/.config create mode 100644 targets/STM32L476RG_NB476/Demos/Kconfig create mode 100644 targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig create mode 100644 targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig.back create mode 100644 targets/STM32L476RG_NB476/Demos/use_coap_demo/use_coap_demo.c create mode 100644 targets/STM32L476RG_NB476/Demos/user_demo.mk create mode 100644 targets/STM32L476RG_NB476/GCC/LOG create mode 100644 targets/STM32L476RG_NB476/GCC/Makefile create mode 100644 targets/STM32L476RG_NB476/GCC/Makefile_Sota create mode 100644 targets/STM32L476RG_NB476/GCC/os.ld create mode 100644 targets/STM32L476RG_NB476/GCC/os_app.ld create mode 100644 targets/STM32L476RG_NB476/GCC/os_loader.ld create mode 100644 targets/STM32L476RG_NB476/GCC/project.mk create mode 100644 targets/STM32L476RG_NB476/Hardware/DHT11/dht11.c create mode 100644 targets/STM32L476RG_NB476/Hardware/DHT11/dht11.h create mode 100644 targets/STM32L476RG_NB476/Hardware/Inc/hal_iwdg.h create mode 100644 targets/STM32L476RG_NB476/Hardware/Inc/hal_qspi_flash.h create mode 100644 targets/STM32L476RG_NB476/Hardware/Inc/hal_rng.h create mode 100644 targets/STM32L476RG_NB476/Hardware/OLED/bmp.h create mode 100644 targets/STM32L476RG_NB476/Hardware/OLED/oled.c create mode 100644 targets/STM32L476RG_NB476/Hardware/OLED/oled.h create mode 100644 targets/STM32L476RG_NB476/Hardware/OLED/oledfont.h create mode 100644 targets/STM32L476RG_NB476/Hardware/Src/hal_iwdg.c create mode 100644 targets/STM32L476RG_NB476/Hardware/Src/hal_qspi_flash.c create mode 100644 targets/STM32L476RG_NB476/Hardware/Src/hal_rng.c create mode 100644 targets/STM32L476RG_NB476/Inc/at_hal.h create mode 100644 targets/STM32L476RG_NB476/Inc/board.h create mode 100644 targets/STM32L476RG_NB476/Inc/common.h create mode 100644 targets/STM32L476RG_NB476/Inc/dwt.h create mode 100644 targets/STM32L476RG_NB476/Inc/gpio.h create mode 100644 targets/STM32L476RG_NB476/Inc/i2c.h create mode 100644 targets/STM32L476RG_NB476/Inc/main.h create mode 100644 targets/STM32L476RG_NB476/Inc/rtc.h create mode 100644 targets/STM32L476RG_NB476/Inc/stm32l476xx.h create mode 100644 targets/STM32L476RG_NB476/Inc/stm32l4xx.h create mode 100644 targets/STM32L476RG_NB476/Inc/stm32l4xx_hal_conf.h create mode 100644 targets/STM32L476RG_NB476/Inc/stm32l4xx_it.h create mode 100644 targets/STM32L476RG_NB476/Inc/sys.h create mode 100644 targets/STM32L476RG_NB476/Inc/sys_init.h create mode 100644 targets/STM32L476RG_NB476/Inc/system_stm32l4xx.h create mode 100644 targets/STM32L476RG_NB476/Inc/usart.h create mode 100644 targets/STM32L476RG_NB476/Kconfig create mode 100644 targets/STM32L476RG_NB476/Lib/hwpatch.lib create mode 100644 targets/STM32L476RG_NB476/Lib/hwpatch_iar.a create mode 100644 targets/STM32L476RG_NB476/Lib/libhwpatch.a create mode 100644 targets/STM32L476RG_NB476/OS_CONFIG/iot_link_config.h create mode 100644 targets/STM32L476RG_NB476/OS_CONFIG/los_builddef.h create mode 100644 targets/STM32L476RG_NB476/OS_CONFIG/los_printf.h create mode 100644 targets/STM32L476RG_NB476/OS_CONFIG/target_config.h create mode 100644 targets/STM32L476RG_NB476/Src/LWM2M_Task.c create mode 100644 targets/STM32L476RG_NB476/Src/dwt.c create mode 100644 targets/STM32L476RG_NB476/Src/flash_adaptor.c create mode 100644 targets/STM32L476RG_NB476/Src/gpio.c create mode 100644 targets/STM32L476RG_NB476/Src/i2c.c create mode 100644 targets/STM32L476RG_NB476/Src/main.c create mode 100644 targets/STM32L476RG_NB476/Src/main.c.back.c create mode 100644 targets/STM32L476RG_NB476/Src/ota_port.c create mode 100644 targets/STM32L476RG_NB476/Src/rtc.c create mode 100644 targets/STM32L476RG_NB476/Src/stm32l4xx_hal_msp.c create mode 100644 targets/STM32L476RG_NB476/Src/stm32l4xx_it.c create mode 100644 targets/STM32L476RG_NB476/Src/sys.c create mode 100644 targets/STM32L476RG_NB476/Src/sys_init.c create mode 100644 targets/STM32L476RG_NB476/Src/system_stm32l4xx.c create mode 100644 targets/STM32L476RG_NB476/Src/uart_debug.c create mode 100644 targets/STM32L476RG_NB476/Src/usart.c create mode 100644 targets/STM32L476RG_NB476/iot_config.h create mode 100644 targets/STM32L476RG_NB476/uart_at/uart_at.c diff --git a/targets/STM32L476RG_NB476/.config b/targets/STM32L476RG_NB476/.config new file mode 100644 index 000000000..27e928fde --- /dev/null +++ b/targets/STM32L476RG_NB476/.config @@ -0,0 +1,44 @@ +#Generated by IoT Link Studio +CONFIG_ARCH_CPU_TYPE="armv7-m" +CONFIG_UARTAT_RCVMAX=2048 +CONFIG_UARTAT_BAUDRATE=9600 +CONFIG_UARTAT_DEVNAME="atdev" +CONFIG_LITEOS_ENABLE=y +# CONFIG_NOVAOS_ENABLE is not set +# CONFIG_LINUXOS_ENABLE is not set +# CONFIG_MACOS_ENABLE is not set +# CONFIG_NEW_OS is not set +CONFIG_AT_ENABLE=y +CONFIG_AT_DEVNAME="atdev" +CONFIG_AT_OOBTABLEN=6 +CONFIG_AT_RECVMAXLEN=1024 +CONFIG_AT_TASKPRIOR=10 +# CONFIG_CJSON_ENABLE is not set +CONFIG_DRIVER_ENABLE=y +CONFIG_LINKLOG_ENABLE=y +CONFIG_LINKQUEUE_ENABLE=y +CONFIG_LINKDEMO_ENABLE=y +CONFIG_STIMER_ENABLE=y +CONFIG_STIMER_STACKSIZE=2048 +CONFIG_STIMER_TASKPRIOR=10 +# CONFIG_STIMER_DEMO_ENABLE is not set +# CONFIG_TCIP_AL_ENABLE is not set +# CONFIG_DTLS_AL_ENABLE is not set +# CONFIG_COAP_AL_ENABLE is not set +# CONFIG_LWM2M_AL_ENABLE is not set +# CONFIG_MQTT_AL_ENABLE is not set +CONFIG_OCSERVICES_ENABLE=y +CONFIG_OCCOAP_ENABLE=y +# CONFIG_OCCOAPTINY_ENABLE is not set +CONFIG_BOUDICA120_ENABLE=y +# CONFIG_OCCOAPNULL is not set +# CONFIG_OCCOAP_DEMO_ENABLE is not set +# CONFIG_OCLWM2M_ENABLE is not set +# CONFIG_OCMQTT_ENABLE is not set +CONFIG_SHELL_ENABLE=y +CONFIG_SHELL_TASK_STACKSIZE=2048 +CONFIG_SHELL_TASK_PRIOR=10 +CONFIG_IOT_LINK_CONFIGFILE="iot_config.h" +# CONFIG_Demo_None is not set +CONFIG_Demo_Use_Coap=y +CONFIG_USER_DEMO="use_coap_demo" diff --git a/targets/STM32L476RG_NB476/Demos/Kconfig b/targets/STM32L476RG_NB476/Demos/Kconfig new file mode 100644 index 000000000..31f46293a --- /dev/null +++ b/targets/STM32L476RG_NB476/Demos/Kconfig @@ -0,0 +1,13 @@ +choice Demo + optional + prompt "User Defined Demo" + config Demo_None + bool "none" + config Demo_Use_Coap + bool "Report temperature" +endchoice + +config USER_DEMO + string + default "use_coap_demo" if Demo_Use_Coap + default "none" \ No newline at end of file diff --git a/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig b/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig new file mode 100644 index 000000000..27e928fde --- /dev/null +++ b/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig @@ -0,0 +1,44 @@ +#Generated by IoT Link Studio +CONFIG_ARCH_CPU_TYPE="armv7-m" +CONFIG_UARTAT_RCVMAX=2048 +CONFIG_UARTAT_BAUDRATE=9600 +CONFIG_UARTAT_DEVNAME="atdev" +CONFIG_LITEOS_ENABLE=y +# CONFIG_NOVAOS_ENABLE is not set +# CONFIG_LINUXOS_ENABLE is not set +# CONFIG_MACOS_ENABLE is not set +# CONFIG_NEW_OS is not set +CONFIG_AT_ENABLE=y +CONFIG_AT_DEVNAME="atdev" +CONFIG_AT_OOBTABLEN=6 +CONFIG_AT_RECVMAXLEN=1024 +CONFIG_AT_TASKPRIOR=10 +# CONFIG_CJSON_ENABLE is not set +CONFIG_DRIVER_ENABLE=y +CONFIG_LINKLOG_ENABLE=y +CONFIG_LINKQUEUE_ENABLE=y +CONFIG_LINKDEMO_ENABLE=y +CONFIG_STIMER_ENABLE=y +CONFIG_STIMER_STACKSIZE=2048 +CONFIG_STIMER_TASKPRIOR=10 +# CONFIG_STIMER_DEMO_ENABLE is not set +# CONFIG_TCIP_AL_ENABLE is not set +# CONFIG_DTLS_AL_ENABLE is not set +# CONFIG_COAP_AL_ENABLE is not set +# CONFIG_LWM2M_AL_ENABLE is not set +# CONFIG_MQTT_AL_ENABLE is not set +CONFIG_OCSERVICES_ENABLE=y +CONFIG_OCCOAP_ENABLE=y +# CONFIG_OCCOAPTINY_ENABLE is not set +CONFIG_BOUDICA120_ENABLE=y +# CONFIG_OCCOAPNULL is not set +# CONFIG_OCCOAP_DEMO_ENABLE is not set +# CONFIG_OCLWM2M_ENABLE is not set +# CONFIG_OCMQTT_ENABLE is not set +CONFIG_SHELL_ENABLE=y +CONFIG_SHELL_TASK_STACKSIZE=2048 +CONFIG_SHELL_TASK_PRIOR=10 +CONFIG_IOT_LINK_CONFIGFILE="iot_config.h" +# CONFIG_Demo_None is not set +CONFIG_Demo_Use_Coap=y +CONFIG_USER_DEMO="use_coap_demo" diff --git a/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig.back b/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig.back new file mode 100644 index 000000000..32d0ef76d --- /dev/null +++ b/targets/STM32L476RG_NB476/Demos/use_coap_demo/defaults.sdkconfig.back @@ -0,0 +1,47 @@ +#Generated by Huawei IoT Studio +CONFIG_ARCH_CPU_TYPE="armv7-m" +CONFIG_UARTAT_RCVMAX=2048 +CONFIG_UARTAT_BAUDRATE=9600 +CONFIG_UARTAT_DEVNAME="atdev" +CONFIG_LITEOS_ENABLE=y +# CONFIG_NOVAOS_ENABLE is not set +# CONFIG_LINUXOS_ENABLE is not set +# CONFIG_MACOS_ENABLE is not set +# CONFIG_NEW_OS is not set +CONFIG_AT_ENABLE=y +CONFIG_AT_DEVNAME="atdev" +CONFIG_AT_OOBTABLEN=6 +CONFIG_AT_RECVMAXLEN=1024 +CONFIG_AT_TASKPRIOR=10 +# CONFIG_CJSON_ENABLE is not set +CONFIG_DRIVER_ENABLE=y +CONFIG_LINKLOG_ENABLE=y +CONFIG_LINKQUEUE_ENABLE=y +CONFIG_LINKDEMO_ENABLE=y +# CONFIG_STIMER_ENABLE=y +# CONFIG_STIMER_STACKSIZE=2048 +# CONFIG_STIMER_TASKPRIOR=10 +# CONFIG_STIMER_DEMO_ENABLE is not set +# CONFIG_TCIP_AL_ENABLE is not set +# CONFIG_DTLS_AL_ENABLE is not set +# CONFIG_COAP_AL_ENABLE is not set +# CONFIG_LWM2M_AL_ENABLE is not set +# CONFIG_MQTT_AL_ENABLE is not set +CONFIG_OCSERVICES_ENABLE=y +CONFIG_OCCOAP_ENABLE=y +#CONFIG_OCLWM2M_ENABLE is not set +# CONFIG_OCLWM2MTINY_ENABLE is not set +CONFIG_BOUDICA120_ENABLE=y +# CONFIG_OCLWM2MNULL is not set +# CONFIG_OCLWM2M_DEMO_ENABLE is not set +# CONFIG_OCMQTT_ENABLE is not set +# CONFIG_OC_MQTTV1_PROFILE is not set +# CONFIG_OC_MQTTV1_DEMO is not set +# CONFIG_OC_MQTTV1_DEMO_BS is not set +CONFIG_SHELL_ENABLE=y +CONFIG_SHELL_TASK_STACKSIZE=2048 +CONFIG_SHELL_TASK_PRIOR=10 +CONFIG_IOT_LINK_CONFIGFILE="iot_config.h" +# CONFIG_Demo_None is not set +CONFIG_Demo_Use_Coap=y +CONFIG_USER_DEMO="use_coap_demo" \ No newline at end of file diff --git a/targets/STM32L476RG_NB476/Demos/use_coap_demo/use_coap_demo.c b/targets/STM32L476RG_NB476/Demos/use_coap_demo/use_coap_demo.c new file mode 100644 index 000000000..d8c0514e3 --- /dev/null +++ b/targets/STM32L476RG_NB476/Demos/use_coap_demo/use_coap_demo.c @@ -0,0 +1,149 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ +/** + * DATE AUTHOR INSTRUCTION + * 2020-04-21 FanXinhao The first version + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dht11.h" +#include "oled.h" + +//DHT11 Data Struct +DHT11_Data_TypeDef dht11_data; +unsigned char DHT11_str[10] = {0}; + + +/* LWM2M server information */ +#define cn_endpoint_id "coap_001" +#define cn_app_server "119.3.250.80" +#define cn_app_port "5683" + +//if your command is very fast,please use a queue here--TODO +#define cn_app_rcv_buf_len 128 +static int8_t s_rcv_buffer[cn_app_rcv_buf_len]; +static int s_rcv_datalen; +static osal_semp_t s_rcv_sync; + +//use this function to push all the message to the buffer +static int app_msg_deal(void *msg, int len) +{ + int ret = -1; + + if(len <= cn_app_rcv_buf_len) + { + memcpy(s_rcv_buffer,msg,len); + s_rcv_datalen = len; + + osal_semp_post(s_rcv_sync); + + ret = 0; + + } + return ret; +} + +int coap_report_task(void *args) +{ + int* handle = NULL; + oc_config_param_t oc_param; + char Temp[10] = {00, 22}; + oc_coap_imp_init(); + + memset(&oc_param,0,sizeof(oc_param)); + + oc_param.app_server.address = cn_app_server; + oc_param.app_server.port = cn_app_port; + oc_param.app_server.ep_id = cn_endpoint_id; + oc_param.boot_mode = en_oc_boot_strap_mode_factory; + oc_param.rcv_func = app_msg_deal; + + handle = oc_coap_config(&oc_param); + if (NULL == handle) + { + printf("config_init fail!\r\n"); + } + else + { + printf("start send message to CDP server!\r\n"); + } + while(1) + { + memset(DHT11_str, 0, 6); + sprintf(Temp,"%02d",(int)dht11_data.temperature); + oc_coap_report(handle, Temp, 2); + osal_task_sleep(10*1000); + } +} + +int Read_DHT11_task(void *args) +{ + + while(1) + { + DHT11_Read_TempAndHumidity(&dht11_data);//read DHT11 + /* oled display */ + OLED_Clear(); + OLED_ShowString(9, 0, "DHT11 Data", 10); + memset(DHT11_str, 0, 6); + sprintf(DHT11_str,"temp %5.2f",dht11_data.temperature); + OLED_ShowString(9, 2, DHT11_str, 5); + memset(DHT11_str, 0, 6); + sprintf(DHT11_str,"humid %5.2f",dht11_data.humidity); + OLED_ShowString(9, 4, DHT11_str, 5); + + osal_task_sleep(5*1000); + + } +} + +int standard_app_demo_main() +{ + osal_task_create("coap_report",coap_report_task, NULL, 0x1000, NULL, 3); + osal_task_create("Read_DHT11",Read_DHT11_task, NULL, 0x500, NULL, 3); + return 0; +} + + + + + diff --git a/targets/STM32L476RG_NB476/Demos/user_demo.mk b/targets/STM32L476RG_NB476/Demos/user_demo.mk new file mode 100644 index 000000000..d7711136f --- /dev/null +++ b/targets/STM32L476RG_NB476/Demos/user_demo.mk @@ -0,0 +1,19 @@ +################################################################################ +# this is used for compile the user defined oc demo +################################################################################ + +#if you have defined multiple demos by yourself, modify this file to compile the chosen demo. + +#example for LiteOS func + + +#example for report temperature +ifeq ($(CONFIG_USER_DEMO), "use_coap_demo") + user_demo_src = ${wildcard $(TARGET_DIR)/Demos/use_coap_demo/*.c} + user_demo_defs = -D CONFIG_USE_COAP_ENABLE=1 +endif + + +C_SOURCES += $(user_demo_src) +C_INCLUDES += $(user_demo_inc) +C_DEFS += $(user_demo_defs) diff --git a/targets/STM32L476RG_NB476/GCC/LOG b/targets/STM32L476RG_NB476/GCC/LOG new file mode 100644 index 000000000..8a0e2ba28 --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/LOG @@ -0,0 +1,135 @@ +mkdir -p build/Demos/use_coap_demo/ +mkdir -p build/Hardware/DHT11/ +mkdir -p build/Hardware/OLED/ +mkdir -p build/Hardware/Src/ +mkdir -p build/Src/ +mkdir -p build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/ +mkdir -p build/iot_link/ +mkdir -p build/iot_link/at/ +mkdir -p build/iot_link/crc/ +mkdir -p build/iot_link/demos/ +mkdir -p build/iot_link/driver/ +mkdir -p build/iot_link/link_log/ +mkdir -p build/iot_link/link_misc/ +mkdir -p build/iot_link/oc/oc_coap/boudica120_oc/ +mkdir -p build/iot_link/oc/oc_coap/oc_coap_al/ +mkdir -p build/iot_link/os/liteos/ +mkdir -p build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/ +mkdir -p build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/ +mkdir -p build/iot_link/os/liteos/arch/arm/arm-m/src/ +mkdir -p build/iot_link/os/liteos/base/core/ +mkdir -p build/iot_link/os/liteos/base/ipc/ +mkdir -p build/iot_link/os/liteos/base/mem/common/ +mkdir -p build/iot_link/os/liteos/base/mem/heap/ +mkdir -p build/iot_link/os/liteos/base/mem/membox/ +mkdir -p build/iot_link/os/liteos/base/misc/ +mkdir -p build/iot_link/os/liteos/base/om/ +mkdir -p build/iot_link/os/liteos/cmsis/ +mkdir -p build/iot_link/os/liteos/extended/tickless/ +mkdir -p build/iot_link/os/liteos/utils/ +mkdir -p build/iot_link/os/osal/ +mkdir -p build/iot_link/queue/ +mkdir -p build/iot_link/shell/ +mkdir -p build/iot_link/stimer/ +mkdir -p build/iot_link/storage/ +mkdir -p build/uart_at/ +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/link_misc/link_ring_buffer.d" -MT"build/iot_link/link_misc/link_ring_buffer.d" -MT"build/iot_link/link_misc/link_ring_buffer.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/link_misc/link_ring_buffer.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc/link_ring_buffer.c -o build/iot_link/link_misc/link_ring_buffer.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/link_misc/link_random.d" -MT"build/iot_link/link_misc/link_random.d" -MT"build/iot_link/link_misc/link_random.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/link_misc/link_random.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc/link_random.c -o build/iot_link/link_misc/link_random.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/link_misc/link_string.d" -MT"build/iot_link/link_misc/link_string.d" -MT"build/iot_link/link_misc/link_string.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/link_misc/link_string.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc/link_string.c -o build/iot_link/link_misc/link_string.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/link_log/link_log.d" -MT"build/iot_link/link_log/link_log.d" -MT"build/iot_link/link_log/link_log.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/link_log/link_log.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log/link_log.c -o build/iot_link/link_log/link_log.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/osal/osal.d" -MT"build/iot_link/os/osal/osal.d" -MT"build/iot_link/os/osal/osal.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/osal/osal.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal/osal.c -o build/iot_link/os/osal/osal.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.c -o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.c -o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.c -o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.c -o build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.c -o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.c -o build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.c -o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/cmsis/cmsis_liteos.d" -MT"build/iot_link/os/liteos/cmsis/cmsis_liteos.d" -MT"build/iot_link/os/liteos/cmsis/cmsis_liteos.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/cmsis/cmsis_liteos.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis/cmsis_liteos.c -o build/iot_link/os/liteos/cmsis/cmsis_liteos.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/utils/rbtree.d" -MT"build/iot_link/os/liteos/utils/rbtree.d" -MT"build/iot_link/os/liteos/utils/rbtree.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/utils/rbtree.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/utils/rbtree.c -o build/iot_link/os/liteos/utils/rbtree.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/los_init.d" -MT"build/iot_link/os/liteos/los_init.d" -MT"build/iot_link/os/liteos/los_init.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/los_init.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/los_init.c -o build/iot_link/os/liteos/los_init.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/liteos_imp.d" -MT"build/iot_link/os/liteos/liteos_imp.d" -MT"build/iot_link/os/liteos/liteos_imp.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/liteos_imp.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/liteos_imp.c -o build/iot_link/os/liteos/liteos_imp.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/newlib_stub.d" -MT"build/iot_link/os/liteos/newlib_stub.d" -MT"build/iot_link/os/liteos/newlib_stub.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/newlib_stub.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/newlib_stub.c -o build/iot_link/os/liteos/newlib_stub.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/malloc.d" -MT"build/iot_link/os/liteos/malloc.d" -MT"build/iot_link/os/liteos/malloc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/malloc.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/malloc.c -o build/iot_link/os/liteos/malloc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/liteos_errno.d" -MT"build/iot_link/os/liteos/liteos_errno.d" -MT"build/iot_link/os/liteos/liteos_errno.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/liteos_errno.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/liteos_errno.c -o build/iot_link/os/liteos/liteos_errno.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I 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-MT"build/iot_link/os/liteos/base/core/los_swtmr.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_swtmr.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_swtmr.c -o build/iot_link/os/liteos/base/core/los_swtmr.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/core/los_priqueue.d" -MT"build/iot_link/os/liteos/base/core/los_priqueue.d" -MT"build/iot_link/os/liteos/base/core/los_priqueue.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_priqueue.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_priqueue.c -o build/iot_link/os/liteos/base/core/los_priqueue.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/core/los_task.d" -MT"build/iot_link/os/liteos/base/core/los_task.d" -MT"build/iot_link/os/liteos/base/core/los_task.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_task.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_task.c -o build/iot_link/os/liteos/base/core/los_task.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I 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-MT"build/iot_link/os/liteos/base/core/los_timeslice.d" -MT"build/iot_link/os/liteos/base/core/los_timeslice.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_timeslice.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_timeslice.c -o build/iot_link/os/liteos/base/core/los_timeslice.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/core/los_sys.d" -MT"build/iot_link/os/liteos/base/core/los_sys.d" -MT"build/iot_link/os/liteos/base/core/los_sys.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_sys.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_sys.c -o build/iot_link/os/liteos/base/core/los_sys.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/core/los_tick.d" -MT"build/iot_link/os/liteos/base/core/los_tick.d" -MT"build/iot_link/os/liteos/base/core/los_tick.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/core/los_tick.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/core/los_tick.c -o build/iot_link/os/liteos/base/core/los_tick.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/ipc/los_rwlock.d" -MT"build/iot_link/os/liteos/base/ipc/los_rwlock.d" -MT"build/iot_link/os/liteos/base/ipc/los_rwlock.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/ipc/los_rwlock.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/ipc/los_rwlock.c -o build/iot_link/os/liteos/base/ipc/los_rwlock.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/ipc/los_mux.d" -MT"build/iot_link/os/liteos/base/ipc/los_mux.d" -MT"build/iot_link/os/liteos/base/ipc/los_mux.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/ipc/los_mux.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/ipc/los_mux.c -o build/iot_link/os/liteos/base/ipc/los_mux.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/ipc/los_sem.d" -MT"build/iot_link/os/liteos/base/ipc/los_sem.d" -MT"build/iot_link/os/liteos/base/ipc/los_sem.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/ipc/los_sem.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/ipc/los_sem.c -o build/iot_link/os/liteos/base/ipc/los_sem.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/ipc/los_event.d" -MT"build/iot_link/os/liteos/base/ipc/los_event.d" -MT"build/iot_link/os/liteos/base/ipc/los_event.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/ipc/los_event.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/ipc/los_event.c -o build/iot_link/os/liteos/base/ipc/los_event.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/ipc/los_queue.d" -MT"build/iot_link/os/liteos/base/ipc/los_queue.d" -MT"build/iot_link/os/liteos/base/ipc/los_queue.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/ipc/los_queue.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/ipc/los_queue.c -o build/iot_link/os/liteos/base/ipc/los_queue.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/heap/los_heap.d" -MT"build/iot_link/os/liteos/base/mem/heap/los_heap.d" -MT"build/iot_link/os/liteos/base/mem/heap/los_heap.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/heap/los_heap.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/heap/los_heap.c -o build/iot_link/os/liteos/base/mem/heap/los_heap.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/heap/los_memory.d" -MT"build/iot_link/os/liteos/base/mem/heap/los_memory.d" -MT"build/iot_link/os/liteos/base/mem/heap/los_memory.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/heap/los_memory.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/heap/los_memory.c -o build/iot_link/os/liteos/base/mem/heap/los_memory.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/membox/los_membox.d" -MT"build/iot_link/os/liteos/base/mem/membox/los_membox.d" -MT"build/iot_link/os/liteos/base/mem/membox/los_membox.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/membox/los_membox.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/membox/los_membox.c -o build/iot_link/os/liteos/base/mem/membox/los_membox.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/common/los_slab.d" -MT"build/iot_link/os/liteos/base/mem/common/los_slab.d" -MT"build/iot_link/os/liteos/base/mem/common/los_slab.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/common/los_slab.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/common/los_slab.c -o build/iot_link/os/liteos/base/mem/common/los_slab.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/common/los_slabmem.d" -MT"build/iot_link/os/liteos/base/mem/common/los_slabmem.d" -MT"build/iot_link/os/liteos/base/mem/common/los_slabmem.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/common/los_slabmem.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/common/los_slabmem.c -o build/iot_link/os/liteos/base/mem/common/los_slabmem.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/mem/common/los_memcheck.d" -MT"build/iot_link/os/liteos/base/mem/common/los_memcheck.d" -MT"build/iot_link/os/liteos/base/mem/common/los_memcheck.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/mem/common/los_memcheck.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/mem/common/los_memcheck.c -o build/iot_link/os/liteos/base/mem/common/los_memcheck.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/misc/los_misc.d" -MT"build/iot_link/os/liteos/base/misc/los_misc.d" -MT"build/iot_link/os/liteos/base/misc/los_misc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/misc/los_misc.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/misc/los_misc.c -o build/iot_link/os/liteos/base/misc/los_misc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/base/om/los_err.d" -MT"build/iot_link/os/liteos/base/om/los_err.d" -MT"build/iot_link/os/liteos/base/om/los_err.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/base/om/los_err.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/om/los_err.c -o build/iot_link/os/liteos/base/om/los_err.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/extended/tickless/los_tickless.d" -MT"build/iot_link/os/liteos/extended/tickless/los_tickless.d" -MT"build/iot_link/os/liteos/extended/tickless/los_tickless.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/os/liteos/extended/tickless/los_tickless.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/tickless/los_tickless.c -o build/iot_link/os/liteos/extended/tickless/los_tickless.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/shell/shell_test.d" -MT"build/iot_link/shell/shell_test.d" -MT"build/iot_link/shell/shell_test.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/shell/shell_test.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell/shell_test.c -o build/iot_link/shell/shell_test.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/shell/shell_main.d" -MT"build/iot_link/shell/shell_main.d" -MT"build/iot_link/shell/shell_main.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/shell/shell_main.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell/shell_main.c -o build/iot_link/shell/shell_main.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/shell/shell_cmd.d" -MT"build/iot_link/shell/shell_cmd.d" -MT"build/iot_link/shell/shell_cmd.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/shell/shell_cmd.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell/shell_cmd.c -o build/iot_link/shell/shell_cmd.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/stimer/stimer.d" -MT"build/iot_link/stimer/stimer.d" -MT"build/iot_link/stimer/stimer.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/stimer/stimer.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/stimer/stimer.c -o build/iot_link/stimer/stimer.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/queue/queue.d" -MT"build/iot_link/queue/queue.d" -MT"build/iot_link/queue/queue.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/queue/queue.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue/queue.c -o build/iot_link/queue/queue.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/driver/driver.d" -MT"build/iot_link/driver/driver.d" -MT"build/iot_link/driver/driver.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/driver/driver.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver/driver.c -o build/iot_link/driver/driver.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/at/at.d" -MT"build/iot_link/at/at.d" -MT"build/iot_link/at/at.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/at/at.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/at/at.c -o build/iot_link/at/at.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/crc/crc16.d" -MT"build/iot_link/crc/crc16.d" -MT"build/iot_link/crc/crc16.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/crc/crc16.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc/crc16.c -o build/iot_link/crc/crc16.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/crc/crc8.d" -MT"build/iot_link/crc/crc8.d" -MT"build/iot_link/crc/crc8.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/crc/crc8.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc/crc8.c -o build/iot_link/crc/crc8.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/crc/crc32.d" -MT"build/iot_link/crc/crc32.d" -MT"build/iot_link/crc/crc32.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/crc/crc32.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc/crc32.c -o build/iot_link/crc/crc32.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.d" -MT"build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.d" -MT"build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.c -o build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.d" -MT"build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.d" -MT"build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.c -o build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/storage/partition.d" -MT"build/iot_link/storage/partition.d" -MT"build/iot_link/storage/partition.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/storage/partition.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage/partition.c -o build/iot_link/storage/partition.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/storage/storage.d" -MT"build/iot_link/storage/storage.d" -MT"build/iot_link/storage/storage.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/storage/storage.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage/storage.c -o build/iot_link/storage/storage.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/demos/app_demo_main.d" -MT"build/iot_link/demos/app_demo_main.d" -MT"build/iot_link/demos/app_demo_main.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/demos/app_demo_main.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/demos/app_demo_main.c -o build/iot_link/demos/app_demo_main.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/link_main.d" -MT"build/iot_link/link_main.d" -MT"build/iot_link/link_main.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/iot_link/link_main.lst /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_main.c -o build/iot_link/link_main.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.d" -MT"build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.lst /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c -o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Hardware/Src/hal_qspi_flash.d" -MT"build/Hardware/Src/hal_qspi_flash.d" -MT"build/Hardware/Src/hal_qspi_flash.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Hardware/Src/hal_qspi_flash.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Src/hal_qspi_flash.c -o build/Hardware/Src/hal_qspi_flash.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Hardware/Src/hal_rng.d" -MT"build/Hardware/Src/hal_rng.d" -MT"build/Hardware/Src/hal_rng.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Hardware/Src/hal_rng.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Src/hal_rng.c -o build/Hardware/Src/hal_rng.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Hardware/Src/hal_iwdg.d" -MT"build/Hardware/Src/hal_iwdg.d" -MT"build/Hardware/Src/hal_iwdg.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Hardware/Src/hal_iwdg.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Src/hal_iwdg.c -o build/Hardware/Src/hal_iwdg.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Hardware/OLED/oled.d" -MT"build/Hardware/OLED/oled.d" -MT"build/Hardware/OLED/oled.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Hardware/OLED/oled.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED/oled.c -o build/Hardware/OLED/oled.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Hardware/DHT11/dht11.d" -MT"build/Hardware/DHT11/dht11.d" -MT"build/Hardware/DHT11/dht11.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Hardware/DHT11/dht11.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.c -o build/Hardware/DHT11/dht11.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I 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-Wa,-a,-ad,-alms=build/Src/main.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/main.c -o build/Src/main.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/system_stm32l4xx.d" -MT"build/Src/system_stm32l4xx.d" -MT"build/Src/system_stm32l4xx.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/system_stm32l4xx.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/system_stm32l4xx.c -o build/Src/system_stm32l4xx.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/stm32l4xx_it.d" -MT"build/Src/stm32l4xx_it.d" -MT"build/Src/stm32l4xx_it.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/stm32l4xx_it.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/stm32l4xx_it.c -o build/Src/stm32l4xx_it.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/sys_init.d" -MT"build/Src/sys_init.d" -MT"build/Src/sys_init.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/sys_init.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/sys_init.c -o build/Src/sys_init.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/usart.d" -MT"build/Src/usart.d" -MT"build/Src/usart.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/usart.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/usart.c -o build/Src/usart.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/uart_debug.d" -MT"build/Src/uart_debug.d" -MT"build/Src/uart_debug.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/uart_debug.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/uart_debug.c -o build/Src/uart_debug.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I 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-Wa,-a,-ad,-alms=build/Src/dwt.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/dwt.c -o build/Src/dwt.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/i2c.d" -MT"build/Src/i2c.d" -MT"build/Src/i2c.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/i2c.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/i2c.c -o build/Src/i2c.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/gpio.d" -MT"build/Src/gpio.d" -MT"build/Src/gpio.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/gpio.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/gpio.c -o build/Src/gpio.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Src/rtc.d" -MT"build/Src/rtc.d" -MT"build/Src/rtc.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Src/rtc.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Src/rtc.c -o build/Src/rtc.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/uart_at/uart_at.d" -MT"build/uart_at/uart_at.d" -MT"build/uart_at/uart_at.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/uart_at/uart_at.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/uart_at/uart_at.c -o build/uart_at/uart_at.o +arm-none-eabi-gcc -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/Demos/use_coap_demo/use_coap_demo.d" -MT"build/Demos/use_coap_demo/use_coap_demo.d" -MT"build/Demos/use_coap_demo/use_coap_demo.o" -Wno-missing-braces -Wa,-a,-ad,-alms=build/Demos/use_coap_demo/use_coap_demo.lst /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Demos/use_coap_demo/use_coap_demo.c -o build/Demos/use_coap_demo/use_coap_demo.o +arm-none-eabi-gcc -x assembler-with-cpp -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -D CONFIG_LINK_LOG_ENABLE=1 -D CONFIG_LITEOS_ENABLE=1 -D CONFIG_SHELL_ENABLE=1 -D CONFIG_DRIVER_ENABLE=1 -D CONFIG_AT_ENABLE=1 -D CONFIG_OC_COAP_BOUDICA120_ENABLE=1 -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG -D CONFIG_USE_COAP_ENABLE=1 -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/inc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_misc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/link_log -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/osal -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/common/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/cmsis -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/base/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/extended/include -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/shell -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/queue -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/driver -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/at -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/crc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/oc_coap_al -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/oc/oc_coap/boudica120_oc -I /home/fanxinhao/Work/LiteOS_Lab/iot_link/storage -I /home/fanxinhao/Work/LiteOS_Lab/iot_link -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/OS_CONFIG -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc -I /home/fanxinhao/Work/LiteOS_Lab/drivers/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/OLED -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Hardware/DHT11 -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Inc -I /home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476 -O0 -g -Wall -fdata-sections -ffunction-sections -g -gdwarf-2 -MMD -MP -MF"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.d" -MT"build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.o" -Wno-missing-braces /home/fanxinhao/Work/LiteOS_Lab/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.S -o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.o +arm-none-eabi-gcc build/iot_link/link_misc/link_ring_buffer.o build/iot_link/link_misc/link_random.o build/iot_link/link_misc/link_string.o build/iot_link/link_log/link_log.o build/iot_link/os/osal/osal.o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/los_exc.o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_dispatch.o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hwi.o build/iot_link/os/liteos/arch/arm/arm-m/src/los_mpu.o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw.o build/iot_link/os/liteos/arch/arm/arm-m/src/los_svc.o build/iot_link/os/liteos/arch/arm/arm-m/src/los_hw_tick.o build/iot_link/os/liteos/cmsis/cmsis_liteos.o build/iot_link/os/liteos/utils/rbtree.o build/iot_link/os/liteos/los_init.o build/iot_link/os/liteos/liteos_imp.o build/iot_link/os/liteos/newlib_stub.o build/iot_link/os/liteos/malloc.o build/iot_link/os/liteos/liteos_errno.o build/iot_link/os/liteos/base/core/los_swtmr.o build/iot_link/os/liteos/base/core/los_priqueue.o build/iot_link/os/liteos/base/core/los_task.o build/iot_link/os/liteos/base/core/los_timeslice.o build/iot_link/os/liteos/base/core/los_sys.o build/iot_link/os/liteos/base/core/los_tick.o build/iot_link/os/liteos/base/ipc/los_rwlock.o build/iot_link/os/liteos/base/ipc/los_mux.o build/iot_link/os/liteos/base/ipc/los_sem.o build/iot_link/os/liteos/base/ipc/los_event.o build/iot_link/os/liteos/base/ipc/los_queue.o build/iot_link/os/liteos/base/mem/heap/los_heap.o build/iot_link/os/liteos/base/mem/heap/los_memory.o build/iot_link/os/liteos/base/mem/membox/los_membox.o build/iot_link/os/liteos/base/mem/common/los_slab.o build/iot_link/os/liteos/base/mem/common/los_slabmem.o build/iot_link/os/liteos/base/mem/common/los_memcheck.o build/iot_link/os/liteos/base/misc/los_misc.o build/iot_link/os/liteos/base/om/los_err.o build/iot_link/os/liteos/extended/tickless/los_tickless.o build/iot_link/shell/shell_test.o build/iot_link/shell/shell_main.o build/iot_link/shell/shell_cmd.o build/iot_link/stimer/stimer.o build/iot_link/queue/queue.o build/iot_link/driver/driver.o build/iot_link/at/at.o build/iot_link/crc/crc16.o build/iot_link/crc/crc8.o build/iot_link/crc/crc32.o build/iot_link/oc/oc_coap/oc_coap_al/oc_coap_al.o build/iot_link/oc/oc_coap/boudica120_oc/boudica120_oc.o build/iot_link/storage/partition.o build/iot_link/storage/storage.o build/iot_link/demos/app_demo_main.o build/iot_link/link_main.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.o build/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.o build/Hardware/Src/hal_qspi_flash.o build/Hardware/Src/hal_rng.o build/Hardware/Src/hal_iwdg.o build/Hardware/OLED/oled.o build/Hardware/DHT11/dht11.o build/Src/main.o build/Src/system_stm32l4xx.o build/Src/stm32l4xx_it.o build/Src/sys_init.o build/Src/usart.o build/Src/uart_debug.o build/Src/dwt.o build/Src/i2c.o build/Src/gpio.o build/Src/rtc.o build/uart_at/uart_at.o build/Demos/use_coap_demo/use_coap_demo.o build/iot_link/os/liteos/arch/arm/arm-m/armv7-m/gcc/los_startup.o -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -specs=nano.specs -T/home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/GCC/os.ld -L/home/fanxinhao/Work/LiteOS_Lab/targets/STM32L476RG_NB476/Lib -lc -lm -lnosys -Wl,-Map=build/Huawei_LiteOS.map,--cref -Wl,--gc-sections -u _printf_float -o build/Huawei_LiteOS.elf +arm-none-eabi-size build/Huawei_LiteOS.elf + text data bss dec hex filename + 76528 848 10136 87512 155d8 build/Huawei_LiteOS.elf +arm-none-eabi-objcopy -O ihex build/Huawei_LiteOS.elf build/Huawei_LiteOS.hex +arm-none-eabi-objcopy -O binary -S build/Huawei_LiteOS.elf build/Huawei_LiteOS.bin diff --git a/targets/STM32L476RG_NB476/GCC/Makefile b/targets/STM32L476RG_NB476/GCC/Makefile new file mode 100644 index 000000000..297746dff --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/Makefile @@ -0,0 +1,170 @@ +################################################################################ +# STM32L431RGx_NB476 GCC compiler Makefile +################################################################################ +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# ------------------------------------------------ + +################################################################################ +# target +################################################################################ +TARGET = Huawei_LiteOS +################################################################################ +# building variables +################################################################################ +# debug build? +DEBUG = 1 +# optimization +OPT = -O0 -g + +################################################################################ +# binaries +################################################################################ +PREFIX = arm-none-eabi- +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +OBJCOPY = $(PREFIX)objcopy +OBJDUMP = $(PREFIX)objdump +AR = $(PREFIX)ar +SZ = $(PREFIX)size +LD = $(PREFIX)ld +HEX = $(OBJCOPY) -O ihex +BIN = $(OBJCOPY) -O binary -S + + +################################################################################ +# paths +################################################################################ +BUILD_DIR = build +LD_FILE = os.ld +MAKEFILE_DIR = $(abspath $(CURDIR)) +LDSCRIPT = $(MAKEFILE_DIR)/$(LD_FILE) +TARGET_DIR = $(abspath $(MAKEFILE_DIR)/..) + +#we should export the SDK_DIR FOR THE iot.mk and project.mk use +ifndef SDK_DIR + SDK_DIR :=$(abspath $(MAKEFILE_DIR)/../../..) +endif + +DRIVERLIB_DIR := $(SDK_DIR)/drivers +IOTLINK_DIR := $(SDK_DIR)/iot_link + +################################################################################ +#common variables for other module or components +C_SOURCES = +C_DEFS = +C_INCLUDES = +LDFLAGS = +ASM_SOURCES_S = +AS_DEFS = +AS_INCLUDES = +PERIFLIB_SOURCES = +LIBS = +LIBDIR = +LDFLAGS = +ASFLAGS = +CFLAGS = + +##########################LOAD THE SOURCES INCLUDES AND DEFINES################# +include ../.config +include $(SDK_DIR)/iot_link/iot.mk +include $(MAKEFILE_DIR)/project.mk + + +################################################################################ +# firmware library +################################################################################ + + +################################################################################ +# CFLAGS +################################################################################ +# cpu +CPU = -mcpu=cortex-m4 +# fpu +FPU = -mfpu=fpv4-sp-d16 +# float-abi +FLOAT-ABI = -mfloat-abi=hard +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# compile gcc flags +ASFLAGS += $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$@" + +# excluded unnecessary warnings +CFLAGS += -Wno-missing-braces + + +# libraries +LIBS += -lc -lm -lnosys +LIBDIR += -L$(TARGET_DIR)/Lib +LDFLAGS += $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections +LDFLAGS += -u _printf_float + + +############HERE WE GET THE C_OBJECT S_OBJECT AND THE PATH ##################### +#all the code for the compile: +#iot_link: which indexed by the iot_link_root, it is the sdk main +#drivers: which maybe used by the targets, it is common for the MCUS +#targets: which developed by the user + +#changge the path for all the sources in directory iot_link targets drivers +#WE WILL CREATE SAME RELATION SHIP IN THE BUILD_DIR, AND IF YOU HAVE SOURCES +#out of SDK_DIR TARGET_DIR, please add them as THIS +C_OBJ := +C_OBJ += $(patsubst $(IOTLINK_DIR)/%.c,$(BUILD_DIR)/iot_link/%.o,$(filter $(IOTLINK_DIR)/%.c,$(C_SOURCES))) +C_OBJ += $(patsubst $(DRIVERLIB_DIR)/%.c,$(BUILD_DIR)/drivers/%.o,$(filter $(DRIVERLIB_DIR)/%.c,$(C_SOURCES))) +C_OBJ += $(patsubst $(TARGET_DIR)/%.c,$(BUILD_DIR)/%.o,$(filter $(TARGET_DIR)/%.c,$(C_SOURCES))) + +S_OBJ := +S_OBJ += $(patsubst $(IOTLINK_DIR)/%.S,$(BUILD_DIR)/iot_link/%.o,$(filter $(IOTLINK_DIR)/%.S,$(ASM_SOURCES_S))) +S_OBJ += $(patsubst $(DRIVERLIB_DIR)/%.S,$(BUILD_DIR)/drivers/%.o,$(filter $(DRIVERLIB_DIR)/%.S,$(ASM_SOURCES_S))) +S_OBJ += $(patsubst $(TARGET_DIR)/%.S,$(BUILD_DIR)/%.o,$(filter $(TARGET_DIR)/%.S,$(ASM_SOURCES_S))) + +OBJ_DIRS := +OBJ_DIRS += $(dir $(C_OBJ)) +OBJ_DIRS += $(dir $(S_OBJ)) +OBJ_DIRS := $(sort $(OBJ_DIRS)) + +#ADD THE SDK_DIR AND TARGET_DIR TO THE SEARCH PATH +vpath %.c $(SDK_DIR):$(TARGET_DIR) +vpath %.S $(SDK_DIR):$(TARGET_DIR) + +#NOW DO THE BUILDING +all:$(BUILD_DIR)/$(TARGET).elf + -$(HEX) $< $(BUILD_DIR)/$(TARGET).hex + -$(BIN) $< $(BUILD_DIR)/$(TARGET).bin + +$(BUILD_DIR)/$(TARGET).elf:$(OBJ_DIRS) $(C_OBJ) $(S_OBJ) + $(CC) $(C_OBJ) $(S_OBJ) $(LDFLAGS) -o $@ + $(SZ) $@ + +#create the necessary path for the object +$(OBJ_DIRS): + -mkdir -p $@ + +#compile the c file to the object, as you know we has map the .c to the .o +$(C_OBJ):$(BUILD_DIR)/%.o:%.c + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(@:%.o=%.lst) $< -o $@ + +#compile the s fike to the object, as you know we has map the .S to the .o +$(S_OBJ):$(BUILD_DIR)/%.o:%.S + $(AS) -c $(CFLAGS) $< -o $@ + + +################################################################################ +# clean up: all you need to do is to remove the build dirs +################################################################################ +clean: + -rm -fR .dep $(BUILD_DIR) + +# *** EOF *** diff --git a/targets/STM32L476RG_NB476/GCC/Makefile_Sota b/targets/STM32L476RG_NB476/GCC/Makefile_Sota new file mode 100644 index 000000000..144b1e28a --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/Makefile_Sota @@ -0,0 +1,187 @@ +########################################################################################################################## +# Cloud_STM32F429IGTx_FIRE GCC compiler Makefile +########################################################################################################################## + +# ------------------------------------------------ +# Generate sota lib (based on gcc) +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = libsota +###################################### +# building variables +###################################### +# debug build? +DEBUG = 0 +# optimization +OPT = -Og + +####################################### +# configuration +####################################### +OTA_IS_NEED_DTLS := yes +ifeq ($(OTA_IS_NEED_DTLS), yes) + OTA_PACK_CHECKSUM := CHECKSUM_SHA256_RSA2048 #(CHECKSUM_SHA256, CHECKSUM_SHA256_RSA2048) +else + OTA_PACK_CHECKSUM := CHECKSUM_NONE +endif +####################################### + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +OBJCOPY = $(PREFIX)objcopy +OBJDUMP = $(PREFIX)objdump +AR = $(PREFIX)ar +SZ = $(PREFIX)size +LD = $(PREFIX)ld +HEX = $(OBJCOPY) -O ihex +BIN = $(OBJCOPY) -O binary -S + + +PROJECTBASE = $(PWD) +override PROJECTBASE := $(abspath $(PROJECTBASE)) +TOP_DIR = $(PROJECTBASE)/../../.. + + +####################################### +# paths +####################################### +# firmware library path +PERIFLIB_PATH = + +# Build path +BUILD_DIR = build +HWPATCH_BUILD_DIR = hwpatch + +# Lib path +LIBDIR = $(PROJECTBASE)/../Lib + +###################################### +# source +###################################### + +# C sources + +ifeq ($(OTA_IS_NEED_DTLS), yes) +MBEDTLS_SRC = \ + ${wildcard $(TOP_DIR)/components/security/mbedtls/mbedtls-2.6.0/library/*.c} + C_SOURCES += $(MBEDTLS_SRC) +endif + +SOTA_SRC = \ + ${wildcard $(TOP_DIR)/components/ota/sota/*.c} + C_SOURCES += $(SOTA_SRC) + +OTA_SRC = \ + ${wildcard $(TOP_DIR)/components/ota/flag_operate/*.c} \ + ${wildcard $(TOP_DIR)/components/ota/package/*.c} + C_SOURCES += $(OTA_SRC) + + +###################################### +# firmware library +###################################### +PERIFLIB_SOURCES = + + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m4 +# fpu +FPU = -mfpu=fpv4-sp-d16 +# float-abi +FLOAT-ABI = -mfloat-abi=hard +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc + +# C defines +C_DEFS = + +ifeq ($(OTA_IS_NEED_DTLS), yes) + C_DEFS += -D WITH_SOTA + C_DEFS += -D MBEDTLS_CONFIG_FILE=\"los_mbedtls_config.h\" +endif + +ifeq ($(OTA_PACK_CHECKSUM), CHECKSUM_NONE) + C_DEFS += -D PACK_CHECKSUM=2 +else ifeq ($(OTA_PACK_CHECKSUM), CHECKSUM_SHA256) + C_DEFS += -D PACK_CHECKSUM=1 +else ifeq ($(OTA_PACK_CHECKSUM), CHECKSUM_SHA256_RSA2048) + C_DEFS += -D PACK_CHECKSUM=0 +else +endif + + +# C includes + +INCLUDE_INC = \ + -I $(TOP_DIR)/include + C_INCLUDES += $(INCLUDE_INC) + +OTA_INC = \ + -I $(TOP_DIR)/components/ota/flag_operate \ + -I $(TOP_DIR)/components/ota/utility + C_INCLUDES += $(OTA_INC) + +MBEDTLS_INC = \ + -I $(TOP_DIR)/components/security/mbedtls/mbedtls-2.6.0/include + C_INCLUDES += $(MBEDTLS_INC) + +MBEDTLS_PORT_INC = \ + -I $(TOP_DIR)/components/security/mbedtls/mbedtls_port + C_INCLUDES += $(MBEDTLS_PORT_INC) + + +# compile gcc flags +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$@" + + +# default action: build all +all: $(BUILD_DIR)/$(HWPATCH_BUILD_DIR)/%.o $(BUILD_DIR)/$(TARGET).a + + +####################################### +# build the sota lib +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) + + +$(BUILD_DIR)/%.o: %.c | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/$(HWPATCH_BUILD_DIR)/%.o: $(LIBDIR)/libhwpatch.a | $(BUILD_DIR) + cd $(BUILD_DIR)/$(HWPATCH_BUILD_DIR) && $(AR) -x $< + +$(BUILD_DIR)/$(TARGET).a: $(OBJECTS) $(BUILD_DIR)/$(HWPATCH_BUILD_DIR)/*.o + $(AR) -r -o $@ $^ && cp $(BUILD_DIR)/$(TARGET).a $(LIBDIR)/$(TARGET).a + $(SZ) $@ + + +$(BUILD_DIR): + mkdir -p $(BUILD_DIR)/$(HWPATCH_BUILD_DIR) + +####################################### +# clean up +####################################### +clean: + -rm -fR .dep $(BUILD_DIR) $(LIBDIR)/$(TARGET).a \ No newline at end of file diff --git a/targets/STM32L476RG_NB476/GCC/os.ld b/targets/STM32L476RG_NB476/GCC/os.ld new file mode 100644 index 000000000..838eb7db9 --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/os.ld @@ -0,0 +1,217 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32L476RGTx series +** 1024Kbytes FLASH and 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20018000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K +RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + __oshell_start = .; + KEEP (*(oshell)) + __oshell_end = .; + + . = ALIGN(4); + __osdriv_start = .; + KEEP (*(osdriv)) + __osdriv_end = .; + + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab : + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + . = ALIGN(8); + __los_heap_addr_start__ = .; + __los_heap_addr_end__ = ORIGIN(RAM) + LENGTH(RAM) - _Min_Stack_Size - 1; + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/targets/STM32L476RG_NB476/GCC/os_app.ld b/targets/STM32L476RG_NB476/GCC/os_app.ld new file mode 100644 index 000000000..e9cf10391 --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/os_app.ld @@ -0,0 +1,203 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F4429IGTx Device with +** 1024KByte FLASH, 192KByte RAM, 64KByte CCM DATA RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ +/*THIS FILE USED TO GENERATE THE APPLICAITON,WHICH NEED THE LOADER SUPPORT*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 1024K-64K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + __oshell_start = .; + KEEP (*(oshell)) + __oshell_end = .; + + . = ALIGN(4); + __osdriv_start = .; + KEEP (*(osdriv)) + __osdriv_end = .; + + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + . = ALIGN(8); + __los_heap_addr_start__ = .; + __los_heap_addr_end__ = ORIGIN(RAM) + LENGTH(RAM) - _Min_Stack_Size - 1; + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/targets/STM32L476RG_NB476/GCC/os_loader.ld b/targets/STM32L476RG_NB476/GCC/os_loader.ld new file mode 100644 index 000000000..def321efc --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/os_loader.ld @@ -0,0 +1,198 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F4429IGTx Device with +** 1024KByte FLASH, 192KByte RAM, 64KByte CCM DATA RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ +/*THIS FILE USED TO GENERATE THE LOADER, which used to load the application*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20030000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K +CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + __oshell_start = .; + KEEP (*(oshell)) + __oshell_end = .; + + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + . = ALIGN(8); + __los_heap_addr_start__ = .; + __los_heap_addr_end__ = ORIGIN(RAM) + LENGTH(RAM) - _Min_Stack_Size - 1; + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/targets/STM32L476RG_NB476/GCC/project.mk b/targets/STM32L476RG_NB476/GCC/project.mk new file mode 100644 index 000000000..f96c2dbe4 --- /dev/null +++ b/targets/STM32L476RG_NB476/GCC/project.mk @@ -0,0 +1,76 @@ +HAL_DRIVER_SRC = \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c \ + $(SDK_DIR)/drivers/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c + C_SOURCES += $(HAL_DRIVER_SRC) + +HARDWARE_SRC = \ + ${wildcard $(TARGET_DIR)/Hardware/Src/*.c} \ + ${wildcard $(TARGET_DIR)/Hardware/OLED/*.c} \ + ${wildcard $(TARGET_DIR)/Hardware/DHT11/*.c} + C_SOURCES += $(HARDWARE_SRC) + +HAL_DRIVER_SRC_NO_BOOTLOADER = \ + $(DRIVERLIB_DIR)/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c \ + $(DRIVERLIB_DIR)/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c \ + $(DRIVERLIB_DIR)/third_party/ST/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c + C_SOURCES += $(HAL_DRIVER_SRC_NO_BOOTLOADER) + +USER_SRC = \ + $(TARGET_DIR)/Src/main.c \ + $(TARGET_DIR)/Src/system_stm32l4xx.c \ + $(TARGET_DIR)/Src/stm32l4xx_it.c \ + $(TARGET_DIR)/Src/sys_init.c \ + $(TARGET_DIR)/Src/usart.c \ + $(TARGET_DIR)/Src/uart_debug.c \ + $(TARGET_DIR)/Src/dwt.c \ + $(TARGET_DIR)/Src/i2c.c \ + $(TARGET_DIR)/Src/gpio.c\ + $(TARGET_DIR)/Src/rtc.c + C_SOURCES += $(USER_SRC) + +ifeq ($(CONFIG_AT_ENABLE),y) + UART_AT_SRC = $(TARGET_DIR)/uart_at/uart_at.c + C_SOURCES += $(UART_AT_SRC) +endif + + OS_CONFIG_INC = \ + -I $(TARGET_DIR)/OS_CONFIG + C_INCLUDES += $(OS_CONFIG_INC) +# C includes +HAL_DRIVER_INC = \ + -I $(DRIVERLIB_DIR)/third_party/ST/STM32L4xx_HAL_Driver/Inc \ + -I $(DRIVERLIB_DIR)/third_party/ST/STM32L4xx_HAL_Driver/Inc/Legacy + C_INCLUDES += $(HAL_DRIVER_INC) +HARDWARE_INC = \ + -I ${wildcard $(TARGET_DIR)/Hardware/Inc} \ + -I ${wildcard $(TARGET_DIR)/Hardware/OLED} \ + -I ${wildcard $(TARGET_DIR)/Hardware/DHT11} + C_INCLUDES += $(HARDWARE_INC) + +USER_INC = \ + -I $(TARGET_DIR)/Inc \ + -I $(TARGET_DIR) + C_INCLUDES += $(USER_INC) + +# C defines +C_DEFS += -D USE_HAL_DRIVER -D STM32L476xx -D NDEBUG + +include $(TARGET_DIR)/Demos/user_demo.mk + + diff --git a/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.c b/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.c new file mode 100644 index 000000000..f0ef29e32 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.c @@ -0,0 +1,183 @@ +#include "los_task.ph" +#include "dht11.h" + +static void DHT11_Mode_IPU(void); +static void DHT11_Mode_Out_PP(void); +static uint8_t DHT11_ReadByte(void); + +/* 函数体 --------------------------------------------------------------------*/ +/** + * 函数功能: + * 输入参数: 无 + * 返 回 值: 无 + * 说 明：无 + */ +void DHT11_Delay(uint32_t time) +{ + uint8_t i; + + while(time) + { + for (i = 0; i < 16; i++) + { + + } + time--; + } +} + +/** + * 函数功能: DHT11 初始化函数 + * 输入参数: 无 + * 返 回 值: 无 + * 说 明：无 + */ +void DHT11_Init ( void ) +{ + DHT11_Dout_GPIO_CLK_ENABLE(); + + DHT11_Mode_Out_PP(); + + DHT11_Dout_HIGH(); // 拉高GPIO + delay10ms(300); +} + +/** + * 函数功能: 使DHT11-DATA引脚变为上拉输入模式 + * 输入参数: 无 + * 返 回 值: 无 + * 说 明：无 + */ +static void DHT11_Mode_IPU(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 串口外设功能GPIO配置 */ + GPIO_InitStruct.Pin = DHT11_Dout_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(DHT11_Dout_PORT, &GPIO_InitStruct); + +} + +/** + * 函数功能: 使DHT11-DATA引脚变为推挽输出模式 + * 输入参数: 无 + * 返 回 值: 无 + * 说 明：无 + */ +static void DHT11_Mode_Out_PP(void) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* 串口外设功能GPIO配置 */ + GPIO_InitStruct.Pin = DHT11_Dout_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(DHT11_Dout_PORT, &GPIO_InitStruct); +} + +/** + * 函数功能: 从DHT11读取一个字节，MSB先行 + * 输入参数: 无 + * 返 回 值: 无 + * 说 明：无 + */ +static uint8_t DHT11_ReadByte ( void ) +{ + uint8_t i, temp=0; + + for(i=0;i<8;i++) + { + /*每bit以50us低电平标置开始，轮询直到从机发出 的50us 低电平 结束*/ + while(DHT11_Data_IN()==GPIO_PIN_RESET); + + /*DHT11 以26~28us的高电平表示“0”，以70us高电平表示“1”， + *通过检测 x us后的电平即可区别这两个状 ，x 即下面的延时 + */ + delayus(40); //延时x us 这个延时需要大于数据0持续的时间即可 + + if(DHT11_Data_IN()==GPIO_PIN_SET)/* x us后仍为高电平表示数据“1” */ + { + /* 等待数据1的高电平结束 */ + while(DHT11_Data_IN()==GPIO_PIN_SET); + + temp|=(uint8_t)(0x01<<(7-i)); //把第7-i位置1，MSB先行 + } + else // x us后为低电平表示数据“0” + { + temp&=(uint8_t)~(0x01<<(7-i)); //把第7-i位置0，MSB先行 + } + } + return temp; +} + + +/** + * 函数功能: 一次完整的数据传输为40bit，高位先出 + * 输入参数: DHT11_Data:DHT11数据类型 + * 返 回 值: ERROR： 读取出错 + * SUCCESS：读取成功 + * 说 明：8bit 湿度整数 + 8bit 湿度小数 + 8bit 温度整数 + 8bit 温度小数 + 8bit 校验和 + */ +uint8_t DHT11_Read_TempAndHumidity(DHT11_Data_TypeDef *DHT11_Data) +{ + uint8_t temp; + uint16_t humi_temp; + + /*输出模式*/ + DHT11_Mode_Out_PP(); + /*主机拉低*/ + DHT11_Dout_LOW(); + /*延时18ms*/ + LOS_TaskDelay(18); + + /*总线拉高 主机延时30us*/ + DHT11_Dout_HIGH(); + + delayus(30); //延时30us + + /*主机设为输入 判断从机响应信号*/ + DHT11_Mode_IPU(); + + /*判断从机是否有低电平响应信号 如不响应则跳出，响应则向下运行*/ + if(DHT11_Data_IN()==GPIO_PIN_RESET) + { + /*轮询直到从机发出 的80us 低电平 响应信号结束*/ + while(DHT11_Data_IN()==GPIO_PIN_RESET); + + /*轮询直到从机发出的 80us 高电平 标置信号结束*/ + while(DHT11_Data_IN()==GPIO_PIN_SET); + + /*开始接收数据*/ + DHT11_Data->humi_high8bit= DHT11_ReadByte(); + DHT11_Data->humi_low8bit = DHT11_ReadByte(); + DHT11_Data->temp_high8bit= DHT11_ReadByte(); + DHT11_Data->temp_low8bit = DHT11_ReadByte(); + DHT11_Data->check_sum = DHT11_ReadByte(); + + /*读取结束，引脚改为输出模式*/ + DHT11_Mode_Out_PP(); + /*主机拉高*/ + DHT11_Dout_HIGH(); + + /* 对数据进行处理 */ + humi_temp=DHT11_Data->humi_high8bit*100+DHT11_Data->humi_low8bit; + DHT11_Data->humidity =(float)humi_temp/100; + + humi_temp=DHT11_Data->temp_high8bit*100+DHT11_Data->temp_low8bit; + DHT11_Data->temperature=(float)humi_temp/100; + + /*检查读取的数据是否正确*/ + temp = DHT11_Data->humi_high8bit + DHT11_Data->humi_low8bit + + DHT11_Data->temp_high8bit+ DHT11_Data->temp_low8bit; + if(DHT11_Data->check_sum==temp) + { + return SUCCESS; + } + else + return ERROR; + } + else + return ERROR; +} diff --git a/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.h b/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.h new file mode 100644 index 000000000..58dce1741 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/DHT11/dht11.h @@ -0,0 +1,29 @@ +#ifndef __DHT11_H__ +#define __DHT11_H__ + +#include "main.h" +#include "dwt.h" +/************************ DHT11 数据类型定义******************************/ +typedef struct +{ + uint8_t humi_high8bit; //原始数据：湿度高8位 + uint8_t humi_low8bit; //原始数据：湿度低8位 + uint8_t temp_high8bit; //原始数据：温度高8位 + uint8_t temp_low8bit; //原始数据：温度高8位 + uint8_t check_sum; //校验和 + float humidity; //实际湿度 + float temperature; //实际温度 +} DHT11_Data_TypeDef; + +#define DHT11_Dout_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define DHT11_Dout_PORT GPIOC +#define DHT11_Dout_PIN GPIO_PIN_13 + +#define DHT11_Dout_LOW() HAL_GPIO_WritePin(DHT11_Dout_PORT,DHT11_Dout_PIN,GPIO_PIN_RESET) +#define DHT11_Dout_HIGH() HAL_GPIO_WritePin(DHT11_Dout_PORT,DHT11_Dout_PIN,GPIO_PIN_SET) +#define DHT11_Data_IN() HAL_GPIO_ReadPin(DHT11_Dout_PORT,DHT11_Dout_PIN) + +void DHT11_Init( void ); +uint8_t DHT11_Read_TempAndHumidity(DHT11_Data_TypeDef * DHT11_Data); +void DHT11_Delay(uint32_t time); +#endif /* __DHT11_H__ */ diff --git a/targets/STM32L476RG_NB476/Hardware/Inc/hal_iwdg.h b/targets/STM32L476RG_NB476/Hardware/Inc/hal_iwdg.h new file mode 100644 index 000000000..7beb70158 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Inc/hal_iwdg.h @@ -0,0 +1,87 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + + /**@defgroup hal_iwdg Watch Dog + * @ingroup hal + */ + +#ifndef _HAL_IWDG_H_ +#define _HAL_IWDG_H_ + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + *@ingroup hal_iwdg + *@brief config the watch dog. + * + *@par Description: + *This API is used to config the watch dog. The time interval of feeding dog is prvscaler*reload/40. + *@attention none. + * + *@param prvscaler [IN] select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler + *@param reload [IN] specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see none. + */ +int hal_iwdg_config(uint8_t prvscaler, uint16_t reload); + +/** + *@ingroup hal_iwdg + *@brief feed the watch dog. + * + *@par Description: + *This API is used to feed the watch dog. + *@attention none. + * + *@param none. + * + *@retval none. + *@par Dependency: none. + *@see none. + */ +void hal_iwdg_feed(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _HAL_IWDG_H_ */ diff --git a/targets/STM32L476RG_NB476/Hardware/Inc/hal_qspi_flash.h b/targets/STM32L476RG_NB476/Hardware/Inc/hal_qspi_flash.h new file mode 100644 index 000000000..d136d96b3 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Inc/hal_qspi_flash.h @@ -0,0 +1,190 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + + /**@defgroup hal_spi_flash SPI Flash Interface + * @ingroup hal + */ + +#ifndef __HAL_SPI_FLASH_H__ +#define __HAL_SPI_FLASH_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@ingroup hal_spi_flash + *@brief config the spi flash. + * + *@par Description: + *This API is used to config the spi flash. + *@attention none. + * + *@param none. + * + *@retval none. + *@par Dependency: none. + *@see none. + */ +void hal_spi_flash_config(void); + +/** + *@ingroup hal_spi_flash + *@brief erase data of spi flash. + * + *@par Description: + *This API is used to erase data of spi flash. + *@attention none. + * + *@param addr [IN] the address of the spi flash to erase. + *@param len [IN] the number of bytes to be erased from addr. + Note that at lease 4K byte will be erased by once. + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see none. + */ +int hal_spi_flash_erase(uint32_t addr, int32_t len); + +/** + *@ingroup hal_spi_flash + *@brief write data to spi flash. + * + *@par Description: + *This API is used to write data to spi flash. You should call @hal_spi_flash_erase before this. + *location is updated by each call so that you don't need to care about write address if you do + *sequential write. + *@attention none. + * + *@param buf [IN] the data to be wrote to spi flash. + *@param len [IN] the length of the buffer. + *@param location [IN/OUT] the address of the spi flash to write. + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see hal_spi_flash_erase. + */ +int hal_spi_flash_write(const void* buf, int32_t len, uint32_t* location); + +/** + *@ingroup hal_spi_flash + *@brief write data to spi flash. + * + *@par Description: + *This API is used to write data to spi flash. You don't need to erase flash by this interface. + *@attention none. + * + *@param buf [IN] the data to be wrote to spi flash. + *@param len [IN] the length of the buffer. + *@param location [IN] the address of the spi flash to write. + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see none. + */ +int hal_spi_flash_erase_write(const void* buf, int32_t len, uint32_t location); + +/** + *@ingroup hal_spi_flash + *@brief read data from spi flash. + * + *@par Description: + *This API is used to read data from spi flash. + *@attention none. + * + *@param buf [OUT] buffer to store the data read from spi flash. + *@param len [IN] the length of the buffer. + *@param location [IN] the address of the spi flash to read. + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see none. + */ +int hal_spi_flash_read(void* buf, int32_t len, uint32_t location); + +/** + *@ingroup hal_spi_flash + *@brief get ID of the target spi flash. + * + *@par Description: + *This API is used to get ID of the target spi flash. + *@attention none. + * + *@param none. + * + *@retval #int ID of the spi flash. + *@par Dependency: none. + *@see none. + */ +int hal_spi_flash_get_id(void); + +/** + *@ingroup hal_spi_flash + *@brief power down the spi flash. + * + *@par Description: + *This API is used to power down the spi flash. + *@attention none. + * + *@param none. + * + *@retval none. + *@par Dependency: none. + *@see none. + */ +void hal_spi_flash_power_down(void); + +/** + *@ingroup hal_spi_flash + *@brief wake up the spi flash. + * + *@par Description: + *This API is used to wake up the spi flash. + *@attention none. + * + *@param none. + * + *@retval none. + *@par Dependency: none. + *@see none. + */ +void hal_spi_flash_wake_up(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_SPI_FLASH_H_ */ diff --git a/targets/STM32L476RG_NB476/Hardware/Inc/hal_rng.h b/targets/STM32L476RG_NB476/Hardware/Inc/hal_rng.h new file mode 100644 index 000000000..0ce365a31 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Inc/hal_rng.h @@ -0,0 +1,102 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + + /**@defgroup hal_rng Ramdon Number + * @ingroup hal + */ + +#ifndef _HAL_RNG_H_ +#define _HAL_RNG_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + *@ingroup hal_rng + *@brief config the rng. + * + *@par Description: + *This API is used to config the rng. + *@attention none. + * + *@param none. + * + *@retval none. + *@par Dependency: none. + *@see none. + */ +void hal_rng_config(void); + +/** + *@ingroup hal_rng + *@brief generate a random number. + * + *@par Description: + *This API is used to generate a random number. + *@attention none. + * + *@param none. + * + *@retval #int random number + *@par Dependency: none. + *@see none. + */ +int hal_rng_generate_number(void); + +/** + *@ingroup hal_rng + *@brief generate the random data. + * + *@par Description: + *This API is used to generate the random data. + *@attention none. + * + *@param buf [OUT] buffer to store the random data. + *@param len [IN] the length of the random data needed to generate. + * + *@retval #int 0 if succeed or -1 if failed. + *@par Dependency: none. + *@see none. + */ +int hal_rng_generate_buffer(void* buf, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_RNG_H_ */ diff --git a/targets/STM32L476RG_NB476/Hardware/OLED/bmp.h b/targets/STM32L476RG_NB476/Hardware/OLED/bmp.h new file mode 100644 index 000000000..ac29bd108 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/OLED/bmp.h @@ -0,0 +1,80 @@ +////////////////////////////////////////////////////////////////////////////////// +// +// +//洢ͼƬݣͼƬСΪ64*32 +// +///////////////////////////////////////////////////////////////////////////////// + +#ifndef __BMP_H +#define __BMP_H +unsigned char BMP1[] = +{0x00,0x06,0x0A,0xFE,0x0A,0xC6,0x00,0xE0,0x00,0xF0,0x00,0xF8,0x00,0x00,0x00,0x00, +0x00,0x00,0xFE,0x7D,0xBB,0xC7,0xEF,0xEF,0xEF,0xEF,0xEF,0xEF,0xEF,0xC7,0xBB,0x7D, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08, +0x0C,0xFE,0xFE,0x0C,0x08,0x20,0x60,0xFE,0xFE,0x60,0x20,0x00,0x00,0x00,0x78,0x48, +0xFE,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xFE,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF, +0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF,0xFF,0x00,0x00,0xFE,0xFF,0x03, +0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF,0xFE,0x00,0x00,0x00,0x00,0xC0,0xC0, +0xC0,0x00,0x00,0x00,0x00,0xFE,0xFF,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03, +0xFF,0xFE,0x00,0x00,0xFE,0xFF,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF, +0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x0C, +0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0xFF,0xFF,0x00,0x00,0x00,0x00,0xE1,0xE1, +0xE1,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0xFF, +0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x1F, +0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x0F,0x00,0x00,0x0F,0x1F,0x18, +0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x0F,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18, +0x1F,0x0F,0x00,0x00,0x0F,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F, +0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x8C,0x42,0x22,0x12,0x0C,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x00,0x04, +0xFE,0x00,0x00,0x00,0x20,0x58,0x44,0xFE,0x40,0x00,0x10,0x10,0x10,0x10,0x10,0x00, +0x00,0x04,0xFE,0x00,0x00,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x10,0x10,0x10,0x10, +0x10,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x00,0x04,0xFE,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x24,0xA4,0x2E,0x24,0xE4,0x24,0x2E,0xA4,0x24,0x00,0x00,0x00,0xF8,0x4A,0x4C, +0x48,0xF8,0x48,0x4C,0x4A,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01, +0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x20,0x10,0x10, +0x10,0x10,0x20,0xC0,0x00,0x00,0xC0,0x20,0x10,0x10,0x10,0x10,0x20,0xC0,0x00,0x00, +0x00,0x12,0x0A,0x07,0x02,0x7F,0x02,0x07,0x0A,0x12,0x00,0x00,0x00,0x0B,0x0A,0x0A, +0x0A,0x7F,0x0A,0x0A,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x40,0x40, +0x40,0x50,0x20,0x5F,0x80,0x00,0x1F,0x20,0x40,0x40,0x40,0x50,0x20,0x5F,0x80,0x00, + +}; + +#endif + + diff --git a/targets/STM32L476RG_NB476/Hardware/OLED/oled.c b/targets/STM32L476RG_NB476/Hardware/OLED/oled.c new file mode 100644 index 000000000..91f0122a5 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/OLED/oled.c @@ -0,0 +1,240 @@ +#include "oled.h" +#include "dwt.h" +#include "oledfont.h" + +#define OLED_WR_address 0x78 + +extern I2C_HandleTypeDef hi2c1; +//OLED���Դ� +//��Ÿ�ʽ����. +//[0]0 1 2 3 ... 127 +//[1]0 1 2 3 ... 127 +//[2]0 1 2 3 ... 127 +//[3]0 1 2 3 ... 127 +//[4]0 1 2 3 ... 127 +//[5]0 1 2 3 ... 127 +//[6]0 1 2 3 ... 127 +//[7]0 1 2 3 ... 127 + +/********************************************** +// IIC Write Command +**********************************************/ +void Write_IIC_Command(unsigned char IIC_Command) +{ + uint8_t tmp[] = {0x00,IIC_Command};//�Ĵ�����ַ������ + HAL_I2C_Master_Transmit(&hi2c1, OLED_WR_address, tmp, 2,100); + delayus(1); +} + +/********************************************** +// IIC Write Data +**********************************************/ +void Write_IIC_Data(unsigned char IIC_Data) +{ + + uint8_t tmp[] = {0x40, IIC_Data};//���ݵ�ַ������ + HAL_I2C_Master_Transmit(&hi2c1, OLED_WR_address, tmp, 2, 20); +} + +void OLED_WR_Byte(uint8_t dat, uint8_t cmd) +{ + if(cmd) + { + Write_IIC_Data(dat); + }else{ + Write_IIC_Command(dat); + } +} + +//�������� +void OLED_Set_Pos(unsigned char x, unsigned char y) +{ + OLED_WR_Byte(0xb0+y, OLED_CMD); + OLED_WR_Byte(((x&0xf0)>>4)|0x10, OLED_CMD); + OLED_WR_Byte((x&0x0f), OLED_CMD); +} + +//����OLED��ʾ +void OLED_Display_On(void) +{ + OLED_WR_Byte(0X8D, OLED_CMD); //SET DCDC���� + OLED_WR_Byte(0X14, OLED_CMD); //DCDC ON + OLED_WR_Byte(0XAF, OLED_CMD); //DISPLAY ON +} + +//�ر�OLED��ʾ +void OLED_Display_Off(void) +{ + OLED_WR_Byte(0X8D, OLED_CMD); //SET DCDC���� + OLED_WR_Byte(0X10, OLED_CMD); //DCDC OFF + OLED_WR_Byte(0XAE, OLED_CMD); //DISPLAY OFF +} + +//��������,������,������Ļ�Ǻ�ɫ��!��û����һ��!!! +void OLED_Clear(void) +{ + uint8_t i, n; + for(i=0; i<8; i++) + { + OLED_WR_Byte (0xb0+i, OLED_CMD); //����ҳ��ַ��0~7�� + OLED_WR_Byte (0x00, OLED_CMD); //������ʾλ�á��е͵�ַ + OLED_WR_Byte (0x10, OLED_CMD); //������ʾλ�á��иߵ�ַ + for(n=0; n<128; n++) + OLED_WR_Byte(0, OLED_DATA); + } //������ʾ +} + +void OLED_On(void) +{ + uint8_t i, n; + for(i=0; i<8; i++) + { + OLED_WR_Byte (0xb0+i, OLED_CMD); //����ҳ��ַ��0~7�� + OLED_WR_Byte (0x00, OLED_CMD); //������ʾλ�á��е͵�ַ + OLED_WR_Byte (0x10, OLED_CMD); //������ʾλ�á��иߵ�ַ + for(n=0; n<128; n++) + OLED_WR_Byte(1, OLED_DATA); + } //������ʾ +} + + +//��ָ��λ����ʾһ���ַ�,���������ַ� +//x:0~127 +//y:0 2 4 6���ֱ��Ӧ��1��2��3��4�� +//size:ѡ�������С 16���߷�16 +void OLED_ShowChar(uint8_t x, uint8_t y, uint8_t chr, uint8_t Char_Size) +{ + unsigned char c=0, i=0; + c=chr - ' ';//�õ�ƫ�ƺ��ֵ + if(x > Max_Column - 1){x = 0;y = y+2;} + if(Char_Size == 16) + { + OLED_Set_Pos(x, y); + for(i=0; i<8; i++) + OLED_WR_Byte(F8X16[c*16+i], OLED_DATA); + OLED_Set_Pos(x , y+1); + for(i=0; i<8; i++) + OLED_WR_Byte(F8X16[c*16+i+8], OLED_DATA); + }else{ + OLED_Set_Pos(x, y); + for(i=0; i<6; i++) + OLED_WR_Byte(F6x8[c][i], OLED_DATA); + } +} + + +//��ʾһ���ַ��� +void OLED_ShowString(uint8_t x, uint8_t y, uint8_t *chr, uint8_t Char_Size) +{ + unsigned char j=0; + while (chr[j] != '\0') + { + OLED_ShowChar(x, y, chr[j], Char_Size); + x += 8; + if(x > 120) + { + x = 0; + y += 2; + } + j++; + } +} + +//��ʾ���� +void OLED_ShowCHinese(uint8_t x, uint8_t y, uint8_t no) +{ + uint8_t t, adder=0; + OLED_Set_Pos(x, y); + for(t=0; t<16; t++) + { + OLED_WR_Byte(Hzk[no][t], OLED_DATA); + adder+=1; + } + OLED_Set_Pos(x, y+1); + for(t=16; t<32; t++) + { + OLED_WR_Byte(Hzk[no][t], OLED_DATA); + adder+=1; + } +} + +/***********������������ʾ��ʾBMPͼƬ128��64��ʼ������(x,y),x�ķ�Χ0��127��yΪҳ�ķ�Χ0��7*****************/ +void OLED_DrawBMP(unsigned char x0, unsigned char y0, unsigned char x1, unsigned char y1, unsigned char BMP[]) +{ + unsigned int j=0; + unsigned char x,y; + + for(y=y0; y +0x00, 0x02, 0x01, 0x51, 0x09, 0x06,// ? +0x00, 0x32, 0x49, 0x59, 0x51, 0x3E,// @ +0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C,// A +0x00, 0x7F, 0x49, 0x49, 0x49, 0x36,// B +0x00, 0x3E, 0x41, 0x41, 0x41, 0x22,// C +0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C,// D +0x00, 0x7F, 0x49, 0x49, 0x49, 0x41,// E +0x00, 0x7F, 0x09, 0x09, 0x09, 0x01,// F +0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A,// G +0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F,// H +0x00, 0x00, 0x41, 0x7F, 0x41, 0x00,// I +0x00, 0x20, 0x40, 0x41, 0x3F, 0x01,// J +0x00, 0x7F, 0x08, 0x14, 0x22, 0x41,// K +0x00, 0x7F, 0x40, 0x40, 0x40, 0x40,// L +0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F,// M +0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F,// N +0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E,// O +0x00, 0x7F, 0x09, 0x09, 0x09, 0x06,// P +0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q +0x00, 0x7F, 0x09, 0x19, 0x29, 0x46,// R +0x00, 0x46, 0x49, 0x49, 0x49, 0x31,// S +0x00, 0x01, 0x01, 0x7F, 0x01, 0x01,// T +0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F,// U +0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F,// V +0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F,// W +0x00, 0x63, 0x14, 0x08, 0x14, 0x63,// X +0x00, 0x07, 0x08, 0x70, 0x08, 0x07,// Y +0x00, 0x61, 0x51, 0x49, 0x45, 0x43,// Z +0x00, 0x00, 0x7F, 0x41, 0x41, 0x00,// [ +0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55,// 55 +0x00, 0x00, 0x41, 0x41, 0x7F, 0x00,// ] +0x00, 0x04, 0x02, 0x01, 0x02, 0x04,// ^ +0x00, 0x40, 0x40, 0x40, 0x40, 0x40,// _ +0x00, 0x00, 0x01, 0x02, 0x04, 0x00,// ' +0x00, 0x20, 0x54, 0x54, 0x54, 0x78,// a +0x00, 0x7F, 0x48, 0x44, 0x44, 0x38,// b +0x00, 0x38, 0x44, 0x44, 0x44, 0x20,// c +0x00, 0x38, 0x44, 0x44, 0x48, 0x7F,// d +0x00, 0x38, 0x54, 0x54, 0x54, 0x18,// e +0x00, 0x08, 0x7E, 0x09, 0x01, 0x02,// f +0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C,// g +0x00, 0x7F, 0x08, 0x04, 0x04, 0x78,// h +0x00, 0x00, 0x44, 0x7D, 0x40, 0x00,// i +0x00, 0x40, 0x80, 0x84, 0x7D, 0x00,// j +0x00, 0x7F, 0x10, 0x28, 0x44, 0x00,// k +0x00, 0x00, 0x41, 0x7F, 0x40, 0x00,// l +0x00, 0x7C, 0x04, 0x18, 0x04, 0x78,// m +0x00, 0x7C, 0x08, 0x04, 0x04, 0x78,// n +0x00, 0x38, 0x44, 0x44, 0x44, 0x38,// o +0x00, 0xFC, 0x24, 0x24, 0x24, 0x18,// p +0x00, 0x18, 0x24, 0x24, 0x18, 0xFC,// q +0x00, 0x7C, 0x08, 0x04, 0x04, 0x08,// r +0x00, 0x48, 0x54, 0x54, 0x54, 0x20,// s +0x00, 0x04, 0x3F, 0x44, 0x40, 0x20,// t +0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C,// u +0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C,// v +0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C,// w +0x00, 0x44, 0x28, 0x10, 0x28, 0x44,// x +0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,// y +0x00, 0x44, 0x64, 0x54, 0x4C, 0x44,// z +0x14, 0x14, 0x14, 0x14, 0x14, 0x14,// horiz lines +}; +/****************************************8*16ĵ************************************/ +const unsigned char F8X16[]= +{ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0 + 0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1 + 0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2 + 0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3 + 0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4 + 0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5 + 0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6 + 0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7 + 0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8 + 0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9 + 0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10 + 0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14 + 0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15 + 0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16 + 0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17 + 0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18 + 0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19 + 0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20 + 0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21 + 0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22 + 0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23 + 0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24 + 0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25 + 0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26 + 0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27 + 0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28 + 0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29 + 0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30 + 0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31 + 0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32 + 0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33 + 0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34 + 0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35 + 0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36 + 0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37 + 0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38 + 0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39 + 0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40 + 0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41 + 0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42 + 0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43 + 0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44 + 0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45 + 0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46 + 0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47 + 0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48 + 0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49 + 0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50 + 0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51 + 0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52 + 0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53 + 0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54 + 0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55 + 0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56 + 0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57 + 0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58 + 0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59 + 0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60 + 0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61 + 0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63 + 0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65 + 0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66 + 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67 + 0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69 + 0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70 + 0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71 + 0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72 + 0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73 + 0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74 + 0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75 + 0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76 + 0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77 + 0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79 + 0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80 + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81 + 0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82 + 0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83 + 0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84 + 0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85 + 0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86 + 0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87 + 0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88 + 0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89 + 0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90 + 0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91 + 0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92 + 0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93 + 0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94 +}; +char Hzk[][32]={ +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x80,0xA0,0x90,0x8E,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0x88,0x88,0x80,0x80,0x00, +0x20,0x20,0x10,0x08,0x04,0x02,0x01,0xFF,0x01,0x02,0x04,0x08,0x10,0x20,0x20,0x00,}, +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x04,0x04,0x04,0x84,0xE4,0x3C,0x27,0x24,0x24,0x24,0x24,0xE4,0x04,0x04,0x04,0x00, +0x04,0x02,0x01,0x00,0xFF,0x09,0x09,0x09,0x09,0x49,0x89,0x7F,0x00,0x00,0x00,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x00,0xFE,0x22,0xFE,0x00,0xFE,0x22,0xFE,0x00,0xFC,0x16,0x25,0x84,0xFC,0x00,0x00, +0x60,0x1F,0x22,0xBF,0x40,0x3F,0x82,0xFF,0x00,0x13,0x12,0x12,0x52,0x82,0x7E,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x40,0x3C,0x10,0xFF,0x10,0x10,0x20,0x10,0x8F,0x78,0x08,0xF8,0x08,0xF8,0x00,0x00, +0x02,0x06,0x02,0xFF,0x01,0x01,0x04,0x42,0x21,0x18,0x46,0x81,0x40,0x3F,0x00,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x02,0xFE,0x92,0x92,0xFE,0x02,0x00,0x10,0x11,0x16,0xF0,0x14,0x13,0x10,0x00,0x00, +0x10,0x1F,0x08,0x08,0xFF,0x04,0x81,0x41,0x31,0x0D,0x03,0x0D,0x31,0x41,0x81,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x00,0xFE,0x02,0x22,0x42,0x82,0x72,0x02,0x22,0x42,0x82,0x72,0x02,0xFE,0x00,0x00, +0x00,0xFF,0x10,0x08,0x06,0x01,0x0E,0x10,0x08,0x06,0x01,0x4E,0x80,0x7F,0x00,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x20,0x20,0x20,0x20,0x20,0x20,0x20,0xFF,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00, +0x80,0x80,0x40,0x20,0x10,0x0C,0x03,0x00,0x03,0x0C,0x10,0x20,0x40,0x80,0x80,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x40,0x40,0x42,0xCC,0x00,0x10,0x10,0xFF,0x10,0x10,0x10,0xFF,0x10,0x10,0x00,0x00, +0x00,0x00,0x00,0x3F,0x11,0x89,0x61,0x1F,0x01,0x01,0x01,0xFF,0x01,0x01,0x01,0x00,}, + +/*-- : --*/ +/*-- 12; ¶ӦĵΪx=16x16 --*/ +{0x20,0x18,0x08,0xEA,0x2C,0x28,0x28,0x2F,0x28,0x28,0x2C,0xEA,0x08,0x28,0x18,0x00, +0x40,0x40,0x48,0x49,0x49,0x49,0x49,0x7F,0x49,0x49,0x49,0x49,0x48,0x40,0x40,0x00,}, + + +}; + +#endif + + diff --git a/targets/STM32L476RG_NB476/Hardware/Src/hal_iwdg.c b/targets/STM32L476RG_NB476/Hardware/Src/hal_iwdg.c new file mode 100644 index 000000000..4dcdabcfc --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Src/hal_iwdg.c @@ -0,0 +1,61 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "hal_iwdg.h" +#include "stm32l4xx.h" +#include "stm32l4xx_hal_iwdg.h" + +#ifdef HAL_IWDG_MODULE_ENABLED + +IWDG_HandleTypeDef g_iwdg_handle; + +int hal_iwdg_config(uint8_t prvscaler, uint16_t reload) +{ + g_iwdg_handle.Instance = IWDG; + g_iwdg_handle.Init.Prescaler = prvscaler; + g_iwdg_handle.Init.Reload = reload; + + if (HAL_IWDG_Init(&g_iwdg_handle) != HAL_OK) + { + return -1; + } + return 0; +} + +void hal_iwdg_feed(void) +{ + (void)HAL_IWDG_Refresh(&g_iwdg_handle); +} + +#endif /* HAL_IWDG_MODULE_ENABLED */ diff --git a/targets/STM32L476RG_NB476/Hardware/Src/hal_qspi_flash.c b/targets/STM32L476RG_NB476/Hardware/Src/hal_qspi_flash.c new file mode 100644 index 000000000..e06fdb312 --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Src/hal_qspi_flash.c @@ -0,0 +1,426 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "hal_qspi_flash.h" +#include "stm32l4xx.h" + +#ifdef HAL_QSPI_MODULE_ENABLED + +#define QSPI_FLASH_PAGESIZE 256 +#define QSPI_FLASH_SECTOR 4096 +#define QSPI_FLASH_ID 0xEF4017 +#define QSPI_FLASH_TOTAL_SIZE 0x7FFFFF + +#define QSPI_FLASH_WriteEnable 0x06 +#define QSPI_FLASH_WriteDisable 0x04 +#define QSPI_FLASH_ReadStatusReg 0x05 +#define QSPI_FLASH_WriteStatusReg 0x01 +#define QSPI_FLASH_ReadData 0x03 +#define QSPI_FLASH_FastReadData 0x0B +#define QSPI_FLASH_FastReadDual 0x3B +#define QSPI_FLASH_PageProgram 0x02 +#define QSPI_FLASH_BlockErase 0xD8 +#define QSPI_FLASH_SectorErase 0x20 +#define QSPI_FLASH_ChipErase 0xC7 +#define QSPI_FLASH_PowerDown 0xB9 +#define QSPI_FLASH_ReleasePowerDown 0xAB +#define QSPI_FLASH_DeviceID 0xAB +#define QSPI_FLASH_ManufactDeviceID 0x90 +#define QSPI_FLASH_JedecDeviceID 0x9F +#define QSPI_FLASH_WIP_FLAG 0x01 +#define QSPI_FLASH_DUMMY_BYTE 0xFF + +#define CHOOSE_BIT_16 16 +#define CHOOSE_BIT_8 8 + + +#define CHECK_RET_RETURN(ret) \ + do \ + { \ + if ((ret) < 0) \ + { \ + return ret; \ + } \ + } while (0) + +QSPI_HandleTypeDef hqspi; + +/* This function is called by inner-HAL lib */ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(qspiHandle->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + + /* USER CODE END QUADSPI_MspInit 0 */ + /* QUADSPI clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + /**QUADSPI GPIO Configuration + PB0 ------> QUADSPI_BK1_IO1 + PB1 ------> QUADSPI_BK1_IO0 + PB10 ------> QUADSPI_CLK + PB11 ------> QUADSPI_BK1_NCS + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } +} + +/* This function is called by inner-HAL lib */ +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle) +{ + + if(qspiHandle->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PB0 ------> QUADSPI_BK1_IO1 + PB1 ------> QUADSPI_BK1_IO0 + PB10 ------> QUADSPI_CLK + PB11 ------> QUADSPI_BK1_NCS + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } +} + + +/** + * @brief QSPI + * + * @param instruction Ҫ͵ָ + * @param address ͵Ŀĵַ + * @param dummyCycles ָ + * @param instructionMode ָģʽ;QSPI_INSTRUCTION_NONE,QSPI_INSTRUCTION_1_LINE,QSPI_INSTRUCTION_2_LINE,QSPI_INSTRUCTION_4_LINE + * @param addressMode ַģʽ; QSPI_ADDRESS_NONE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_2_LINE,QSPI_ADDRESS_4_LINE + * @param addressSize ַ;QSPI_ADDRESS_8_BITS,QSPI_ADDRESS_16_BITS,QSPI_ADDRESS_24_BITS,QSPI_ADDRESS_32_BITS + * @param dataMode ģʽ; QSPI_DATA_NONE,QSPI_DATA_1_LINE,QSPI_DATA_2_LINE,QSPI_DATA_4_LINE + * + * @return void + */ +uint32_t QSPI_Send_CMD(uint32_t instruction, uint32_t address, uint32_t dummyCycles, uint32_t instructionMode, uint32_t addressMode, uint32_t addressSize, uint32_t dataMode) +{ + QSPI_CommandTypeDef s_command; + + s_command.Instruction = instruction; //ָ + s_command.Address = address; //ַ + s_command.DummyCycles = dummyCycles; //ÿָ + s_command.InstructionMode = instructionMode; //ָģʽ + s_command.AddressMode = addressMode; //ַģʽ + s_command.AddressSize = addressSize; //ַ + s_command.DataMode = dataMode; //ģʽ + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; //ÿζָ + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; //޽ֽ + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; //رDDRģʽ + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + + return HAL_QSPI_Command(&hqspi, &s_command, 5000); +} + +uint8_t QSPI_Receive(const uint8_t * buf, uint32_t datalen) +{ + hqspi.Instance->DLR = datalen - 1; //Configuration data length + if(HAL_QSPI_Receive(&hqspi, (uint8_t * )buf, 5000) == HAL_OK) return 0; //receive data + + else return 1; +} + +uint8_t QSPI_Transmit(const int8_t * buf, uint32_t datalen) +{ + hqspi.Instance->DLR = datalen - 1; //Configuration data length + if(HAL_QSPI_Transmit(&hqspi, (uint8_t * )buf, 5000) == HAL_OK) return 0; //send data + + else return 1; +} + +static void prv_spi_flash_write_enable(void) +{ + QSPI_Send_CMD(QSPI_FLASH_WriteEnable, 0, 0, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_NONE, QSPI_ADDRESS_8_BITS, QSPI_DATA_NONE); +} + +static void prv_spi_flash_wait_write_end(void) +{ + uint8_t status = 0; + + + /* Loop as long as the memory is busy with a write cycle */ + do + { + /* Send a dummy byte to generate the clock needed by the FLASH + and put the value of the status register in status variable */ + QSPI_Send_CMD(QSPI_FLASH_ReadStatusReg, 0, 0, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_NONE, QSPI_ADDRESS_8_BITS, QSPI_DATA_1_LINE); + QSPI_Receive(&status, 1); + + } while ((status & QSPI_FLASH_WIP_FLAG) == SET); /* Write in progress */ + +} + +static int prv_spi_flash_write_page(const uint8_t* buf, uint32_t addr, int32_t len) +{ + int ret = 0; + + if(0 == len) + { + return 0; + } + + prv_spi_flash_write_enable(); //Write enable + + QSPI_Send_CMD(QSPI_FLASH_PageProgram, addr, 0, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_ADDRESS_24_BITS, QSPI_DATA_1_LINE); + QSPI_Transmit((const int8_t *)buf, len); + + prv_spi_flash_wait_write_end(); //Waiting for Writing to End + + return ret; +} + + int prv_spi_flash_erase_sector(uint32_t addr) +{ + //printf("fe:%x\r\n",addr); //flash, + int ret = 0; + prv_spi_flash_write_enable(); //Write enable + prv_spi_flash_wait_write_end(); + + ret=QSPI_Send_CMD(QSPI_FLASH_SectorErase, addr, 0, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_ADDRESS_24_BITS, QSPI_DATA_NONE); + + prv_spi_flash_wait_write_end(); //Waiting for Writing to End + + return ret; +} + +void hal_spi_flash_config(void) +{ + hqspi.Instance = QUADSPI; + hqspi.Init.ClockPrescaler = 0; + hqspi.Init.FifoThreshold = 4; + hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; + hqspi.Init.FlashSize = POSITION_VAL(0x1000000) - 1; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + hqspi.Init.FlashID = QSPI_FLASH_ID_1; + hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + if (HAL_QSPI_Init(&hqspi) != HAL_OK) + { + Error_Handler(); + } + +} + +int hal_spi_flash_erase(uint32_t addr, int32_t len) +{ + uint32_t begin; + uint32_t end; + int i; + + if (len < 0 + || addr > QSPI_FLASH_TOTAL_SIZE + || addr + len > QSPI_FLASH_TOTAL_SIZE) + { + return -1; + } + + begin = addr / QSPI_FLASH_SECTOR * QSPI_FLASH_SECTOR; + end = (addr + len - 1) / QSPI_FLASH_SECTOR * QSPI_FLASH_SECTOR; + + for (i = begin; i <= end; i += QSPI_FLASH_SECTOR) + { + if (prv_spi_flash_erase_sector(i) == -1) + { + return -1; + } + } + + return 0; +} + +int hal_spi_flash_write(const void* buf, int32_t len, uint32_t* location) +{ + const uint8_t* pbuf = (const uint8_t*)buf; + int page_cnt = 0; + int remain_cnt = 0; + int temp = 0; + uint32_t loc_addr; + uint8_t addr = 0; + uint8_t count = 0; + int i; + int ret = 0; + + if (NULL == pbuf + || NULL == location + || len < 0 + || *location > QSPI_FLASH_TOTAL_SIZE + || len + *location > QSPI_FLASH_TOTAL_SIZE) + { + return -1; + } + + loc_addr = *location; + addr = loc_addr % QSPI_FLASH_PAGESIZE; + count = QSPI_FLASH_PAGESIZE - addr; + page_cnt = len / QSPI_FLASH_PAGESIZE; + remain_cnt = len % QSPI_FLASH_PAGESIZE; + + if (addr == 0) /* addr is aligned to SPI_FLASH_PAGESIZE */ + { + if (page_cnt == 0) /* len < SPI_FLASH_PAGESIZE */ + { + ret = prv_spi_flash_write_page(pbuf, loc_addr, len); + CHECK_RET_RETURN(ret); + } + else /* len > SPI_FLASH_PAGESIZE */ + { + for (i = 0; i < page_cnt; ++i) + { + ret = prv_spi_flash_write_page(pbuf + i * QSPI_FLASH_PAGESIZE, loc_addr, QSPI_FLASH_PAGESIZE); + CHECK_RET_RETURN(ret); + loc_addr += QSPI_FLASH_PAGESIZE; + } + + ret = prv_spi_flash_write_page(pbuf + page_cnt * QSPI_FLASH_PAGESIZE, loc_addr, remain_cnt); + CHECK_RET_RETURN(ret); + } + } + else /* addr is not aligned to SPI_FLASH_PAGESIZE */ + { + if (page_cnt == 0) /* len < SPI_FLASH_PAGESIZE */ + { + if (remain_cnt > count) /* (len + loc_addr) > SPI_FLASH_PAGESIZE */ + { + temp = remain_cnt - count; + + ret = prv_spi_flash_write_page(pbuf, loc_addr, count); + CHECK_RET_RETURN(ret); + + ret = prv_spi_flash_write_page(pbuf + count, loc_addr + count, temp); + CHECK_RET_RETURN(ret); + } + else + { + ret = prv_spi_flash_write_page(pbuf, loc_addr, len); + CHECK_RET_RETURN(ret); + } + } + else /* len > SPI_FLASH_PAGESIZE */ + { + len -= count; + page_cnt = len / QSPI_FLASH_PAGESIZE; + remain_cnt = len % QSPI_FLASH_PAGESIZE; + + ret = prv_spi_flash_write_page(pbuf, loc_addr, count); + CHECK_RET_RETURN(ret); + loc_addr += count; + + for (i = 0; i < page_cnt; ++i) + { + ret = prv_spi_flash_write_page(pbuf + count + i * QSPI_FLASH_PAGESIZE, loc_addr, QSPI_FLASH_PAGESIZE); + CHECK_RET_RETURN(ret); + loc_addr += QSPI_FLASH_PAGESIZE; + } + + if (remain_cnt != 0) + { + ret = prv_spi_flash_write_page(pbuf + count + page_cnt * QSPI_FLASH_PAGESIZE, loc_addr, remain_cnt); + CHECK_RET_RETURN(ret); + } + } + } + + *location += len; + return ret; + +} + +int hal_spi_flash_erase_write(const void* buf, int32_t len, uint32_t location) +{ + int ret = 0; + + ret = hal_spi_flash_erase(location, len); + CHECK_RET_RETURN(ret); + ret = hal_spi_flash_write(buf, len, &location); + + return ret; +} + +int hal_spi_flash_read(void* buf, int32_t len, uint32_t location) +{ + int ret = 0; + uint8_t* pbuf = (uint8_t*)buf; + + if (NULL == pbuf + || len < 0 + || location > QSPI_FLASH_TOTAL_SIZE + || len + location > QSPI_FLASH_TOTAL_SIZE) + { + return -1; + } + + QSPI_Send_CMD(QSPI_FLASH_FastReadData, location, 8, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_ADDRESS_24_BITS, QSPI_DATA_1_LINE); + QSPI_Receive(buf, len); + + return ret; + +} + +int hal_spi_flash_get_id(void) +{ + + uint8_t temp[2]; + uint16_t deviceid; + QSPI_Send_CMD(QSPI_FLASH_JedecDeviceID, 0, 0, QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_ADDRESS_24_BITS, QSPI_DATA_1_LINE); + QSPI_Receive(temp, 2); + deviceid = (temp[0] << 8) | temp[1]; + return deviceid; +} + + +#endif /* HAL_QSPI_MODULE_ENABLED */ diff --git a/targets/STM32L476RG_NB476/Hardware/Src/hal_rng.c b/targets/STM32L476RG_NB476/Hardware/Src/hal_rng.c new file mode 100644 index 000000000..8a2ec9cbc --- /dev/null +++ b/targets/STM32L476RG_NB476/Hardware/Src/hal_rng.c @@ -0,0 +1,89 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include +#include "hal_rng.h" +#include "stm32l4xx.h" +#include "stm32l4xx_hal_rng.h" + +#ifdef HAL_RNG_MODULE_ENABLED + +RNG_HandleTypeDef g_rng_handle; + +void hal_rng_config(void) +{ + __HAL_RCC_RNG_CLK_ENABLE(); + g_rng_handle.Instance = RNG; + (void)HAL_RNG_Init(&g_rng_handle); +} + +int hal_rng_generate_number() +{ + uint32_t random_number; + + if (HAL_RNG_GenerateRandomNumber(&g_rng_handle, &random_number) != HAL_OK) + { + return 0U; + } + + return (int)random_number; +} + +int hal_rng_generate_buffer(void* buf, size_t len) +{ + size_t i; + uint32_t random_number; + uint8_t* pbuf; + + if (NULL == buf) + { + return -1; + } + + pbuf = (uint8_t*)buf; + + for (i = 0; i < len; i += sizeof(uint32_t)) + { + if (HAL_RNG_GenerateRandomNumber(&g_rng_handle, &random_number) != HAL_OK) + { + return -1; + } + memcpy(pbuf + i, &random_number, + sizeof(uint32_t) > len - i ? len - i : sizeof(uint32_t)); + } + + return 0; +} + +#endif /* HAL_RNG_MODULE_ENABLED */ diff --git a/targets/STM32L476RG_NB476/Inc/at_hal.h b/targets/STM32L476RG_NB476/Inc/at_hal.h new file mode 100644 index 000000000..7c86ffbe1 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/at_hal.h @@ -0,0 +1,49 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#ifndef __AT_HAL_H__ +#define __AT_HAL_H__ + +#include "at_frame/at_main.h" + +void at_transmit(uint8_t * cmd, int32_t len,int flag); +int32_t at_usart_init(void); +void at_usart_deinit(void); +int read_resp(uint8_t *buf, recv_buff* recv_buf); +void write_at_task_msg(at_msg_type_e type); + + +#endif + + diff --git a/targets/STM32L476RG_NB476/Inc/board.h b/targets/STM32L476RG_NB476/Inc/board.h new file mode 100644 index 000000000..f858933b9 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/board.h @@ -0,0 +1,81 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +// error code +#define OTA_ERRNO_OK 0 +#define OTA_ERRNO_ILEGAL_PARAM -1 +#define OTA_ERRNO_INTEGRITY_CHECK -2 +#define OTA_ERRNO_SPI_FLASH_READ -3 +#define OTA_ERRNO_SPI_FLASH_WRITE -4 +#define OTA_ERRNO_INNER_FLASH_READ -5 +#define OTA_ERRNO_INNER_FLASH_WRITE -6 +#define OTA_ERRNO_ILEGAL_PC -7 +#define OTA_ERRNO_ILEGAL_STACK -8 +#define OTA_ERRNO_INTERNEL -9 + +// SPI flash address +#define OTA_FLAG_ADDR1 0x00000000 +#define OTA_FLAG_ADDR2 0x00004000 +#define MQTT_INFO_ADDR 0x00008000 +#define MQTT_INFO_SIZE 0x00008000 +#define OTA_IMAGE_DOWNLOAD_ADDR (MQTT_INFO_ADDR + MQTT_INFO_SIZE) +#define OTA_IMAGE_DOWNLOAD_SIZE 0x00040000 +#define OTA_IMAGE_BCK_ADDR (OTA_IMAGE_DOWNLOAD_ADDR + OTA_IMAGE_DOWNLOAD_SIZE) +#define OTA_IMAGE_BCK_SIZE 0x00040000 +#define OTA_IMAGE_DIFF_UPGRADE_ADDR (OTA_IMAGE_BCK_ADDR + OTA_IMAGE_BCK_SIZE) +#define OTA_IMAGE_DIFF_UPGRADE_SIZE 0x00040000 + +// Built in flash address +#define OTA_DEFAULT_IMAGE_ADDR 0x08010000 + +int board_jump2app(void); +int board_update_copy(int32_t old_image_len, int32_t new_image_len, uint32_t new_image_addr); +int board_rollback_copy(int32_t image_len); + +#if defined(__cplusplus) +} +#endif + +#endif /* _BOARD_H_*/ + + diff --git a/targets/STM32L476RG_NB476/Inc/common.h b/targets/STM32L476RG_NB476/Inc/common.h new file mode 100644 index 000000000..23862b2ee --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/common.h @@ -0,0 +1,54 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +/**@defgroup atiny_adapter Agenttiny Adapter + * @ingroup agent + */ + +#ifndef COMMON_H +#define COMMON_H +#include +#include +#include "osdepends/atiny_osdep.h" + +#define OK 0 +#define ERR -1 + +#define HAL_OTA_LOG(fmt, ...) \ +(void)printf("[%s:%d][%lu]" fmt "\r\n", __FUNCTION__, __LINE__, (uint32_t) atiny_gettime_ms(), ##__VA_ARGS__) + + +#endif //COMMON_H + + diff --git a/targets/STM32L476RG_NB476/Inc/dwt.h b/targets/STM32L476RG_NB476/Inc/dwt.h new file mode 100644 index 000000000..c07f43e47 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/dwt.h @@ -0,0 +1,54 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#ifndef __DWT_H_ +#define __DWT_H_ +#include "stm32l4xx.h" +#include "los_hwi.h" +#define DWT_CR *(volatile uint32_t *)0xE0001000 + +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004 + +#define DEM_CR *(volatile uint32_t *)0xE000EDFC + +#define DEM_CR_TRCENA (1 << 24) + +#define DWT_CR_CYCCNTENA (1 << 0) + +#define delayms(msec) delayus(msec*1000) + +void dwt_delay_init(uint32_t clk); +void delayus(uint32_t usec); +void delay10ms(__IO uint32_t nTime); +#endif diff --git a/targets/STM32L476RG_NB476/Inc/gpio.h b/targets/STM32L476RG_NB476/Inc/gpio.h new file mode 100644 index 000000000..6a60e56fe --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/gpio.h @@ -0,0 +1,57 @@ +/** + ****************************************************************************** + * File Name : gpio.h + * Description : This file contains all the functions prototypes for + * the gpio + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __gpio_H +#define __gpio_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ pinoutConfig_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/i2c.h b/targets/STM32L476RG_NB476/Inc/i2c.h new file mode 100644 index 000000000..68e67e5c6 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/i2c.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * File Name : I2C.h + * Description : This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __i2c_H +#define __i2c_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ +extern void _Error_Handler(char *, int); +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ i2c_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/main.h b/targets/STM32L476RG_NB476/Inc/main.h new file mode 100644 index 000000000..8c8929b8e --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/main.h @@ -0,0 +1,101 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" +/* Includes LiteOS------------------------------------------------------------------*/ + +#include "los_base.h" +#include "los_config.h" +#include "los_sys.h" +#include "los_typedef.h" +#include "los_event.ph" +#include "los_event.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void _Error_Handler(char *, int); + +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define DHT11_DATA_Pin GPIO_PIN_13 +#define DHT11_DATA_GPIO_Port GPIOC +#define KEY4_Pin GPIO_PIN_0 +#define KEY4_GPIO_Port GPIOC +#define KEY3_Pin GPIO_PIN_1 +#define KEY3_GPIO_Port GPIOC +#define KEY2_Pin GPIO_PIN_2 +#define KEY2_GPIO_Port GPIOC +#define KEY1_Pin GPIO_PIN_3 +#define KEY1_GPIO_Port GPIOC +#define LED_Pin GPIO_PIN_2 +#define LED_GPIO_Port GPIOB +#define NB_RI_Pin GPIO_PIN_15 +#define NB_RI_GPIO_Port GPIOB +#define NB_EN_Pin GPIO_PIN_6 +#define NB_EN_GPIO_Port GPIOC +#define OLED_SCL_Pin GPIO_PIN_6 +#define OLED_SCL_GPIO_Port GPIOB +#define OLED_SDA_Pin GPIO_PIN_7 +#define OLED_SDA_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/rtc.h b/targets/STM32L476RG_NB476/Inc/rtc.h new file mode 100644 index 000000000..89675029b --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/rtc.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * File Name : RTC.h + * Description : This file provides code for the configuration + * of the RTC instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __rtc_H +#define __rtc_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern RTC_HandleTypeDef hrtc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_RTC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ rtc_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/stm32l476xx.h b/targets/STM32L476RG_NB476/Inc/stm32l476xx.h new file mode 100644 index 000000000..923447b8c --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/stm32l476xx.h @@ -0,0 +1,18481 @@ +/** + ****************************************************************************** + * @file stm32l476xx.h + * @author MCD Application Team + * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l476xx + * @{ + */ + +#ifndef __STM32L476xx_H +#define __STM32L476xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + LCD_IRQn = 78, /*!< LCD global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ +} FLASH_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ + __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) + +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) + + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) + +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) + + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN ((CAN_TypeDef *) CAN1_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC1_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +/* Aliases to keep compatibility after DFSDM renaming */ +#define DFSDM_Channel0 DFSDM1_Channel0 +#define DFSDM_Channel1 DFSDM1_Channel1 +#define DFSDM_Channel2 DFSDM1_Channel2 +#define DFSDM_Channel3 DFSDM1_Channel3 +#define DFSDM_Channel4 DFSDM1_Channel4 +#define DFSDM_Channel5 DFSDM1_Channel5 +#define DFSDM_Channel6 DFSDM1_Channel6 +#define DFSDM_Channel7 DFSDM1_Channel7 +#define DFSDM_Filter0 DFSDM1_Filter0 +#define DFSDM_Filter1 DFSDM1_Filter1 +#define DFSDM_Filter2 DFSDM1_Filter2 +#define DFSDM_Filter3 DFSDM1_Filter3 +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ +#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ +#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx + * @{ + */ + +#ifndef __STM32L4xx_H +#define __STM32L4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L4) +#define STM32L4 +#endif /* STM32L4 */ + +/* Uncomment the line below according to the target STM32L4 device used in your + application + */ + +#if !defined (STM32L412xx) && !defined (STM32L422xx) && \ + !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ + !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ + !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ + !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ + !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) + /* #define STM32L412xx */ /*!< STM32L412xx Devices */ + /* #define STM32L422xx */ /*!< STM32L422xx Devices */ + /* #define STM32L431xx */ /*!< STM32L431xx Devices */ + /* #define STM32L432xx */ /*!< STM32L432xx Devices */ + /* #define STM32L433xx */ /*!< STM32L433xx Devices */ + /* #define STM32L442xx */ /*!< STM32L442xx Devices */ + /* #define STM32L443xx */ /*!< STM32L443xx Devices */ + /* #define STM32L451xx */ /*!< STM32L451xx Devices */ + /* #define STM32L452xx */ /*!< STM32L452xx Devices */ + /* #define STM32L462xx */ /*!< STM32L462xx Devices */ + /* #define STM32L471xx */ /*!< STM32L471xx Devices */ + /* #define STM32L475xx */ /*!< STM32L475xx Devices */ + /* #define STM32L476xx */ /*!< STM32L476xx Devices */ + /* #define STM32L485xx */ /*!< STM32L485xx Devices */ + /* #define STM32L486xx */ /*!< STM32L486xx Devices */ + /* #define STM32L496xx */ /*!< STM32L496xx Devices */ + /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ + /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ + /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ + /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ + /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ + /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ + /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L4_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L412xx) + #include "stm32l412xx.h" +#elif defined(STM32L422xx) + #include "stm32l422xx.h" +#elif defined(STM32L431xx) + #include "stm32l431xx.h" +#elif defined(STM32L432xx) + #include "stm32l432xx.h" +#elif defined(STM32L433xx) + #include "stm32l433xx.h" +#elif defined(STM32L442xx) + #include "stm32l442xx.h" +#elif defined(STM32L443xx) + #include "stm32l443xx.h" +#elif defined(STM32L451xx) + #include "stm32l451xx.h" +#elif defined(STM32L452xx) + #include "stm32l452xx.h" +#elif defined(STM32L462xx) + #include "stm32l462xx.h" +#elif defined(STM32L471xx) + #include "stm32l471xx.h" +#elif defined(STM32L475xx) + #include "stm32l475xx.h" +#elif defined(STM32L476xx) + #include "stm32l476xx.h" +#elif defined(STM32L485xx) + #include "stm32l485xx.h" +#elif defined(STM32L486xx) + #include "stm32l486xx.h" +#elif defined(STM32L496xx) + #include "stm32l496xx.h" +#elif defined(STM32L4A6xx) + #include "stm32l4a6xx.h" +#elif defined(STM32L4R5xx) + #include "stm32l4r5xx.h" +#elif defined(STM32L4R7xx) + #include "stm32l4r7xx.h" +#elif defined(STM32L4R9xx) + #include "stm32l4r9xx.h" +#elif defined(STM32L4S5xx) + #include "stm32l4s5xx.h" +#elif defined(STM32L4S7xx) + #include "stm32l4s7xx.h" +#elif defined(STM32L4S9xx) + #include "stm32l4s9xx.h" +#else + #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/stm32l4xx_hal_conf.h b/targets/STM32L476RG_NB476/Inc/stm32l4xx_hal_conf.h new file mode 100644 index 000000000..a62efea54 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/stm32l4xx_hal_conf.h @@ -0,0 +1,440 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_HAL_CONF_H +#define __STM32L4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DFSDM_MODULE_ENABLED */ +/*#define HAL_DSI_MODULE_ENABLED */ +/*#define HAL_FIREWALL_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_OSPI_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_SWPMI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +//#define HAL_EXTI_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @brief External clock source for SAI2 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l4xx_hal_rcc.h" + #include "stm32l4xx_hal_rcc_ex.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l4xx_hal_dma.h" + #include "stm32l4xx_hal_dma_ex.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32l4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32l4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32l4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32l4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l4xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32l4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32l4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32l4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l4xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32l4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32l4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32l4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32l4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32l4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32l4xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32l4xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32l4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(char *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/stm32l4xx_it.h b/targets/STM32L476RG_NB476/Inc/stm32l4xx_it.h new file mode 100644 index 000000000..62c17d102 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/stm32l4xx_it.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_IT_H +#define __STM32L4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void LPUART1_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/sys.h b/targets/STM32L476RG_NB476/Inc/sys.h new file mode 100644 index 000000000..0f51f9f68 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/sys.h @@ -0,0 +1,56 @@ +/** + ****************************************************************************** + * File Name : SYS.h + * Description : This file provides code for the configuration + * of the SYS instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __sys_H +#define __sys_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SYS_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ sys_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/sys_init.h b/targets/STM32L476RG_NB476/Inc/sys_init.h new file mode 100644 index 000000000..c1ead497b --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/sys_init.h @@ -0,0 +1,83 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SYS_H_ +#define __SYS_H_ + +/* Includes LiteOS------------------------------------------------------------------*/ + +#include "los_base.h" +#include "los_config.h" +#include "los_sys.h" +#include "los_typedef.h" +#include "los_task.ph" +#include "los_hwi.h" +#include "los_sem.h" +#include "los_event.h" +#include "los_memory.h" +#include "los_queue.ph" + +#include "stdlib.h" +#include "string.h" +#include + +#include "stm32l4xx_hal.h" +#include "stm32l4xx_it.h" +#include "hal_rng.h" +#include "dwt.h" +#include "usart.h" +#include "gpio.h" +#include "i2c.h" + + +#ifdef WITH_DTLS +#include "mbedtls/net.h" +#include "mbedtls/ssl.h" +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +uint32_t HAL_GetTick(void); +void _Error_Handler(char *, int); +void SystemClock_Config(void); +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H_ */ + diff --git a/targets/STM32L476RG_NB476/Inc/system_stm32l4xx.h b/targets/STM32L476RG_NB476/Inc/system_stm32l4xx.h new file mode 100644 index 000000000..9eceb0008 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/system_stm32l4xx.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L4XX_H +#define __SYSTEM_STM32L4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L4xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Inc/usart.h b/targets/STM32L476RG_NB476/Inc/usart.h new file mode 100644 index 000000000..46ea804b8 --- /dev/null +++ b/targets/STM32L476RG_NB476/Inc/usart.h @@ -0,0 +1,62 @@ +/** + ****************************************************************************** + * File Name : USART.h + * Description : This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __usart_H +#define __usart_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef hlpuart1; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart3; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_LPUART1_UART_Init(void); +void MX_USART1_UART_Init(void); +void MX_USART3_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ usart_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Kconfig b/targets/STM32L476RG_NB476/Kconfig new file mode 100644 index 000000000..ac25e9f1d --- /dev/null +++ b/targets/STM32L476RG_NB476/Kconfig @@ -0,0 +1,58 @@ +# +# Copyright (c) [2020] Huawei Technologies Co.,Ltd.All rights reserved. +# +# LiteOS NOVA is licensed under the Mulan PSL v1. +# You can use this software according to the terms and conditions of the Mulan PSL v1. +# You may obtain a copy of Mulan PSL v1 at: +# +# http://license.coscl.org.cn/MulanPSL +# +# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +# FIT FOR A PARTICULAR PURPOSE. +# See the Mulan PSL v1 for more details. +# + +menu "LiteOS for STM32L476_NB476 Project configuration For IoT Link" + +comment "This is a demo project and hope you enjoy it" + +config ARCH_CPU_TYPE + string "Select the cpu arch:armv7-m armv6-m riscv32 x86-64" + default "armv7-m" + +config UARTAT_RCVMAX + int "Config the at uart receive buffer size" + default 2048 + +config UARTAT_BAUDRATE + int "Config the at uart baud rate" + default 9600 + +config UARTAT_DEVNAME + string "Config the at uart device name" + default "atdev" + +rsource "../../iot_link/Kconfig" + + +choice Demo + optional + prompt "User Defined Demo" + config Demo_None + bool "none" + config Demo_Use_Coap + bool "Report temperature" + select OC_COAP + select SHELL_ENABLE + select AT_ENABLE + select BOUDICA120 +endchoice + +config USER_DEMO + string + default "use_coap_demo" if Demo_Use_Coap + default "none" + + +endmenu diff --git a/targets/STM32L476RG_NB476/Lib/hwpatch.lib b/targets/STM32L476RG_NB476/Lib/hwpatch.lib new file mode 100644 index 0000000000000000000000000000000000000000..1eee9bd446538ebede90232d5f4e7aaddc10904c GIT binary patch literal 118352 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Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ +/** + * DATE AUTHOR INSTRUCTION + * 2019-07-27 14:49 zhangqianfu The first version + * + */ +#ifndef LITEOS_LAB_TARGETS_STM32L431_BEARPI_OS_CONFIG_IOT_LINK_CONFIG_H_ +#define LITEOS_LAB_TARGETS_STM32L431_BEARPI_OS_CONFIG_IOT_LINK_CONFIG_H_ + +#define CONFIG_AT_DEVICENAME "atdev_BC95" +#define CONFIG_AT_BAUDRATE 9600 + +#endif /* LITEOS_LAB_TARGETS_STM32L431_BEARPI_OS_CONFIG_IOT_LINK_CONFIG_H_ */ diff --git a/targets/STM32L476RG_NB476/OS_CONFIG/los_builddef.h b/targets/STM32L476RG_NB476/OS_CONFIG/los_builddef.h new file mode 100644 index 000000000..b208f6e07 --- /dev/null +++ b/targets/STM32L476RG_NB476/OS_CONFIG/los_builddef.h @@ -0,0 +1,239 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * HuaweiLite OS may be subject to applicable export control laws and regulations, which might + * include those applicable to HuaweiLite OS of U.S. and the country in which you are located. + * Import, export and usage of HuaweiLite OS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +/**@defgroup los_builddef + * @ingroup kernel + */ + +#ifndef _LOS_BUILDEF_H +#define _LOS_BUILDEF_H +#include "los_compiler.h" +#include "string.h" +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cpluscplus */ +#endif /* __cpluscplus */ + +/** + * @ingroup los_builddef + * Define inline keyword + */ + +/** + * @ingroup los_builddef + * Little endian + */ +#define OS_LITTLE_ENDIAN 0x1234 + +/** + * @ingroup los_builddef + * Big endian + */ +#define OS_BIG_ENDIAN 0x4321 + +/** + * @ingroup los_builddef + * Byte order + */ +#ifndef OS_BYTE_ORDER +#define OS_BYTE_ORDER OS_LITTLE_ENDIAN +#endif + +/* Define OS code data sections */ +/*The indicator function is inline*/ + +/** + * @ingroup los_builddef + * Allow inline sections + */ +#ifndef LITE_OS_SEC_ALW_INLINE +#define LITE_OS_SEC_ALW_INLINE //__attribute__((always_inline)) +#endif + +/** + * @ingroup los_builddef + * Vector table section + */ +#ifndef LITE_OS_SEC_VEC +#define LITE_OS_SEC_VEC __attribute__ ((section(".data.vector"))) +#endif + +/** + * @ingroup los_builddef + * .Text section (Code section) + */ +#ifndef LITE_OS_SEC_TEXT +#define LITE_OS_SEC_TEXT //__attribute__((section(".sram.text"))) +#endif + +/** + * @ingroup los_builddef + * .Text.ddr section + */ +#ifndef LITE_OS_SEC_TEXT_MINOR +#define LITE_OS_SEC_TEXT_MINOR // __attribute__((section(".dyn.text"))) +#endif + +/** + * @ingroup los_builddef + * .Text.init section + */ +#ifndef LITE_OS_SEC_TEXT_INIT +#define LITE_OS_SEC_TEXT_INIT //__attribute__((section(".dyn.text"))) +#endif + +/** + * @ingroup los_builddef + * Redirect .Text section (Code section) + */ +#ifndef LITE_OS_SEC_TEXT_REDIRECT +#define LITE_OS_SEC_TEXT_REDIRECT LITE_OS_SEC_TEXT +#endif + +/** + * @ingroup los_builddef + * Redirect .Text.ddr section + */ +#ifndef LITE_OS_SEC_TEXT_MINOR_REDIRECT +#define LITE_OS_SEC_TEXT_MINOR_REDIRECT LITE_OS_SEC_TEXT_MINOR +#endif + +/** + * @ingroup los_builddef + * Redirect .Text.init section + */ +#ifndef LITE_OS_SEC_TEXT_INIT_REDIRECT +#define LITE_OS_SEC_TEXT_INIT_REDIRECT LITE_OS_SEC_TEXT_INIT +#endif + +/** + * @ingroup los_builddef + * .Data section + */ +#ifndef LITE_OS_SEC_DATA +#define LITE_OS_SEC_DATA //__attribute__((section(".dyn.data"))) +#endif + +/** + * @ingroup los_builddef + * .Data.init section + */ +#ifndef LITE_OS_SEC_DATA_INIT +#define LITE_OS_SEC_DATA_INIT //__attribute__((section(".dyn.data"))) +#endif + +/** + * @ingroup los_builddef + * Not initialized variable section + */ +#ifndef LITE_OS_SEC_BSS +#define LITE_OS_SEC_BSS //__attribute__((section(".sym.bss"))) +#endif + +/** + * @ingroup los_builddef + * .bss.ddr section + */ +#ifndef LITE_OS_SEC_BSS_MINOR +#define LITE_OS_SEC_BSS_MINOR +#endif + +/** + * @ingroup los_builddef + * .bss.init sections + */ +#ifndef LITE_OS_SEC_BSS_INIT +#define LITE_OS_SEC_BSS_INIT +#endif + +#ifndef LITE_OS_SEC_TEXT_DATA +#define LITE_OS_SEC_TEXT_DATA //__attribute__((section(".dyn.data"))) +#define LITE_OS_SEC_TEXT_BSS //__attribute__((section(".dyn.bss"))) +#define LITE_OS_SEC_TEXT_RODATA //__attribute__((section(".dyn.rodata"))) +#endif + +#ifndef LITE_OS_SEC_SYMDATA +#define LITE_OS_SEC_SYMDATA //__attribute__((section(".sym.data"))) +#endif + +#ifndef LITE_OS_SEC_SYMBSS +#define LITE_OS_SEC_SYMBSS //__attribute__((section(".sym.bss"))) +#endif + + +#ifndef LITE_OS_SEC_KEEP_DATA_DDR +#define LITE_OS_SEC_KEEP_DATA_DDR //__attribute__((section(".keep.data.ddr"))) +#endif + +#ifndef LITE_OS_SEC_KEEP_TEXT_DDR +#define LITE_OS_SEC_KEEP_TEXT_DDR //__attribute__((section(".keep.text.ddr"))) +#endif + +#ifndef LITE_OS_SEC_KEEP_DATA_SRAM +#define LITE_OS_SEC_KEEP_DATA_SRAM //__attribute__((section(".keep.data.sram"))) +#endif + +#ifndef LITE_OS_SEC_KEEP_TEXT_SRAM +#define LITE_OS_SEC_KEEP_TEXT_SRAM //__attribute__((section(".keep.text.sram"))) +#endif + +#ifndef LITE_OS_SEC_BSS_MINOR +#define LITE_OS_SEC_BSS_MINOR +#endif + +/** + * @ingroup los_builddef + * .text.libsec section + */ +#ifndef LIB_SECURE_SEC_TEXT +#define LIB_SECURE_SEC_TEXT +#endif + +/** + * @ingroup los_builddef + * .text.libc section + */ +#ifndef LIBC_SEC_TEXT +#define LIBC_SEC_TEXT +#endif + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cpluscplus */ +#endif /* __cpluscplus */ + + +#endif /* _LOS_BUILDEF_H */ diff --git a/targets/STM32L476RG_NB476/OS_CONFIG/los_printf.h b/targets/STM32L476RG_NB476/OS_CONFIG/los_printf.h new file mode 100644 index 000000000..0a7a71802 --- /dev/null +++ b/targets/STM32L476RG_NB476/OS_CONFIG/los_printf.h @@ -0,0 +1,115 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +/**@defgroup los_printf Printf + * @ingroup kernel + */ + +#ifndef _LOS_PRINTF_H +#define _LOS_PRINTF_H +//#ifdef LOSCFG_LIB_LIBC +#include "stdarg.h" +//#endif +#ifdef LOSCFG_LIB_LIBCMINI +#include "libcmini.h" +#endif +#include "los_typedef.h" +#include "los_config.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define LOS_EMG_LEVEL 0 + +#define LOS_COMMOM_LEVEL (LOS_EMG_LEVEL + 1) + +#define LOS_ERR_LEVEL (LOS_COMMOM_LEVEL + 1) + +#define LOS_WARN_LEVEL (LOS_ERR_LEVEL + 1) + +#define LOS_INFO_LEVEL (LOS_WARN_LEVEL + 1) + +#define LOS_DEBUG_LEVEL (LOS_INFO_LEVEL + 1) + +#define PRINT_LEVEL LOS_ERR_LEVEL + +#if PRINT_LEVEL < LOS_DEBUG_LEVEL +#define PRINT_DEBUG(fmt, args...) +#else +#define PRINT_DEBUG(fmt, args...) do{(printf("[DEBUG] "), printf(fmt, ##args));}while(0) +#endif + +#if PRINT_LEVEL < LOS_INFO_LEVEL +#define PRINT_INFO(fmt, args...) +#else +#define PRINT_INFO(fmt, args...) do{(printf("[INFO] "), printf(fmt, ##args));}while(0) +#endif + +#if PRINT_LEVEL < LOS_WARN_LEVEL +#define PRINT_WARN(fmt, args...) +#else +#define PRINT_WARN(fmt, args...) do{(printf("[WARN] "), printf(fmt, ##args));}while(0) +#endif + +#if PRINT_LEVEL < LOS_ERR_LEVEL +#define PRINT_ERR(fmt, args...) +#else +#define PRINT_ERR(fmt, args...) do{(printf("[ERR] "), printf(fmt, ##args));}while(0) +#endif + +#if PRINT_LEVEL < LOS_COMMOM_LEVEL +#define PRINTK(fmt, args...) +#else +#define PRINTK(fmt, args...) printf(fmt, ##args) +#endif + +#if PRINT_LEVEL < LOS_EMG_LEVEL +#define PRINT_EMG(fmt, args...) +#else +#define PRINT_EMG(fmt, args...) do{(printf("[EMG] "), printf(fmt, ##args));}while(0) +#endif + +#define PRINT_RELEASE(fmt, args...) printf(fmt, ##args) + + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#endif /* _LOS_PRINTF_H */ diff --git a/targets/STM32L476RG_NB476/OS_CONFIG/target_config.h b/targets/STM32L476RG_NB476/OS_CONFIG/target_config.h new file mode 100644 index 000000000..65cb59be4 --- /dev/null +++ b/targets/STM32L476RG_NB476/OS_CONFIG/target_config.h @@ -0,0 +1,399 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +/**@defgroup los_config System configuration items + * @ingroup kernel + */ + +#ifndef _TARGET_CONFIG_H +#define _TARGET_CONFIG_H + +#include "los_typedef.h" +#include "stm32l4xx.h" + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif /* __cplusplus */ +#endif /* __cplusplus */ + +#define LOSCFG_CORTEX_M4 + +/*============================================================================= + System clock module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * System clock (unit: HZ) + */ +#define OS_SYS_CLOCK (SystemCoreClock) + +/** + * @ingroup los_config + * Number of Ticks in one second + */ +#define LOSCFG_BASE_CORE_TICK_PER_SECOND (1000UL) + +/** + * @ingroup los_config + * External configuration item for timer tailoring + */ +#define LOSCFG_BASE_CORE_TICK_HW_TIME NO + +/** + * @ingroup los_config + * Configuration liteos kernel tickless + */ +#define LOSCFG_KERNEL_TICKLESS NO + +/*============================================================================= + Hardware interrupt module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for hardware interrupt tailoring + */ +#define LOSCFG_PLATFORM_HWI YES + +/** + * @ingroup los_config + * Maximum number of used hardware interrupts, including Tick timer interrupts. + */ +#define LOSCFG_PLATFORM_HWI_LIMIT 96 + + +/*============================================================================= + Task module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Default task priority + */ +#define LOSCFG_BASE_CORE_TSK_DEFAULT_PRIO 10 + +/** + * @ingroup los_config + * Maximum supported number of tasks except the idle task rather than the number of usable tasks + */ +#define LOSCFG_BASE_CORE_TSK_LIMIT 15 // max num task + +/** + * @ingroup los_config + * Size of the idle task stack + */ +#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE (0x500U) // IDLE task stack + +/** + * @ingroup los_config + * Default task stack size + */ +#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE (0x2D0U) // default stack + +/** + * @ingroup los_config + * Minimum stack size. + */ +#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE (0x130U) + +/** + * @ingroup los_config + * Configuration item for task Robin tailoring + */ +#define LOSCFG_BASE_CORE_TIMESLICE YES + +/** + * @ingroup los_config + * Longest execution time of tasks with the same priorities + */ +#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT 10 + +/** + * @ingroup los_config + * Configuration item for task (stack) monitoring module tailoring + */ +#define LOSCFG_BASE_CORE_TSK_MONITOR YES + +/** + * @ingroup los_config + * Configuration item for task perf task filter hook + */ +#define LOSCFG_BASE_CORE_EXC_TSK_SWITCH YES + +/** + * @ingroup los_config + * Configuration item for performance moniter unit + */ +#define OS_INCLUDE_PERF YES + +/** + * @ingroup los_config + * Define a usable task priority.Highest task priority. + */ +#define LOS_TASK_PRIORITY_HIGHEST 0 + +/** + * @ingroup los_config + * Define a usable task priority.Lowest task priority. + */ +#define LOS_TASK_PRIORITY_LOWEST 31 + + +/*============================================================================= + Semaphore module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for semaphore module tailoring + */ +#define LOSCFG_BASE_IPC_SEM YES + +/** + * @ingroup los_config + * Maximum supported number of semaphores + */ +#define LOSCFG_BASE_IPC_SEM_LIMIT 20 // the max sem-numb + + +/*============================================================================= + Mutex module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for mutex module tailoring + */ +#define LOSCFG_BASE_IPC_MUX YES + +/** + * @ingroup los_config + * Maximum supported number of mutexes + */ +#define LOSCFG_BASE_IPC_MUX_LIMIT 20 // the max mutex-num + + +/*============================================================================= + Queue module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for queue module tailoring + */ +#define LOSCFG_BASE_IPC_QUEUE YES + +/** + * @ingroup los_config + * Maximum supported number of queues rather than the number of usable queues + */ +#define LOSCFG_BASE_IPC_QUEUE_LIMIT 10 //the max queue-numb + + +/*============================================================================= + Software timer module configuration +=============================================================================*/ + +#if (LOSCFG_BASE_IPC_QUEUE == YES) +/** + * @ingroup los_config + * Configuration item for software timer module tailoring + */ +#define LOSCFG_BASE_CORE_SWTMR YES + +#define LOSCFG_BASE_CORE_TSK_SWTMR_STACK_SIZE LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE + +#define LOSCFG_BASE_CORE_SWTMR_TASK YES + +#define LOSCFG_BASE_CORE_SWTMR_ALIGN YES +#if(LOSCFG_BASE_CORE_SWTMR == NO && LOSCFG_BASE_CORE_SWTMR_ALIGN == YES) + #error "swtmr align first need support swmtr, should make LOSCFG_BASE_CORE_SWTMR = YES" +#endif + +/** + * @ingroup los_config + * Maximum supported number of software timers rather than the number of usable software timers + */ +#define LOSCFG_BASE_CORE_SWTMR_LIMIT 16 // the max SWTMR numb + +/** + * @ingroup los_config + * Max number of software timers ID + */ +#define OS_SWTMR_MAX_TIMERID ((65535/LOSCFG_BASE_CORE_SWTMR_LIMIT) * LOSCFG_BASE_CORE_SWTMR_LIMIT) + +/** + * @ingroup los_config + * Maximum size of a software timer queue + */ +#define OS_SWTMR_HANDLE_QUEUE_SIZE (LOSCFG_BASE_CORE_SWTMR_LIMIT + 0) + +/** + * @ingroup los_config + * Minimum divisor of software timer multiple alignment + */ +#define LOS_COMMON_DIVISOR 10 +#endif + + +/*============================================================================= + Memory module configuration +=============================================================================*/ + +#define LOSCFG_HEAP_IMPROVED YES +#define LOSCFG_MEM_STATISTICS YES +#define LOSCFG_CONFIG_CM_TLSF + +/** + * @ingroup los_config + * Configuration module tailoring of mem node integrity checking + */ +#define LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK YES + +/** + * @ingroup los_config + * Configuration module tailoring of mem node size checking + */ +#define LOSCFG_BASE_MEM_NODE_SIZE_CHECK YES + +#define LOSCFG_MEMORY_BESTFIT YES + +/** + * @ingroup los_config + * Configuration module tailoring of more mempry pool checking + */ +#define LOSCFG_MEM_MUL_POOL YES + +/** + * @ingroup los_config + * Number of memory checking blocks + */ +#define OS_SYS_MEM_NUM 20 + +/** + * @ingroup los_config + * Configuration module tailoring of slab memory + */ +#define LOSCFG_KERNEL_MEM_SLAB YES + + +/*============================================================================= + fw Interface configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for the monitoring of task communication + */ +#define LOSCFG_COMPAT_CMSIS_FW YES + + +/*============================================================================= + others +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration system wake-up info to open + */ +#define OS_SR_WAKEUP_INFO YES + +/** + * @ingroup los_config + * Configuration CMSIS_OS_VER + */ +#define CMSIS_OS_VER 2 + + +/*============================================================================= + Exception module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for exception tailoring + */ +#define LOSCFG_PLATFORM_EXC NO + + +/*============================================================================= + Runstop module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for runstop module tailoring + */ +#define LOSCFG_KERNEL_RUNSTOP NO + + +/*============================================================================= + track configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for track + */ +#define LOSCFG_BASE_MISC_TRACK NO + +/** + * @ingroup los_config + * Max count of track items + */ +#define LOSCFG_BASE_MISC_TRACK_MAX_COUNT 1024 + +/*============================================================================= + VFS module configuration +=============================================================================*/ + +/** + * @ingroup los_config + * Configuration item for enabling LiteOS VFS + */ +#ifndef LOSCFG_ENABLE_VFS +#define LOSCFG_ENABLE_VFS YES +#endif + +#ifdef __cplusplus +#if __cplusplus +} +#endif /* __cplusplus */ +#endif /* __cplusplus */ + + +#endif /* _TARGET_CONFIG_H */ diff --git a/targets/STM32L476RG_NB476/Src/LWM2M_Task.c b/targets/STM32L476RG_NB476/Src/LWM2M_Task.c new file mode 100644 index 000000000..f87758550 --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/LWM2M_Task.c @@ -0,0 +1,93 @@ +#include +#include +#include + +#include "los_typedef.h" +#include "los_task.h" +#include +#include +#include + +/* LWM2M服务器相关配置 */ +#define cn_endpoint_id "coap_001" +#define cn_app_server "119.3.250.80" +#define cn_app_port "5683" + +//if your command is very fast,please use a queue here--TODO +#define cn_app_rcv_buf_len 128 +static int8_t s_rcv_buffer[cn_app_rcv_buf_len]; +static int s_rcv_datalen; +static osal_semp_t s_rcv_sync; + + + +//use this function to push all the message to the buffer +static int app_msg_deal(void *msg, int len) +{ + int ret = -1; + + if(len <= cn_app_rcv_buf_len) + { + memcpy(s_rcv_buffer,msg,len); + s_rcv_datalen = len; + + osal_semp_post(s_rcv_sync); + + ret = 0; + + } + return ret; +} + + +int task2(void *args) +{ + int* handle = NULL; + oc_config_param_t oc_param; + char Temp[2] = {00, 22}; + + memset(&oc_param,0,sizeof(oc_param)); + + oc_param.app_server.address = cn_app_server; + oc_param.app_server.port = cn_app_port; + oc_param.app_server.ep_id = cn_endpoint_id; + oc_param.boot_mode = en_oc_boot_strap_mode_factory; + oc_param.rcv_func = app_msg_deal; + + handle = oc_coap_config(&oc_param); + if (NULL == handle) + { + return NULL; + } + else + { + printf("start send message to SDP server!\r\n"); + } + while(1) + { + oc_coap_report(handle, Temp, 2); + osal_task_sleep(60*1000); + + } +} + +int Creat_task2() +{ + int ret = -1; + UINT32 uwRet = LOS_OK; + UINT32 handle; + TSK_INIT_PARAM_S task2_init_param; + + memset (&task2_init_param, 0, sizeof (TSK_INIT_PARAM_S)); + task2_init_param.uwArg = (unsigned int)NULL; + task2_init_param.usTaskPrio = 2; + task2_init_param.pcName =(char *) "task2"; + task2_init_param.pfnTaskEntry = (TSK_ENTRY_FUNC)task2; + task2_init_param.uwStackSize = 0x1000; + uwRet = LOS_TaskCreate(&handle, &task2_init_param); + if(LOS_OK == uwRet){ + ret = 0; + } + printf("Task2 init success!!\r\n"); + return ret; +} diff --git a/targets/STM32L476RG_NB476/Src/dwt.c b/targets/STM32L476RG_NB476/Src/dwt.c new file mode 100644 index 000000000..cafff589a --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/dwt.c @@ -0,0 +1,72 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "dwt.h" + +static uint32_t cpuclkfeq; + +void dwt_delay_init(uint32_t clk) +{ + cpuclkfeq = clk; + DEM_CR |= DEM_CR_TRCENA; + //DWT_CYCCNT = 0u; + DWT_CR |= DWT_CR_CYCCNTENA; +} + +void delayus(uint32_t usec) + +{ + uint32_t startts, endts, ts; + UINT32 uwIntSave; + startts = DWT_CYCCNT; + + ts = usec * (cpuclkfeq / (1000 * 1000)); + endts = startts + ts; + uwIntSave = LOS_IntLock(); + if(endts > startts) + { + while(DWT_CYCCNT < endts); + } + else + { + while(DWT_CYCCNT > endts); + while(DWT_CYCCNT < endts); + } + (VOID)LOS_IntRestore(uwIntSave); +} + +void delay10ms(__IO uint32_t nTime) +{ + delayus(1000 * nTime); +} diff --git a/targets/STM32L476RG_NB476/Src/flash_adaptor.c b/targets/STM32L476RG_NB476/Src/flash_adaptor.c new file mode 100644 index 000000000..90a0a4d0c --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/flash_adaptor.c @@ -0,0 +1,122 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "flash_adaptor.h" +#include "hal_spi_flash.h" +#include +#include +#include +#include +#include "common.h" + +#define FLASH_BLOCK_SIZE 0x1000 +#define FLASH_BLOCK_MASK 0xfff + + +int flash_adaptor_write(uint32_t offset, const uint8_t *buffer, uint32_t len) +{ + int ret = ERR; + uint8_t *block_buff; + + if((NULL == buffer) || (0 == len) || (len > FLASH_BLOCK_SIZE) + || ((offset & FLASH_BLOCK_MASK))) + { + HAL_OTA_LOG("invalid param len %ld, offset %ld", len, offset); + return ERR; + } + + if (len == FLASH_BLOCK_SIZE) + { + ret = hal_spi_flash_erase_write(buffer, FLASH_BLOCK_SIZE, offset); + if(ret != OK) + { + HAL_OTA_LOG("hal_ota_write_flash fail offset %lu, len %u", offset, FLASH_BLOCK_SIZE); + } + return ret; + } + + block_buff = osal_malloc(FLASH_BLOCK_SIZE); + if(NULL == block_buff) + { + HAL_OTA_LOG("atiny_malloc fail"); + return ERR; + } + + ret = hal_spi_flash_read(block_buff + len, FLASH_BLOCK_SIZE - len, offset + len); + if(ret != OK) + { + HAL_OTA_LOG("hal_spi_flash_read fail offset %lu, len %lu", offset + len, FLASH_BLOCK_SIZE - len); + goto EXIT; + } + (void)memcpy(block_buff, buffer, len); + ret = hal_spi_flash_erase_write(block_buff, FLASH_BLOCK_SIZE, offset); + if(ret != OK) + { + HAL_OTA_LOG("hal_ota_write_flash fail offset %lu, len %u", offset, FLASH_BLOCK_SIZE); + } +EXIT: + osal_free(block_buff); + return ret; +} + + + +void flash_adaptor_init(void) +{ + hal_spi_flash_config(); +} + +int flash_adaptor_write_mqtt_info(const void *buffer, uint32_t len) +{ + if(len > MQTT_INFO_SIZE) + { + HAL_OTA_LOG("err offset len %lu", len); + return ERR; + } + + return flash_adaptor_write(MQTT_INFO_ADDR, (const uint8_t *)buffer, len); +} + +int flash_adaptor_read_mqtt_info(void *buffer, uint32_t len) +{ + if(len > MQTT_INFO_SIZE) + { + HAL_OTA_LOG("err offset len %lu", len); + return ERR; + } + return hal_spi_flash_read(buffer, len, MQTT_INFO_ADDR); +} + + + diff --git a/targets/STM32L476RG_NB476/Src/gpio.c b/targets/STM32L476RG_NB476/Src/gpio.c new file mode 100644 index 000000000..a04cdb6cf --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/gpio.c @@ -0,0 +1,91 @@ +/** + ****************************************************************************** + * File Name : gpio.c + * Description : This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(NB_EN_GPIO_Port, NB_EN_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PCPin PCPin PCPin PCPin + PCPin */ + GPIO_InitStruct.Pin = DHT11_DATA_Pin|KEY4_Pin|KEY3_Pin|KEY2_Pin + |KEY1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = LED_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = NB_RI_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(NB_RI_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = NB_EN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(NB_EN_GPIO_Port, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/i2c.c b/targets/STM32L476RG_NB476/Src/i2c.c new file mode 100644 index 000000000..a98f99b5b --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/i2c.c @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * File Name : I2C.c + * Description : This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c1; + +/* I2C1 init function */ +void MX_I2C1_Init(void) +{ + + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x10909CEC; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = OLED_SCL_Pin|OLED_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* I2C1 clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB6 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(GPIOB, OLED_SCL_Pin|OLED_SDA_Pin); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/main.c b/targets/STM32L476RG_NB476/Src/main.c new file mode 100644 index 000000000..cb4b99459 --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/main.c @@ -0,0 +1,143 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ +#include "main.h" +#include "sys_init.h" +#include "mem.h" + +#include "los_base.h" +#include "los_task.ph" +#include "los_typedef.h" +#include "los_sys.h" + +/*****Private includes******/ +#include "i2c.h" +#include "usart.h" +#include "rtc.h" +#include "gpio.h" +#include "stdio.h" +#include "oled.h" +#include "bmp.h" +#include "dht11.h" +/***************************/ + +#if defined (__CC_ARM) +extern char Image$$RW_IRAM1$$ZI$$Limit []; +extern char Image$$ARM_LIB_STACKHEAP$$Base []; +#elif defined (__GNUC__) +extern char __los_heap_addr_start__ []; +extern char __los_heap_addr_end__ []; +#else +#error "fix me" +#endif + +const struct phys_mem system_phys_mem [] = + { +#if defined (__CC_ARM) + { Image$$RW_IRAM1$$ZI$$Limit, Image$$ARM_LIB_STACKHEAP$$Base }, +#elif defined (__GNUC__) + {(unsigned long) __los_heap_addr_start__,(unsigned long) __los_heap_addr_end__ }, +#else +#error "fix me" +#endif + { 0, 0 } + }; + +VOID HardWare_Init(VOID) +{ + HAL_Init(); + /* Configure the system clock */ + SystemClock_Config(); + MX_GPIO_Init(); + MX_I2C1_Init(); + MX_RTC_Init(); + dwt_delay_init(SystemCoreClock); + /* Init OLED */ + OLED_Init(); + OLED_Clear(); + OLED_ShowCHinese(9, 0, 0);//Zhu + OLED_ShowCHinese(27, 0, 1);//You + OLED_ShowCHinese(45, 0, 2);//Peng + OLED_ShowCHinese(63, 0, 3);//Wu + OLED_ShowCHinese(81, 0, 4);//Lian + OLED_ShowCHinese(99, 0, 5);//Wang + OLED_ShowCHinese(36, 2, 6);//Da + OLED_ShowCHinese(54, 2, 7);//Jiang + OLED_ShowCHinese(72, 2, 8);//Tang + OLED_ShowString(18, 4, "L476_LiTeOS", 16); + OLED_ShowString(48, 6, "NBIOT", 16); + //delayus(1000); + /* Init DHT11 */ + DHT11_Init(); + +} + +extern int link_main(void *args); +static int link_test() +{ + int ret = -1; + UINT32 uwRet = LOS_OK; + UINT32 handle; + TSK_INIT_PARAM_S task_init_param; + + memset (&task_init_param, 0, sizeof (TSK_INIT_PARAM_S)); + task_init_param.uwArg = (unsigned int)NULL; + task_init_param.usTaskPrio = 2; + task_init_param.pcName =(char *) "link_main"; + task_init_param.pfnTaskEntry = (TSK_ENTRY_FUNC)link_main; + task_init_param.uwStackSize = 0x1000; + uwRet = LOS_TaskCreate(&handle, &task_init_param); + if(LOS_OK == uwRet){ + ret = 0; + } + return ret; +} + +int main(void) +{ + UINT32 uwRet = LOS_OK; + HardWare_Init(); + uwRet = LOS_KernelInit(); + if (uwRet != LOS_OK) + { + return LOS_NOK; + } + + extern void shell_uart_init(int baud); + shell_uart_init(115200); + + link_test(); + + (void)LOS_Start(); + return 0; +} diff --git a/targets/STM32L476RG_NB476/Src/main.c.back.c b/targets/STM32L476RG_NB476/Src/main.c.back.c new file mode 100644 index 000000000..2ab2e481c --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/main.c.back.c @@ -0,0 +1,429 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "i2c.h" +#include "usart.h" +#include "rtc.h" +#include "gpio.h" +#include "stdio.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "oled.h" +#include "bmp.h" +#include "dht11.h" +#include "sys_init.h" +#include "mem.h" + +#include "los_base.h" +#include "los_task.ph" +#include "los_typedef.h" +#include "los_sys.h" +#include +#include + +#if defined (__CC_ARM) +extern char Image$$RW_IRAM1$$ZI$$Limit []; +extern char Image$$ARM_LIB_STACKHEAP$$Base []; +#elif defined (__GNUC__) +extern char __los_heap_addr_start__ []; +extern char __los_heap_addr_end__ []; +#else +#error "fix me" +#endif + +const struct phys_mem system_phys_mem [] = + { +#if defined (__CC_ARM) + { Image$$RW_IRAM1$$ZI$$Limit, Image$$ARM_LIB_STACKHEAP$$Base }, +#elif defined (__GNUC__) + {(unsigned long) __los_heap_addr_start__,(unsigned long) __los_heap_addr_end__ }, +#else +#error "fix me" +#endif + { 0, 0 } + }; + + + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ +VOID HardWare_Init(VOID); +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +DHT11_Data_TypeDef dht11; +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +static void MX_NVIC_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* shell 命令 */ +static int shell_Temp(int argc,const char *argv[]){ + printf("temp = %.2f ; humi = %.2f\r\n",dht11.temperature,dht11.humidity); + return 0; +} +OSSHELL_EXPORT_CMD(shell_Temp,"readTemp","readTemp"); + + +/* 温度检测相关 */ +static void DHT11timer_callback(void *arg) +{ + DHT11_Read_TempAndHumidity(&dht11); +} + + +/* 该任务用于初始化所有外设以及NBIOT + * + */ +int task1(void *args) +{ + + osal_init(); //如果不调用该函数，printf无法使用 + +/* 初始化软件定时器，用于DHT11采集温湿度信息 + * + */ +#if CONFIG_STIMER_ENABLE + + stimer_init(); + +#endif + +/* 初始化shell，可以自定义各种指令，推荐使用MobaXterm_Personal_10.4软件，普通的串口助手会乱码 + * + */ +#if CONFIG_SHELL_ENABLE + + shell_init(); +#endif + +#define CONFIG_DRIVER_ENABLE 1 +/* 初始化设备注册框架用于注册at指令使用的串口 + * + */ +#if CONFIG_DRIVER_ENABLE + #include + ///< install the driver framework for the link + los_driv_init(); +#endif + +#define CONFIG_AT_ENABLE 1 +/* 初始化AT框架用于NBiot模块 + * + */ +#if CONFIG_AT_ENABLE + #include + #include + extern bool_t uart_at_init(int baud); + + + #ifndef CONFIG_AT_BAUDRATE + #define CONFIG_AT_BAUDRATE 9600 + #endif + + #ifndef CONFIG_AT_DEVICENAME + #define CONFIG_AT_DEVICENAME "atdev" + #endif + + + ///< install the at framework for the link + uart_at_init(CONFIG_AT_BAUDRATE); + at_init(CONFIG_AT_DEVICENAME); +#endif + + +//////////////////////////// OC LWM2M /////// ///////////////////////////// +#if CONFIG_OC_LWM2M_ENABLE + #include + oc_lwm2m_init(); + + #if CONFIG_OC_LWM2M_AGENT_ENABLE + #include + oc_lwm2m_install_agent(); + #endif + + #if CONFIG_OC_LWM2M_BOUDICA150_ENABLE + #include + #define cn_app_bands "5" //bc95电信卡5 + boudica150_init(NULL,NULL,cn_app_bands); + #endif + + #if CONFIG_OC_LWM2M_BOUDICA120_ENABLE + #include + #define cn_app_bands "5" //bc95电信卡5 + oc_lwm2m_imp_init(); + #endif +#endif + +////////////////////////// COAP PROTOCOL ///////////////////////////////// +#ifdef CONFIG_OCCOAP_ENABLE + #include + oc_coap_init(); +#endif + +#if CONFIG_OC_COAP_BOUDICA120_ENABLE + #include + oc_coap_imp_init(); +#endif + + /* 创建一个定时器，用于DHT11采集温湿度 + * + */ + stimer_create("DHT11timer",DHT11timer_callback,NULL,1*1000,cn_stimer_flag_start); + + printf("task1 init succsee!\r\n"); + printf("start init task2\r\n"); + int Creat_task2(); + Creat_task2(); + while (1) + { + HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin); + LOS_TaskDelay(2000); + + } +} + +static int Creat_task1() +{ + int ret = -1; + UINT32 uwRet = LOS_OK; + UINT32 handle; + TSK_INIT_PARAM_S task1_init_param; + + memset (&task1_init_param, 0, sizeof (TSK_INIT_PARAM_S)); + task1_init_param.uwArg = (unsigned int)NULL; + task1_init_param.usTaskPrio = 2; + task1_init_param.pcName =(char *) "task1"; + task1_init_param.pfnTaskEntry = (TSK_ENTRY_FUNC)task1; + task1_init_param.uwStackSize = 0x1000; + uwRet = LOS_TaskCreate(&handle, &task1_init_param); + if(LOS_OK == uwRet){ + ret = 0; + } + return ret; +} +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + UINT32 uwRet = LOS_OK; + /* USER CODE END 1 */ + + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); //这里配置了中断分组以及系统时钟 + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_I2C1_Init(); + //MX_LPUART1_UART_Init(); + MX_RTC_Init(); + //MX_USART1_UART_Init(); + //MX_USART3_UART_Init(); + HardWare_Init(); + /* Initialize interrupts */ + //MX_NVIC_Init(); + /* USER CODE BEGIN 2 */ + //任务创建 + HardWare_Init(); + uwRet = LOS_KernelInit(); + if (uwRet != LOS_OK) + { + return LOS_NOK; + } + + extern void shell_uart_init(int baud); + shell_uart_init(115200); + //printf("Hello World! This is LiteOS!\r\n"); + + Creat_task1(); + + (void)LOS_Start(); + return 0; + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_LPUART1 + |RCC_PERIPHCLK_I2C1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } +} + +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) +{ + /* LPUART1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 1, 0); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); +} + +/* USER CODE BEGIN 4 */ +VOID HardWare_Init(VOID) +{ + //初始化延时函数 + dwt_delay_init(SystemCoreClock); + //初始化OLED + OLED_Init(); + OLED_Clear(); + OLED_ShowCHinese(9, 0, 0);//朱 + OLED_ShowCHinese(27, 0, 1);//有 + OLED_ShowCHinese(45, 0, 2);//鹏 + OLED_ShowCHinese(63, 0, 3);//物 + OLED_ShowCHinese(81, 0, 4);//联 + OLED_ShowCHinese(99, 0, 5);//网 + OLED_ShowCHinese(36, 2, 6);//大 + OLED_ShowCHinese(54, 2, 7);//讲 + OLED_ShowCHinese(72, 2, 8);//堂 + OLED_ShowString(18, 4, "L476_LiTeOS", 16); + OLED_ShowString(48, 6, "NBIOT", 16); + //delayus(1000); + //初始化DHT11 + DHT11_Init(); +} +/* USER CODE END 4 */ + + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/ota_port.c b/targets/STM32L476RG_NB476/Src/ota_port.c new file mode 100644 index 000000000..09428f04c --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/ota_port.c @@ -0,0 +1,107 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "ota_port.h" +#include "common.h" +#include "flag_manager.h" +#include "upgrade_flag.h" +#include +#include +#include +#include "flash_adaptor.h" +#include "hal_spi_flash.h" + + +static const uint32_t g_flash_base_addrs[] = {OTA_IMAGE_DOWNLOAD_ADDR, OTA_IMAGE_DOWNLOAD_ADDR, OTA_FLAG_ADDR1}; +static const uint32_t g_flash_max_size[] = {OTA_IMAGE_DOWNLOAD_SIZE, OTA_IMAGE_DOWNLOAD_SIZE, FLASH_BLOCK_SIZE}; + +static int hal_check_flash_param(ota_flash_type_e type, int32_t len, uint32_t location) +{ + if (type > OTA_UPDATE_INFO) + { + HAL_OTA_LOG("err type %d", type); + return ERR; + } + + if(len > g_flash_max_size[type]) + { + HAL_OTA_LOG("err offset %lu, len %lu", location, len); + return ERR; + } + + return OK; +} + +static int hal_read_flash(ota_flash_type_e type, void *buf, int32_t len, uint32_t location) +{ + if (hal_check_flash_param(type, len, location) != OK) + { + return ERR; + } + + return hal_spi_flash_read(buf, len, g_flash_base_addrs[type] + location); +} + +static int hal_write_flash(ota_flash_type_e type, const void *buf, int32_t len, uint32_t location) +{ + if (hal_check_flash_param(type, len, location) != OK) + { + return ERR; + } + + return flash_adaptor_write(g_flash_base_addrs[type] + location, (const uint8_t *)buf, len); +} + +void hal_init_ota(void) +{ + flash_adaptor_init(); +} + + +void hal_get_ota_opt(ota_opt_s *opt) +{ + if (opt == NULL) + { + HAL_OTA_LOG("opt NULL"); + return; + } + + memset(opt, 0, sizeof(*opt)); + opt->read_flash = hal_read_flash; + opt->write_flash = hal_write_flash; + opt->flash_block_size = FLASH_BLOCK_SIZE; +} + + + diff --git a/targets/STM32L476RG_NB476/Src/rtc.c b/targets/STM32L476RG_NB476/Src/rtc.c new file mode 100644 index 000000000..fdac41b89 --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/rtc.c @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * File Name : RTC.c + * Description : This file provides code for the configuration + * of the RTC instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "rtc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + +} + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + + if(rtcHandle->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle) +{ + + if(rtcHandle->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/stm32l4xx_hal_msp.c b/targets/STM32L476RG_NB476/Src/stm32l4xx_hal_msp.c new file mode 100644 index 000000000..db41b739d --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/stm32l4xx_hal_msp.c @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32l4xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/stm32l4xx_it.c b/targets/STM32L476RG_NB476/Src/stm32l4xx_it.c new file mode 100644 index 000000000..9ce9a7f0a --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/stm32l4xx_it.c @@ -0,0 +1,190 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l4xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern UART_HandleTypeDef hlpuart1; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles LPUART1 global interrupt. + */ +void LPUART1_IRQHandler(void) +{ + /* USER CODE BEGIN LPUART1_IRQn 0 */ + + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + /* USER CODE BEGIN LPUART1_IRQn 1 */ + + /* USER CODE END LPUART1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/sys.c b/targets/STM32L476RG_NB476/Src/sys.c new file mode 100644 index 000000000..1cc132eaa --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/sys.c @@ -0,0 +1,37 @@ +/** + ****************************************************************************** + * File Name : SYS.c + * Description : This file provides code for the configuration + * of the SYS instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "sys.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* SYS init function */ +void MX_SYS_Init(void) +{ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/sys_init.c b/targets/STM32L476RG_NB476/Src/sys_init.c new file mode 100644 index 000000000..6f7fd3df4 --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/sys_init.c @@ -0,0 +1,160 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "sys_init.h" + + +uint32_t HAL_GetTick(void) +{ + return (uint32_t)LOS_TickCountGet(); +} + +/** + * @brief This function is executed in case of error occurrence. + * @param file: The file name as string. + * @param line: The line in file as a number. + * @retval None + */ +void _Error_Handler(char *file, int line) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + while(1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + + + + + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + + +/* + * atiny_adapter user interface + */ +void atiny_usleep(unsigned long usec) +{ + delayus((uint32_t)usec); +} + +int atiny_random(void *output, size_t len) +{ + return hal_rng_generate_buffer(output, len); +} + +void atiny_reboot(void) +{ + HAL_NVIC_SystemReset(); +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_LPUART1 + |RCC_PERIPHCLK_I2C1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } +} diff --git a/targets/STM32L476RG_NB476/Src/system_stm32l4xx.c b/targets/STM32L476RG_NB476/Src/system_stm32l4xx.c new file mode 100644 index 000000000..1db59ec93 --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/system_stm32l4xx.c @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * PLLSAI2_P | NA + *----------------------------------------------------------------------------- + * PLLSAI2_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI2_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include "stm32l4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000U; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= 0xEAF6FFFFU; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000U; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/Src/uart_debug.c b/targets/STM32L476RG_NB476/Src/uart_debug.c new file mode 100644 index 000000000..7967584ed --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/uart_debug.c @@ -0,0 +1,150 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "usart.h" + +#include "stm32l4xx.h" +#include +#include + +#include +#include + +#include +#include +#include + +#define CN_RCV_RING_BUFLEN 128 + +static USART_TypeDef* s_pUSART = USART1; +static uint32_t s_uwIRQn = USART1_IRQn; + +static bool_t s_uart_init = false; + +/* USART1 init function */ +UART_HandleTypeDef uart_debug; +static tag_ring_buffer_t s_uartdebug_rcv_ring; +static unsigned char s_uartdebug_rcv_ringmem[CN_RCV_RING_BUFLEN]; +static UINT32 s_uartdebug_rcv_sync; +static void uart_debug_irq(void) +{ + unsigned char value; + if(__HAL_UART_GET_FLAG(&uart_debug, UART_FLAG_RXNE) != RESET) + { + value = (uint8_t)(uart_debug.Instance->RDR & 0x00FF); + ring_buffer_write(&s_uartdebug_rcv_ring,&value,1); + LOS_SemPost(s_uartdebug_rcv_sync); + } + else if (__HAL_UART_GET_FLAG(&uart_debug,UART_FLAG_IDLE) != RESET) + { + __HAL_UART_CLEAR_IDLEFLAG(&uart_debug); + } +} +void shell_uart_init(int baud) +{ + uart_debug.Instance = s_pUSART; + uart_debug.Init.BaudRate = baud; + uart_debug.Init.WordLength = UART_WORDLENGTH_8B; + uart_debug.Init.StopBits = UART_STOPBITS_1; + uart_debug.Init.Parity = UART_PARITY_NONE; + uart_debug.Init.Mode = UART_MODE_TX_RX; + uart_debug.Init.HwFlowCtl = UART_HWCONTROL_NONE; + uart_debug.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&uart_debug) != HAL_OK) + { + return; + } + LOS_HwiCreate(s_uwIRQn, 3, 0, uart_debug_irq, 0); + //__HAL_UART_ENABLE_IT(&uart_debug, UART_IT_IDLE); + __HAL_UART_ENABLE_IT(&uart_debug, UART_IT_RXNE); + + //create the receive buffer and receive sync + extern UINT32 osSemCreate (UINT16 usCount, UINT16 usMaxCount, UINT32 *puwSemHandle); + osSemCreate(0,CN_RCV_RING_BUFLEN,(UINT32 *)&s_uartdebug_rcv_sync); + ring_buffer_init(&s_uartdebug_rcv_ring,s_uartdebug_rcv_ringmem,CN_RCV_RING_BUFLEN,0,0); + s_uart_init = true; + +} + + +/* define fputc */ +#if defined ( __CC_ARM ) || defined ( __ICCARM__ ) /* KEIL and IAR: printf will call fputc to print */ +int fputc(int ch, FILE *f) +{ + HAL_UART_Transmit(&uart_debug, (uint8_t *)&ch, 1, 0xFFFF); + return ch; +} +int fgetc(FILE *f){ + int ret = 0; + unsigned char value; + do + { + if(LOS_OK == LOS_SemPend(s_uartdebug_rcv_sync,LOS_WAIT_FOREVER)) + { + ret = ring_buffer_read(&s_uartdebug_rcv_ring,&value,1); + } + }while(ret <=0); + ret = value; + return ret; +} +#elif defined ( __GNUC__ ) /* GCC: printf will call _write to print */ + + + + +__attribute__((used)) int _write(int fd, char *ptr, int len) +{ + + if(s_uart_init) + { + HAL_UART_Transmit(&uart_debug, (uint8_t *)ptr, len, 0xFFFF); + } + return len; +} +__attribute__((used)) int _read(int fd, char *ptr, int len) +{ + int ret = 0; + unsigned char value; + do + { + if(LOS_OK == LOS_SemPend(s_uartdebug_rcv_sync,LOS_WAIT_FOREVER)) + { + ret = ring_buffer_read(&s_uartdebug_rcv_ring,&value,1); + } + }while(ret <=0); + *(unsigned char *)ptr = value; + return 1; +} + +#endif diff --git a/targets/STM32L476RG_NB476/Src/usart.c b/targets/STM32L476RG_NB476/Src/usart.c new file mode 100644 index 000000000..44d8cd2df --- /dev/null +++ b/targets/STM32L476RG_NB476/Src/usart.c @@ -0,0 +1,237 @@ +/** + ****************************************************************************** + * File Name : USART.c + * Description : This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef hlpuart1; +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart3; + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + + hlpuart1.Instance = LPUART1; + hlpuart1.Init.BaudRate = 115200; + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + hlpuart1.Init.StopBits = UART_STOPBITS_1; + hlpuart1.Init.Parity = UART_PARITY_NONE; + hlpuart1.Init.Mode = UART_MODE_TX_RX; + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + { + Error_Handler(); + } + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspInit 0 */ + + /* USER CODE END LPUART1_MspInit 0 */ + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**LPUART1 GPIO Configuration + PB10 ------> LPUART1_RX + PB11 ------> LPUART1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN LPUART1_MspInit 1 */ + + /* USER CODE END LPUART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART3 GPIO Configuration + PC4 ------> USART3_TX + PC5 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==LPUART1) + { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); + + /**LPUART1 GPIO Configuration + PB10 ------> LPUART1_RX + PB11 ------> LPUART1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); + + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + /* USER CODE BEGIN LPUART1_MspDeInit 1 */ + + /* USER CODE END LPUART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PC4 ------> USART3_TX + PC5 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/STM32L476RG_NB476/iot_config.h b/targets/STM32L476RG_NB476/iot_config.h new file mode 100644 index 000000000..b9d5b7b48 --- /dev/null +++ b/targets/STM32L476RG_NB476/iot_config.h @@ -0,0 +1,26 @@ +#define CONFIG_ARCH_CPU_TYPE "armv7-m" +#define CONFIG_UARTAT_RCVMAX 2048 +#define CONFIG_UARTAT_BAUDRATE 9600 +#define CONFIG_UARTAT_DEVNAME "atdev" +#define CONFIG_LITEOS_ENABLE 1 +#define CONFIG_AT_ENABLE 1 +#define CONFIG_AT_DEVNAME "atdev" +#define CONFIG_AT_OOBTABLEN 6 +#define CONFIG_AT_RECVMAXLEN 1024 +#define CONFIG_AT_TASKPRIOR 10 +#define CONFIG_DRIVER_ENABLE 1 +#define CONFIG_LINKLOG_ENABLE 1 +#define CONFIG_LINKQUEUE_ENABLE 1 +#define CONFIG_LINKDEMO_ENABLE 1 +#define CONFIG_STIMER_ENABLE 1 +#define CONFIG_STIMER_STACKSIZE 2048 +#define CONFIG_STIMER_TASKPRIOR 10 +#define CONFIG_OCSERVICES_ENABLE 1 +#define CONFIG_BOUDICA120_ENABLE 1 +#define CONFIG_SHELL_ENABLE 1 +#define CONFIG_SHELL_TASK_STACKSIZE 2048 +#define CONFIG_SHELL_TASK_PRIOR 10 +#define CONFIG_IOT_LINK_CONFIGFILE "iot_config.h" +#define CONFIG_Demo_Agriculture 1 +#define CONFIG_USER_DEMO "use_coap_demo" +#define CONFIG_OCCOAP_ENABLE 1 diff --git a/targets/STM32L476RG_NB476/uart_at/uart_at.c b/targets/STM32L476RG_NB476/uart_at/uart_at.c new file mode 100644 index 000000000..40ae59f74 --- /dev/null +++ b/targets/STM32L476RG_NB476/uart_at/uart_at.c @@ -0,0 +1,270 @@ +/*---------------------------------------------------------------------------- + * Copyright (c) <2016-2018>, + * All rights reserved. + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other materials + * provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific prior written + * permission. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Notice of Export Control Law + * =============================================== + * Huawei LiteOS may be subject to applicable export control laws and regulations, which might + * include those applicable to Huawei LiteOS of U.S. and the country in which you are located. + * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such + * applicable export control laws and regulations. + *---------------------------------------------------------------------------*/ + +#include "usart.h" +#include "stm32l4xx.h" +#include +#include +#include +#include +#include +#include "sys/fcntl.h" +#include + + +UART_HandleTypeDef uart_at; +static USART_TypeDef* s_pUSART = USART3; +static uint32_t s_uwIRQn = USART3_IRQn; + +#ifndef CONFIG_UARTAT_RCVMAX +#define CONFIG_UARTAT_RCVMAX 1024 //cache a frame +#endif + +#ifndef CONFIG_UARTAT_BAUDRATE +#define CONFIG_UARTAT_BAUDRATE 115200 +#endif + + +#ifndef CONFIG_UARTAT_DEVNAME +#define CONFIG_UARTAT_DEVNAME "atdev" +#endif + +#define CN_RCVMEM_LEN CONFIG_UARTAT_RCVMAX + + +struct atio_cb +{ + unsigned short w_next; //the next position to be write + osal_semp_t rcvsync; //if a frame has been written to the ring, then active it + tag_ring_buffer_t rcvring; + unsigned char rcvbuf[CONFIG_UARTAT_RCVMAX]; + unsigned char rcvringmem[CN_RCVMEM_LEN]; + //for the debug here + unsigned int rframeover; //how many times the frame has been over the max length + unsigned int rframedrop; //how many frame has been droped for memmory + unsigned int sndlen; //how many bytes has been sent + unsigned int rcvlen; //how many bytes has been received + unsigned int sndframe; //how many frame has been sent + unsigned int rcvframe; //how many frame has been received + unsigned int rcvringrst; //how many times the receive ring has been reset +}; +static struct atio_cb g_atio_cb; + + +/******************************************************************************* +function :use this function to deal the uart interrupt +parameters : +instruction :we cached the data in the temp buffer,when the idle interrupt reached, + then we write the data and the length to the ring if the ring has enough + space +*******************************************************************************/ +static void atio_irq(void) +{ + unsigned char value; + unsigned short ringspace; + if(__HAL_UART_GET_FLAG(&uart_at, UART_FLAG_RXNE) != RESET) + { + value = (uint8_t)(uart_at.Instance->RDR & 0x00FF); + g_atio_cb.rcvlen++; + if(g_atio_cb.w_next < CONFIG_UARTAT_RCVMAX) + { + g_atio_cb.rcvbuf[g_atio_cb.w_next] = value; + g_atio_cb.w_next++; + } + else + { + g_atio_cb.rframeover++; + } + } + else if (__HAL_UART_GET_FLAG(&uart_at,UART_FLAG_IDLE) != RESET) + { + __HAL_UART_CLEAR_IDLEFLAG(&uart_at); + ringspace = CN_RCVMEM_LEN - ring_buffer_datalen(&g_atio_cb.rcvring); + if(ringspace < g_atio_cb.w_next) //not enough mem + { + g_atio_cb.rframedrop++; + } + else + { + //write data to the ring buffer:len+data format + ringspace = g_atio_cb.w_next; + ring_buffer_write(&g_atio_cb.rcvring,(unsigned char *)&ringspace,sizeof(ringspace)); + ring_buffer_write(&g_atio_cb.rcvring,g_atio_cb.rcvbuf,ringspace); + (void) osal_semp_post(g_atio_cb.rcvsync); + g_atio_cb.rcvframe++; + } + g_atio_cb.w_next=0; //write from the head + } + else ///< clear the flags + { + __HAL_UART_CLEAR_PEFLAG(&uart_at); + __HAL_UART_CLEAR_FEFLAG(&uart_at); + __HAL_UART_CLEAR_NEFLAG(&uart_at); + __HAL_UART_CLEAR_OREFLAG(&uart_at); + } + + +} + +/******************************************************************************* +function :use this function to initialize the uart +parameters : +instruction : +*******************************************************************************/ +bool_t uart_at_init(void *pri) +{ + //initialize the at controller + (void) memset(&g_atio_cb,0,sizeof(g_atio_cb)); + if(false == osal_semp_create(&g_atio_cb.rcvsync,CN_RCVMEM_LEN,0)) + { + printf("%s:semp create error\n\r",__FUNCTION__); + goto EXIT_SEMP; + } + ring_buffer_init(&g_atio_cb.rcvring,g_atio_cb.rcvringmem,CN_RCVMEM_LEN,0,0); + + uart_at.Instance = s_pUSART; + uart_at.Init.BaudRate = CONFIG_UARTAT_BAUDRATE; + uart_at.Init.WordLength = UART_WORDLENGTH_8B; + uart_at.Init.StopBits = UART_STOPBITS_1; + uart_at.Init.Parity = UART_PARITY_NONE; + uart_at.Init.HwFlowCtl = UART_HWCONTROL_NONE; + uart_at.Init.Mode = UART_MODE_TX_RX; + uart_at.Init.OverSampling = UART_OVERSAMPLING_16; + if(HAL_UART_Init(&uart_at) != HAL_OK) + { + _Error_Handler(__FILE__, __LINE__); + } + __HAL_UART_CLEAR_FLAG(&uart_at,UART_FLAG_TC); + LOS_HwiCreate(s_uwIRQn, 3, 0, atio_irq, 0); + __HAL_UART_ENABLE_IT(&uart_at, UART_IT_IDLE); + __HAL_UART_ENABLE_IT(&uart_at, UART_IT_RXNE); + return true; + +EXIT_SEMP: + return false; +} + +void uart_at_deinit(void *pri) +{ + __HAL_UART_DISABLE(&uart_at); + __HAL_UART_DISABLE_IT(&uart_at, UART_IT_IDLE); + __HAL_UART_DISABLE_IT(&uart_at, UART_IT_RXNE); +} + +/******************************************************************************* +function :use this function to send a frame to the uart +parameters : +instruction : +*******************************************************************************/ +static ssize_t uart_at_send(const char *buf, size_t len,uint32_t timeout) +{ + HAL_UART_Transmit(&uart_at,(unsigned char *)buf,len,timeout); + g_atio_cb.sndlen += len; + g_atio_cb.sndframe ++; + + return len; +} +/******************************************************************************* +function :use this function to read a frame from the uart +parameters : +instruction : +*******************************************************************************/ +static ssize_t uart_at_receive(void *buf,size_t len,uint32_t timeout) +{ + unsigned short cpylen; + unsigned short framelen; + unsigned short readlen; + int32_t ret = 0; + unsigned int lock; + if(osal_semp_pend(g_atio_cb.rcvsync,timeout)) + { + lock = LOS_IntLock(); + readlen = sizeof(framelen); + cpylen = ring_buffer_read(&g_atio_cb.rcvring,(unsigned char *)&framelen,readlen); + if(cpylen != readlen) + { + ring_buffer_reset(&g_atio_cb.rcvring); //bad ring format here + g_atio_cb.rcvringrst++; + } + else + { + if(framelen > len) + { + ring_buffer_reset(&g_atio_cb.rcvring); //bad ring format here + g_atio_cb.rcvringrst++; + } + else + { + readlen = framelen; + cpylen = ring_buffer_read(&g_atio_cb.rcvring,(unsigned char *)buf,readlen); + if(cpylen != framelen) + { + ring_buffer_reset(&g_atio_cb.rcvring); //bad ring format here + g_atio_cb.rcvringrst++; + } + else + { + ret = cpylen; + } + } + } + LOS_IntRestore(lock); + } + return ret; +} + +//make it as the at device here +static ssize_t __at_read (void *pri,size_t offset,void *buf,size_t len, uint32_t timeout) +{ + return uart_at_receive(buf,len, timeout); + +} +static ssize_t __at_write (void *pri, size_t offset,const void *buf,size_t len,uint32_t timeout) +{ + return uart_at_send(buf, len, timeout); + +} + + +static const los_driv_op_t s_at_op = { + + .init = uart_at_init, + .deinit = uart_at_deinit, + .read = __at_read, + .write = __at_write, +}; + +OSDRIV_EXPORT(uart_at_driv,CONFIG_UARTAT_DEVNAME,(los_driv_op_t *)&s_at_op,NULL,O_RDWR); + +