input_clocks.kicad_sch

(kicad_sch (version 20211123) (generator eeschema)

  (uuid 73f1815b-660b-4030-b62e-8f3aec934864)

  (paper "A4")

  (title_block
    (title "Generator 0.0125 - 6.4 GHz (or up to 20 GHz)")
    (date "2021-12-30")
    (rev "211230-001")
    (company "Petr Polasek")
    (comment 1 "001, 2021-12-30 01:03")
    (comment 2 "TCXO / external input")
    (comment 3 "LMX2572 (6.4 GHz) / LMX2592 (9.8GHz) / LMX2594 (15 GHz) / LMX2595 (20 GHz)")
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    (stroke (width 0) (type default) (color 0 0 0 0))
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  (text "48V overvoltage protection.\nThe TC2-1T+ doesn't have pri-sec voltage rating!\nBefore assembling the TVS, check that the\nTC2-1T+ can withstand at least 75 V DC.\nCheck by test, check every unit for one minute (before assembly)."
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  (text "40 MHz reference with CMOS output,\n0.5 PPM initial tolerance,\n0.28 PPM temp. tolerance (-40 to +85°C),\n0.5 PPM/year aging.\nVC should allow enough trimming for at least 4.5 years."
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  (text "DO NOT update the logic gate.\nFor unknown reasons, its VCC pin\noverrides net name."
    (at 115.57 29.21 0)
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  (text "Differential overvoltage protection. Clips large signals\nwithout lowering slew rate. Can be replaced by most\nmicrowave NPN transistors. Do not use diodes as these\ntend to be too slow or have high capacitance except for\nspecial types."
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  (text "VCTCXO" (at 208.28 40.64 0)
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  (text "Duty factor / DC corrector" (at 29.21 21.59 0)
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  (text "Reference frequency input" (at 30.48 109.22 0)
    (effects (font (size 5.08 5.08)) (justify left bottom))
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  (text "Duty factor correcting circuitry for\nexternal reference input. Assemble\nonly when problems with DF on\nexternal ref. appear."
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  (text "Idiotic ...G66 symbol. The floating labels are power supply."
    (at 82.55 30.48 0)
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  (text "Duty factor correcting circuitry.\nAssemble only when needed."
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  (text "Direct logic refin.\nOnly for internal use.\nNot protected.\nGround not isolated."
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  (text "The Si53301 requires slew rate at least 750 V/us to meet 50 fs additive jitter.\nThis would require 5.5 Vpk-pk @ 10 MHz or 1.45 Vpk-pk at 40 MHz for sine wave.\nTherefore, clipped sine wave or rectangle is required for best jitter performance.\nThe clipped sine should have slew rate at least 400 V/us and voltage at least 150 mVpp,\nedges should be shorter than 1 ns."
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