From aab466f422500842adb62ddb7b1357e2e123ebb2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 25 Jul 2022 02:31:20 +0200 Subject: [PATCH 01/91] kernel: backport generic phylink validate Backport generic phylink validate series and make use of it for mtk_eth_soc Ethernet driver as well as mt7530 DSA driver. Signed-off-by: Daniel Golle --- ...ylink-add-MAC-phy_interface_t-bitmap.patch | 24 ++ ...supported_interfaces-for-phylink-val.patch | 98 +++++ ...populate-supported_interfaces-member.patch | 63 +++ ...net-dsa-consolidate-phylink-creation.patch | 149 +++++++ ...phylink_get_interfaces-with-phylink_.patch | 51 +++ ...d-support-for-phylink-mac_select_pcs.patch | 59 +++ ...y-add-phy_interface_t-bitmap-support.patch | 61 +++ ...mac_select_pcs-method-to-phylink_mac.patch | 197 +++++++++ ...-add-generic-validate-implementation.patch | 341 ++++++++++++++++ ...e-helpers-for-iterating-through-port.patch | 68 ++++ ...-net-phylink-add-pcs_validate-method.patch | 106 +++++ ...k-add-legacy_pre_march2020-indicator.patch | 43 ++ ...-DSA-phylink-as-legacy_pre_march2020.patch | 36 ++ ...net-phylink-use-legacy_pre_march2020.patch | 115 ++++++ ...populate-supported_interfaces-member.patch | 43 ++ ...remove-interface-checks-in-mtk_valid.patch | 75 ++++ ...drop-use-of-phylink_helper_basex_spe.patch | 42 ++ ...eth_soc-use-phylink_generic_validate.patch | 84 ++++ ...mark-as-a-legacy_pre_march2020-drive.patch | 29 ++ ...remove-a-copy-of-the-NAPI_POLL_WEIGH.patch | 40 ++ ...9-mtk_eth_soc-remove-unused-mac-mode.patch | 35 ++ ...tk_eth_soc-remove-unused-sgmii-flags.patch | 40 ++ ...add-mask-and-update-PCS-speed-defini.patch | 40 ++ ...eth_soc-correct-802.3z-speed-setting.patch | 60 +++ ...th_soc-correct-802.3z-duplex-setting.patch | 101 +++++ ...stop-passing-phylink-state-to-sgmii-.patch | 60 +++ ...mtk_eth_soc-provide-mtk_sgmii_config.patch | 89 ++++ ...add-fixme-comment-for-state-speed-us.patch | 38 ++ ...c-move-MAC_MCR-setting-to-mac_finish.patch | 79 ++++ ...move-restoration-of-SYSCFG0-to-mac_f.patch | 57 +++ ...convert-code-structure-to-suit-split.patch | 254 ++++++++++++ ...soc-partially-convert-to-phylink_pcs.patch | 262 ++++++++++++ ...terate-using-dsa_switch_for_each_use.patch | 106 +++++ ...opulate-supported_interfaces-and-mac.patch | 166 ++++++++ ...t-dsa-mt7530-remove-interface-checks.patch | 172 ++++++++ ...rop-use-of-phylink_helper_basex_spee.patch | 34 ++ ...nly-indicate-linkmodes-that-can-be-s.patch | 86 ++++ ...-switch-to-use-phylink_get_linkmodes.patch | 131 ++++++ ...530-partially-convert-to-phylink_pcs.patch | 385 ++++++++++++++++++ ...ove-autoneg-handling-to-PCS-validati.patch | 80 ++++ ...19-net-dsa-mt7530-mark-as-non-legacy.patch | 34 ++ ...mt753x-fix-pcs-conversion-regression.patch | 116 ++++++ ...t7530-rework-mt7530_hw_vlan_-add-del.patch | 87 ++++ ...et-dsa-mt7530-rework-mt753-01-_setup.patch | 75 ++++ ...et-cpu-port-via-dp-cpu_dp-instead-of.patch | 117 ++++++ ...PHY-initialization-with-MTU-setup-in.patch | 4 +- ...nl_lock-sections-in-dsa_slave_create.patch | 2 +- ...switch-operations-for-tracking-the-m.patch | 6 +- ...net-mtk_eth_soc-enable-threaded-NAPI.patch | 8 +- ...detach-callback-to-struct-phy_driver.patch | 2 +- ...mediatek-add-flow-offload-for-mt7623.patch | 2 +- ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 2 +- ...ernet-mtk_eth_soc-announce-2500baseT.patch | 10 - ...ethernet-mediatek-support-net-labels.patch | 4 +- ...y-simplify-phy_link_change-arguments.patch | 4 +- .../721-NET-no-auto-carrier-off-support.patch | 2 +- 56 files changed, 4446 insertions(+), 28 deletions(-) create mode 100644 target/linux/generic/backport-5.15/703-01-v5.16-net-phylink-add-MAC-phy_interface_t-bitmap.patch create mode 100644 target/linux/generic/backport-5.15/703-02-v5.16-net-phylink-use-supported_interfaces-for-phylink-val.patch create mode 100644 target/linux/generic/backport-5.15/703-03-v5.16-net-dsa-populate-supported_interfaces-member.patch create mode 100644 target/linux/generic/backport-5.15/703-04-v5.17-net-dsa-consolidate-phylink-creation.patch create mode 100644 target/linux/generic/backport-5.15/703-05-v5.17-net-dsa-replace-phylink_get_interfaces-with-phylink_.patch create mode 100644 target/linux/generic/backport-5.15/703-06-v5.18-net-dsa-add-support-for-phylink-mac_select_pcs.patch create mode 100644 target/linux/generic/backport-5.15/703-07-v5.16-net-phy-add-phy_interface_t-bitmap-support.patch create mode 100644 target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch create mode 100644 target/linux/generic/backport-5.15/703-09-v5.17-net-phylink-add-generic-validate-implementation.patch create mode 100644 target/linux/generic/backport-5.15/703-10-v5.16-net-dsa-introduce-helpers-for-iterating-through-port.patch create mode 100644 target/linux/generic/backport-5.15/703-11-v5.17-net-phylink-add-pcs_validate-method.patch create mode 100644 target/linux/generic/backport-5.15/703-12-v5.17-net-phylink-add-legacy_pre_march2020-indicator.patch create mode 100644 target/linux/generic/backport-5.15/703-13-v5.17-net-dsa-mark-DSA-phylink-as-legacy_pre_march2020.patch create mode 100644 target/linux/generic/backport-5.15/703-14-v5.17-net-phylink-use-legacy_pre_march2020.patch create mode 100644 target/linux/generic/backport-5.15/704-01-v5.17-net-mtk_eth_soc-populate-supported_interfaces-member.patch create mode 100644 target/linux/generic/backport-5.15/704-02-v5.17-net-mtk_eth_soc-remove-interface-checks-in-mtk_valid.patch create mode 100644 target/linux/generic/backport-5.15/704-03-v5.17-net-mtk_eth_soc-drop-use-of-phylink_helper_basex_spe.patch create mode 100644 target/linux/generic/backport-5.15/704-04-v5.17-net-mtk_eth_soc-use-phylink_generic_validate.patch create mode 100644 target/linux/generic/backport-5.15/704-05-v5.17-net-mtk_eth_soc-mark-as-a-legacy_pre_march2020-drive.patch create mode 100644 target/linux/generic/backport-5.15/704-06-v5.19-eth-mtk_eth_soc-remove-a-copy-of-the-NAPI_POLL_WEIGH.patch create mode 100644 target/linux/generic/backport-5.15/704-07-v5.19-mtk_eth_soc-remove-unused-mac-mode.patch create mode 100644 target/linux/generic/backport-5.15/704-08-v5.19-net-mtk_eth_soc-remove-unused-sgmii-flags.patch create mode 100644 target/linux/generic/backport-5.15/704-09-v5.19-net-mtk_eth_soc-add-mask-and-update-PCS-speed-defini.patch create mode 100644 target/linux/generic/backport-5.15/704-10-v5.19-net-mtk_eth_soc-correct-802.3z-speed-setting.patch create mode 100644 target/linux/generic/backport-5.15/704-11-v5.19-net-mtk_eth_soc-correct-802.3z-duplex-setting.patch create mode 100644 target/linux/generic/backport-5.15/704-12-v5.19-net-mtk_eth_soc-stop-passing-phylink-state-to-sgmii-.patch create mode 100644 target/linux/generic/backport-5.15/704-13-v5.19-net-mtk_eth_soc-provide-mtk_sgmii_config.patch create mode 100644 target/linux/generic/backport-5.15/704-14-v5.19-net-mtk_eth_soc-add-fixme-comment-for-state-speed-us.patch create mode 100644 target/linux/generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch create mode 100644 target/linux/generic/backport-5.15/704-16-v5.19-net-mtk_eth_soc-move-restoration-of-SYSCFG0-to-mac_f.patch create mode 100644 target/linux/generic/backport-5.15/704-17-v5.19-net-mtk_eth_soc-convert-code-structure-to-suit-split.patch create mode 100644 target/linux/generic/backport-5.15/704-18-v5.19-net-mtk_eth_soc-partially-convert-to-phylink_pcs.patch create mode 100644 target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch create mode 100644 target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch create mode 100644 target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch create mode 100644 target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch create mode 100644 target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch create mode 100644 target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch create mode 100644 target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch create mode 100644 target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch create mode 100644 target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch create mode 100644 target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch create mode 100644 target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch create mode 100644 target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch create mode 100644 target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch delete mode 100644 target/linux/mediatek/patches-5.15/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch diff --git a/target/linux/generic/backport-5.15/703-01-v5.16-net-phylink-add-MAC-phy_interface_t-bitmap.patch b/target/linux/generic/backport-5.15/703-01-v5.16-net-phylink-add-MAC-phy_interface_t-bitmap.patch new file mode 100644 index 00000000000000..b72faec8d958ae --- /dev/null +++ b/target/linux/generic/backport-5.15/703-01-v5.16-net-phylink-add-MAC-phy_interface_t-bitmap.patch @@ -0,0 +1,24 @@ +From 38c310eb46f5f80213a92093af11af270c209a76 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Tue, 26 Oct 2021 11:06:06 +0100 +Subject: [PATCH] net: phylink: add MAC phy_interface_t bitmap + +Add a phy_interface_t bitmap so the MAC driver can specifiy which PHY +interface modes it supports. + +Signed-off-by: Russell King +Signed-off-by: David S. Miller +--- + include/linux/phylink.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -76,6 +76,7 @@ struct phylink_config { + bool ovr_an_inband; + void (*get_fixed_state)(struct phylink_config *config, + struct phylink_link_state *state); ++ DECLARE_PHY_INTERFACE_MASK(supported_interfaces); + }; + + /** diff --git a/target/linux/generic/backport-5.15/703-02-v5.16-net-phylink-use-supported_interfaces-for-phylink-val.patch b/target/linux/generic/backport-5.15/703-02-v5.16-net-phylink-use-supported_interfaces-for-phylink-val.patch new file mode 100644 index 00000000000000..8996fc8d45486b --- /dev/null +++ b/target/linux/generic/backport-5.15/703-02-v5.16-net-phylink-use-supported_interfaces-for-phylink-val.patch @@ -0,0 +1,98 @@ +From d25f3a74f30aace819163dfa54f2a4b8ca1dc932 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 26 Oct 2021 11:06:11 +0100 +Subject: [PATCH] net: phylink: use supported_interfaces for phylink + validation + +If the network device supplies a supported interface bitmap, we can use +that during phylink's validation to simplify MAC drivers in two ways by +using the supported_interfaces bitmap to: + +1. reject unsupported interfaces before calling into the MAC driver. +2. generate the set of all supported link modes across all supported + interfaces (used mainly for SFP, but also some 10G PHYs.) + +Suggested-by: Sean Anderson +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 36 ++++++++++++++++++++++++++++++++++++ + include/linux/phylink.h | 12 ++++++++++-- + 2 files changed, 46 insertions(+), 2 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -155,9 +155,45 @@ static const char *phylink_an_mode_str(u + return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown"; + } + ++static int phylink_validate_any(struct phylink *pl, unsigned long *supported, ++ struct phylink_link_state *state) ++{ ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(all_adv) = { 0, }; ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(all_s) = { 0, }; ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(s); ++ struct phylink_link_state t; ++ int intf; ++ ++ for (intf = 0; intf < PHY_INTERFACE_MODE_MAX; intf++) { ++ if (test_bit(intf, pl->config->supported_interfaces)) { ++ linkmode_copy(s, supported); ++ ++ t = *state; ++ t.interface = intf; ++ pl->mac_ops->validate(pl->config, s, &t); ++ linkmode_or(all_s, all_s, s); ++ linkmode_or(all_adv, all_adv, t.advertising); ++ } ++ } ++ ++ linkmode_copy(supported, all_s); ++ linkmode_copy(state->advertising, all_adv); ++ ++ return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; ++} ++ + static int phylink_validate(struct phylink *pl, unsigned long *supported, + struct phylink_link_state *state) + { ++ if (!phy_interface_empty(pl->config->supported_interfaces)) { ++ if (state->interface == PHY_INTERFACE_MODE_NA) ++ return phylink_validate_any(pl, supported, state); ++ ++ if (!test_bit(state->interface, ++ pl->config->supported_interfaces)) ++ return -EINVAL; ++ } ++ + pl->mac_ops->validate(pl->config, supported, state); + + return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -67,6 +67,8 @@ enum phylink_op_type { + * @ovr_an_inband: if true, override PCS to MLO_AN_INBAND + * @get_fixed_state: callback to execute to determine the fixed link state, + * if MAC link is at %MLO_AN_FIXED mode. ++ * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx ++ * are supported by the MAC/PCS. + */ + struct phylink_config { + struct device *dev; +@@ -134,8 +136,14 @@ struct phylink_mac_ops { + * based on @state->advertising and/or @state->speed and update + * @state->interface accordingly. See phylink_helper_basex_speed(). + * +- * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink expects the +- * MAC driver to return all supported link modes. ++ * When @config->supported_interfaces has been set, phylink will iterate ++ * over the supported interfaces to determine the full capability of the ++ * MAC. The validation function must not print errors if @state->interface ++ * is set to an unexpected value. ++ * ++ * When @config->supported_interfaces is empty, phylink will call this ++ * function with @state->interface set to %PHY_INTERFACE_MODE_NA, and ++ * expects the MAC driver to return all supported link modes. + * + * If the @state->interface mode is not supported, then the @supported + * mask must be cleared. diff --git a/target/linux/generic/backport-5.15/703-03-v5.16-net-dsa-populate-supported_interfaces-member.patch b/target/linux/generic/backport-5.15/703-03-v5.16-net-dsa-populate-supported_interfaces-member.patch new file mode 100644 index 00000000000000..83d1f7ee7c0ab5 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-03-v5.16-net-dsa-populate-supported_interfaces-member.patch @@ -0,0 +1,63 @@ +From c07c6e8eb4b38bae921f9e2f108d1e7f8e14226e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Beh=C3=BAn?= +Date: Thu, 28 Oct 2021 18:00:14 +0100 +Subject: [PATCH] net: dsa: populate supported_interfaces member +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add a new DSA switch operation, phylink_get_interfaces, which should +fill in which PHY_INTERFACE_MODE_* are supported by given port. + +Use this before phylink_create() to fill phylinks supported_interfaces +member, allowing phylink to determine which PHY_INTERFACE_MODEs are +supported. + +Signed-off-by: Marek Behún +[tweaked patch and description to add more complete support -- rmk] +Signed-off-by: Russell King +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + include/net/dsa.h | 2 ++ + net/dsa/port.c | 4 ++++ + net/dsa/slave.c | 4 ++++ + 3 files changed, 10 insertions(+) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -626,6 +626,8 @@ struct dsa_switch_ops { + /* + * PHYLINK integration + */ ++ void (*phylink_get_interfaces)(struct dsa_switch *ds, int port, ++ unsigned long *supported_interfaces); + void (*phylink_validate)(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state); +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1172,6 +1172,10 @@ static int dsa_port_phylink_register(str + dp->pl_config.type = PHYLINK_DEV; + dp->pl_config.pcs_poll = ds->pcs_poll; + ++ if (ds->ops->phylink_get_interfaces) ++ ds->ops->phylink_get_interfaces(ds, dp->index, ++ dp->pl_config.supported_interfaces); ++ + dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(port_dn), + mode, &dsa_port_phylink_mac_ops); + if (IS_ERR(dp->pl)) { +--- a/net/dsa/slave.c ++++ b/net/dsa/slave.c +@@ -1837,6 +1837,10 @@ static int dsa_slave_phy_setup(struct ne + dp->pl_config.poll_fixed_state = true; + } + ++ if (ds->ops->phylink_get_interfaces) ++ ds->ops->phylink_get_interfaces(ds, dp->index, ++ dp->pl_config.supported_interfaces); ++ + dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(port_dn), mode, + &dsa_port_phylink_mac_ops); + if (IS_ERR(dp->pl)) { diff --git a/target/linux/generic/backport-5.15/703-04-v5.17-net-dsa-consolidate-phylink-creation.patch b/target/linux/generic/backport-5.15/703-04-v5.17-net-dsa-consolidate-phylink-creation.patch new file mode 100644 index 00000000000000..8b58c8331230be --- /dev/null +++ b/target/linux/generic/backport-5.15/703-04-v5.17-net-dsa-consolidate-phylink-creation.patch @@ -0,0 +1,149 @@ +From 21bd64bd717dedac96f53b668144cbe37d3c12d4 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 30 Nov 2021 13:09:55 +0000 +Subject: [PATCH] net: dsa: consolidate phylink creation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The code in port.c and slave.c creating the phylink instance is very +similar - let's consolidate this into a single function. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Marek Behún +Reviewed-by: Andrew Lunn +Signed-off-by: Jakub Kicinski +--- + net/dsa/dsa_priv.h | 2 +- + net/dsa/port.c | 44 ++++++++++++++++++++++++++++---------------- + net/dsa/slave.c | 19 +++---------------- + 3 files changed, 32 insertions(+), 33 deletions(-) + +--- a/net/dsa/dsa_priv.h ++++ b/net/dsa/dsa_priv.h +@@ -260,13 +260,13 @@ int dsa_port_mrp_add_ring_role(const str + const struct switchdev_obj_ring_role_mrp *mrp); + int dsa_port_mrp_del_ring_role(const struct dsa_port *dp, + const struct switchdev_obj_ring_role_mrp *mrp); ++int dsa_port_phylink_create(struct dsa_port *dp); + int dsa_port_link_register_of(struct dsa_port *dp); + void dsa_port_link_unregister_of(struct dsa_port *dp); + int dsa_port_hsr_join(struct dsa_port *dp, struct net_device *hsr); + void dsa_port_hsr_leave(struct dsa_port *dp, struct net_device *hsr); + int dsa_port_tag_8021q_vlan_add(struct dsa_port *dp, u16 vid, bool broadcast); + void dsa_port_tag_8021q_vlan_del(struct dsa_port *dp, u16 vid, bool broadcast); +-extern const struct phylink_mac_ops dsa_port_phylink_mac_ops; + + static inline bool dsa_port_offloads_bridge_port(struct dsa_port *dp, + const struct net_device *dev) +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1076,7 +1076,7 @@ static void dsa_port_phylink_mac_link_up + speed, duplex, tx_pause, rx_pause); + } + +-const struct phylink_mac_ops dsa_port_phylink_mac_ops = { ++static const struct phylink_mac_ops dsa_port_phylink_mac_ops = { + .validate = dsa_port_phylink_validate, + .mac_pcs_get_state = dsa_port_phylink_mac_pcs_get_state, + .mac_config = dsa_port_phylink_mac_config, +@@ -1085,6 +1085,30 @@ const struct phylink_mac_ops dsa_port_ph + .mac_link_up = dsa_port_phylink_mac_link_up, + }; + ++int dsa_port_phylink_create(struct dsa_port *dp) ++{ ++ struct dsa_switch *ds = dp->ds; ++ phy_interface_t mode; ++ int err; ++ ++ err = of_get_phy_mode(dp->dn, &mode); ++ if (err) ++ mode = PHY_INTERFACE_MODE_NA; ++ ++ if (ds->ops->phylink_get_interfaces) ++ ds->ops->phylink_get_interfaces(ds, dp->index, ++ dp->pl_config.supported_interfaces); ++ ++ dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), ++ mode, &dsa_port_phylink_mac_ops); ++ if (IS_ERR(dp->pl)) { ++ pr_err("error creating PHYLINK: %ld\n", PTR_ERR(dp->pl)); ++ return PTR_ERR(dp->pl); ++ } ++ ++ return 0; ++} ++ + static int dsa_port_setup_phy_of(struct dsa_port *dp, bool enable) + { + struct dsa_switch *ds = dp->ds; +@@ -1161,27 +1185,15 @@ static int dsa_port_phylink_register(str + { + struct dsa_switch *ds = dp->ds; + struct device_node *port_dn = dp->dn; +- phy_interface_t mode; + int err; + +- err = of_get_phy_mode(port_dn, &mode); +- if (err) +- mode = PHY_INTERFACE_MODE_NA; +- + dp->pl_config.dev = ds->dev; + dp->pl_config.type = PHYLINK_DEV; + dp->pl_config.pcs_poll = ds->pcs_poll; + +- if (ds->ops->phylink_get_interfaces) +- ds->ops->phylink_get_interfaces(ds, dp->index, +- dp->pl_config.supported_interfaces); +- +- dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(port_dn), +- mode, &dsa_port_phylink_mac_ops); +- if (IS_ERR(dp->pl)) { +- pr_err("error creating PHYLINK: %ld\n", PTR_ERR(dp->pl)); +- return PTR_ERR(dp->pl); +- } ++ err = dsa_port_phylink_create(dp); ++ if (err) ++ return err; + + err = phylink_of_phy_connect(dp->pl, port_dn, 0); + if (err && err != -ENODEV) { +--- a/net/dsa/slave.c ++++ b/net/dsa/slave.c +@@ -1817,14 +1817,9 @@ static int dsa_slave_phy_setup(struct ne + struct dsa_port *dp = dsa_slave_to_port(slave_dev); + struct device_node *port_dn = dp->dn; + struct dsa_switch *ds = dp->ds; +- phy_interface_t mode; + u32 phy_flags = 0; + int ret; + +- ret = of_get_phy_mode(port_dn, &mode); +- if (ret) +- mode = PHY_INTERFACE_MODE_NA; +- + dp->pl_config.dev = &slave_dev->dev; + dp->pl_config.type = PHYLINK_NETDEV; + +@@ -1837,17 +1832,9 @@ static int dsa_slave_phy_setup(struct ne + dp->pl_config.poll_fixed_state = true; + } + +- if (ds->ops->phylink_get_interfaces) +- ds->ops->phylink_get_interfaces(ds, dp->index, +- dp->pl_config.supported_interfaces); +- +- dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(port_dn), mode, +- &dsa_port_phylink_mac_ops); +- if (IS_ERR(dp->pl)) { +- netdev_err(slave_dev, +- "error creating PHYLINK: %ld\n", PTR_ERR(dp->pl)); +- return PTR_ERR(dp->pl); +- } ++ ret = dsa_port_phylink_create(dp); ++ if (ret) ++ return ret; + + if (ds->ops->get_phy_flags) + phy_flags = ds->ops->get_phy_flags(ds, dp->index); diff --git a/target/linux/generic/backport-5.15/703-05-v5.17-net-dsa-replace-phylink_get_interfaces-with-phylink_.patch b/target/linux/generic/backport-5.15/703-05-v5.17-net-dsa-replace-phylink_get_interfaces-with-phylink_.patch new file mode 100644 index 00000000000000..4cea5994da2dc5 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-05-v5.17-net-dsa-replace-phylink_get_interfaces-with-phylink_.patch @@ -0,0 +1,51 @@ +From 072eea6c22b2af680c3949e64f9adde278c71e68 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 30 Nov 2021 13:10:01 +0000 +Subject: [PATCH] net: dsa: replace phylink_get_interfaces() with + phylink_get_caps() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Phylink needs slightly more information than phylink_get_interfaces() +allows us to get from the DSA drivers - we need the MAC capabilities. +Replace the phylink_get_interfaces() method with phylink_get_caps() to +allow DSA drivers to fill in the phylink_config MAC capabilities field +as well. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Marek Behún +Reviewed-by: Andrew Lunn +Signed-off-by: Jakub Kicinski +--- + include/net/dsa.h | 4 ++-- + net/dsa/port.c | 5 ++--- + 2 files changed, 4 insertions(+), 5 deletions(-) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -626,8 +626,8 @@ struct dsa_switch_ops { + /* + * PHYLINK integration + */ +- void (*phylink_get_interfaces)(struct dsa_switch *ds, int port, +- unsigned long *supported_interfaces); ++ void (*phylink_get_caps)(struct dsa_switch *ds, int port, ++ struct phylink_config *config); + void (*phylink_validate)(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state); +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1095,9 +1095,8 @@ int dsa_port_phylink_create(struct dsa_p + if (err) + mode = PHY_INTERFACE_MODE_NA; + +- if (ds->ops->phylink_get_interfaces) +- ds->ops->phylink_get_interfaces(ds, dp->index, +- dp->pl_config.supported_interfaces); ++ if (ds->ops->phylink_get_caps) ++ ds->ops->phylink_get_caps(ds, dp->index, &dp->pl_config); + + dp->pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), + mode, &dsa_port_phylink_mac_ops); diff --git a/target/linux/generic/backport-5.15/703-06-v5.18-net-dsa-add-support-for-phylink-mac_select_pcs.patch b/target/linux/generic/backport-5.15/703-06-v5.18-net-dsa-add-support-for-phylink-mac_select_pcs.patch new file mode 100644 index 00000000000000..a28d14d27a3c2a --- /dev/null +++ b/target/linux/generic/backport-5.15/703-06-v5.18-net-dsa-add-support-for-phylink-mac_select_pcs.patch @@ -0,0 +1,59 @@ +From bde018222c6b084ac32933a9f933581dd83da18e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 17 Feb 2022 18:30:35 +0000 +Subject: [PATCH] net: dsa: add support for phylink mac_select_pcs() + +Add DSA support for the phylink mac_select_pcs() method so DSA drivers +can return provide phylink with the appropriate PCS for the PHY +interface mode. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + include/net/dsa.h | 3 +++ + net/dsa/port.c | 15 +++++++++++++++ + 2 files changed, 18 insertions(+) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -631,6 +631,9 @@ struct dsa_switch_ops { + void (*phylink_validate)(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state); ++ struct phylink_pcs *(*phylink_mac_select_pcs)(struct dsa_switch *ds, ++ int port, ++ phy_interface_t iface); + int (*phylink_mac_link_state)(struct dsa_switch *ds, int port, + struct phylink_link_state *state); + void (*phylink_mac_config)(struct dsa_switch *ds, int port, +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1012,6 +1012,20 @@ static void dsa_port_phylink_mac_pcs_get + } + } + ++static struct phylink_pcs * ++dsa_port_phylink_mac_select_pcs(struct phylink_config *config, ++ phy_interface_t interface) ++{ ++ struct dsa_port *dp = container_of(config, struct dsa_port, pl_config); ++ struct dsa_switch *ds = dp->ds; ++ struct phylink_pcs *pcs = NULL; ++ ++ if (ds->ops->phylink_mac_select_pcs) ++ pcs = ds->ops->phylink_mac_select_pcs(ds, dp->index, interface); ++ ++ return pcs; ++} ++ + static void dsa_port_phylink_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +@@ -1078,6 +1092,7 @@ static void dsa_port_phylink_mac_link_up + + static const struct phylink_mac_ops dsa_port_phylink_mac_ops = { + .validate = dsa_port_phylink_validate, ++ .mac_select_pcs = dsa_port_phylink_mac_select_pcs, + .mac_pcs_get_state = dsa_port_phylink_mac_pcs_get_state, + .mac_config = dsa_port_phylink_mac_config, + .mac_an_restart = dsa_port_phylink_mac_an_restart, diff --git a/target/linux/generic/backport-5.15/703-07-v5.16-net-phy-add-phy_interface_t-bitmap-support.patch b/target/linux/generic/backport-5.15/703-07-v5.16-net-phy-add-phy_interface_t-bitmap-support.patch new file mode 100644 index 00000000000000..1a7817b0f96db0 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-07-v5.16-net-phy-add-phy_interface_t-bitmap-support.patch @@ -0,0 +1,61 @@ +From 8e20f591f204f8db7f1182918f8e2285d3f589e0 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 26 Oct 2021 11:06:01 +0100 +Subject: [PATCH] net: phy: add phy_interface_t bitmap support + +Add support for a bitmap for phy interface modes, which includes: +- a macro to declare the interface bitmap +- an inline helper to zero the interface bitmap +- an inline helper to detect an empty interface bitmap +- inline helpers to do a bitwise AND and OR operations on two interface + bitmaps + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + include/linux/phy.h | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -155,6 +155,40 @@ typedef enum { + PHY_INTERFACE_MODE_MAX, + } phy_interface_t; + ++/* PHY interface mode bitmap handling */ ++#define DECLARE_PHY_INTERFACE_MASK(name) \ ++ DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX) ++ ++static inline void phy_interface_zero(unsigned long *intf) ++{ ++ bitmap_zero(intf, PHY_INTERFACE_MODE_MAX); ++} ++ ++static inline bool phy_interface_empty(const unsigned long *intf) ++{ ++ return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX); ++} ++ ++static inline void phy_interface_and(unsigned long *dst, const unsigned long *a, ++ const unsigned long *b) ++{ ++ bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX); ++} ++ ++static inline void phy_interface_or(unsigned long *dst, const unsigned long *a, ++ const unsigned long *b) ++{ ++ bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX); ++} ++ ++static inline void phy_interface_set_rgmii(unsigned long *intf) ++{ ++ __set_bit(PHY_INTERFACE_MODE_RGMII, intf); ++ __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf); ++ __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf); ++ __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf); ++} ++ + /* + * phy_supported_speeds - return all speeds currently supported by a PHY device + */ diff --git a/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch b/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch new file mode 100644 index 00000000000000..e1cfc3f4397a5d --- /dev/null +++ b/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch @@ -0,0 +1,197 @@ +From d1e86325af377129adb7fc6f34eb044ca6068b47 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 15 Dec 2021 15:34:15 +0000 +Subject: [PATCH] net: phylink: add mac_select_pcs() method to phylink_mac_ops + +mac_select_pcs() allows us to have an explicit point to query which +PCS the MAC wishes to use for a particular PHY interface mode, thereby +allowing us to add support to validate the link settings with the PCS. + +Phylink will also use this to select the PCS to be used during a major +configuration event without the MAC driver needing to call +phylink_set_pcs(). + +Note that if mac_select_pcs() is present, the supported_interfaces +bitmap must be filled in; this avoids mac_select_pcs() being called +with PHY_INTERFACE_MODE_NA when we want to get support for all +interface types. Phylink will return an error in phylink_create() +unless this condition is satisfied. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 68 +++++++++++++++++++++++++++++++++------ + include/linux/phylink.h | 18 +++++++++++ + 2 files changed, 77 insertions(+), 9 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -155,6 +155,23 @@ static const char *phylink_an_mode_str(u + return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown"; + } + ++static int phylink_validate_mac_and_pcs(struct phylink *pl, ++ unsigned long *supported, ++ struct phylink_link_state *state) ++{ ++ struct phylink_pcs *pcs; ++ ++ if (pl->mac_ops->mac_select_pcs) { ++ pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); ++ if (IS_ERR(pcs)) ++ return PTR_ERR(pcs); ++ } ++ ++ pl->mac_ops->validate(pl->config, supported, state); ++ ++ return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; ++} ++ + static int phylink_validate_any(struct phylink *pl, unsigned long *supported, + struct phylink_link_state *state) + { +@@ -170,9 +187,10 @@ static int phylink_validate_any(struct p + + t = *state; + t.interface = intf; +- pl->mac_ops->validate(pl->config, s, &t); +- linkmode_or(all_s, all_s, s); +- linkmode_or(all_adv, all_adv, t.advertising); ++ if (!phylink_validate_mac_and_pcs(pl, s, &t)) { ++ linkmode_or(all_s, all_s, s); ++ linkmode_or(all_adv, all_adv, t.advertising); ++ } + } + } + +@@ -194,9 +212,7 @@ static int phylink_validate(struct phyli + return -EINVAL; + } + +- pl->mac_ops->validate(pl->config, supported, state); +- +- return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; ++ return phylink_validate_mac_and_pcs(pl, supported, state); + } + + static int phylink_parse_fixedlink(struct phylink *pl, +@@ -486,10 +502,21 @@ static void phylink_mac_pcs_an_restart(s + static void phylink_major_config(struct phylink *pl, bool restart, + const struct phylink_link_state *state) + { ++ struct phylink_pcs *pcs = NULL; + int err; + + phylink_dbg(pl, "major config %s\n", phy_modes(state->interface)); + ++ if (pl->mac_ops->mac_select_pcs) { ++ pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); ++ if (IS_ERR(pcs)) { ++ phylink_err(pl, ++ "mac_select_pcs unexpectedly failed: %pe\n", ++ pcs); ++ return; ++ } ++ } ++ + if (pl->mac_ops->mac_prepare) { + err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode, + state->interface); +@@ -500,6 +527,12 @@ static void phylink_major_config(struct + } + } + ++ /* If we have a new PCS, switch to the new PCS after preparing the MAC ++ * for the change. ++ */ ++ if (pcs) ++ phylink_set_pcs(pl, pcs); ++ + phylink_mac_config(pl, state); + + if (pl->pcs_ops) { +@@ -879,6 +912,14 @@ struct phylink *phylink_create(struct ph + struct phylink *pl; + int ret; + ++ /* Validate the supplied configuration */ ++ if (mac_ops->mac_select_pcs && ++ phy_interface_empty(config->supported_interfaces)) { ++ dev_err(config->dev, ++ "phylink: error: empty supported_interfaces but mac_select_pcs() method present\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ + pl = kzalloc(sizeof(*pl), GFP_KERNEL); + if (!pl) + return ERR_PTR(-ENOMEM); +@@ -946,9 +987,10 @@ EXPORT_SYMBOL_GPL(phylink_create); + * @pl: a pointer to a &struct phylink returned from phylink_create() + * @pcs: a pointer to the &struct phylink_pcs + * +- * Bind the MAC PCS to phylink. This may be called after phylink_create(), +- * in mac_prepare() or mac_config() methods if it is desired to dynamically +- * change the PCS. ++ * Bind the MAC PCS to phylink. This may be called after phylink_create(). ++ * If it is desired to dynamically change the PCS, then the preferred method ++ * is to use mac_select_pcs(), but it may also be called in mac_prepare() ++ * or mac_config(). + * + * Please note that there are behavioural changes with the mac_config() + * callback if a PCS is present (denoting a newer setup) so removing a PCS +@@ -959,6 +1001,14 @@ void phylink_set_pcs(struct phylink *pl, + { + pl->pcs = pcs; + pl->pcs_ops = pcs->ops; ++ ++ if (!pl->phylink_disable_state && ++ pl->cfg_link_an_mode == MLO_AN_INBAND) { ++ if (pl->config->pcs_poll || pcs->poll) ++ mod_timer(&pl->link_poll, jiffies + HZ); ++ else ++ del_timer(&pl->link_poll); ++ } + } + EXPORT_SYMBOL_GPL(phylink_set_pcs); + +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -84,6 +84,7 @@ struct phylink_config { + /** + * struct phylink_mac_ops - MAC operations structure. + * @validate: Validate and update the link configuration. ++ * @mac_select_pcs: Select a PCS for the interface mode. + * @mac_pcs_get_state: Read the current link state from the hardware. + * @mac_prepare: prepare for a major reconfiguration of the interface. + * @mac_config: configure the MAC for the selected mode and state. +@@ -98,6 +99,8 @@ struct phylink_mac_ops { + void (*validate)(struct phylink_config *config, + unsigned long *supported, + struct phylink_link_state *state); ++ struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config, ++ phy_interface_t interface); + void (*mac_pcs_get_state)(struct phylink_config *config, + struct phylink_link_state *state); + int (*mac_prepare)(struct phylink_config *config, unsigned int mode, +@@ -150,6 +153,21 @@ struct phylink_mac_ops { + */ + void validate(struct phylink_config *config, unsigned long *supported, + struct phylink_link_state *state); ++/** ++ * mac_select_pcs: Select a PCS for the interface mode. ++ * @config: a pointer to a &struct phylink_config. ++ * @interface: PHY interface mode for PCS ++ * ++ * Return the &struct phylink_pcs for the specified interface mode, or ++ * NULL if none is required, or an error pointer on error. ++ * ++ * This must not modify any state. It is used to query which PCS should ++ * be used. Phylink will use this during validation to ensure that the ++ * configuration is valid, and when setting a configuration to internally ++ * set the PCS that will be used. ++ */ ++struct phylink_pcs *mac_select_pcs(struct phylink_config *config, ++ phy_interface_t interface); + + /** + * mac_pcs_get_state() - Read the current inband link state from the hardware diff --git a/target/linux/generic/backport-5.15/703-09-v5.17-net-phylink-add-generic-validate-implementation.patch b/target/linux/generic/backport-5.15/703-09-v5.17-net-phylink-add-generic-validate-implementation.patch new file mode 100644 index 00000000000000..73c8b414da5fdf --- /dev/null +++ b/target/linux/generic/backport-5.15/703-09-v5.17-net-phylink-add-generic-validate-implementation.patch @@ -0,0 +1,341 @@ +From 34ae2c09d46a2d0abd907e139b466f798e4095a8 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 15 Nov 2021 10:00:27 +0000 +Subject: [PATCH] net: phylink: add generic validate implementation + +Add a generic validate() implementation using the supported_interfaces +and a bitmask of MAC pause/speed/duplex capabilities. This allows us +to entirely eliminate many driver private validate() implementations. + +We expose the underlying phylink_get_linkmodes() function so that +drivers which have special needs can still benefit from conversion. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 252 ++++++++++++++++++++++++++++++++++++++ + include/linux/phylink.h | 31 +++++ + 2 files changed, 283 insertions(+) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -172,6 +172,258 @@ static int phylink_validate_mac_and_pcs( + return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; + } + ++static void phylink_caps_to_linkmodes(unsigned long *linkmodes, ++ unsigned long caps) ++{ ++ if (caps & MAC_SYM_PAUSE) ++ __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, linkmodes); ++ ++ if (caps & MAC_ASYM_PAUSE) ++ __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, linkmodes); ++ ++ if (caps & MAC_10HD) ++ __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, linkmodes); ++ ++ if (caps & MAC_10FD) ++ __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, linkmodes); ++ ++ if (caps & MAC_100HD) { ++ __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_100FD) { ++ __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_1000HD) ++ __set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, linkmodes); ++ ++ if (caps & MAC_1000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_2500FD) { ++ __set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_5000FD) ++ __set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, linkmodes); ++ ++ if (caps & MAC_10000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_25000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_40000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_50000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_56000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_100000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseCR_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_200000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT, linkmodes); ++ } ++ ++ if (caps & MAC_400000FD) { ++ __set_bit(ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, ++ linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, linkmodes); ++ __set_bit(ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT, linkmodes); ++ } ++} ++ ++/** ++ * phylink_get_linkmodes() - get acceptable link modes ++ * @linkmodes: ethtool linkmode mask (must be already initialised) ++ * @interface: phy interface mode defined by &typedef phy_interface_t ++ * @mac_capabilities: bitmask of MAC capabilities ++ * ++ * Set all possible pause, speed and duplex linkmodes in @linkmodes that ++ * are supported by the @interface mode and @mac_capabilities. @linkmodes ++ * must have been initialised previously. ++ */ ++void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface, ++ unsigned long mac_capabilities) ++{ ++ unsigned long caps = MAC_SYM_PAUSE | MAC_ASYM_PAUSE; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; ++ fallthrough; ++ ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_GMII: ++ caps |= MAC_1000HD | MAC_1000FD; ++ fallthrough; ++ ++ case PHY_INTERFACE_MODE_REVRMII: ++ case PHY_INTERFACE_MODE_RMII: ++ case PHY_INTERFACE_MODE_REVMII: ++ case PHY_INTERFACE_MODE_MII: ++ caps |= MAC_10HD | MAC_10FD; ++ fallthrough; ++ ++ case PHY_INTERFACE_MODE_100BASEX: ++ caps |= MAC_100HD | MAC_100FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_TBI: ++ case PHY_INTERFACE_MODE_MOCA: ++ case PHY_INTERFACE_MODE_RTBI: ++ case PHY_INTERFACE_MODE_1000BASEX: ++ caps |= MAC_1000HD; ++ fallthrough; ++ case PHY_INTERFACE_MODE_TRGMII: ++ caps |= MAC_1000FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_2500BASEX: ++ caps |= MAC_2500FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_5GBASER: ++ caps |= MAC_5000FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_XGMII: ++ case PHY_INTERFACE_MODE_RXAUI: ++ case PHY_INTERFACE_MODE_XAUI: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_10GKR: ++ caps |= MAC_10000FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_25GBASER: ++ caps |= MAC_25000FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_XLGMII: ++ caps |= MAC_40000FD; ++ break; ++ ++ case PHY_INTERFACE_MODE_INTERNAL: ++ caps |= ~0; ++ break; ++ ++ case PHY_INTERFACE_MODE_NA: ++ case PHY_INTERFACE_MODE_MAX: ++ case PHY_INTERFACE_MODE_SMII: ++ break; ++ } ++ ++ phylink_caps_to_linkmodes(linkmodes, caps & mac_capabilities); ++} ++EXPORT_SYMBOL_GPL(phylink_get_linkmodes); ++ ++/** ++ * phylink_generic_validate() - generic validate() callback implementation ++ * @config: a pointer to a &struct phylink_config. ++ * @supported: ethtool bitmask for supported link modes. ++ * @state: a pointer to a &struct phylink_link_state. ++ * ++ * Generic implementation of the validate() callback that MAC drivers can ++ * use when they pass the range of supported interfaces and MAC capabilities. ++ * This makes use of phylink_get_linkmodes(). ++ */ ++void phylink_generic_validate(struct phylink_config *config, ++ unsigned long *supported, ++ struct phylink_link_state *state) ++{ ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; ++ ++ phylink_set_port_modes(mask); ++ phylink_set(mask, Autoneg); ++ phylink_get_linkmodes(mask, state->interface, config->mac_capabilities); ++ ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); ++} ++EXPORT_SYMBOL_GPL(phylink_generic_validate); ++ + static int phylink_validate_any(struct phylink *pl, unsigned long *supported, + struct phylink_link_state *state) + { +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -20,6 +20,29 @@ enum { + MLO_AN_PHY = 0, /* Conventional PHY */ + MLO_AN_FIXED, /* Fixed-link mode */ + MLO_AN_INBAND, /* In-band protocol */ ++ ++ MAC_SYM_PAUSE = BIT(0), ++ MAC_ASYM_PAUSE = BIT(1), ++ MAC_10HD = BIT(2), ++ MAC_10FD = BIT(3), ++ MAC_10 = MAC_10HD | MAC_10FD, ++ MAC_100HD = BIT(4), ++ MAC_100FD = BIT(5), ++ MAC_100 = MAC_100HD | MAC_100FD, ++ MAC_1000HD = BIT(6), ++ MAC_1000FD = BIT(7), ++ MAC_1000 = MAC_1000HD | MAC_1000FD, ++ MAC_2500FD = BIT(8), ++ MAC_5000FD = BIT(9), ++ MAC_10000FD = BIT(10), ++ MAC_20000FD = BIT(11), ++ MAC_25000FD = BIT(12), ++ MAC_40000FD = BIT(13), ++ MAC_50000FD = BIT(14), ++ MAC_56000FD = BIT(15), ++ MAC_100000FD = BIT(16), ++ MAC_200000FD = BIT(17), ++ MAC_400000FD = BIT(18), + }; + + static inline bool phylink_autoneg_inband(unsigned int mode) +@@ -69,6 +92,7 @@ enum phylink_op_type { + * if MAC link is at %MLO_AN_FIXED mode. + * @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx + * are supported by the MAC/PCS. ++ * @mac_capabilities: MAC pause/speed/duplex capabilities. + */ + struct phylink_config { + struct device *dev; +@@ -79,6 +103,7 @@ struct phylink_config { + void (*get_fixed_state)(struct phylink_config *config, + struct phylink_link_state *state); + DECLARE_PHY_INTERFACE_MASK(supported_interfaces); ++ unsigned long mac_capabilities; + }; + + /** +@@ -460,6 +485,12 @@ void pcs_link_up(struct phylink_pcs *pcs + phy_interface_t interface, int speed, int duplex); + #endif + ++void phylink_get_linkmodes(unsigned long *linkmodes, phy_interface_t interface, ++ unsigned long mac_capabilities); ++void phylink_generic_validate(struct phylink_config *config, ++ unsigned long *supported, ++ struct phylink_link_state *state); ++ + struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *, + phy_interface_t iface, + const struct phylink_mac_ops *mac_ops); diff --git a/target/linux/generic/backport-5.15/703-10-v5.16-net-dsa-introduce-helpers-for-iterating-through-port.patch b/target/linux/generic/backport-5.15/703-10-v5.16-net-dsa-introduce-helpers-for-iterating-through-port.patch new file mode 100644 index 00000000000000..a55623519ce960 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-10-v5.16-net-dsa-introduce-helpers-for-iterating-through-port.patch @@ -0,0 +1,68 @@ +From 82b318983c515f29b8b3a0dad9f6a5fe8a68a7f4 Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean +Date: Wed, 20 Oct 2021 20:49:49 +0300 +Subject: [PATCH] net: dsa: introduce helpers for iterating through ports using + dp + +Since the DSA conversion from the ds->ports array into the dst->ports +list, the DSA API has encouraged driver writers, as well as the core +itself, to write inefficient code. + +Currently, code that wants to filter by a specific type of port when +iterating, like {!unused, user, cpu, dsa}, uses the dsa_is_*_port helper. +Under the hood, this uses dsa_to_port which iterates again through +dst->ports. But the driver iterates through the port list already, so +the complexity is quadratic for the typical case of a single-switch +tree. + +This patch introduces some iteration helpers where the iterator is +already a struct dsa_port *dp, so that the other variant of the +filtering functions, dsa_port_is_{unused,user,cpu_dsa}, can be used +directly on the iterator. This eliminates the second lookup. + +These functions can be used both by the core and by drivers. + +Signed-off-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Signed-off-by: David S. Miller +--- + include/net/dsa.h | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/include/net/dsa.h ++++ b/include/net/dsa.h +@@ -476,6 +476,34 @@ static inline bool dsa_is_user_port(stru + return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_USER; + } + ++#define dsa_tree_for_each_user_port(_dp, _dst) \ ++ list_for_each_entry((_dp), &(_dst)->ports, list) \ ++ if (dsa_port_is_user((_dp))) ++ ++#define dsa_switch_for_each_port(_dp, _ds) \ ++ list_for_each_entry((_dp), &(_ds)->dst->ports, list) \ ++ if ((_dp)->ds == (_ds)) ++ ++#define dsa_switch_for_each_port_safe(_dp, _next, _ds) \ ++ list_for_each_entry_safe((_dp), (_next), &(_ds)->dst->ports, list) \ ++ if ((_dp)->ds == (_ds)) ++ ++#define dsa_switch_for_each_port_continue_reverse(_dp, _ds) \ ++ list_for_each_entry_continue_reverse((_dp), &(_ds)->dst->ports, list) \ ++ if ((_dp)->ds == (_ds)) ++ ++#define dsa_switch_for_each_available_port(_dp, _ds) \ ++ dsa_switch_for_each_port((_dp), (_ds)) \ ++ if (!dsa_port_is_unused((_dp))) ++ ++#define dsa_switch_for_each_user_port(_dp, _ds) \ ++ dsa_switch_for_each_port((_dp), (_ds)) \ ++ if (dsa_port_is_user((_dp))) ++ ++#define dsa_switch_for_each_cpu_port(_dp, _ds) \ ++ dsa_switch_for_each_port((_dp), (_ds)) \ ++ if (dsa_port_is_cpu((_dp))) ++ + static inline u32 dsa_user_ports(struct dsa_switch *ds) + { + u32 mask = 0; diff --git a/target/linux/generic/backport-5.15/703-11-v5.17-net-phylink-add-pcs_validate-method.patch b/target/linux/generic/backport-5.15/703-11-v5.17-net-phylink-add-pcs_validate-method.patch new file mode 100644 index 00000000000000..add2e6e352ba05 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-11-v5.17-net-phylink-add-pcs_validate-method.patch @@ -0,0 +1,106 @@ +From 0d22d4b626a4eaa3196019092eb6c1919e9f8caa Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 15 Dec 2021 15:34:20 +0000 +Subject: [PATCH] net: phylink: add pcs_validate() method + +Add a hook for PCS to validate the link parameters. This avoids MAC +drivers having to have knowledge of their PCS in their validate() +method, thereby allowing several MAC drivers to be simplfied. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/phy/phylink.c | 31 +++++++++++++++++++++++++++++++ + include/linux/phylink.h | 20 ++++++++++++++++++++ + 2 files changed, 51 insertions(+) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -160,13 +160,44 @@ static int phylink_validate_mac_and_pcs( + struct phylink_link_state *state) + { + struct phylink_pcs *pcs; ++ int ret; + ++ /* Get the PCS for this interface mode */ + if (pl->mac_ops->mac_select_pcs) { + pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); + if (IS_ERR(pcs)) + return PTR_ERR(pcs); ++ } else { ++ pcs = pl->pcs; + } + ++ if (pcs) { ++ /* The PCS, if present, must be setup before phylink_create() ++ * has been called. If the ops is not initialised, print an ++ * error and backtrace rather than oopsing the kernel. ++ */ ++ if (!pcs->ops) { ++ phylink_err(pl, "interface %s: uninitialised PCS\n", ++ phy_modes(state->interface)); ++ dump_stack(); ++ return -EINVAL; ++ } ++ ++ /* Validate the link parameters with the PCS */ ++ if (pcs->ops->pcs_validate) { ++ ret = pcs->ops->pcs_validate(pcs, supported, state); ++ if (ret < 0 || phylink_is_empty_linkmode(supported)) ++ return -EINVAL; ++ ++ /* Ensure the advertising mask is a subset of the ++ * supported mask. ++ */ ++ linkmode_and(state->advertising, state->advertising, ++ supported); ++ } ++ } ++ ++ /* Then validate the link parameters with the MAC */ + pl->mac_ops->validate(pl->config, supported, state); + + return phylink_is_empty_linkmode(supported) ? -EINVAL : 0; +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -396,6 +396,7 @@ struct phylink_pcs { + + /** + * struct phylink_pcs_ops - MAC PCS operations structure. ++ * @pcs_validate: validate the link configuration. + * @pcs_get_state: read the current MAC PCS link state from the hardware. + * @pcs_config: configure the MAC PCS for the selected mode and state. + * @pcs_an_restart: restart 802.3z BaseX autonegotiation. +@@ -403,6 +404,8 @@ struct phylink_pcs { + * (where necessary). + */ + struct phylink_pcs_ops { ++ int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, ++ const struct phylink_link_state *state); + void (*pcs_get_state)(struct phylink_pcs *pcs, + struct phylink_link_state *state); + int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode, +@@ -416,6 +419,23 @@ struct phylink_pcs_ops { + + #if 0 /* For kernel-doc purposes only. */ + /** ++ * pcs_validate() - validate the link configuration. ++ * @pcs: a pointer to a &struct phylink_pcs. ++ * @supported: ethtool bitmask for supported link modes. ++ * @state: a const pointer to a &struct phylink_link_state. ++ * ++ * Validate the interface mode, and advertising's autoneg bit, removing any ++ * media ethtool link modes that would not be supportable from the supported ++ * mask. Phylink will propagate the changes to the advertising mask. See the ++ * &struct phylink_mac_ops validate() method. ++ * ++ * Returns -EINVAL if the interface mode/autoneg mode is not supported. ++ * Returns non-zero positive if the link state can be supported. ++ */ ++int pcs_validate(struct phylink_pcs *pcs, unsigned long *supported, ++ const struct phylink_link_state *state); ++ ++/** + * pcs_get_state() - Read the current inband link state from the hardware + * @pcs: a pointer to a &struct phylink_pcs. + * @state: a pointer to a &struct phylink_link_state. diff --git a/target/linux/generic/backport-5.15/703-12-v5.17-net-phylink-add-legacy_pre_march2020-indicator.patch b/target/linux/generic/backport-5.15/703-12-v5.17-net-phylink-add-legacy_pre_march2020-indicator.patch new file mode 100644 index 00000000000000..6fbde1250784a6 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-12-v5.17-net-phylink-add-legacy_pre_march2020-indicator.patch @@ -0,0 +1,43 @@ +From 3e5b1feccea7db576353ffc302f78d522e4116e6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 9 Dec 2021 13:11:32 +0000 +Subject: [PATCH] net: phylink: add legacy_pre_march2020 indicator + +Add a boolean to phylink_config to indicate whether a driver has not +been updated for the changes in commit 7cceb599d15d ("net: phylink: +avoid mac_config calls"), and thus are reliant on the old behaviour. + +We were currently keying the phylink behaviour on the presence of a +PCS, but this is sub-optimal for modern drivers that may not have a +PCS. + +This commit merely introduces the new flag, but does not add any use, +since we need all legacy drivers to set this flag before it can be +used. Once these legacy drivers have been updated, we can remove this +flag. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + include/linux/phylink.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -84,6 +84,8 @@ enum phylink_op_type { + * struct phylink_config - PHYLINK configuration structure + * @dev: a pointer to a struct device associated with the MAC + * @type: operation type of PHYLINK instance ++ * @legacy_pre_march2020: driver has not been updated for March 2020 updates ++ * (See commit 7cceb599d15d ("net: phylink: avoid mac_config calls") + * @pcs_poll: MAC PCS cannot provide link change interrupt + * @poll_fixed_state: if true, starts link_poll, + * if MAC link is at %MLO_AN_FIXED mode. +@@ -97,6 +99,7 @@ enum phylink_op_type { + struct phylink_config { + struct device *dev; + enum phylink_op_type type; ++ bool legacy_pre_march2020; + bool pcs_poll; + bool poll_fixed_state; + bool ovr_an_inband; diff --git a/target/linux/generic/backport-5.15/703-13-v5.17-net-dsa-mark-DSA-phylink-as-legacy_pre_march2020.patch b/target/linux/generic/backport-5.15/703-13-v5.17-net-dsa-mark-DSA-phylink-as-legacy_pre_march2020.patch new file mode 100644 index 00000000000000..dff0db5db659ff --- /dev/null +++ b/target/linux/generic/backport-5.15/703-13-v5.17-net-dsa-mark-DSA-phylink-as-legacy_pre_march2020.patch @@ -0,0 +1,36 @@ +From 0a9f0794d9bd67e590a9488afe87fbb0419d9539 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 9 Dec 2021 13:11:38 +0000 +Subject: [PATCH] net: dsa: mark DSA phylink as legacy_pre_march2020 + +The majority of DSA drivers do not make use of the PCS support, and +thus operate in legacy mode. In order to preserve this behaviour in +future, we need to set the legacy_pre_march2020 flag so phylink knows +this may require the legacy calls. + +There are some DSA drivers that do make use of PCS support, and these +will continue operating as before - legacy_pre_march2020 will not +prevent split-PCS support enabling the newer phylink behaviour. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + net/dsa/port.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1110,6 +1110,13 @@ int dsa_port_phylink_create(struct dsa_p + if (err) + mode = PHY_INTERFACE_MODE_NA; + ++ /* Presence of phylink_mac_link_state or phylink_mac_an_restart is ++ * an indicator of a legacy phylink driver. ++ */ ++ if (ds->ops->phylink_mac_link_state || ++ ds->ops->phylink_mac_an_restart) ++ dp->pl_config.legacy_pre_march2020 = true; ++ + if (ds->ops->phylink_get_caps) + ds->ops->phylink_get_caps(ds, dp->index, &dp->pl_config); + diff --git a/target/linux/generic/backport-5.15/703-14-v5.17-net-phylink-use-legacy_pre_march2020.patch b/target/linux/generic/backport-5.15/703-14-v5.17-net-phylink-use-legacy_pre_march2020.patch new file mode 100644 index 00000000000000..361fa10d4d59ae --- /dev/null +++ b/target/linux/generic/backport-5.15/703-14-v5.17-net-phylink-use-legacy_pre_march2020.patch @@ -0,0 +1,115 @@ +From 001f4261fe4d5ae710cf1f445b6cae6d9d3ae26e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 9 Dec 2021 13:11:48 +0000 +Subject: [PATCH] net: phylink: use legacy_pre_march2020 + +Use the legacy flag to indicate whether we should operate in legacy +mode. This allows us to stop using the presence of a PCS as an +indicator to the age of the phylink user, and make PCS presence +optional. + +Legacy mode involves: +1) calling mac_config() whenever the link comes up +2) calling mac_config() whenever the inband advertisement changes, + possibly followed by a call to mac_an_restart() +3) making use of mac_an_restart() +4) making use of mac_pcs_get_state() + +All the above functionality was moved to a seperate "PCS" block of +operations in March 2020. + +Update the documents to indicate that the differences that this flag +makes. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 12 ++++++------ + include/linux/phylink.h | 17 +++++++++++++++++ + 2 files changed, 23 insertions(+), 6 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -777,7 +777,7 @@ static void phylink_mac_pcs_an_restart(s + phylink_autoneg_inband(pl->cur_link_an_mode)) { + if (pl->pcs_ops) + pl->pcs_ops->pcs_an_restart(pl->pcs); +- else ++ else if (pl->config->legacy_pre_march2020) + pl->mac_ops->mac_an_restart(pl->config); + } + } +@@ -855,7 +855,7 @@ static int phylink_change_inband_advert( + if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state)) + return 0; + +- if (!pl->pcs_ops) { ++ if (!pl->pcs_ops && pl->config->legacy_pre_march2020) { + /* Legacy method */ + phylink_mac_config(pl, &pl->link_config); + phylink_mac_pcs_an_restart(pl); +@@ -900,7 +900,8 @@ static void phylink_mac_pcs_get_state(st + + if (pl->pcs_ops) + pl->pcs_ops->pcs_get_state(pl->pcs, state); +- else if (pl->mac_ops->mac_pcs_get_state) ++ else if (pl->mac_ops->mac_pcs_get_state && ++ pl->config->legacy_pre_march2020) + pl->mac_ops->mac_pcs_get_state(pl->config, state); + else + state->link = 0; +@@ -1094,12 +1095,11 @@ static void phylink_resolve(struct work_ + } + phylink_major_config(pl, false, &link_state); + pl->link_config.interface = link_state.interface; +- } else if (!pl->pcs_ops) { ++ } else if (!pl->pcs_ops && pl->config->legacy_pre_march2020) { + /* The interface remains unchanged, only the speed, + * duplex or pause settings have changed. Call the + * old mac_config() method to configure the MAC/PCS +- * only if we do not have a PCS installed (an +- * unconverted user.) ++ * only if we do not have a legacy MAC driver. + */ + phylink_mac_config(pl, &link_state); + } +--- a/include/linux/phylink.h ++++ b/include/linux/phylink.h +@@ -208,6 +208,10 @@ struct phylink_pcs *mac_select_pcs(struc + * negotiation completion state in @state->an_complete, and link up state + * in @state->link. If possible, @state->lp_advertising should also be + * populated. ++ * ++ * Note: This is a legacy method. This function will not be called unless ++ * legacy_pre_march2020 is set in &struct phylink_config and there is no ++ * PCS attached. + */ + void mac_pcs_get_state(struct phylink_config *config, + struct phylink_link_state *state); +@@ -248,6 +252,15 @@ int mac_prepare(struct phylink_config *c + * guaranteed to be correct, and so any mac_config() implementation must + * never reference these fields. + * ++ * Note: For legacy March 2020 drivers (drivers with legacy_pre_march2020 set ++ * in their &phylnk_config and which don't have a PCS), this function will be ++ * called on each link up event, and to also change the in-band advert. For ++ * non-legacy drivers, it will only be called to reconfigure the MAC for a ++ * "major" change in e.g. interface mode. It will not be called for changes ++ * in speed, duplex or pause modes or to change the in-band advertisement. ++ * In any case, it is strongly preferred that speed, duplex and pause settings ++ * are handled in the mac_link_up() method and not in this method. ++ * + * (this requires a rewrite - please refer to mac_link_up() for situations + * where the PCS and MAC are not tightly integrated.) + * +@@ -332,6 +345,10 @@ int mac_finish(struct phylink_config *co + /** + * mac_an_restart() - restart 802.3z BaseX autonegotiation + * @config: a pointer to a &struct phylink_config. ++ * ++ * Note: This is a legacy method. This function will not be called unless ++ * legacy_pre_march2020 is set in &struct phylink_config and there is no ++ * PCS attached. + */ + void mac_an_restart(struct phylink_config *config); + diff --git a/target/linux/generic/backport-5.15/704-01-v5.17-net-mtk_eth_soc-populate-supported_interfaces-member.patch b/target/linux/generic/backport-5.15/704-01-v5.17-net-mtk_eth_soc-populate-supported_interfaces-member.patch new file mode 100644 index 00000000000000..43e1f9cc31bb96 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-01-v5.17-net-mtk_eth_soc-populate-supported_interfaces-member.patch @@ -0,0 +1,43 @@ +From 83800d29f0c578e82554e7d4c6bfdbdf9b6cf428 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 16 Nov 2021 10:06:43 +0000 +Subject: [PATCH] net: mtk_eth_soc: populate supported_interfaces member + +Populate the phy interface mode bitmap for the Mediatek driver with +interfaces modes supported by the MAC. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3352,6 +3352,26 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; ++ __set_bit(PHY_INTERFACE_MODE_MII, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ mac->phylink_config.supported_interfaces); ++ ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) ++ phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); ++ ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) ++ __set_bit(PHY_INTERFACE_MODE_TRGMII, ++ mac->phylink_config.supported_interfaces); ++ ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_1000BASEX, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ mac->phylink_config.supported_interfaces); ++ } + + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), diff --git a/target/linux/generic/backport-5.15/704-02-v5.17-net-mtk_eth_soc-remove-interface-checks-in-mtk_valid.patch b/target/linux/generic/backport-5.15/704-02-v5.17-net-mtk_eth_soc-remove-interface-checks-in-mtk_valid.patch new file mode 100644 index 00000000000000..05a84c4f67956e --- /dev/null +++ b/target/linux/generic/backport-5.15/704-02-v5.17-net-mtk_eth_soc-remove-interface-checks-in-mtk_valid.patch @@ -0,0 +1,75 @@ +From db81ca153814475d7e07365d46a4d1134bd122e2 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 16 Nov 2021 10:06:48 +0000 +Subject: [PATCH] net: mtk_eth_soc: remove interface checks in mtk_validate() + +As phylink checks the interface mode against the supported_interfaces +bitmap, we no longer need to validate the interface mode, nor handle +PHY_INTERFACE_MODE_NA in the validation function. Remove these to +simplify the implementation. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 34 --------------------- + 1 file changed, 34 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -567,24 +567,8 @@ static void mtk_validate(struct phylink_ + unsigned long *supported, + struct phylink_link_state *state) + { +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + +- if (state->interface != PHY_INTERFACE_MODE_NA && +- state->interface != PHY_INTERFACE_MODE_MII && +- state->interface != PHY_INTERFACE_MODE_GMII && +- !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && +- phy_interface_mode_is_rgmii(state->interface)) && +- !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && +- !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && +- !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && +- (state->interface == PHY_INTERFACE_MODE_SGMII || +- phy_interface_mode_is_8023z(state->interface)))) { +- linkmode_zero(supported); +- return; +- } +- + phylink_set_port_modes(mask); + phylink_set(mask, Autoneg); + +@@ -611,7 +595,6 @@ static void mtk_validate(struct phylink_ + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_REVMII: +- case PHY_INTERFACE_MODE_NA: + default: + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); +@@ -620,23 +603,6 @@ static void mtk_validate(struct phylink_ + break; + } + +- if (state->interface == PHY_INTERFACE_MODE_NA) { +- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseX_Full); +- phylink_set(mask, 2500baseX_Full); +- } +- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseT_Half); +- phylink_set(mask, 1000baseX_Full); +- } +- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseT_Half); +- } +- } +- + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + diff --git a/target/linux/generic/backport-5.15/704-03-v5.17-net-mtk_eth_soc-drop-use-of-phylink_helper_basex_spe.patch b/target/linux/generic/backport-5.15/704-03-v5.17-net-mtk_eth_soc-drop-use-of-phylink_helper_basex_spe.patch new file mode 100644 index 00000000000000..a3cfab7f881f72 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-03-v5.17-net-mtk_eth_soc-drop-use-of-phylink_helper_basex_spe.patch @@ -0,0 +1,42 @@ +From 71d927494463c4f016d828e1134da26b7e961af5 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 16 Nov 2021 10:06:53 +0000 +Subject: [PATCH] net: mtk_eth_soc: drop use of phylink_helper_basex_speed() + +Now that we have a better method to select SFP interface modes, we +no longer need to use phylink_helper_basex_speed() in a driver's +validation function, and we can also get rid of our hack to indicate +both 1000base-X and 2500base-X if the comphy is present to make that +work. Remove this hack and use of phylink_helper_basex_speed(). + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -577,8 +577,9 @@ static void mtk_validate(struct phylink_ + phylink_set(mask, 1000baseT_Full); + break; + case PHY_INTERFACE_MODE_1000BASEX: +- case PHY_INTERFACE_MODE_2500BASEX: + phylink_set(mask, 1000baseX_Full); ++ break; ++ case PHY_INTERFACE_MODE_2500BASEX: + phylink_set(mask, 2500baseX_Full); + break; + case PHY_INTERFACE_MODE_GMII: +@@ -608,11 +609,6 @@ static void mtk_validate(struct phylink_ + + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); +- +- /* We can only operate at 2500BaseX or 1000BaseX. If requested +- * to advertise both, only report advertising at 2500BaseX. +- */ +- phylink_helper_basex_speed(state); + } + + static const struct phylink_mac_ops mtk_phylink_ops = { diff --git a/target/linux/generic/backport-5.15/704-04-v5.17-net-mtk_eth_soc-use-phylink_generic_validate.patch b/target/linux/generic/backport-5.15/704-04-v5.17-net-mtk_eth_soc-use-phylink_generic_validate.patch new file mode 100644 index 00000000000000..7f3734a76546ab --- /dev/null +++ b/target/linux/generic/backport-5.15/704-04-v5.17-net-mtk_eth_soc-use-phylink_generic_validate.patch @@ -0,0 +1,84 @@ +From a4238f6ce151afa331375d74a5033b76da637644 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Tue, 16 Nov 2021 10:06:58 +0000 +Subject: [PATCH] net: mtk_eth_soc: use phylink_generic_validate() + +mtk_eth_soc has no special behaviour in its validation implementation, +so can be switched to phylink_generic_validate(). + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 53 ++------------------- + 1 file changed, 4 insertions(+), 49 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -563,56 +563,8 @@ static void mtk_mac_link_up(struct phyli + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); + } + +-static void mtk_validate(struct phylink_config *config, +- unsigned long *supported, +- struct phylink_link_state *state) +-{ +- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +- +- phylink_set_port_modes(mask); +- phylink_set(mask, Autoneg); +- +- switch (state->interface) { +- case PHY_INTERFACE_MODE_TRGMII: +- phylink_set(mask, 1000baseT_Full); +- break; +- case PHY_INTERFACE_MODE_1000BASEX: +- phylink_set(mask, 1000baseX_Full); +- break; +- case PHY_INTERFACE_MODE_2500BASEX: +- phylink_set(mask, 2500baseX_Full); +- break; +- case PHY_INTERFACE_MODE_GMII: +- case PHY_INTERFACE_MODE_RGMII: +- case PHY_INTERFACE_MODE_RGMII_ID: +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII_TXID: +- phylink_set(mask, 1000baseT_Half); +- fallthrough; +- case PHY_INTERFACE_MODE_SGMII: +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseX_Full); +- fallthrough; +- case PHY_INTERFACE_MODE_MII: +- case PHY_INTERFACE_MODE_RMII: +- case PHY_INTERFACE_MODE_REVMII: +- default: +- phylink_set(mask, 10baseT_Half); +- phylink_set(mask, 10baseT_Full); +- phylink_set(mask, 100baseT_Half); +- phylink_set(mask, 100baseT_Full); +- break; +- } +- +- phylink_set(mask, Pause); +- phylink_set(mask, Asym_Pause); +- +- linkmode_and(supported, supported, mask); +- linkmode_and(state->advertising, state->advertising, mask); +-} +- + static const struct phylink_mac_ops mtk_phylink_ops = { +- .validate = mtk_validate, ++ .validate = phylink_generic_validate, + .mac_pcs_get_state = mtk_mac_pcs_get_state, + .mac_an_restart = mtk_mac_an_restart, + .mac_config = mtk_mac_config, +@@ -3314,6 +3266,9 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; ++ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | ++ MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; ++ + __set_bit(PHY_INTERFACE_MODE_MII, + mac->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_GMII, diff --git a/target/linux/generic/backport-5.15/704-05-v5.17-net-mtk_eth_soc-mark-as-a-legacy_pre_march2020-drive.patch b/target/linux/generic/backport-5.15/704-05-v5.17-net-mtk_eth_soc-mark-as-a-legacy_pre_march2020-drive.patch new file mode 100644 index 00000000000000..6aa99acf77d86d --- /dev/null +++ b/target/linux/generic/backport-5.15/704-05-v5.17-net-mtk_eth_soc-mark-as-a-legacy_pre_march2020-drive.patch @@ -0,0 +1,29 @@ +From b06515367facfadcf5e70cf6f39db749cf4eb5e3 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Thu, 9 Dec 2021 13:11:43 +0000 +Subject: [PATCH] net: mtk_eth_soc: mark as a legacy_pre_march2020 driver + +mtk_eth_soc has not been updated for commit 7cceb599d15d ("net: phylink: +avoid mac_config calls"), and makes use of state->speed and +state->duplex in contravention of the phylink documentation. This makes +reliant on the legacy behaviours, so mark it as a legacy driver. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3266,6 +3266,10 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; ++ /* This driver makes use of state->speed/state->duplex in ++ * mac_config ++ */ ++ mac->phylink_config.legacy_pre_march2020 = true; + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; + diff --git a/target/linux/generic/backport-5.15/704-06-v5.19-eth-mtk_eth_soc-remove-a-copy-of-the-NAPI_POLL_WEIGH.patch b/target/linux/generic/backport-5.15/704-06-v5.19-eth-mtk_eth_soc-remove-a-copy-of-the-NAPI_POLL_WEIGH.patch new file mode 100644 index 00000000000000..e5f70e36f0bb97 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-06-v5.19-eth-mtk_eth_soc-remove-a-copy-of-the-NAPI_POLL_WEIGH.patch @@ -0,0 +1,40 @@ +From 889e3691b9d6573de133da1f5e78f590e52152cd Mon Sep 17 00:00:00 2001 +From: Jakub Kicinski +Date: Thu, 28 Apr 2022 14:23:13 -0700 +Subject: [PATCH] eth: mtk_eth_soc: remove a copy of the NAPI_POLL_WEIGHT + define + +Defining local versions of NAPI_POLL_WEIGHT with the same +values in the drivers just makes refactoring harder. + +Signed-off-by: Jakub Kicinski +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - + 2 files changed, 2 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3565,9 +3565,9 @@ static int mtk_probe(struct platform_dev + */ + init_dummy_netdev(ð->dummy_dev); + netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, +- MTK_NAPI_WEIGHT); ++ NAPI_POLL_WEIGHT); + netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, +- MTK_NAPI_WEIGHT); ++ NAPI_POLL_WEIGHT); + + platform_set_drvdata(pdev, eth); + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -25,7 +25,6 @@ + #define MTK_TX_DMA_BUF_LEN 0x3fff + #define MTK_TX_DMA_BUF_LEN_V2 0xffff + #define MTK_DMA_SIZE 512 +-#define MTK_NAPI_WEIGHT 64 + #define MTK_MAC_COUNT 2 + #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) + #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) diff --git a/target/linux/generic/backport-5.15/704-07-v5.19-mtk_eth_soc-remove-unused-mac-mode.patch b/target/linux/generic/backport-5.15/704-07-v5.19-mtk_eth_soc-remove-unused-mac-mode.patch new file mode 100644 index 00000000000000..4d896cdf39273d --- /dev/null +++ b/target/linux/generic/backport-5.15/704-07-v5.19-mtk_eth_soc-remove-unused-mac-mode.patch @@ -0,0 +1,35 @@ +From 0600bdde1fae75fb9bad72033d28edddc72b44b2 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:54:31 +0100 +Subject: [PATCH 01/12] net: mtk_eth_soc: remove unused mac->mode + +mac->mode is only ever written to in one location, and is thus +superflous. Remove it. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 - + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - + 2 files changed, 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -3261,7 +3261,6 @@ static int mtk_add_mac(struct mtk_eth *e + + /* mac config is not set */ + mac->interface = PHY_INTERFACE_MODE_NA; +- mac->mode = MLO_AN_PHY; + mac->speed = SPEED_UNKNOWN; + + mac->phylink_config.dev = ð->netdev[id]->dev; +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1085,7 +1085,6 @@ struct mtk_eth { + struct mtk_mac { + int id; + phy_interface_t interface; +- unsigned int mode; + int speed; + struct device_node *of_node; + struct phylink *phylink; diff --git a/target/linux/generic/backport-5.15/704-08-v5.19-net-mtk_eth_soc-remove-unused-sgmii-flags.patch b/target/linux/generic/backport-5.15/704-08-v5.19-net-mtk_eth_soc-remove-unused-sgmii-flags.patch new file mode 100644 index 00000000000000..39aa24157edaf3 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-08-v5.19-net-mtk_eth_soc-remove-unused-sgmii-flags.patch @@ -0,0 +1,40 @@ +From 5a7a2f4b29d7546244da7d8bbc1962fce5b230f2 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:54:36 +0100 +Subject: [PATCH 02/12] net: mtk_eth_soc: remove unused sgmii flags + +The "flags" member of struct mtk_sgmii appears to be unused, as are +the MTK_SGMII_PHYSPEED_* and MTK_HAS_FLAGS() macros. Remove them. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 -------- + 1 file changed, 8 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -956,23 +956,15 @@ struct mtk_soc_data { + /* currently no SoC has more than 2 macs */ + #define MTK_MAX_DEVS 2 + +-#define MTK_SGMII_PHYSPEED_AN BIT(31) +-#define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0) +-#define MTK_SGMII_PHYSPEED_1000 BIT(0) +-#define MTK_SGMII_PHYSPEED_2500 BIT(1) +-#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x)) +- + /* struct mtk_sgmii - This is the structure holding sgmii regmap and its + * characteristics + * @regmap: The register map pointing at the range used to setup + * SGMII modes +- * @flags: The enum refers to which mode the sgmii wants to run on + * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap + */ + + struct mtk_sgmii { + struct regmap *regmap[MTK_MAX_DEVS]; +- u32 flags[MTK_MAX_DEVS]; + u32 ana_rgc3; + }; + diff --git a/target/linux/generic/backport-5.15/704-09-v5.19-net-mtk_eth_soc-add-mask-and-update-PCS-speed-defini.patch b/target/linux/generic/backport-5.15/704-09-v5.19-net-mtk_eth_soc-add-mask-and-update-PCS-speed-defini.patch new file mode 100644 index 00000000000000..f2e1f86bacf139 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-09-v5.19-net-mtk_eth_soc-add-mask-and-update-PCS-speed-defini.patch @@ -0,0 +1,40 @@ +From bc5e93e0cd22e360eda23859b939280205567580 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:54:42 +0100 +Subject: [PATCH 03/12] net: mtk_eth_soc: add mask and update PCS speed + definitions + +The PCS speed setting is a two bit field, but it is defined as two +separate bits. Add a bitfield mask for the speed definitions, an + use the FIELD_PREP() macro to define each PCS speed. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include "mtk_ppe.h" + + #define MTK_QDMA_PAGE_SIZE 2048 +@@ -473,9 +474,10 @@ + #define SGMSYS_SGMII_MODE 0x20 + #define SGMII_IF_MODE_BIT0 BIT(0) + #define SGMII_SPEED_DUPLEX_AN BIT(1) +-#define SGMII_SPEED_10 0x0 +-#define SGMII_SPEED_100 BIT(2) +-#define SGMII_SPEED_1000 BIT(3) ++#define SGMII_SPEED_MASK GENMASK(3, 2) ++#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) ++#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) ++#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) + #define SGMII_DUPLEX_FULL BIT(4) + #define SGMII_IF_MODE_BIT5 BIT(5) + #define SGMII_REMOTE_FAULT_DIS BIT(8) diff --git a/target/linux/generic/backport-5.15/704-10-v5.19-net-mtk_eth_soc-correct-802.3z-speed-setting.patch b/target/linux/generic/backport-5.15/704-10-v5.19-net-mtk_eth_soc-correct-802.3z-speed-setting.patch new file mode 100644 index 00000000000000..fb1ee4e310eb58 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-10-v5.19-net-mtk_eth_soc-correct-802.3z-speed-setting.patch @@ -0,0 +1,60 @@ +From 7da3f901f8ecb425105fad39a0f5de73306abe52 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:54:47 +0100 +Subject: [PATCH 04/12] net: mtk_eth_soc: correct 802.3z speed setting + +Phylink does not guarantee that state->speed will be set correctly in +the mac_config() call, so it's a bug that the driver makes use of it. +Moreover, it is making use of it in a function that is only ever called +for 1000BASE-X and 2500BASE-X which operate at a fixed speed which +happens to be the same setting irrespective of the interface mode. We +can simply remove the switch statement and just set the SGMII interface +speed. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 18 +++++------------- + 1 file changed, 5 insertions(+), 13 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -34,6 +34,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + return 0; + } + ++/* For SGMII interface mode */ + int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) + { + unsigned int val; +@@ -60,6 +61,9 @@ int mtk_sgmii_setup_mode_an(struct mtk_s + return 0; + } + ++/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a ++ * fixed speed. ++ */ + int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, + const struct phylink_link_state *state) + { +@@ -82,19 +86,7 @@ int mtk_sgmii_setup_mode_force(struct mt + /* SGMII force mode setting */ + regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); + val &= ~SGMII_IF_MODE_MASK; +- +- switch (state->speed) { +- case SPEED_10: +- val |= SGMII_SPEED_10; +- break; +- case SPEED_100: +- val |= SGMII_SPEED_100; +- break; +- case SPEED_2500: +- case SPEED_1000: +- val |= SGMII_SPEED_1000; +- break; +- } ++ val |= SGMII_SPEED_1000; + + if (state->duplex == DUPLEX_FULL) + val |= SGMII_DUPLEX_FULL; diff --git a/target/linux/generic/backport-5.15/704-11-v5.19-net-mtk_eth_soc-correct-802.3z-duplex-setting.patch b/target/linux/generic/backport-5.15/704-11-v5.19-net-mtk_eth_soc-correct-802.3z-duplex-setting.patch new file mode 100644 index 00000000000000..140ff3cab5e1a6 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-11-v5.19-net-mtk_eth_soc-correct-802.3z-duplex-setting.patch @@ -0,0 +1,101 @@ +From a459187390bb221827f9c07866c3a5ffbdf9622b Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Wed, 18 May 2022 15:54:52 +0100 +Subject: [PATCH 05/12] net: mtk_eth_soc: correct 802.3z duplex setting + +Phylink does not guarantee that state->duplex will be set correctly in +the mac_config() call, so it's a bug that the driver makes use of it. + +Move the 802.3z PCS duplex configuration to mac_link_up(). + +Signed-off-by: Russell King +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 16 +++++++++++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + + drivers/net/ethernet/mediatek/mtk_sgmii.c | 22 +++++++++++++++------ + 3 files changed, 29 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -532,8 +532,18 @@ static void mtk_mac_link_up(struct phyli + { + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); +- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); ++ u32 mcr; + ++ if (phy_interface_mode_is_8023z(interface)) { ++ struct mtk_eth *eth = mac->hw; ++ ++ /* Decide how GMAC and SGMIISYS be mapped */ ++ int sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? ++ 0 : mac->id; ++ mtk_sgmii_link_up(eth->sgmii, sid, speed, duplex); ++ } ++ ++ mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); + mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | + MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | + MAC_MCR_FORCE_RX_FC); +@@ -3265,9 +3275,7 @@ static int mtk_add_mac(struct mtk_eth *e + + mac->phylink_config.dev = ð->netdev[id]->dev; + mac->phylink_config.type = PHYLINK_NETDEV; +- /* This driver makes use of state->speed/state->duplex in +- * mac_config +- */ ++ /* This driver makes use of state->speed in mac_config */ + mac->phylink_config.legacy_pre_march2020 = true; + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1103,6 +1103,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); + int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, + const struct phylink_link_state *state); ++void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex); + void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -83,14 +83,10 @@ int mtk_sgmii_setup_mode_force(struct mt + val &= ~SGMII_AN_ENABLE; + regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); + +- /* SGMII force mode setting */ ++ /* Set the speed etc but leave the duplex unchanged */ + regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); +- val &= ~SGMII_IF_MODE_MASK; ++ val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK; + val |= SGMII_SPEED_1000; +- +- if (state->duplex == DUPLEX_FULL) +- val |= SGMII_DUPLEX_FULL; +- + regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); + + /* Release PHYA power down state */ +@@ -101,6 +97,20 @@ int mtk_sgmii_setup_mode_force(struct mt + return 0; + } + ++/* For 1000BASE-X and 2500BASE-X interface modes */ ++void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex) ++{ ++ unsigned int val; ++ ++ /* SGMII force duplex setting */ ++ regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); ++ val &= ~SGMII_DUPLEX_FULL; ++ if (duplex == DUPLEX_FULL) ++ val |= SGMII_DUPLEX_FULL; ++ ++ regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); ++} ++ + void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) + { + struct mtk_sgmii *ss = eth->sgmii; diff --git a/target/linux/generic/backport-5.15/704-12-v5.19-net-mtk_eth_soc-stop-passing-phylink-state-to-sgmii-.patch b/target/linux/generic/backport-5.15/704-12-v5.19-net-mtk_eth_soc-stop-passing-phylink-state-to-sgmii-.patch new file mode 100644 index 00000000000000..56b5e43e532647 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-12-v5.19-net-mtk_eth_soc-stop-passing-phylink-state-to-sgmii-.patch @@ -0,0 +1,60 @@ +From 4ce5a0bd3958ed248f0325bfcb95339f7c74feb2 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:54:57 +0100 +Subject: [PATCH 06/12] net: mtk_eth_soc: stop passing phylink state to sgmii + setup + +Now that mtk_sgmii_setup_mode_force() only uses the interface mode +from the phylink state, pass just the interface mode into this +function. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++-- + 3 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -437,7 +437,7 @@ static void mtk_mac_config(struct phylin + /* Setup SGMIISYS with the determined property */ + if (state->interface != PHY_INTERFACE_MODE_SGMII) + err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, +- state); ++ state->interface); + else if (phylink_autoneg_inband(mode)) + err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1102,7 +1102,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + u32 ana_rgc3); + int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); + int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, +- const struct phylink_link_state *state); ++ phy_interface_t interface); + void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex); + void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -65,7 +65,7 @@ int mtk_sgmii_setup_mode_an(struct mtk_s + * fixed speed. + */ + int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, +- const struct phylink_link_state *state) ++ phy_interface_t interface) + { + unsigned int val; + +@@ -74,7 +74,7 @@ int mtk_sgmii_setup_mode_force(struct mt + + regmap_read(ss->regmap[id], ss->ana_rgc3, &val); + val &= ~RG_PHY_SPEED_MASK; +- if (state->interface == PHY_INTERFACE_MODE_2500BASEX) ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) + val |= RG_PHY_SPEED_3_125G; + regmap_write(ss->regmap[id], ss->ana_rgc3, val); + diff --git a/target/linux/generic/backport-5.15/704-13-v5.19-net-mtk_eth_soc-provide-mtk_sgmii_config.patch b/target/linux/generic/backport-5.15/704-13-v5.19-net-mtk_eth_soc-provide-mtk_sgmii_config.patch new file mode 100644 index 00000000000000..4c91cf68f4ca53 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-13-v5.19-net-mtk_eth_soc-provide-mtk_sgmii_config.patch @@ -0,0 +1,89 @@ +From 1ec619ee4a052fb9ac48b57554ac2722a0bfe73c Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:02 +0100 +Subject: [PATCH 07/12] net: mtk_eth_soc: provide mtk_sgmii_config() + +Provide mtk_sgmii_config() to wrap up the decisions about which SGMII +configuration will be called. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 ++--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 20 +++++++++++++++++--- + 3 files changed, 20 insertions(+), 12 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -435,12 +435,7 @@ static void mtk_mac_config(struct phylin + 0 : mac->id; + + /* Setup SGMIISYS with the determined property */ +- if (state->interface != PHY_INTERFACE_MODE_SGMII) +- err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, +- state->interface); +- else if (phylink_autoneg_inband(mode)) +- err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); +- ++ err = mtk_sgmii_config(eth->sgmii, sid, mode, state->interface); + if (err) + goto init_err; + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1100,9 +1100,8 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne + + int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, + u32 ana_rgc3); +-int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); +-int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, +- phy_interface_t interface); ++int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, ++ phy_interface_t interface); + void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex); + void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -35,7 +35,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + } + + /* For SGMII interface mode */ +-int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) ++static int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) + { + unsigned int val; + +@@ -64,8 +64,8 @@ int mtk_sgmii_setup_mode_an(struct mtk_s + /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a + * fixed speed. + */ +-int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, +- phy_interface_t interface) ++static int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, ++ phy_interface_t interface) + { + unsigned int val; + +@@ -97,6 +97,20 @@ int mtk_sgmii_setup_mode_force(struct mt + return 0; + } + ++int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, ++ phy_interface_t interface) ++{ ++ int err = 0; ++ ++ /* Setup SGMIISYS with the determined property */ ++ if (interface != PHY_INTERFACE_MODE_SGMII) ++ err = mtk_sgmii_setup_mode_force(ss, id, interface); ++ else if (phylink_autoneg_inband(mode)) ++ err = mtk_sgmii_setup_mode_an(ss, id); ++ ++ return err; ++} ++ + /* For 1000BASE-X and 2500BASE-X interface modes */ + void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex) + { diff --git a/target/linux/generic/backport-5.15/704-14-v5.19-net-mtk_eth_soc-add-fixme-comment-for-state-speed-us.patch b/target/linux/generic/backport-5.15/704-14-v5.19-net-mtk_eth_soc-add-fixme-comment-for-state-speed-us.patch new file mode 100644 index 00000000000000..8080a2ca441e0b --- /dev/null +++ b/target/linux/generic/backport-5.15/704-14-v5.19-net-mtk_eth_soc-add-fixme-comment-for-state-speed-us.patch @@ -0,0 +1,38 @@ +From 650a49bc65df6b0e0051a8f62d7c22d95a8f350d Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:07 +0100 +Subject: [PATCH 08/12] net: mtk_eth_soc: add fixme comment for state->speed + use + +Add a fixme comment for the last remaining incorrect usage of +state->speed in the mac_config() method, which is strangely in a code +path which is only run when the PHY interface mode changes. + +This means if we are in RGMII mode, changes in state->speed will not +cause the INTF_MODE, TRGMII_RCK_CTRL and TRGMII_TCK_CTRL registers to +be set according to the speed, nor will the TRGPLL clock be set to the +correct value. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -374,6 +374,14 @@ static void mtk_mac_config(struct phylin + state->interface)) + goto err_phy; + } else { ++ /* FIXME: this is incorrect. Not only does it ++ * use state->speed (which is not guaranteed ++ * to be correct) but it also makes use of it ++ * in a code path that will only be reachable ++ * when the PHY interface mode changes, not ++ * when the speed changes. Consequently, RGMII ++ * is probably broken. ++ */ + mtk_gmac0_rgmii_adjust(mac->hw, + state->interface, + state->speed); diff --git a/target/linux/generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch b/target/linux/generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch new file mode 100644 index 00000000000000..368db4cca26ddb --- /dev/null +++ b/target/linux/generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch @@ -0,0 +1,79 @@ +From 0e37ad71b2ff772009595002da2860999e98e14e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:12 +0100 +Subject: [PATCH 09/12] net: mtk_eth_soc: move MAC_MCR setting to mac_finish() + +Move the setting of the MTK_MAC_MCR register from the end of mac_config +into the phylink mac_finish() method, to keep it as the very last write +that is done during configuration. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++------- + 1 file changed, 22 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -316,8 +316,8 @@ static void mtk_mac_config(struct phylin + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); + struct mtk_eth *eth = mac->hw; +- u32 mcr_cur, mcr_new, sid, i; + int val, ge_mode, err = 0; ++ u32 sid, i; + + /* MT76x8 has no hardware settings between for the MAC */ + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && +@@ -455,16 +455,6 @@ static void mtk_mac_config(struct phylin + return; + } + +- /* Setup gmac */ +- mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); +- mcr_new = mcr_cur; +- mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | +- MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; +- +- /* Only update control register when needed! */ +- if (mcr_new != mcr_cur) +- mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); +- + return; + + err_phy: +@@ -477,6 +467,26 @@ init_err: + mac->id, phy_modes(state->interface), err); + } + ++static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, ++ phy_interface_t interface) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ u32 mcr_cur, mcr_new; ++ ++ /* Setup gmac */ ++ mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); ++ mcr_new = mcr_cur; ++ mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | ++ MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; ++ ++ /* Only update control register when needed! */ ++ if (mcr_new != mcr_cur) ++ mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); ++ ++ return 0; ++} ++ + static void mtk_mac_pcs_get_state(struct phylink_config *config, + struct phylink_link_state *state) + { +@@ -581,6 +591,7 @@ static const struct phylink_mac_ops mtk_ + .mac_pcs_get_state = mtk_mac_pcs_get_state, + .mac_an_restart = mtk_mac_an_restart, + .mac_config = mtk_mac_config, ++ .mac_finish = mtk_mac_finish, + .mac_link_down = mtk_mac_link_down, + .mac_link_up = mtk_mac_link_up, + }; diff --git a/target/linux/generic/backport-5.15/704-16-v5.19-net-mtk_eth_soc-move-restoration-of-SYSCFG0-to-mac_f.patch b/target/linux/generic/backport-5.15/704-16-v5.19-net-mtk_eth_soc-move-restoration-of-SYSCFG0-to-mac_f.patch new file mode 100644 index 00000000000000..ad6ec60288faab --- /dev/null +++ b/target/linux/generic/backport-5.15/704-16-v5.19-net-mtk_eth_soc-move-restoration-of-SYSCFG0-to-mac_f.patch @@ -0,0 +1,57 @@ +From 21089867278deb2a110b685e3cd33f64f9ce41e2 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:17 +0100 +Subject: [PATCH 10/12] net: mtk_eth_soc: move restoration of SYSCFG0 to + mac_finish() + +The SGMIISYS configuration is performed while ETHSYS_SYSCFG0 is in a +disabled state. In order to preserve this when we switch to phylink_pcs +we need to move the restoration of this register to the mac_finish() +callback. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 11 +++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 + + 2 files changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -447,8 +447,8 @@ static void mtk_mac_config(struct phylin + if (err) + goto init_err; + +- regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, +- SYSCFG0_SGMII_MASK, val); ++ /* Save the syscfg0 value for mac_finish */ ++ mac->syscfg0 = val; + } else if (phylink_autoneg_inband(mode)) { + dev_err(eth->dev, + "In-band mode not supported in non SGMII mode!\n"); +@@ -472,8 +472,15 @@ static int mtk_mac_finish(struct phylink + { + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); ++ struct mtk_eth *eth = mac->hw; + u32 mcr_cur, mcr_new; + ++ /* Enable SGMII */ ++ if (interface == PHY_INTERFACE_MODE_SGMII || ++ phy_interface_mode_is_8023z(interface)) ++ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, ++ SYSCFG0_SGMII_MASK, mac->syscfg0); ++ + /* Setup gmac */ + mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); + mcr_new = mcr_cur; +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1087,6 +1087,7 @@ struct mtk_mac { + struct mtk_hw_stats *hw_stats; + __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; + int hwlro_ip_cnt; ++ unsigned int syscfg0; + }; + + /* the struct describing the SoC. these are declared in the soc_xyz.c files */ diff --git a/target/linux/generic/backport-5.15/704-17-v5.19-net-mtk_eth_soc-convert-code-structure-to-suit-split.patch b/target/linux/generic/backport-5.15/704-17-v5.19-net-mtk_eth_soc-convert-code-structure-to-suit-split.patch new file mode 100644 index 00000000000000..623658f459c78a --- /dev/null +++ b/target/linux/generic/backport-5.15/704-17-v5.19-net-mtk_eth_soc-convert-code-structure-to-suit-split.patch @@ -0,0 +1,254 @@ +From 901f3fbe13c3e56f0742e02717ccbfabbc95c463 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:22 +0100 +Subject: [PATCH 11/12] net: mtk_eth_soc: convert code structure to suit split + PCS support + +Provide a mtk_pcs structure which encapsulates everything that the PCS +functions need (the regmap and ana_rgc3 offset), and use this in the +PCS functions. Provide shim functions to convert from the existing +"mtk_sgmii_*" interface to the converted PCS functions. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 15 ++- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 123 +++++++++++--------- + 2 files changed, 79 insertions(+), 59 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -958,16 +958,23 @@ struct mtk_soc_data { + /* currently no SoC has more than 2 macs */ + #define MTK_MAX_DEVS 2 + +-/* struct mtk_sgmii - This is the structure holding sgmii regmap and its +- * characteristics ++/* struct mtk_pcs - This structure holds each sgmii regmap and associated ++ * data + * @regmap: The register map pointing at the range used to setup + * SGMII modes + * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap + */ ++struct mtk_pcs { ++ struct regmap *regmap; ++ u32 ana_rgc3; ++}; + ++/* struct mtk_sgmii - This is the structure holding sgmii regmap and its ++ * characteristics ++ * @pcs Array of individual PCS structures ++ */ + struct mtk_sgmii { +- struct regmap *regmap[MTK_MAX_DEVS]; +- u32 ana_rgc3; ++ struct mtk_pcs pcs[MTK_MAX_DEVS]; + }; + + /* struct mtk_eth - This is the main datasructure for holding the state +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -9,90 +9,71 @@ + + #include + #include ++#include + #include + + #include "mtk_eth_soc.h" + +-int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) +-{ +- struct device_node *np; +- int i; +- +- ss->ana_rgc3 = ana_rgc3; +- +- for (i = 0; i < MTK_MAX_DEVS; i++) { +- np = of_parse_phandle(r, "mediatek,sgmiisys", i); +- if (!np) +- break; +- +- ss->regmap[i] = syscon_node_to_regmap(np); +- of_node_put(np); +- if (IS_ERR(ss->regmap[i])) +- return PTR_ERR(ss->regmap[i]); +- } +- +- return 0; +-} +- + /* For SGMII interface mode */ +-static int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) ++static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) + { + unsigned int val; + +- if (!ss->regmap[id]) ++ if (!mpcs->regmap) + return -EINVAL; + + /* Setup the link timer and QPHY power up inside SGMIISYS */ +- regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER, ++ regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, + SGMII_LINK_TIMER_DEFAULT); + +- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); ++ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); + val |= SGMII_REMOTE_FAULT_DIS; +- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); ++ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + +- regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); ++ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); + val |= SGMII_AN_RESTART; +- regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); ++ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + +- regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); ++ regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); + val &= ~SGMII_PHYA_PWD; +- regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + + return 0; ++ + } + + /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a + * fixed speed. + */ +-static int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, +- phy_interface_t interface) ++static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs, ++ phy_interface_t interface) + { + unsigned int val; + +- if (!ss->regmap[id]) ++ if (!mpcs->regmap) + return -EINVAL; + +- regmap_read(ss->regmap[id], ss->ana_rgc3, &val); ++ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); + val &= ~RG_PHY_SPEED_MASK; + if (interface == PHY_INTERFACE_MODE_2500BASEX) + val |= RG_PHY_SPEED_3_125G; +- regmap_write(ss->regmap[id], ss->ana_rgc3, val); ++ regmap_write(mpcs->regmap, mpcs->ana_rgc3, val); + + /* Disable SGMII AN */ +- regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); ++ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); + val &= ~SGMII_AN_ENABLE; +- regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); ++ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + + /* Set the speed etc but leave the duplex unchanged */ +- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); ++ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); + val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK; + val |= SGMII_SPEED_1000; +- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); ++ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + + /* Release PHYA power down state */ +- regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); ++ regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); + val &= ~SGMII_PHYA_PWD; +- regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + + return 0; + } +@@ -100,44 +81,76 @@ static int mtk_sgmii_setup_mode_force(st + int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, + phy_interface_t interface) + { ++ struct mtk_pcs *mpcs = &ss->pcs[id]; + int err = 0; + + /* Setup SGMIISYS with the determined property */ + if (interface != PHY_INTERFACE_MODE_SGMII) +- err = mtk_sgmii_setup_mode_force(ss, id, interface); ++ err = mtk_pcs_setup_mode_force(mpcs, interface); + else if (phylink_autoneg_inband(mode)) +- err = mtk_sgmii_setup_mode_an(ss, id); ++ err = mtk_pcs_setup_mode_an(mpcs); + + return err; + } + +-/* For 1000BASE-X and 2500BASE-X interface modes */ +-void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex) ++static void mtk_pcs_restart_an(struct mtk_pcs *mpcs) ++{ ++ unsigned int val; ++ ++ if (!mpcs->regmap) ++ return; ++ ++ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); ++ val |= SGMII_AN_RESTART; ++ regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); ++} ++ ++static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex) + { + unsigned int val; + + /* SGMII force duplex setting */ +- regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); ++ regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); + val &= ~SGMII_DUPLEX_FULL; + if (duplex == DUPLEX_FULL) + val |= SGMII_DUPLEX_FULL; + +- regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); ++ regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); ++} ++ ++/* For 1000BASE-X and 2500BASE-X interface modes */ ++void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex) ++{ ++ mtk_pcs_link_up(&ss->pcs[id], speed, duplex); ++} ++ ++int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) ++{ ++ struct device_node *np; ++ int i; ++ ++ for (i = 0; i < MTK_MAX_DEVS; i++) { ++ np = of_parse_phandle(r, "mediatek,sgmiisys", i); ++ if (!np) ++ break; ++ ++ ss->pcs[i].ana_rgc3 = ana_rgc3; ++ ss->pcs[i].regmap = syscon_node_to_regmap(np); ++ of_node_put(np); ++ if (IS_ERR(ss->pcs[i].regmap)) ++ return PTR_ERR(ss->pcs[i].regmap); ++ } ++ ++ return 0; + } + + void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) + { +- struct mtk_sgmii *ss = eth->sgmii; +- unsigned int val, sid; ++ unsigned int sid; + + /* Decide how GMAC and SGMIISYS be mapped */ + sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? + 0 : mac_id; + +- if (!ss->regmap[sid]) +- return; +- +- regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val); +- val |= SGMII_AN_RESTART; +- regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val); ++ mtk_pcs_restart_an(ð->sgmii->pcs[sid]); + } diff --git a/target/linux/generic/backport-5.15/704-18-v5.19-net-mtk_eth_soc-partially-convert-to-phylink_pcs.patch b/target/linux/generic/backport-5.15/704-18-v5.19-net-mtk_eth_soc-partially-convert-to-phylink_pcs.patch new file mode 100644 index 00000000000000..df675e289995f4 --- /dev/null +++ b/target/linux/generic/backport-5.15/704-18-v5.19-net-mtk_eth_soc-partially-convert-to-phylink_pcs.patch @@ -0,0 +1,262 @@ +From 14a44ab0330d290fade1403a920e299cc56d7300 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 18 May 2022 15:55:28 +0100 +Subject: [PATCH 12/12] net: mtk_eth_soc: partially convert to phylink_pcs + +Partially convert mtk_eth_soc to phylink_pcs, moving the configuration, +link up and AN restart over. However, it seems mac_pcs_get_state() +doesn't actually get the state from the PCS, so we can't convert that +over without a better understanding of the hardware. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++---------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 ++- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 55 +++++++++++---------- + 3 files changed, 53 insertions(+), 58 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -310,6 +310,25 @@ static void mtk_gmac0_rgmii_adjust(struc + mtk_w32(eth, val, TRGMII_TCK_CTRL); + } + ++static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, ++ phy_interface_t interface) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ struct mtk_eth *eth = mac->hw; ++ unsigned int sid; ++ ++ if (interface == PHY_INTERFACE_MODE_SGMII || ++ phy_interface_mode_is_8023z(interface)) { ++ sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? ++ 0 : mac->id; ++ ++ return mtk_sgmii_select_pcs(eth->sgmii, sid); ++ } ++ ++ return NULL; ++} ++ + static void mtk_mac_config(struct phylink_config *config, unsigned int mode, + const struct phylink_link_state *state) + { +@@ -317,7 +336,7 @@ static void mtk_mac_config(struct phylin + phylink_config); + struct mtk_eth *eth = mac->hw; + int val, ge_mode, err = 0; +- u32 sid, i; ++ u32 i; + + /* MT76x8 has no hardware settings between for the MAC */ + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && +@@ -438,15 +457,6 @@ static void mtk_mac_config(struct phylin + SYSCFG0_SGMII_MASK, + ~(u32)SYSCFG0_SGMII_MASK); + +- /* Decide how GMAC and SGMIISYS be mapped */ +- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? +- 0 : mac->id; +- +- /* Setup SGMIISYS with the determined property */ +- err = mtk_sgmii_config(eth->sgmii, sid, mode, state->interface); +- if (err) +- goto init_err; +- + /* Save the syscfg0 value for mac_finish */ + mac->syscfg0 = val; + } else if (phylink_autoneg_inband(mode)) { +@@ -526,14 +536,6 @@ static void mtk_mac_pcs_get_state(struct + state->pause |= MLO_PAUSE_TX; + } + +-static void mtk_mac_an_restart(struct phylink_config *config) +-{ +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); +- +- mtk_sgmii_restart_an(mac->hw, mac->id); +-} +- + static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) + { +@@ -554,15 +556,6 @@ static void mtk_mac_link_up(struct phyli + phylink_config); + u32 mcr; + +- if (phy_interface_mode_is_8023z(interface)) { +- struct mtk_eth *eth = mac->hw; +- +- /* Decide how GMAC and SGMIISYS be mapped */ +- int sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? +- 0 : mac->id; +- mtk_sgmii_link_up(eth->sgmii, sid, speed, duplex); +- } +- + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); + mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | + MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | +@@ -595,8 +588,8 @@ static void mtk_mac_link_up(struct phyli + + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, ++ .mac_select_pcs = mtk_mac_select_pcs, + .mac_pcs_get_state = mtk_mac_pcs_get_state, +- .mac_an_restart = mtk_mac_an_restart, + .mac_config = mtk_mac_config, + .mac_finish = mtk_mac_finish, + .mac_link_down = mtk_mac_link_down, +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -963,10 +963,12 @@ struct mtk_soc_data { + * @regmap: The register map pointing at the range used to setup + * SGMII modes + * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap ++ * @pcs: Phylink PCS structure + */ + struct mtk_pcs { + struct regmap *regmap; + u32 ana_rgc3; ++ struct phylink_pcs pcs; + }; + + /* struct mtk_sgmii - This is the structure holding sgmii regmap and its +@@ -1106,12 +1108,9 @@ void mtk_stats_update_mac(struct mtk_mac + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); + u32 mtk_r32(struct mtk_eth *eth, unsigned reg); + ++struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id); + int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, + u32 ana_rgc3); +-int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, +- phy_interface_t interface); +-void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex); +-void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -14,14 +14,16 @@ + + #include "mtk_eth_soc.h" + ++static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs) ++{ ++ return container_of(pcs, struct mtk_pcs, pcs); ++} ++ + /* For SGMII interface mode */ + static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) + { + unsigned int val; + +- if (!mpcs->regmap) +- return -EINVAL; +- + /* Setup the link timer and QPHY power up inside SGMIISYS */ + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, + SGMII_LINK_TIMER_DEFAULT); +@@ -50,9 +52,6 @@ static int mtk_pcs_setup_mode_force(stru + { + unsigned int val; + +- if (!mpcs->regmap) +- return -EINVAL; +- + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); + val &= ~RG_PHY_SPEED_MASK; + if (interface == PHY_INTERFACE_MODE_2500BASEX) +@@ -78,10 +77,12 @@ static int mtk_pcs_setup_mode_force(stru + return 0; + } + +-int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode, +- phy_interface_t interface) ++static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) + { +- struct mtk_pcs *mpcs = &ss->pcs[id]; ++ struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); + int err = 0; + + /* Setup SGMIISYS with the determined property */ +@@ -93,22 +94,25 @@ int mtk_sgmii_config(struct mtk_sgmii *s + return err; + } + +-static void mtk_pcs_restart_an(struct mtk_pcs *mpcs) ++static void mtk_pcs_restart_an(struct phylink_pcs *pcs) + { ++ struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); + unsigned int val; + +- if (!mpcs->regmap) +- return; +- + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); + val |= SGMII_AN_RESTART; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + } + +-static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex) ++static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, int speed, int duplex) + { ++ struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); + unsigned int val; + ++ if (!phy_interface_mode_is_8023z(interface)) ++ return; ++ + /* SGMII force duplex setting */ + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); + val &= ~SGMII_DUPLEX_FULL; +@@ -118,11 +122,11 @@ static void mtk_pcs_link_up(struct mtk_p + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + } + +-/* For 1000BASE-X and 2500BASE-X interface modes */ +-void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex) +-{ +- mtk_pcs_link_up(&ss->pcs[id], speed, duplex); +-} ++static const struct phylink_pcs_ops mtk_pcs_ops = { ++ .pcs_config = mtk_pcs_config, ++ .pcs_an_restart = mtk_pcs_restart_an, ++ .pcs_link_up = mtk_pcs_link_up, ++}; + + int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) + { +@@ -139,18 +143,17 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + of_node_put(np); + if (IS_ERR(ss->pcs[i].regmap)) + return PTR_ERR(ss->pcs[i].regmap); ++ ++ ss->pcs[i].pcs.ops = &mtk_pcs_ops; + } + + return 0; + } + +-void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) ++struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id) + { +- unsigned int sid; +- +- /* Decide how GMAC and SGMIISYS be mapped */ +- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? +- 0 : mac_id; ++ if (!ss->pcs[id].regmap) ++ return NULL; + +- mtk_pcs_restart_an(ð->sgmii->pcs[sid]); ++ return &ss->pcs[id].pcs; + } diff --git a/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch new file mode 100644 index 00000000000000..74567109c57a12 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-01-v5.17-net-dsa-mt7530-iterate-using-dsa_switch_for_each_use.patch @@ -0,0 +1,106 @@ +From 505560028b6deb9b4385cf6100f05ca6f4aacaf8 Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean +Date: Mon, 6 Dec 2021 18:57:49 +0200 +Subject: [PATCH 01/13] net: dsa: mt7530: iterate using + dsa_switch_for_each_user_port in bridging ops + +Avoid repeated calls to dsa_to_port() (some hidden behind dsa_is_user_port +and some in plain sight) by keeping two struct dsa_port references: one +to the port passed as argument, and another to the other ports of the +switch that we're iterating over. + +dsa_to_port(ds, i) gets replaced by other_dp, i gets replaced by +other_port which is derived from other_dp->index, dsa_is_user_port is +handled by the DSA iterator. + +Signed-off-by: Vladimir Oltean +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++++++----------------- + 1 file changed, 30 insertions(+), 22 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1188,27 +1188,31 @@ static int + mt7530_port_bridge_join(struct dsa_switch *ds, int port, + struct net_device *bridge) + { +- struct mt7530_priv *priv = ds->priv; ++ struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; + u32 port_bitmap = BIT(MT7530_CPU_PORT); +- int i; ++ struct mt7530_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ dsa_switch_for_each_user_port(other_dp, ds) { ++ int other_port = other_dp->index; ++ ++ if (dp == other_dp) ++ continue; ++ + /* Add this port to the port matrix of the other ports in the + * same bridge. If the port is disabled, port matrix is kept + * and not being setup until the port becomes enabled. + */ +- if (dsa_is_user_port(ds, i) && i != port) { +- if (dsa_to_port(ds, i)->bridge_dev != bridge) +- continue; +- if (priv->ports[i].enable) +- mt7530_set(priv, MT7530_PCR_P(i), +- PCR_MATRIX(BIT(port))); +- priv->ports[i].pm |= PCR_MATRIX(BIT(port)); ++ if (other_dp->bridge_dev != bridge) ++ continue; + +- port_bitmap |= BIT(i); +- } ++ if (priv->ports[other_port].enable) ++ mt7530_set(priv, MT7530_PCR_P(other_port), ++ PCR_MATRIX(BIT(port))); ++ priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); ++ ++ port_bitmap |= BIT(other_port); + } + + /* Add the all other ports to this port matrix. */ +@@ -1301,24 +1305,28 @@ static void + mt7530_port_bridge_leave(struct dsa_switch *ds, int port, + struct net_device *bridge) + { ++ struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; + struct mt7530_priv *priv = ds->priv; +- int i; + + mutex_lock(&priv->reg_mutex); + +- for (i = 0; i < MT7530_NUM_PORTS; i++) { ++ dsa_switch_for_each_user_port(other_dp, ds) { ++ int other_port = other_dp->index; ++ ++ if (dp == other_dp) ++ continue; ++ + /* Remove this port from the port matrix of the other ports + * in the same bridge. If the port is disabled, port matrix + * is kept and not being setup until the port becomes enabled. + */ +- if (dsa_is_user_port(ds, i) && i != port) { +- if (dsa_to_port(ds, i)->bridge_dev != bridge) +- continue; +- if (priv->ports[i].enable) +- mt7530_clear(priv, MT7530_PCR_P(i), +- PCR_MATRIX(BIT(port))); +- priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); +- } ++ if (other_dp->bridge_dev != bridge) ++ continue; ++ ++ if (priv->ports[other_port].enable) ++ mt7530_clear(priv, MT7530_PCR_P(other_port), ++ PCR_MATRIX(BIT(port))); ++ priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); + } + + /* Set the cpu port to be the only one in the port matrix of diff --git a/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch new file mode 100644 index 00000000000000..690cc78fb5aa96 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-02-v5.19-net-dsa-mt7530-populate-supported_interfaces-and-mac.patch @@ -0,0 +1,166 @@ +From a1da54bcd664fc27169386db966575675ac3ccb0 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:01 +0100 +Subject: [PATCH 02/13] net: dsa: mt7530: populate supported_interfaces and + mac_capabilities +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Populate the supported interfaces and MAC capabilities for mt7530, +mt7531 and mt7621 DSA switches. Filling this in will enable phylink +to pre-check the PHY interface mode against the the supported +interfaces bitmap prior to calling the validate function, and will +eventually allow us to convert to using the generic validation. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 74 ++++++++++++++++++++++++++++++++++++++++ + drivers/net/dsa/mt7530.h | 2 ++ + 2 files changed, 76 insertions(+) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2385,6 +2385,32 @@ mt7531_setup(struct dsa_switch *ds) + return 0; + } + ++static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, ++ struct phylink_config *config) ++{ ++ switch (port) { ++ case 0 ... 4: /* Internal phy */ ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ config->supported_interfaces); ++ break; ++ ++ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ ++ phy_interface_set_rgmii(config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_MII, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ config->supported_interfaces); ++ break; ++ ++ case 6: /* 1st cpu port */ ++ __set_bit(PHY_INTERFACE_MODE_RGMII, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_TRGMII, ++ config->supported_interfaces); ++ break; ++ } ++} ++ + static bool + mt7530_phy_mode_supported(struct dsa_switch *ds, int port, + const struct phylink_link_state *state) +@@ -2421,6 +2447,37 @@ static bool mt7531_is_rgmii_port(struct + return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); + } + ++static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, ++ struct phylink_config *config) ++{ ++ struct mt7530_priv *priv = ds->priv; ++ ++ switch (port) { ++ case 0 ... 4: /* Internal phy */ ++ __set_bit(PHY_INTERFACE_MODE_GMII, ++ config->supported_interfaces); ++ break; ++ ++ case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ ++ if (mt7531_is_rgmii_port(priv, port)) { ++ phy_interface_set_rgmii(config->supported_interfaces); ++ break; ++ } ++ fallthrough; ++ ++ case 6: /* 1st cpu port supports sgmii/8023z only */ ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_1000BASEX, ++ config->supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ config->supported_interfaces); ++ ++ config->mac_capabilities |= MAC_2500FD; ++ break; ++ } ++} ++ + static bool + mt7531_phy_mode_supported(struct dsa_switch *ds, int port, + const struct phylink_link_state *state) +@@ -2899,6 +2956,18 @@ mt7531_cpu_port_config(struct dsa_switch + return 0; + } + ++static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, ++ struct phylink_config *config) ++{ ++ struct mt7530_priv *priv = ds->priv; ++ ++ /* This switch only supports full-duplex at 1Gbps */ ++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | ++ MAC_10 | MAC_100 | MAC_1000FD; ++ ++ priv->info->mac_port_get_caps(ds, port, config); ++} ++ + static void + mt7530_mac_port_validate(struct dsa_switch *ds, int port, + unsigned long *supported) +@@ -3134,6 +3203,7 @@ static const struct dsa_switch_ops mt753 + .port_vlan_del = mt7530_port_vlan_del, + .port_mirror_add = mt753x_port_mirror_add, + .port_mirror_del = mt753x_port_mirror_del, ++ .phylink_get_caps = mt753x_phylink_get_caps, + .phylink_validate = mt753x_phylink_validate, + .phylink_mac_link_state = mt753x_phylink_mac_link_state, + .phylink_mac_config = mt753x_phylink_mac_config, +@@ -3151,6 +3221,7 @@ static const struct mt753x_info mt753x_t + .phy_read = mt7530_phy_read, + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, ++ .mac_port_get_caps = mt7530_mac_port_get_caps, + .phy_mode_supported = mt7530_phy_mode_supported, + .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, +@@ -3162,6 +3233,7 @@ static const struct mt753x_info mt753x_t + .phy_read = mt7530_phy_read, + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, ++ .mac_port_get_caps = mt7530_mac_port_get_caps, + .phy_mode_supported = mt7530_phy_mode_supported, + .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, +@@ -3174,6 +3246,7 @@ static const struct mt753x_info mt753x_t + .phy_write = mt7531_ind_phy_write, + .pad_setup = mt7531_pad_setup, + .cpu_port_config = mt7531_cpu_port_config, ++ .mac_port_get_caps = mt7531_mac_port_get_caps, + .phy_mode_supported = mt7531_phy_mode_supported, + .mac_port_validate = mt7531_mac_port_validate, + .mac_port_get_state = mt7531_phylink_mac_link_state, +@@ -3236,6 +3309,7 @@ mt7530_probe(struct mdio_device *mdiodev + */ + if (!priv->info->sw_setup || !priv->info->pad_setup || + !priv->info->phy_read || !priv->info->phy_write || ++ !priv->info->mac_port_get_caps || + !priv->info->phy_mode_supported || + !priv->info->mac_port_validate || + !priv->info->mac_port_get_state || !priv->info->mac_port_config) +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -769,6 +769,8 @@ struct mt753x_info { + int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); + int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); + int (*cpu_port_config)(struct dsa_switch *ds, int port); ++ void (*mac_port_get_caps)(struct dsa_switch *ds, int port, ++ struct phylink_config *config); + bool (*phy_mode_supported)(struct dsa_switch *ds, int port, + const struct phylink_link_state *state); + void (*mac_port_validate)(struct dsa_switch *ds, int port, diff --git a/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch new file mode 100644 index 00000000000000..60eee013d1a393 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-03-v5.19-net-dsa-mt7530-remove-interface-checks.patch @@ -0,0 +1,172 @@ +From e3f6719e2269868ca129b05da50cd55786848954 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:06 +0100 +Subject: [PATCH 03/13] net: dsa: mt7530: remove interface checks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +As phylink checks the interface mode against the supported_interfaces +bitmap, we no longer need to validate the interface mode, nor handle +PHY_INTERFACE_MODE_NA in the validation function. Remove these to +simplify the implementation. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 82 ---------------------------------------- + drivers/net/dsa/mt7530.h | 2 - + 2 files changed, 84 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2411,37 +2411,6 @@ static void mt7530_mac_port_get_caps(str + } + } + +-static bool +-mt7530_phy_mode_supported(struct dsa_switch *ds, int port, +- const struct phylink_link_state *state) +-{ +- struct mt7530_priv *priv = ds->priv; +- +- switch (port) { +- case 0 ... 4: /* Internal phy */ +- if (state->interface != PHY_INTERFACE_MODE_GMII) +- return false; +- break; +- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ +- if (!phy_interface_mode_is_rgmii(state->interface) && +- state->interface != PHY_INTERFACE_MODE_MII && +- state->interface != PHY_INTERFACE_MODE_GMII) +- return false; +- break; +- case 6: /* 1st cpu port */ +- if (state->interface != PHY_INTERFACE_MODE_RGMII && +- state->interface != PHY_INTERFACE_MODE_TRGMII) +- return false; +- break; +- default: +- dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, +- port); +- return false; +- } +- +- return true; +-} +- + static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) + { + return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); +@@ -2478,44 +2447,6 @@ static void mt7531_mac_port_get_caps(str + } + } + +-static bool +-mt7531_phy_mode_supported(struct dsa_switch *ds, int port, +- const struct phylink_link_state *state) +-{ +- struct mt7530_priv *priv = ds->priv; +- +- switch (port) { +- case 0 ... 4: /* Internal phy */ +- if (state->interface != PHY_INTERFACE_MODE_GMII) +- return false; +- break; +- case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ +- if (mt7531_is_rgmii_port(priv, port)) +- return phy_interface_mode_is_rgmii(state->interface); +- fallthrough; +- case 6: /* 1st cpu port supports sgmii/8023z only */ +- if (state->interface != PHY_INTERFACE_MODE_SGMII && +- !phy_interface_mode_is_8023z(state->interface)) +- return false; +- break; +- default: +- dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, +- port); +- return false; +- } +- +- return true; +-} +- +-static bool +-mt753x_phy_mode_supported(struct dsa_switch *ds, int port, +- const struct phylink_link_state *state) +-{ +- struct mt7530_priv *priv = ds->priv; +- +- return priv->info->phy_mode_supported(ds, port, state); +-} +- + static int + mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) + { +@@ -2770,9 +2701,6 @@ mt753x_phylink_mac_config(struct dsa_swi + struct mt7530_priv *priv = ds->priv; + u32 mcr_cur, mcr_new; + +- if (!mt753x_phy_mode_supported(ds, port, state)) +- goto unsupported; +- + switch (port) { + case 0 ... 4: /* Internal phy */ + if (state->interface != PHY_INTERFACE_MODE_GMII) +@@ -2990,12 +2918,6 @@ mt753x_phylink_validate(struct dsa_switc + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + struct mt7530_priv *priv = ds->priv; + +- if (state->interface != PHY_INTERFACE_MODE_NA && +- !mt753x_phy_mode_supported(ds, port, state)) { +- linkmode_zero(supported); +- return; +- } +- + phylink_set_port_modes(mask); + + if (state->interface != PHY_INTERFACE_MODE_TRGMII && +@@ -3222,7 +3144,6 @@ static const struct mt753x_info mt753x_t + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .phy_mode_supported = mt7530_phy_mode_supported, + .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, +@@ -3234,7 +3155,6 @@ static const struct mt753x_info mt753x_t + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .phy_mode_supported = mt7530_phy_mode_supported, + .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, +@@ -3247,7 +3167,6 @@ static const struct mt753x_info mt753x_t + .pad_setup = mt7531_pad_setup, + .cpu_port_config = mt7531_cpu_port_config, + .mac_port_get_caps = mt7531_mac_port_get_caps, +- .phy_mode_supported = mt7531_phy_mode_supported, + .mac_port_validate = mt7531_mac_port_validate, + .mac_port_get_state = mt7531_phylink_mac_link_state, + .mac_port_config = mt7531_mac_config, +@@ -3310,7 +3229,6 @@ mt7530_probe(struct mdio_device *mdiodev + if (!priv->info->sw_setup || !priv->info->pad_setup || + !priv->info->phy_read || !priv->info->phy_write || + !priv->info->mac_port_get_caps || +- !priv->info->phy_mode_supported || + !priv->info->mac_port_validate || + !priv->info->mac_port_get_state || !priv->info->mac_port_config) + return -EINVAL; +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -771,8 +771,6 @@ struct mt753x_info { + int (*cpu_port_config)(struct dsa_switch *ds, int port); + void (*mac_port_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); +- bool (*phy_mode_supported)(struct dsa_switch *ds, int port, +- const struct phylink_link_state *state); + void (*mac_port_validate)(struct dsa_switch *ds, int port, + unsigned long *supported); + int (*mac_port_get_state)(struct dsa_switch *ds, int port, diff --git a/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch new file mode 100644 index 00000000000000..22bb2068de0a61 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-04-v5.19-net-dsa-mt7530-drop-use-of-phylink_helper_basex_spee.patch @@ -0,0 +1,34 @@ +From 58344a3b85f1bd5ffddfc2c11f6f2bf688b5f990 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:12 +0100 +Subject: [PATCH 04/13] net: dsa: mt7530: drop use of + phylink_helper_basex_speed() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Now that we have a better method to select SFP interface modes, we +no longer need to use phylink_helper_basex_speed() in a driver's +validation function. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 5 ----- + 1 file changed, 5 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2942,11 +2942,6 @@ mt753x_phylink_validate(struct dsa_switc + + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); +- +- /* We can only operate at 2500BaseX or 1000BaseX. If requested +- * to advertise both, only report advertising at 2500BaseX. +- */ +- phylink_helper_basex_speed(state); + } + + static int diff --git a/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch new file mode 100644 index 00000000000000..d5d7c54974632f --- /dev/null +++ b/target/linux/generic/backport-5.15/705-05-v5.19-net-dsa-mt7530-only-indicate-linkmodes-that-can-be-s.patch @@ -0,0 +1,86 @@ +From 3c1d788a62dc648d1846049b66119ebb69dedd52 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:17 +0100 +Subject: [PATCH 05/13] net: dsa: mt7530: only indicate linkmodes that can be + supported +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Now that mt7530 is not using the basex helper, it becomes unnecessary to +indicate support for both 1000baseX and 2500baseX when one of the 803.3z +PHY interface modes is being selected. Ensure that the driver indicates +only those linkmodes that can actually be supported by the PHY interface +mode. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 12 ++++++++---- + drivers/net/dsa/mt7530.h | 1 + + 2 files changed, 9 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2518,12 +2518,13 @@ static int mt7531_rgmii_setup(struct mt7 + } + + static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, ++ phy_interface_t interface, + unsigned long *supported) + { + /* Port5 supports ethier RGMII or SGMII. + * Port6 supports SGMII only. + */ +- if (port == 6) { ++ if (port == 6 && interface == PHY_INTERFACE_MODE_2500BASEX) { + phylink_set(supported, 2500baseX_Full); + phylink_set(supported, 2500baseT_Full); + } +@@ -2898,16 +2899,18 @@ static void mt753x_phylink_get_caps(stru + + static void + mt7530_mac_port_validate(struct dsa_switch *ds, int port, ++ phy_interface_t interface, + unsigned long *supported) + { + } + + static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, ++ phy_interface_t interface, + unsigned long *supported) + { + struct mt7530_priv *priv = ds->priv; + +- mt7531_sgmii_validate(priv, port, supported); ++ mt7531_sgmii_validate(priv, port, interface, supported); + } + + static void +@@ -2930,12 +2933,13 @@ mt753x_phylink_validate(struct dsa_switc + } + + /* This switch only supports 1G full-duplex. */ +- if (state->interface != PHY_INTERFACE_MODE_MII) { ++ if (state->interface != PHY_INTERFACE_MODE_MII && ++ state->interface != PHY_INTERFACE_MODE_2500BASEX) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + } + +- priv->info->mac_port_validate(ds, port, mask); ++ priv->info->mac_port_validate(ds, port, state->interface, mask); + + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -772,6 +772,7 @@ struct mt753x_info { + void (*mac_port_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); + void (*mac_port_validate)(struct dsa_switch *ds, int port, ++ phy_interface_t interface, + unsigned long *supported); + int (*mac_port_get_state)(struct dsa_switch *ds, int port, + struct phylink_link_state *state); diff --git a/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch new file mode 100644 index 00000000000000..4a2c2f151d5f6f --- /dev/null +++ b/target/linux/generic/backport-5.15/705-06-v5.19-net-dsa-mt7530-switch-to-use-phylink_get_linkmodes.patch @@ -0,0 +1,131 @@ +From 1c2211cb15dd3957fb26c0e1615eceb5db851ad6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:22 +0100 +Subject: [PATCH 06/13] net: dsa: mt7530: switch to use phylink_get_linkmodes() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Switch mt7530 to use phylink_get_linkmodes() to generate the ethtool +linkmodes that can be supported. We are unable to use the generic +helper for this as pause modes are dependent on the interface as +the Autoneg bit depends on the interface mode. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 57 ++++------------------------------------ + 1 file changed, 5 insertions(+), 52 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2517,19 +2517,6 @@ static int mt7531_rgmii_setup(struct mt7 + return 0; + } + +-static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, +- phy_interface_t interface, +- unsigned long *supported) +-{ +- /* Port5 supports ethier RGMII or SGMII. +- * Port6 supports SGMII only. +- */ +- if (port == 6 && interface == PHY_INTERFACE_MODE_2500BASEX) { +- phylink_set(supported, 2500baseX_Full); +- phylink_set(supported, 2500baseT_Full); +- } +-} +- + static void + mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, + unsigned int mode, phy_interface_t interface, +@@ -2898,51 +2885,21 @@ static void mt753x_phylink_get_caps(stru + } + + static void +-mt7530_mac_port_validate(struct dsa_switch *ds, int port, +- phy_interface_t interface, +- unsigned long *supported) +-{ +-} +- +-static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, +- phy_interface_t interface, +- unsigned long *supported) +-{ +- struct mt7530_priv *priv = ds->priv; +- +- mt7531_sgmii_validate(priv, port, interface, supported); +-} +- +-static void + mt753x_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) + { + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +- struct mt7530_priv *priv = ds->priv; ++ u32 caps; ++ ++ caps = dsa_to_port(ds, port)->pl_config.mac_capabilities; + + phylink_set_port_modes(mask); ++ phylink_get_linkmodes(mask, state->interface, caps); + + if (state->interface != PHY_INTERFACE_MODE_TRGMII && +- !phy_interface_mode_is_8023z(state->interface)) { +- phylink_set(mask, 10baseT_Half); +- phylink_set(mask, 10baseT_Full); +- phylink_set(mask, 100baseT_Half); +- phylink_set(mask, 100baseT_Full); ++ !phy_interface_mode_is_8023z(state->interface)) + phylink_set(mask, Autoneg); +- } +- +- /* This switch only supports 1G full-duplex. */ +- if (state->interface != PHY_INTERFACE_MODE_MII && +- state->interface != PHY_INTERFACE_MODE_2500BASEX) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseX_Full); +- } +- +- priv->info->mac_port_validate(ds, port, state->interface, mask); +- +- phylink_set(mask, Pause); +- phylink_set(mask, Asym_Pause); + + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); +@@ -3143,7 +3100,6 @@ static const struct mt753x_info mt753x_t + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, + }, +@@ -3154,7 +3110,6 @@ static const struct mt753x_info mt753x_t + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .mac_port_validate = mt7530_mac_port_validate, + .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, + }, +@@ -3166,7 +3121,6 @@ static const struct mt753x_info mt753x_t + .pad_setup = mt7531_pad_setup, + .cpu_port_config = mt7531_cpu_port_config, + .mac_port_get_caps = mt7531_mac_port_get_caps, +- .mac_port_validate = mt7531_mac_port_validate, + .mac_port_get_state = mt7531_phylink_mac_link_state, + .mac_port_config = mt7531_mac_config, + .mac_pcs_an_restart = mt7531_sgmii_restart_an, +@@ -3228,7 +3182,6 @@ mt7530_probe(struct mdio_device *mdiodev + if (!priv->info->sw_setup || !priv->info->pad_setup || + !priv->info->phy_read || !priv->info->phy_write || + !priv->info->mac_port_get_caps || +- !priv->info->mac_port_validate || + !priv->info->mac_port_get_state || !priv->info->mac_port_config) + return -EINVAL; + diff --git a/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch new file mode 100644 index 00000000000000..8a66b7fb0bbeed --- /dev/null +++ b/target/linux/generic/backport-5.15/705-07-v5.19-net-dsa-mt7530-partially-convert-to-phylink_pcs.patch @@ -0,0 +1,385 @@ +From fd993fd59d96d5e2d5972ec4ca1f9651025c987b Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:27 +0100 +Subject: [PATCH 07/13] net: dsa: mt7530: partially convert to phylink_pcs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Partially convert the mt7530 driver to use phylink's PCS support. This +is a partial implementation as we don't move anything into the +pcs_config method yet - this driver supports SGMII or 1000BASE-X +without in-band. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 144 +++++++++++++++++++++++---------------- + drivers/net/dsa/mt7530.h | 21 +++--- + 2 files changed, 95 insertions(+), 70 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -24,6 +24,11 @@ + + #include "mt7530.h" + ++static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) ++{ ++ return container_of(pcs, struct mt753x_pcs, pcs); ++} ++ + /* String, offset, and register size in bytes if different from 4 bytes */ + static const struct mt7530_mib_desc mt7530_mib[] = { + MIB_DESC(1, 0x00, "TxDrop"), +@@ -2517,12 +2522,11 @@ static int mt7531_rgmii_setup(struct mt7 + return 0; + } + +-static void +-mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex) ++static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, int speed, int duplex) + { +- struct mt7530_priv *priv = ds->priv; ++ struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; ++ int port = pcs_to_mt753x_pcs(pcs)->port; + unsigned int val; + + /* For adjusting speed and duplex of SGMII force mode. */ +@@ -2548,6 +2552,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw + + /* MT7531 SGMII 1G force mode can only work in full duplex mode, + * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. ++ * ++ * The speed check is unnecessary as the MAC capabilities apply ++ * this restriction. --rmk + */ + if ((speed == SPEED_10 || speed == SPEED_100) && + duplex != DUPLEX_FULL) +@@ -2623,9 +2630,10 @@ static int mt7531_sgmii_setup_mode_an(st + return 0; + } + +-static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) ++static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) + { +- struct mt7530_priv *priv = ds->priv; ++ struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; ++ int port = pcs_to_mt753x_pcs(pcs)->port; + u32 val; + + /* Only restart AN when AN is enabled */ +@@ -2682,6 +2690,24 @@ mt753x_mac_config(struct dsa_switch *ds, + return priv->info->mac_port_config(ds, port, mode, state->interface); + } + ++static struct phylink_pcs * ++mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, ++ phy_interface_t interface) ++{ ++ struct mt7530_priv *priv = ds->priv; ++ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_TRGMII: ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ return &priv->pcs[port].pcs; ++ ++ default: ++ return NULL; ++ } ++} ++ + static void + mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, + const struct phylink_link_state *state) +@@ -2743,17 +2769,6 @@ unsupported: + mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); + } + +-static void +-mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) +-{ +- struct mt7530_priv *priv = ds->priv; +- +- if (!priv->info->mac_pcs_an_restart) +- return; +- +- priv->info->mac_pcs_an_restart(ds, port); +-} +- + static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +@@ -2763,16 +2778,13 @@ static void mt753x_phylink_mac_link_down + mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); + } + +-static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex) ++static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, ++ unsigned int mode, ++ phy_interface_t interface, ++ int speed, int duplex) + { +- struct mt7530_priv *priv = ds->priv; +- +- if (!priv->info->mac_pcs_link_up) +- return; +- +- priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); ++ if (pcs->ops->pcs_link_up) ++ pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); + } + + static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, +@@ -2785,8 +2797,6 @@ static void mt753x_phylink_mac_link_up(s + struct mt7530_priv *priv = ds->priv; + u32 mcr; + +- mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); +- + mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; + + /* MT753x MAC works in 1G full duplex mode for all up-clocked +@@ -2866,6 +2876,8 @@ mt7531_cpu_port_config(struct dsa_switch + return ret; + mt7530_write(priv, MT7530_PMCR_P(port), + PMCR_CPU_PORT_SETTING(priv->id)); ++ mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, ++ interface, speed, DUPLEX_FULL); + mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, + speed, DUPLEX_FULL, true, true); + +@@ -2905,16 +2917,13 @@ mt753x_phylink_validate(struct dsa_switc + linkmode_and(state->advertising, state->advertising, mask); + } + +-static int +-mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, +- struct phylink_link_state *state) ++static void mt7530_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) + { +- struct mt7530_priv *priv = ds->priv; ++ struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; ++ int port = pcs_to_mt753x_pcs(pcs)->port; + u32 pmsr; + +- if (port < 0 || port >= MT7530_NUM_PORTS) +- return -EINVAL; +- + pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); + + state->link = (pmsr & PMSR_LINK); +@@ -2941,8 +2950,6 @@ mt7530_phylink_mac_link_state(struct dsa + state->pause |= MLO_PAUSE_RX; + if (pmsr & PMSR_TX_FC) + state->pause |= MLO_PAUSE_TX; +- +- return 1; + } + + static int +@@ -2984,32 +2991,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 + return 0; + } + +-static int +-mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, +- struct phylink_link_state *state) ++static void mt7531_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) + { +- struct mt7530_priv *priv = ds->priv; ++ struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; ++ int port = pcs_to_mt753x_pcs(pcs)->port; + + if (state->interface == PHY_INTERFACE_MODE_SGMII) +- return mt7531_sgmii_pcs_get_state_an(priv, port, state); +- +- return -EOPNOTSUPP; ++ mt7531_sgmii_pcs_get_state_an(priv, port, state); ++ else ++ state->link = false; + } + +-static int +-mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, +- struct phylink_link_state *state) ++static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) + { +- struct mt7530_priv *priv = ds->priv; ++ return 0; ++} + +- return priv->info->mac_port_get_state(ds, port, state); ++static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) ++{ + } + ++static const struct phylink_pcs_ops mt7530_pcs_ops = { ++ .pcs_get_state = mt7530_pcs_get_state, ++ .pcs_config = mt753x_pcs_config, ++ .pcs_an_restart = mt7530_pcs_an_restart, ++}; ++ ++static const struct phylink_pcs_ops mt7531_pcs_ops = { ++ .pcs_get_state = mt7531_pcs_get_state, ++ .pcs_config = mt753x_pcs_config, ++ .pcs_an_restart = mt7531_pcs_an_restart, ++ .pcs_link_up = mt7531_pcs_link_up, ++}; ++ + static int + mt753x_setup(struct dsa_switch *ds) + { + struct mt7530_priv *priv = ds->priv; + int ret = priv->info->sw_setup(ds); ++ int i; + + if (ret) + return ret; +@@ -3022,6 +3046,13 @@ mt753x_setup(struct dsa_switch *ds) + if (ret && priv->irq) + mt7530_free_irq_common(priv); + ++ /* Initialise the PCS devices */ ++ for (i = 0; i < priv->ds->num_ports; i++) { ++ priv->pcs[i].pcs.ops = priv->info->pcs_ops; ++ priv->pcs[i].priv = priv; ++ priv->pcs[i].port = i; ++ } ++ + return ret; + } + +@@ -3083,9 +3114,8 @@ static const struct dsa_switch_ops mt753 + .port_mirror_del = mt753x_port_mirror_del, + .phylink_get_caps = mt753x_phylink_get_caps, + .phylink_validate = mt753x_phylink_validate, +- .phylink_mac_link_state = mt753x_phylink_mac_link_state, ++ .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, + .phylink_mac_config = mt753x_phylink_mac_config, +- .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, + .phylink_mac_link_down = mt753x_phylink_mac_link_down, + .phylink_mac_link_up = mt753x_phylink_mac_link_up, + .get_mac_eee = mt753x_get_mac_eee, +@@ -3095,36 +3125,34 @@ static const struct dsa_switch_ops mt753 + static const struct mt753x_info mt753x_table[] = { + [ID_MT7621] = { + .id = ID_MT7621, ++ .pcs_ops = &mt7530_pcs_ops, + .sw_setup = mt7530_setup, + .phy_read = mt7530_phy_read, + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, + }, + [ID_MT7530] = { + .id = ID_MT7530, ++ .pcs_ops = &mt7530_pcs_ops, + .sw_setup = mt7530_setup, + .phy_read = mt7530_phy_read, + .phy_write = mt7530_phy_write, + .pad_setup = mt7530_pad_clk_setup, + .mac_port_get_caps = mt7530_mac_port_get_caps, +- .mac_port_get_state = mt7530_phylink_mac_link_state, + .mac_port_config = mt7530_mac_config, + }, + [ID_MT7531] = { + .id = ID_MT7531, ++ .pcs_ops = &mt7531_pcs_ops, + .sw_setup = mt7531_setup, + .phy_read = mt7531_ind_phy_read, + .phy_write = mt7531_ind_phy_write, + .pad_setup = mt7531_pad_setup, + .cpu_port_config = mt7531_cpu_port_config, + .mac_port_get_caps = mt7531_mac_port_get_caps, +- .mac_port_get_state = mt7531_phylink_mac_link_state, + .mac_port_config = mt7531_mac_config, +- .mac_pcs_an_restart = mt7531_sgmii_restart_an, +- .mac_pcs_link_up = mt7531_sgmii_link_up_force, + }, + }; + +@@ -3182,7 +3210,7 @@ mt7530_probe(struct mdio_device *mdiodev + if (!priv->info->sw_setup || !priv->info->pad_setup || + !priv->info->phy_read || !priv->info->phy_write || + !priv->info->mac_port_get_caps || +- !priv->info->mac_port_get_state || !priv->info->mac_port_config) ++ !priv->info->mac_port_config) + return -EINVAL; + + priv->id = priv->info->id; +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -741,6 +741,12 @@ static const char *p5_intf_modes(unsigne + + struct mt7530_priv; + ++struct mt753x_pcs { ++ struct phylink_pcs pcs; ++ struct mt7530_priv *priv; ++ int port; ++}; ++ + /* struct mt753x_info - This is the main data structure for holding the specific + * part for each supported device + * @sw_setup: Holding the handler to a device initialization +@@ -752,18 +758,14 @@ struct mt7530_priv; + * port + * @mac_port_validate: Holding the way to set addition validate type for a + * certan MAC port +- * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain +- * MAC port + * @mac_port_config: Holding the way setting up the PHY attribute to a + * certain MAC port +- * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a +- * certain MAC port +- * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs +- * of the certain MAC port + */ + struct mt753x_info { + enum mt753x_id id; + ++ const struct phylink_pcs_ops *pcs_ops; ++ + int (*sw_setup)(struct dsa_switch *ds); + int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); + int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); +@@ -774,15 +776,9 @@ struct mt753x_info { + void (*mac_port_validate)(struct dsa_switch *ds, int port, + phy_interface_t interface, + unsigned long *supported); +- int (*mac_port_get_state)(struct dsa_switch *ds, int port, +- struct phylink_link_state *state); + int (*mac_port_config)(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface); +- void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port); +- void (*mac_pcs_link_up)(struct dsa_switch *ds, int port, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex); + }; + + /* struct mt7530_priv - This is the main data structure for holding the state +@@ -824,6 +820,7 @@ struct mt7530_priv { + u8 mirror_tx; + + struct mt7530_port ports[MT7530_NUM_PORTS]; ++ struct mt753x_pcs pcs[MT7530_NUM_PORTS]; + /* protect among processes for registers access*/ + struct mutex reg_mutex; + int irq; diff --git a/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch new file mode 100644 index 00000000000000..2d8b4d5d571242 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-08-v5.19-net-dsa-mt7530-move-autoneg-handling-to-PCS-validati.patch @@ -0,0 +1,80 @@ +From 2b0ee6768f3ac09072e5fd60b36580924e1cfa1c Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:32 +0100 +Subject: [PATCH 08/13] net: dsa: mt7530: move autoneg handling to PCS + validation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move the autoneg bit handling to the PCS validation, which allows us to +get rid of mt753x_phylink_validate() and rely on the default +phylink_generic_validate() implementation for the MAC side. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 28 ++++++++++------------------ + 1 file changed, 10 insertions(+), 18 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2896,25 +2896,16 @@ static void mt753x_phylink_get_caps(stru + priv->info->mac_port_get_caps(ds, port, config); + } + +-static void +-mt753x_phylink_validate(struct dsa_switch *ds, int port, +- unsigned long *supported, +- struct phylink_link_state *state) +-{ +- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +- u32 caps; +- +- caps = dsa_to_port(ds, port)->pl_config.mac_capabilities; +- +- phylink_set_port_modes(mask); +- phylink_get_linkmodes(mask, state->interface, caps); ++static int mt753x_pcs_validate(struct phylink_pcs *pcs, ++ unsigned long *supported, ++ const struct phylink_link_state *state) ++{ ++ /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ ++ if (state->interface == PHY_INTERFACE_MODE_TRGMII || ++ phy_interface_mode_is_8023z(state->interface)) ++ phylink_clear(supported, Autoneg); + +- if (state->interface != PHY_INTERFACE_MODE_TRGMII && +- !phy_interface_mode_is_8023z(state->interface)) +- phylink_set(mask, Autoneg); +- +- linkmode_and(supported, supported, mask); +- linkmode_and(state->advertising, state->advertising, mask); ++ return 0; + } + + static void mt7530_pcs_get_state(struct phylink_pcs *pcs, +@@ -3016,12 +3007,14 @@ static void mt7530_pcs_an_restart(struct + } + + static const struct phylink_pcs_ops mt7530_pcs_ops = { ++ .pcs_validate = mt753x_pcs_validate, + .pcs_get_state = mt7530_pcs_get_state, + .pcs_config = mt753x_pcs_config, + .pcs_an_restart = mt7530_pcs_an_restart, + }; + + static const struct phylink_pcs_ops mt7531_pcs_ops = { ++ .pcs_validate = mt753x_pcs_validate, + .pcs_get_state = mt7531_pcs_get_state, + .pcs_config = mt753x_pcs_config, + .pcs_an_restart = mt7531_pcs_an_restart, +@@ -3113,7 +3106,6 @@ static const struct dsa_switch_ops mt753 + .port_mirror_add = mt753x_port_mirror_add, + .port_mirror_del = mt753x_port_mirror_del, + .phylink_get_caps = mt753x_phylink_get_caps, +- .phylink_validate = mt753x_phylink_validate, + .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, + .phylink_mac_config = mt753x_phylink_mac_config, + .phylink_mac_link_down = mt753x_phylink_mac_link_down, diff --git a/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch new file mode 100644 index 00000000000000..849a9925a157f3 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-09-v5.19-net-dsa-mt7530-mark-as-non-legacy.patch @@ -0,0 +1,34 @@ +From 5bc26de9bfaa6bb5539c09d4435dced98f429cfc Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 11 Apr 2022 10:46:37 +0100 +Subject: [PATCH 09/13] net: dsa: mt7530: mark as non-legacy +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The mt7530 driver does not make use of the speed, duplex, pause or +advertisement in its phylink_mac_config() implementation, so it can be +marked as a non-legacy driver. + +Tested-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: Paolo Abeni +--- + drivers/net/dsa/mt7530.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2893,6 +2893,12 @@ static void mt753x_phylink_get_caps(stru + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000FD; + ++ /* This driver does not make use of the speed, duplex, pause or the ++ * advertisement in its mac_config, so it is safe to mark this driver ++ * as non-legacy. ++ */ ++ config->legacy_pre_march2020 = false; ++ + priv->info->mac_port_get_caps(ds, port, config); + } + diff --git a/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch new file mode 100644 index 00000000000000..89f6e7509b2180 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-10-v5.19-net-dsa-mt753x-fix-pcs-conversion-regression.patch @@ -0,0 +1,116 @@ +From 1f15b5e8733115cee65342bcaafeaf0368809fae Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 25 Apr 2022 22:28:02 +0100 +Subject: [PATCH 10/13] net: dsa: mt753x: fix pcs conversion regression + +Daniel Golle reports that the conversion of mt753x to phylink PCS caused +an oops as below. + +The problem is with the placement of the PCS initialisation, which +occurs after mt7531_setup() has been called. However, burited in this +function is a call to setup the CPU port, which requires the PCS +structure to be already setup. + +Fix this by changing the initialisation order. + +Unable to handle kernel NULL pointer dereference at virtual address 0000000000000020 +Mem abort info: + ESR = 0x96000005 + EC = 0x25: DABT (current EL), IL = 32 bits + SET = 0, FnV = 0 + EA = 0, S1PTW = 0 + FSC = 0x05: level 1 translation fault +Data abort info: + ISV = 0, ISS = 0x00000005 + CM = 0, WnR = 0 +user pgtable: 4k pages, 39-bit VAs, pgdp=0000000046057000 +[0000000000000020] pgd=0000000000000000, p4d=0000000000000000, pud=0000000000000000 +Internal error: Oops: 96000005 [#1] SMP +Modules linked in: +CPU: 0 PID: 32 Comm: kworker/u4:1 Tainted: G S 5.18.0-rc3-next-20220422+ #0 +Hardware name: Bananapi BPI-R64 (DT) +Workqueue: events_unbound deferred_probe_work_func +pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) +pc : mt7531_cpu_port_config+0xcc/0x1b0 +lr : mt7531_cpu_port_config+0xc0/0x1b0 +sp : ffffffc008d5b980 +x29: ffffffc008d5b990 x28: ffffff80060562c8 x27: 00000000f805633b +x26: ffffff80001a8880 x25: 00000000000009c4 x24: 0000000000000016 +x23: ffffff8005eb6470 x22: 0000000000003600 x21: ffffff8006948080 +x20: 0000000000000000 x19: 0000000000000006 x18: 0000000000000000 +x17: 0000000000000001 x16: 0000000000000001 x15: 02963607fcee069e +x14: 0000000000000000 x13: 0000000000000030 x12: 0101010101010101 +x11: ffffffc037302000 x10: 0000000000000870 x9 : ffffffc008d5b800 +x8 : ffffff800028f950 x7 : 0000000000000001 x6 : 00000000662b3000 +x5 : 00000000000002f0 x4 : 0000000000000000 x3 : ffffff800028f080 +x2 : 0000000000000000 x1 : ffffff800028f080 x0 : 0000000000000000 +Call trace: + mt7531_cpu_port_config+0xcc/0x1b0 + mt753x_cpu_port_enable+0x24/0x1f0 + mt7531_setup+0x49c/0x5c0 + mt753x_setup+0x20/0x31c + dsa_register_switch+0x8bc/0x1020 + mt7530_probe+0x118/0x200 + mdio_probe+0x30/0x64 + really_probe.part.0+0x98/0x280 + __driver_probe_device+0x94/0x140 + driver_probe_device+0x40/0x114 + __device_attach_driver+0xb0/0x10c + bus_for_each_drv+0x64/0xa0 + __device_attach+0xa8/0x16c + device_initial_probe+0x10/0x20 + bus_probe_device+0x94/0x9c + deferred_probe_work_func+0x80/0xb4 + process_one_work+0x200/0x3a0 + worker_thread+0x260/0x4c0 + kthread+0xd4/0xe0 + ret_from_fork+0x10/0x20 +Code: 9409e911 937b7e60 8b0002a0 f9405800 (f9401005) +---[ end trace 0000000000000000 ]--- + +Reported-by: Daniel Golle +Tested-by: Daniel Golle +Fixes: cbd1f243bc41 ("net: dsa: mt7530: partially convert to phylink_pcs") +Signed-off-by: Russell King (Oracle) +Reviewed-by: Florian Fainelli +Link: https://lore.kernel.org/r/E1nj6FW-007WZB-5Y@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3031,9 +3031,16 @@ static int + mt753x_setup(struct dsa_switch *ds) + { + struct mt7530_priv *priv = ds->priv; +- int ret = priv->info->sw_setup(ds); +- int i; ++ int i, ret; + ++ /* Initialise the PCS devices */ ++ for (i = 0; i < priv->ds->num_ports; i++) { ++ priv->pcs[i].pcs.ops = priv->info->pcs_ops; ++ priv->pcs[i].priv = priv; ++ priv->pcs[i].port = i; ++ } ++ ++ ret = priv->info->sw_setup(ds); + if (ret) + return ret; + +@@ -3045,13 +3052,6 @@ mt753x_setup(struct dsa_switch *ds) + if (ret && priv->irq) + mt7530_free_irq_common(priv); + +- /* Initialise the PCS devices */ +- for (i = 0; i < priv->ds->num_ports; i++) { +- priv->pcs[i].pcs.ops = priv->info->pcs_ops; +- priv->pcs[i].priv = priv; +- priv->pcs[i].port = i; +- } +- + return ret; + } + diff --git a/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch new file mode 100644 index 00000000000000..77b4fa11023d34 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-11-v6.0-net-dsa-mt7530-rework-mt7530_hw_vlan_-add-del.patch @@ -0,0 +1,87 @@ +From e26be16262e1fc1e9f1798c12762663bd9c265c6 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 10 Jun 2022 19:05:37 +0200 +Subject: [PATCH 11/13] net: dsa: mt7530: rework mt7530_hw_vlan_{add,del} + +Rework vlan_add/vlan_del functions in preparation for dynamic cpu port. + +Currently BIT(MT7530_CPU_PORT) is added to new_members, even though +mt7530_port_vlan_add() will be called on the CPU port too. + +Let DSA core decide when to call port_vlan_add for the CPU port, rather +than doing it implicitly. + +We can do autonomous forwarding in a certain VLAN, but not add br0 to that +VLAN and avoid flooding the CPU with those packets, if software knows it +doesn't need to process them. + +Suggested-by: Vladimir Oltean +Signed-off-by: Frank Wunderlich +Reviewed-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 30 ++++++++++++------------------ + 1 file changed, 12 insertions(+), 18 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1522,11 +1522,11 @@ static void + mt7530_hw_vlan_add(struct mt7530_priv *priv, + struct mt7530_hw_vlan_entry *entry) + { ++ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); + u8 new_members; + u32 val; + +- new_members = entry->old_members | BIT(entry->port) | +- BIT(MT7530_CPU_PORT); ++ new_members = entry->old_members | BIT(entry->port); + + /* Validate the entry with independent learning, create egress tag per + * VLAN and joining the port as one of the port members. +@@ -1537,22 +1537,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p + + /* Decide whether adding tag or not for those outgoing packets from the + * port inside the VLAN. +- */ +- val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : +- MT7530_VLAN_EGRESS_TAG; +- mt7530_rmw(priv, MT7530_VAWD2, +- ETAG_CTRL_P_MASK(entry->port), +- ETAG_CTRL_P(entry->port, val)); +- +- /* CPU port is always taken as a tagged port for serving more than one ++ * CPU port is always taken as a tagged port for serving more than one + * VLANs across and also being applied with egress type stack mode for + * that VLAN tags would be appended after hardware special tag used as + * DSA tag. + */ ++ if (dsa_port_is_cpu(dp)) ++ val = MT7530_VLAN_EGRESS_STACK; ++ else if (entry->untagged) ++ val = MT7530_VLAN_EGRESS_UNTAG; ++ else ++ val = MT7530_VLAN_EGRESS_TAG; + mt7530_rmw(priv, MT7530_VAWD2, +- ETAG_CTRL_P_MASK(MT7530_CPU_PORT), +- ETAG_CTRL_P(MT7530_CPU_PORT, +- MT7530_VLAN_EGRESS_STACK)); ++ ETAG_CTRL_P_MASK(entry->port), ++ ETAG_CTRL_P(entry->port, val)); + } + + static void +@@ -1571,11 +1569,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p + return; + } + +- /* If certain member apart from CPU port is still alive in the VLAN, +- * the entry would be kept valid. Otherwise, the entry is got to be +- * disabled. +- */ +- if (new_members && new_members != BIT(MT7530_CPU_PORT)) { ++ if (new_members) { + val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | + VLAN_VALID; + mt7530_write(priv, MT7530_VAWD1, val); diff --git a/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch b/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch new file mode 100644 index 00000000000000..2324336ed8422e --- /dev/null +++ b/target/linux/generic/backport-5.15/705-12-v6.0-net-dsa-mt7530-rework-mt753-01-_setup.patch @@ -0,0 +1,75 @@ +From 1f0dfd443eea7fc3e818e96f7c8264913ba41859 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 10 Jun 2022 19:05:38 +0200 +Subject: [PATCH 12/13] net: dsa: mt7530: rework mt753[01]_setup + +Enumerate available cpu-ports instead of using hardcoded constant. + +Suggested-by: Vladimir Oltean +Signed-off-by: Frank Wunderlich +Reviewed-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 25 +++++++++++++++++++++---- + 1 file changed, 21 insertions(+), 4 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2087,11 +2087,12 @@ static int + mt7530_setup(struct dsa_switch *ds) + { + struct mt7530_priv *priv = ds->priv; ++ struct device_node *dn = NULL; + struct device_node *phy_node; + struct device_node *mac_np; + struct mt7530_dummy_poll p; + phy_interface_t interface; +- struct device_node *dn; ++ struct dsa_port *cpu_dp; + u32 id, val; + int ret, i; + +@@ -2099,7 +2100,19 @@ mt7530_setup(struct dsa_switch *ds) + * controller also is the container for two GMACs nodes representing + * as two netdev instances. + */ +- dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; ++ dsa_switch_for_each_cpu_port(cpu_dp, ds) { ++ dn = cpu_dp->master->dev.of_node->parent; ++ /* It doesn't matter which CPU port is found first, ++ * their masters should share the same parent OF node ++ */ ++ break; ++ } ++ ++ if (!dn) { ++ dev_err(ds->dev, "parent OF node of DSA master not found"); ++ return -EINVAL; ++ } ++ + ds->assisted_learning_on_cpu_port = true; + ds->mtu_enforcement_ingress = true; + +@@ -2261,6 +2274,7 @@ mt7531_setup(struct dsa_switch *ds) + { + struct mt7530_priv *priv = ds->priv; + struct mt7530_dummy_poll p; ++ struct dsa_port *cpu_dp; + u32 val, id; + int ret, i; + +@@ -2333,8 +2347,11 @@ mt7531_setup(struct dsa_switch *ds) + CORE_PLL_GROUP4, val); + + /* BPDU to CPU port */ +- mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, +- BIT(MT7530_CPU_PORT)); ++ dsa_switch_for_each_cpu_port(cpu_dp, ds) { ++ mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, ++ BIT(cpu_dp->index)); ++ break; ++ } + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, + MT753X_BPDU_CPU_ONLY); + diff --git a/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch new file mode 100644 index 00000000000000..3b5ce7363fcc37 --- /dev/null +++ b/target/linux/generic/backport-5.15/705-13-v6.0-net-dsa-mt7530-get-cpu-port-via-dp-cpu_dp-instead-of.patch @@ -0,0 +1,117 @@ +From ad2606f6fafae3a7d41c4f2af5554c8f6adecbc7 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 10 Jun 2022 19:05:39 +0200 +Subject: [PATCH 13/13] net: dsa: mt7530: get cpu-port via dp->cpu_dp instead + of constant + +Replace last occurences of hardcoded cpu-port by cpu_dp member of +dsa_port struct. + +Now the constant can be dropped. + +Suggested-by: Vladimir Oltean +Signed-off-by: Frank Wunderlich +Reviewed-by: Vladimir Oltean +Reviewed-by: Florian Fainelli +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530.c | 27 ++++++++++++++++++++------- + drivers/net/dsa/mt7530.h | 1 - + 2 files changed, 20 insertions(+), 8 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1038,6 +1038,7 @@ static int + mt7530_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phy) + { ++ struct dsa_port *dp = dsa_to_port(ds, port); + struct mt7530_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); +@@ -1046,7 +1047,11 @@ mt7530_port_enable(struct dsa_switch *ds + * restore the port matrix if the port is the member of a certain + * bridge. + */ +- priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); ++ if (dsa_port_is_user(dp)) { ++ struct dsa_port *cpu_dp = dp->cpu_dp; ++ ++ priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); ++ } + priv->ports[port].enable = true; + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, + priv->ports[port].pm); +@@ -1194,7 +1199,8 @@ mt7530_port_bridge_join(struct dsa_switc + struct net_device *bridge) + { + struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; +- u32 port_bitmap = BIT(MT7530_CPU_PORT); ++ struct dsa_port *cpu_dp = dp->cpu_dp; ++ u32 port_bitmap = BIT(cpu_dp->index); + struct mt7530_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); +@@ -1271,9 +1277,12 @@ mt7530_port_set_vlan_unaware(struct dsa_ + * the CPU port get out of VLAN filtering mode. + */ + if (all_user_ports_removed) { +- mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), ++ struct dsa_port *dp = dsa_to_port(ds, port); ++ struct dsa_port *cpu_dp = dp->cpu_dp; ++ ++ mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), + PCR_MATRIX(dsa_user_ports(priv->ds))); +- mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG ++ mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG + | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); + } + } +@@ -1311,6 +1320,7 @@ mt7530_port_bridge_leave(struct dsa_swit + struct net_device *bridge) + { + struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; ++ struct dsa_port *cpu_dp = dp->cpu_dp; + struct mt7530_priv *priv = ds->priv; + + mutex_lock(&priv->reg_mutex); +@@ -1339,8 +1349,8 @@ mt7530_port_bridge_leave(struct dsa_swit + */ + if (priv->ports[port].enable) + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, +- PCR_MATRIX(BIT(MT7530_CPU_PORT))); +- priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); ++ PCR_MATRIX(BIT(cpu_dp->index))); ++ priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); + + /* When a port is removed from the bridge, the port would be set up + * back to the default as is at initial boot which is a VLAN-unaware +@@ -1503,6 +1513,9 @@ static int + mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, + struct netlink_ext_ack *extack) + { ++ struct dsa_port *dp = dsa_to_port(ds, port); ++ struct dsa_port *cpu_dp = dp->cpu_dp; ++ + if (vlan_filtering) { + /* The port is being kept as VLAN-unaware port when bridge is + * set up with vlan_filtering not being set, Otherwise, the +@@ -1510,7 +1523,7 @@ mt7530_port_vlan_filtering(struct dsa_sw + * for becoming a VLAN-aware port. + */ + mt7530_port_set_vlan_aware(ds, port); +- mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); ++ mt7530_port_set_vlan_aware(ds, cpu_dp->index); + } else { + mt7530_port_set_vlan_unaware(ds, port); + } +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -8,7 +8,6 @@ + + #define MT7530_NUM_PORTS 7 + #define MT7530_NUM_PHYS 5 +-#define MT7530_CPU_PORT 6 + #define MT7530_NUM_FDB_RECORDS 2048 + #define MT7530_ALL_MEMBERS 0xff + diff --git a/target/linux/generic/backport-5.15/765-1-net-next-net-dsa-reorder-PHY-initialization-with-MTU-setup-in.patch b/target/linux/generic/backport-5.15/765-1-net-next-net-dsa-reorder-PHY-initialization-with-MTU-setup-in.patch index 1786bf03452e56..77cf63b809be20 100644 --- a/target/linux/generic/backport-5.15/765-1-net-next-net-dsa-reorder-PHY-initialization-with-MTU-setup-in.patch +++ b/target/linux/generic/backport-5.15/765-1-net-next-net-dsa-reorder-PHY-initialization-with-MTU-setup-in.patch @@ -22,7 +22,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/slave.c +++ b/net/dsa/slave.c -@@ -1986,13 +1986,6 @@ int dsa_slave_create(struct dsa_port *po +@@ -1977,13 +1977,6 @@ int dsa_slave_create(struct dsa_port *po port->slave = slave_dev; dsa_slave_setup_tagger(slave_dev); @@ -36,7 +36,7 @@ Signed-off-by: David S. Miller netif_carrier_off(slave_dev); ret = dsa_slave_phy_setup(slave_dev); -@@ -2004,6 +1997,13 @@ int dsa_slave_create(struct dsa_port *po +@@ -1995,6 +1988,13 @@ int dsa_slave_create(struct dsa_port *po } rtnl_lock(); diff --git a/target/linux/generic/backport-5.15/765-2-net-next-net-dsa-merge-rtnl_lock-sections-in-dsa_slave_create.patch b/target/linux/generic/backport-5.15/765-2-net-next-net-dsa-merge-rtnl_lock-sections-in-dsa_slave_create.patch index c2493a08fd91d1..50aa5d8f0dd534 100644 --- a/target/linux/generic/backport-5.15/765-2-net-next-net-dsa-merge-rtnl_lock-sections-in-dsa_slave_create.patch +++ b/target/linux/generic/backport-5.15/765-2-net-next-net-dsa-merge-rtnl_lock-sections-in-dsa_slave_create.patch @@ -16,7 +16,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/slave.c +++ b/net/dsa/slave.c -@@ -1997,14 +1997,12 @@ int dsa_slave_create(struct dsa_port *po +@@ -1988,14 +1988,12 @@ int dsa_slave_create(struct dsa_port *po } rtnl_lock(); diff --git a/target/linux/generic/backport-5.15/766-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch b/target/linux/generic/backport-5.15/766-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch index d73b7455866cbb..7c6a3a3f8d770d 100644 --- a/target/linux/generic/backport-5.15/766-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch +++ b/target/linux/generic/backport-5.15/766-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch @@ -68,7 +68,7 @@ Signed-off-by: David S. Miller static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p) { return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED; -@@ -916,6 +926,13 @@ struct dsa_switch_ops { +@@ -949,6 +959,13 @@ struct dsa_switch_ops { int (*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid, u16 flags); int (*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid); @@ -175,7 +175,7 @@ Signed-off-by: David S. Miller --- a/net/dsa/slave.c +++ b/net/dsa/slave.c -@@ -2320,6 +2320,36 @@ static int dsa_slave_netdevice_event(str +@@ -2311,6 +2311,36 @@ static int dsa_slave_netdevice_event(str err = dsa_port_lag_change(dp, info->lower_state_info); return notifier_from_errno(err); } @@ -212,7 +212,7 @@ Signed-off-by: David S. Miller case NETDEV_GOING_DOWN: { struct dsa_port *dp, *cpu_dp; struct dsa_switch_tree *dst; -@@ -2331,6 +2361,8 @@ static int dsa_slave_netdevice_event(str +@@ -2322,6 +2352,8 @@ static int dsa_slave_netdevice_event(str cpu_dp = dev->dsa_ptr; dst = cpu_dp->ds->dst; diff --git a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index 4b5c47420438bd..e3e338bd4ffc65 100644 --- a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2443,8 +2443,8 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -2381,8 +2381,8 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -2456,8 +2456,8 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -2394,8 +2394,8 @@ static irqreturn_t mtk_handle_irq_tx(int eth->tx_events++; if (likely(napi_schedule_prep(ð->tx_napi))) { @@ -30,12 +30,12 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -3623,6 +3623,8 @@ static int mtk_probe(struct platform_dev +@@ -3585,6 +3585,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); + eth->dummy_dev.threaded = 1; + strcpy(eth->dummy_dev.name, "mtk_eth"); netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, - MTK_NAPI_WEIGHT); + NAPI_POLL_WEIGHT); netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, diff --git a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch index 24b64c6ce6746b..d6e7f40f3b6741 100644 --- a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch +++ b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos sysfs_remove_link(&dev->dev.kobj, "phydev"); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -789,6 +789,12 @@ struct phy_driver { +@@ -823,6 +823,12 @@ struct phy_driver { /** @handle_interrupt: Override default interrupt handling */ irqreturn_t (*handle_interrupt)(struct phy_device *phydev); diff --git a/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch b/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch index deb25e652daec4..4c0d1001e0fc3c 100644 --- a/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch +++ b/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch @@ -14,7 +14,7 @@ Signed-off-by: Frank Wunderlich --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3675,6 +3675,7 @@ static const struct mtk_soc_data mt2701_ +@@ -3637,6 +3637,7 @@ static const struct mtk_soc_data mt2701_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch index 45c650b34a362f..de1079ffae5165 100644 --- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch @@ -103,7 +103,7 @@ Signed-off-by: David S. Miller ret = mtk_mdio_busy_wait(eth); if (ret < 0) -@@ -683,6 +726,7 @@ static int mtk_mdio_init(struct mtk_eth +@@ -621,6 +664,7 @@ static int mtk_mdio_init(struct mtk_eth eth->mii_bus->name = "mdio"; eth->mii_bus->read = mtk_mdio_read; eth->mii_bus->write = mtk_mdio_write; diff --git a/target/linux/mediatek/patches-5.15/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch b/target/linux/mediatek/patches-5.15/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch deleted file mode 100644 index a7878ecb1b4f47..00000000000000 --- a/target/linux/mediatek/patches-5.15/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -667,6 +667,7 @@ static void mtk_validate(struct phylink_ - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); -+ phylink_set(mask, 2500baseT_Full); - phylink_set(mask, 2500baseX_Full); - } - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { diff --git a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch index f6ac8360ee3506..8a39c81e01774b 100644 --- a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3290,6 +3290,7 @@ static const struct net_device_ops mtk_n +@@ -3228,6 +3228,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -3385,6 +3386,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -3347,6 +3348,9 @@ static int mtk_add_mac(struct mtk_eth *e else eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; diff --git a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index afdfc892d575ce..063b317fd5ce24 100644 --- a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c phydev->mii_ts->link_state(phydev->mii_ts, phydev); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -946,7 +946,8 @@ void phylink_destroy(struct phylink *pl) +@@ -1315,7 +1315,8 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); @@ -107,7 +107,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c bool tx_pause, rx_pause; --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -669,7 +669,7 @@ struct phy_device { +@@ -703,7 +703,7 @@ struct phy_device { u8 mdix; u8 mdix_ctrl; diff --git a/target/linux/ramips/patches-5.15/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-5.15/721-NET-no-auto-carrier-off-support.patch index 97086fa95069a0..365bdc688020a1 100644 --- a/target/linux/ramips/patches-5.15/721-NET-no-auto-carrier-off-support.patch +++ b/target/linux/ramips/patches-5.15/721-NET-no-auto-carrier-off-support.patch @@ -37,7 +37,7 @@ Signed-off-by: John Crispin break; --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -586,6 +586,7 @@ struct phy_device { +@@ -620,6 +620,7 @@ struct phy_device { unsigned downshifted_rate:1; unsigned is_on_sfp_module:1; unsigned mac_managed_pm:1; From e504fdae4e1d0e7ae112828ec9f71db6f9821c71 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 15 Aug 2022 18:50:10 +0200 Subject: [PATCH 02/91] kernel: add pending mtk_sgmii and phy improvements from @lynxis Add pending patches from Alexander 'lynxis' Couzens which are required for RealTek NBase-T PHYs or SFP+ cages to work when connected to the SGMII interface provided by recent MediaTek SoCs [1]. The patches for MT753x fix link speed limitation on CPU ports observed by many users which is due to reset being carried out wrongly [2]. [1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=* [2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=* Signed-off-by: Daniel Golle --- ...rtl8221-allow-to-configure-SERDES-mo.patch | 101 ++++++++++++++++++ ...531-only-do-PLL-once-after-the-reset.patch | 67 ++++++++++++ ...e-all-MACs-are-powered-down-before-r.patch | 28 +++++ ...-net-mtk_sgmii-implement-mtk_pcs_ops.patch | 44 ++++++++ ..._sgmii-fix-powering-up-the-SGMII-phy.patch | 39 +++++++ ...sure-the-SGMII-PHY-is-powered-down-o.patch | 65 +++++++++++ ...k_pcs_setup_mode_an-don-t-rely-on-re.patch | 31 ++++++ ...t-the-speed-according-to-the-phy-int.patch | 47 ++++++++ .../729-net-mtk_eth_soc-improve-comment.patch | 22 ++++ ...enable-PCS-polling-to-allow-SFP-work.patch | 23 ++++ 10 files changed, 467 insertions(+) create mode 100644 target/linux/generic/pending-5.15/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch create mode 100644 target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch create mode 100644 target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch create mode 100644 target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch create mode 100644 target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch create mode 100644 target/linux/generic/pending-5.15/726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch create mode 100644 target/linux/generic/pending-5.15/727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch create mode 100644 target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch create mode 100644 target/linux/generic/pending-5.15/729-net-mtk_eth_soc-improve-comment.patch create mode 100644 target/linux/generic/pending-5.15/730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch diff --git a/target/linux/generic/pending-5.15/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch b/target/linux/generic/pending-5.15/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch new file mode 100644 index 00000000000000..703a0b8b72b24b --- /dev/null +++ b/target/linux/generic/pending-5.15/721-net-phy-realtek-rtl8221-allow-to-configure-SERDES-mo.patch @@ -0,0 +1,101 @@ +From ace6abaa0f9203083fe4c0a6a74da2d96410b625 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Sat, 13 Aug 2022 12:49:33 +0200 +Subject: [PATCH 01/10] net: phy: realtek: rtl8221: allow to configure SERDES + mode + +The rtl8221 supports multiple SERDES modes: +- SGMII +- 2500base-x +- HiSGMII + +Further it supports rate adaption on SERDES links to allow +slow ethernet speeds (10/100/1000mbit) to work on 2500base-x/HiSGMII +links without reducing the SERDES speed. + +When operating without rate adapters the SERDES link will follow the +ethernet speed. + +Signed-off-by: Alexander Couzens +--- + drivers/net/phy/realtek.c | 48 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -53,6 +53,15 @@ + RTL8201F_ISR_LINK) + #define RTL8201F_IER 0x13 + ++#define RTL8221B_MMD_SERDES_CTRL MDIO_MMD_VEND1 ++#define RTL8221B_MMD_PHY_CTRL MDIO_MMD_VEND2 ++#define RTL8221B_SERDES_OPTION 0x697a ++#define RTL8221B_SERDES_OPTION_MODE_MASK GENMASK(5, 0) ++#define RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII 0 ++#define RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII 1 ++#define RTL8221B_SERDES_OPTION_MODE_2500BASEX 2 ++#define RTL8221B_SERDES_OPTION_MODE_HISGMII 3 ++ + #define RTL8366RB_POWER_SAVE 0x15 + #define RTL8366RB_POWER_SAVE_ON BIT(12) + +@@ -841,6 +850,43 @@ static irqreturn_t rtl9000a_handle_inter + return IRQ_HANDLED; + } + ++static int rtl8221b_config_init(struct phy_device *phydev) ++{ ++ u16 option_mode; ++ ++ switch (phydev->interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII; ++ break; ++ default: ++ return 0; ++ } ++ ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, ++ 0x75f3, 0); ++ ++ phy_modify_mmd_changed(phydev, RTL8221B_MMD_SERDES_CTRL, ++ RTL8221B_SERDES_OPTION, ++ RTL8221B_SERDES_OPTION_MODE_MASK, option_mode); ++ switch (option_mode) { ++ case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII: ++ case RTL8221B_SERDES_OPTION_MODE_2500BASEX: ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503); ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455); ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020); ++ break; ++ case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII: ++ case RTL8221B_SERDES_OPTION_MODE_HISGMII: ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503); ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433); ++ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020); ++ break; ++ } ++ ++ return 0; ++} ++ + static struct phy_driver realtek_drvs[] = { + { + PHY_ID_MATCH_EXACT(0x00008201), +@@ -981,6 +1027,7 @@ static struct phy_driver realtek_drvs[] + PHY_ID_MATCH_EXACT(0x001cc849), + .name = "RTL8221B-VB-CG 2.5Gbps PHY", + .get_features = rtl822x_get_features, ++ .config_init = rtl8221b_config_init, + .config_aneg = rtl822x_config_aneg, + .read_status = rtl822x_read_status, + .suspend = genphy_suspend, +@@ -992,6 +1039,7 @@ static struct phy_driver realtek_drvs[] + .name = "RTL8221B-VM-CG 2.5Gbps PHY", + .get_features = rtl822x_get_features, + .config_aneg = rtl822x_config_aneg, ++ .config_init = rtl8221b_config_init, + .read_status = rtl822x_read_status, + .suspend = genphy_suspend, + .resume = rtlgen_resume, diff --git a/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch b/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch new file mode 100644 index 00000000000000..6fd450d7f9a46e --- /dev/null +++ b/target/linux/generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch @@ -0,0 +1,67 @@ +From 9fec662b54fc956b776df15c704e996c61292850 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Sat, 13 Aug 2022 13:05:09 +0200 +Subject: [PATCH 02/10] net: mt7531: only do PLL once after the reset + +Move the PLL init of the switch out of the pad configuration of the port +6 (usally cpu port). + +Fix a unidirectional 100 mbit limitation on 1 gbit or 2.5 gbit links for +outbound traffic on port 5 or port 6. + +Signed-off-by: Alexander Couzens +--- + drivers/net/dsa/mt7530.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -506,14 +506,19 @@ static bool mt7531_dual_sgmii_supported( + static int + mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) + { +- struct mt7530_priv *priv = ds->priv; ++ return 0; ++} ++ ++static void ++mt7531_pll_setup(struct mt7530_priv *priv) ++{ + u32 top_sig; + u32 hwstrap; + u32 xtal; + u32 val; + + if (mt7531_dual_sgmii_supported(priv)) +- return 0; ++ return; + + val = mt7530_read(priv, MT7531_CREV); + top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); +@@ -592,8 +597,6 @@ mt7531_pad_setup(struct dsa_switch *ds, + val |= EN_COREPLL; + mt7530_write(priv, MT7531_PLLGP_EN, val); + usleep_range(25, 35); +- +- return 0; + } + + static void +@@ -2326,6 +2329,8 @@ mt7531_setup(struct dsa_switch *ds) + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | + SYS_CTRL_REG_RST); + ++ mt7531_pll_setup(priv); ++ + if (mt7531_dual_sgmii_supported(priv)) { + priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; + +@@ -2882,8 +2887,6 @@ mt7531_cpu_port_config(struct dsa_switch + case 6: + interface = PHY_INTERFACE_MODE_2500BASEX; + +- mt7531_pad_setup(ds, interface); +- + priv->p6_interface = interface; + break; + default: diff --git a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch new file mode 100644 index 00000000000000..cc12d72110a5eb --- /dev/null +++ b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch @@ -0,0 +1,28 @@ +From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Sat, 13 Aug 2022 13:08:22 +0200 +Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before + reset + +The datasheet [1] explicit describes it as requirement for a reset. + +[1] MT7531 Reference Manual for Development Board rev 1.0, page 735 + +Signed-off-by: Alexander Couzens +--- + drivers/net/dsa/mt7530.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2324,6 +2324,10 @@ mt7531_setup(struct dsa_switch *ds) + return -ENODEV; + } + ++ /* all MACs must be forced link-down before sw reset */ ++ for (i = 0; i < MT7530_NUM_PORTS; i++) ++ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); ++ + /* Reset the switch through internal reset */ + mt7530_write(priv, MT7530_SYS_CTRL, + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | diff --git a/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch b/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch new file mode 100644 index 00000000000000..896f0169d2b945 --- /dev/null +++ b/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch @@ -0,0 +1,44 @@ +From cbfed00575d15eafd85efd9619b7ecc0836a4aa7 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Sat, 13 Aug 2022 14:42:12 +0200 +Subject: [PATCH 04/10] net: mtk_sgmii: implement mtk_pcs_ops + +Implement mtk_pcs_ops for the SGMII pcs to read the current state +of the hardware. + +Signed-off-by: Alexander Couzens +[added DUPLEX_FULL] +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -122,10 +122,26 @@ static void mtk_pcs_link_up(struct phyli + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + } + ++static void mtk_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) ++{ ++ struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); ++ unsigned int val; ++ ++ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); ++ state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000; ++ ++ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); ++ state->an_complete = !!(val & SGMII_AN_COMPLETE); ++ state->link = !!(val & SGMII_LINK_STATYS); ++ state->duplex = DUPLEX_FULL; ++ state->pause = 0; ++} ++ + static const struct phylink_pcs_ops mtk_pcs_ops = { + .pcs_config = mtk_pcs_config, + .pcs_an_restart = mtk_pcs_restart_an, + .pcs_link_up = mtk_pcs_link_up, ++ .pcs_get_state = mtk_pcs_get_state, + }; + + int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) diff --git a/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch b/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch new file mode 100644 index 00000000000000..0fa357d48f7199 --- /dev/null +++ b/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch @@ -0,0 +1,39 @@ +From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Sat, 13 Aug 2022 14:48:51 +0200 +Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy + +There are certain race condition when the SGMII_PHYA_PWD register still +contains 0x9 which prevents the SGMII from working properly. + +The SGMII still shows link but no traffic can flow. + +Signed-off-by: Alexander Couzens +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct + val |= SGMII_AN_RESTART; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + +- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); +- val &= ~SGMII_PHYA_PWD; +- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; + +@@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + + /* Release PHYA power down state */ +- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); +- val &= ~SGMII_PHYA_PWD; +- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; + } diff --git a/target/linux/generic/pending-5.15/726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch b/target/linux/generic/pending-5.15/726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch new file mode 100644 index 00000000000000..329b41cf03a435 --- /dev/null +++ b/target/linux/generic/pending-5.15/726-net-mtk_sgmii-ensure-the-SGMII-PHY-is-powered-down-o.patch @@ -0,0 +1,65 @@ +From 9daea9b71d060d93d7394ac465b2e5ee0b7e7bca Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Mon, 15 Aug 2022 16:02:01 +0200 +Subject: [PATCH 06/10] net: mtk_sgmii: ensure the SGMII PHY is powered down on + configuration + +The code expect the PHY to be in power down (which is only true after reset). +Allow the changes of SGMII parameters more than once. +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -7,6 +7,7 @@ + * + */ + ++#include + #include + #include + #include +@@ -24,6 +25,9 @@ static int mtk_pcs_setup_mode_an(struct + { + unsigned int val; + ++ /* PHYA power down */ ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); ++ + /* Setup the link timer and QPHY power up inside SGMIISYS */ + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, + SGMII_LINK_TIMER_DEFAULT); +@@ -36,6 +40,10 @@ static int mtk_pcs_setup_mode_an(struct + val |= SGMII_AN_RESTART; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + ++ /* Release PHYA power down state ++ * unknown how much the QPHY needs but it is racy without a sleep ++ */ ++ usleep_range(50, 100); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; +@@ -50,6 +58,9 @@ static int mtk_pcs_setup_mode_force(stru + { + unsigned int val; + ++ /* PHYA power down */ ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); ++ + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); + val &= ~RG_PHY_SPEED_MASK; + if (interface == PHY_INTERFACE_MODE_2500BASEX) +@@ -67,7 +78,10 @@ static int mtk_pcs_setup_mode_force(stru + val |= SGMII_SPEED_1000; + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + +- /* Release PHYA power down state */ ++ /* Release PHYA power down state ++ * unknown how much the QPHY needs but it is racy without a sleep ++ */ ++ usleep_range(50, 100); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; diff --git a/target/linux/generic/pending-5.15/727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch b/target/linux/generic/pending-5.15/727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch new file mode 100644 index 00000000000000..5bc187cfc820d4 --- /dev/null +++ b/target/linux/generic/pending-5.15/727-net-mtk_sgmii-mtk_pcs_setup_mode_an-don-t-rely-on-re.patch @@ -0,0 +1,31 @@ +From e4dca7affb8c03438b63bdb5fddefd6ad2431cfd Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Mon, 15 Aug 2022 14:59:29 +0200 +Subject: [PATCH 07/10] net: mtk_sgmii: mtk_pcs_setup_mode_an: don't rely on + register defaults + +Ensure autonegotiation is enabled. + +Signed-off-by: Alexander Couzens +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -32,12 +32,13 @@ static int mtk_pcs_setup_mode_an(struct + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, + SGMII_LINK_TIMER_DEFAULT); + ++ /* disable remote fault & enable auto neg */ + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); +- val |= SGMII_REMOTE_FAULT_DIS; ++ val |= SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN; + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); +- val |= SGMII_AN_RESTART; ++ val |= SGMII_AN_RESTART | SGMII_AN_ENABLE; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + + /* Release PHYA power down state diff --git a/target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch b/target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch new file mode 100644 index 00000000000000..0b17f77eef4511 --- /dev/null +++ b/target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch @@ -0,0 +1,47 @@ +From 952b64575613d26163a5afa5ff8bfdb57840091b Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Mon, 15 Aug 2022 15:00:14 +0200 +Subject: [PATCH 08/10] net: mtk_sgmii: set the speed according to the phy + interface in AN + +The non auto-negotioting code path is setting the correct speed for the +interface. Ensure auto-negotiation code path is doing it as well. + +Signed-off-by: Alexander Couzens +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -21,13 +21,20 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st + } + + /* For SGMII interface mode */ +-static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs) ++static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface) + { + unsigned int val; + + /* PHYA power down */ + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD); + ++ /* Set SGMII phy speed */ ++ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); ++ val &= ~RG_PHY_SPEED_MASK; ++ if (interface == PHY_INTERFACE_MODE_2500BASEX) ++ val |= RG_PHY_SPEED_3_125G; ++ regmap_write(mpcs->regmap, mpcs->ana_rgc3, val); ++ + /* Setup the link timer and QPHY power up inside SGMIISYS */ + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, + SGMII_LINK_TIMER_DEFAULT); +@@ -100,7 +107,7 @@ static int mtk_pcs_config(struct phylink + if (interface != PHY_INTERFACE_MODE_SGMII) + err = mtk_pcs_setup_mode_force(mpcs, interface); + else if (phylink_autoneg_inband(mode)) +- err = mtk_pcs_setup_mode_an(mpcs); ++ err = mtk_pcs_setup_mode_an(mpcs, interface); + + return err; + } diff --git a/target/linux/generic/pending-5.15/729-net-mtk_eth_soc-improve-comment.patch b/target/linux/generic/pending-5.15/729-net-mtk_eth_soc-improve-comment.patch new file mode 100644 index 00000000000000..80144850ec2323 --- /dev/null +++ b/target/linux/generic/pending-5.15/729-net-mtk_eth_soc-improve-comment.patch @@ -0,0 +1,22 @@ +From 06773f19cffd6c9d34dcbc8320169afef5ab60ba Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Mon, 15 Aug 2022 13:58:07 +0200 +Subject: [PATCH 09/10] net: mtk_eth_soc: improve comment + +Signed-off-by: Alexander Couzens +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -80,7 +80,8 @@ static int mtk_pcs_setup_mode_force(stru + val &= ~SGMII_AN_ENABLE; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + +- /* Set the speed etc but leave the duplex unchanged */ ++ /* Set the speed etc but leave the duplex unchanged. ++ * The SGMII mode for 2.5gbit is the same as for 1gbit, expect the speed in ANA_RGC3 */ + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val); + val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK; + val |= SGMII_SPEED_1000; diff --git a/target/linux/generic/pending-5.15/730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch b/target/linux/generic/pending-5.15/730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch new file mode 100644 index 00000000000000..6c7fd6a6bfdb05 --- /dev/null +++ b/target/linux/generic/pending-5.15/730-mtk_sgmii-enable-PCS-polling-to-allow-SFP-work.patch @@ -0,0 +1,23 @@ +From 95dcd0f223d7cab6e25bc19088016e5eb4ca1804 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Tue, 16 Aug 2022 00:22:11 +0200 +Subject: [PATCH 10/10] mtk_sgmii: enable PCS polling to allow SFP work + +Currently there is no IRQ handling (even the SGMII supports it). +Enable polling to support SFP ports. + +Signed-off-by: Alexander Couzens +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -180,6 +180,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, + return PTR_ERR(ss->pcs[i].regmap); + + ss->pcs[i].pcs.ops = &mtk_pcs_ops; ++ ss->pcs[i].pcs.poll = 1; + } + + return 0; From c2bc1bd99aabe1298c93cebc0a434c91c754f3ca Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 13 Jul 2022 04:29:34 +0100 Subject: [PATCH 03/91] uboot-mediatek: add support for Bananapi BPi-R3 The Bananapi BPi-R3 board can boot from eMMC, SD card, SPI-NAND and SPI-NOR, depending on the position of switches controlling the BOOTSEL bootstrap pins as we as hard-wired chip-select lines. The position of the chip-select switch SW6 decides whether either SD card or eMMC can be accessed, SW5 selects either SPI-NAND or SPI-NOR. Generate U-Boot for all 4 boot options. The SD card version allows installation to SPI-NAND and SPI-NOR (eMMC cannot be accessed simultanously with the SD card), the SPI-NAND version allows installation to eMMC. Signed-off-by: Daniel Golle --- package/boot/uboot-mediatek/Makefile | 63 +- .../patches/430-add-bpi-r3.patch | 1368 +++++++++++++++++ 2 files changed, 1428 insertions(+), 3 deletions(-) create mode 100644 package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index c89fb197ae1d0f..7bfc8fd64bfa18 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -180,7 +180,60 @@ define U-Boot/mt7986_rfb BUILD_SUBTARGET:=filogic BUILD_DEVICES:=mediatek_mt7986-rfb UBOOT_CONFIG:=mt7986_rfb - UBOOT_IMAGE:=u-boot.bin + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-sdmmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-emmc + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-sdmmc + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-sd + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-sdmmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-snand + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-snand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-nor + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-nor + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-nor-ddr4 + FIP_COMPRESS:=1 endef UBOOT_TARGETS := \ @@ -199,6 +252,10 @@ UBOOT_TARGETS := \ mt7628_rfb \ ravpower_rp-wd009 \ mt7629_rfb \ + mt7986_bananapi_bpi-r3-emmc \ + mt7986_bananapi_bpi-r3-sdmmc \ + mt7986_bananapi_bpi-r3-snand \ + mt7986_bananapi_bpi-r3-nor \ mt7986_rfb ifdef CONFIG_TARGET_mediatek @@ -207,11 +264,11 @@ endif define Build/fip-image $(if $(FIP_COMPRESS),\ - xz -f -e -k -9 -C crc32 $(STAGING_DIR_IMAGE)/$(BUILD_SUBTARGET)-$(BL2_BOOTDEV)-$(BL2_DDRBLOB)ddr-bl31.bin ;\ + xz -f -e -k -9 -C crc32 $(STAGING_DIR_IMAGE)/$(if $(BL2_SOC),$(BL2_SOC),$(BUILD_SUBTARGET))-$(BL2_BOOTDEV)-$(if $(BL2_DDRTYPE),$(BL2_DDRTYPE)-)$(if $(BL2_DDRBLOB),$(BL2_DDRBLOB)ddr-)bl31.bin ;\ xz -f -e -k -9 -C crc32 $(PKG_BUILD_DIR)/u-boot.bin \ ) $(STAGING_DIR_HOST)/bin/fiptool create \ - --soc-fw $(STAGING_DIR_IMAGE)/$(BUILD_SUBTARGET)-$(BL2_BOOTDEV)-$(BL2_DDRBLOB)ddr-bl31.bin$(if $(FIP_COMPRESS),.xz) \ + --soc-fw $(STAGING_DIR_IMAGE)/$(if $(BL2_SOC),$(BL2_SOC),$(BUILD_SUBTARGET))-$(BL2_BOOTDEV)-$(if $(BL2_DDRTYPE),$(BL2_DDRTYPE)-)$(if $(BL2_DDRBLOB),$(BL2_DDRBLOB)ddr-)bl31.bin$(if $(FIP_COMPRESS),.xz) \ --nt-fw $(PKG_BUILD_DIR)/u-boot.bin$(if $(FIP_COMPRESS),.xz) \ $(PKG_BUILD_DIR)/u-boot.fip endef diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch new file mode 100644 index 00000000000000..48835e43af72fb --- /dev/null +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -0,0 +1,1368 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1211,6 +1211,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7981-snfi-nand-rfb.dtb \ + mt7981-emmc-rfb.dtb \ + mt7981-sd-rfb.dtb \ ++ mt7986a-bpi-r3-sd.dtb \ ++ mt7986a-bpi-r3-emmc.dtb \ + mt7986a-rfb.dtb \ + mt7986b-rfb.dtb \ + mt7986a-sd-rfb.dtb \ +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-emmc_defconfig +@@ -0,0 +1,192 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++# CONFIG_ENABLE_NAND_NMBM is not set +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-nor_defconfig +@@ -0,0 +1,193 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="u-boot-env" ++CONFIG_ENV_OFFSET=0x0 ++CONFIG_ENV_OFFSET_REDUND=0x20000 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_ENV_SIZE_REDUND=0x20000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++#CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SF=y ++#CONFIG_CMD_NAND=y ++#CONFIG_CMD_NAND_TRIMFFS=y ++# CONFIG_ENABLE_NAND_NMBM is not set +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-sd_defconfig +@@ -0,0 +1,192 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++# CONFIG_ENABLE_NAND_NMBM is not set +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-snand_defconfig +@@ -0,0 +1,193 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++#CONFIG_DM_SPI_FLASH=y ++#CONFIG_SPI_FLASH_MTD=y ++#CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_MTD=y ++#CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++# CONFIG_ENABLE_NAND_NMBM is not set +--- /dev/null ++++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7986a-bpi-r3-sd.dts" ++#include ++/ { ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; ++ +--- /dev/null ++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts +@@ -0,0 +1,269 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih ++ */ ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "BananaPi BPi-R3"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_green: green { ++ label = "green:status"; ++ gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led_status_blue: blue { ++ label = "blue:status"; ++ gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0"; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nor@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x40000>; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x40000>; ++ }; ++ ++ partition@80000 { ++ label = "reserved"; ++ reg = <0x80000 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "fip"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@180000 { ++ label = "recovery"; ++ reg = <0x180000 0xa80000>; ++ }; ++ ++ partition@c00000 { ++ label = "fit"; ++ reg = <0xc00000 0x1400000>; ++ }; ++ }; ++ }; ++ ++ spi_nand@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@80000 { ++ label = "factory"; ++ reg = <0x80000 0x300000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++ cap-sd-highspeed; ++ r_smpl = <1>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; ++ +--- /dev/null ++++ b/bananapi_bpi-r3_sdmmc_env +@@ -0,0 +1,75 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/mmcblk0p65 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [SD card] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Install bootloader, recovery and production to NOR.=if sf probe ; then run nor_init ; else echo "NOR not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_7=Install bootloader, recovery and production to NAND.=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_update_conf=if nand info ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-snand ; else if sf probe ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-nor ; else setenv bootconf config-mt7986a-bananapi-bpi-r3 ; fi ; fi ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run boot_update_conf ; run sdmmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run boot_update_conf ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_sdmmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400 ++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_nor_bl2=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x2800 && mmc read $loadaddr $offset 0x400 ++sdmmc_read_nor_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3000 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000 ++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000 ++nor_erase_env=mtd erase u-boot-env ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb ++nor_init=run nor_init_bl && run nor_init_openwrt ++nor_init_bl=run sdmmc_read_nor_bl2 && run mtd_write_bl2 && run sdmmc_read_nor_fip && run mtd_write_fip && run nor_erase_env ++nor_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run nor_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run nor_write_production ++ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ++ubi_init=run ubi_init_bl && run ubi_format && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install ++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production ++ubi_init_bl=run sdmmc_read_snand_bl2 && run mtd_write_bl2 && run sdmmc_read_snand_fip && run mtd_write_fip ++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_emmc_install=ubi check emmc_install && ubi remote emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/bananapi_bpi-r3_nor_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/mtdblock0p1 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3-emmc-nor ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-nor-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-nor-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [SPI-NOR] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_preloader ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run nor_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run nor_read_recovery ; bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader ++boot_update_conf=if mmc partconf 0 ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-nor ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-nor ; fi ++boot_nor=run boot_production ; run boot_recovery ++boot_write_fip=mtd erase fip && mtd write fip $loadaddr ++boot_write_preloader=mtd erase bl2 && mtd write bl2 $loadaddr ++reset_factory=mtd erase u-boot-env ++nor_read_production=mtd read fit $loadaddr 0x0 0x1000 && imsz $loadaddr image_size && mtd read fit $loadaddr 0x0 $image_size ++nor_read_recovery=mtd read recovery $loadaddr 0x0 0x1000 && imsz $loadaddr image_size && mtd read recovery $loadaddr 0x0 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/bananapi_bpi-r3_snand_env +@@ -0,0 +1,69 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/ubiblock0_2p1 ++bootconf=config-mt7986a-bananapi-bpi-r3-snand ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-snand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-snand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [SPI-NAND] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to NAND.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to NAND.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Install bootloader, recovery and production to eMMC.=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_update_conf ; run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++boot_update_conf=if mmc partconf 0 ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-snand ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-snand ; fi ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv ++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr ++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" +--- /dev/null ++++ b/bananapi_bpi-r3_emmc_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/mmcblk0p65 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3-emmc ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= ( ( ( OpenWrt ) ) ) [eMMC] ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_emmc=run boot_update_conf ; run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_update_conf=if nand info ; then setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-snand ; else setenv bootconf config-mt7986a-bananapi-bpi-r3-emmc-nor ; fi ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver" From 38f7e932a5bbbf0f6dbc64ac05aa59e27c7ceec6 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 16 Jul 2022 21:07:20 +0100 Subject: [PATCH 04/91] uboot-envtools: add support for Bananapi BPi-R3 Create new mediatek_filogic file and add entries for environment on MMC, UBI and NOR for the Bananapi BPi-R3. Signed-off-by: Daniel Golle --- .../uboot-envtools/files/mediatek_filogic | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 package/boot/uboot-envtools/files/mediatek_filogic diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic new file mode 100644 index 00000000000000..a82f140a6e58b3 --- /dev/null +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -0,0 +1,45 @@ +# +# Copyright (C) 2021 OpenWrt.org +# + +[ -e /etc/config/ubootenv ] && exit 0 + +touch /etc/config/ubootenv + +. /lib/uboot-envtools.sh +. /lib/functions.sh + +board=$(board_name) + +case "$board" in +bananapi,bpi-r3) + . /lib/upgrade/common.sh + export_bootdevice + export_partdevice rootdev 0 + case "$rootdev" in + mmc*) + local envdev=$(find_mmc_part "ubootenv" $rootdev) + ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1" + ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1" + ;; + mtd*) + local envdev=/dev/mtd$(find_mtd_index "u-boot-env") + ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1" + ubootenv_add_uci_config "$envdev" "0x20000" "0x20000" "0x20000" "1" + ;; + *) + . /lib/upgrade/nand.sh + local envubi=$(nand_find_ubi ubi) + local envdev=/dev/$(nand_find_volume $envubi ubootenv) + local envdev2=/dev/$(nand_find_volume $envubi ubootenv2) + ubootenv_add_uci_config "$envdev" "0x0" "0x1f000" "0x1f000" "1" + ubootenv_add_uci_config "$envdev2" "0x0" "0x1f000" "0x1f000" "1" + ;; + esac + ;; +esac + +config_load ubootenv +config_foreach ubootenv_add_app_config ubootenv + +exit 0 From a96382c1bb204698cd43e82193877c10e4b63027 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 13 Jul 2022 04:30:32 +0100 Subject: [PATCH 05/91] mediatek: add support for Bananapi BPi-R3 The Bananapi BPi-R3 is a development router board built around the MediaTek Filogic 830 (MT7986A) SoC. The board can boot either from microSD, SPI-NAND, SPI-NOR or eMMC. Only either SPI-NAND or SPI-NOR can be used at the same time, also only either microSD or eMMC can be used. The various storage options can be selected using small SMD switches on the board. Specs: * MediaTek MT7986A (Filogic 830) 4x ARM Cortex A53 * 4T4R 2.4G 802.11bgnax (MT7975N) * 4T4R 5G 802.11anac/ax (MT7975P) * 2 GB DDR4 RAM * 8 GB eMMC * 128 MB SPI-NAND flash * 32 MB SPI-NOR flash * on-board MT7531 GbE switch * 2x SFP+ (1 GbE / 2.5 GbE) * 5x GbE network port * miniPCIe slot (only USB 2.0 connected) * uSIM slot (connected to miniPCIe interface) * M.2 KEY-E PCIe interface (PCIe x2) * microSD card interface * 26 PIN GPIO Hardware details: https://wiki.banana-pi.org/Banana_Pi_BPI-R3 Working: * all 4 boot methods incl. installation via U-Boot, sysupgrade, ... * copper LAN and WAN ports * SFP1 (connected to gmac1, eth1 in Linux) * WiFi * LEDs * Buttons * PSTORE/ramoops based dual-boot Not Working (missing driver features): * SFP2 (connected to MT7531 switch) Untested: * M.2/NGFF slot (PCIe x2) * mPCIe slot (USB 2.0 + SIM) Signed-off-by: Daniel Golle --- .../uci-defaults/99_fwenv-store-ethaddr.sh | 8 +- .../dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts | 80 +++ .../mt7986a-bananapi-bpi-r3-emmc-snand.dts | 71 +++ .../dts/mt7986a-bananapi-bpi-r3-nor.dts | 58 ++ .../dts/mt7986a-bananapi-bpi-r3-snand.dts | 49 ++ .../mediatek/dts/mt7986a-bananapi-bpi-r3.dts | 540 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 4 + .../base-files/lib/upgrade/platform.sh | 41 +- target/linux/mediatek/image/filogic.mk | 71 +++ 9 files changed, 920 insertions(+), 2 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts create mode 100644 target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-snand.dts create mode 100644 target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-nor.dts create mode 100644 target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-snand.dts create mode 100644 target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts diff --git a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh index b078b8f8ce988c..5dec158a93f41c 100644 --- a/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh +++ b/target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh @@ -1,6 +1,6 @@ [ ! -e /etc/fw_env.config ] && exit 0 -. /lib/functions.sh +. /lib/functions/system.sh case "$(board_name)" in bananapi,bpi-r2|\ @@ -9,6 +9,12 @@ unielec,u7623-02) [ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] && fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)" ;; +bananapi,bpi-r3) + [ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] && + fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)" + [ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] && + fw_setenv eth1addr "$(macaddr_add $(cat /sys/class/net/eth0/address) 1)" + ;; esac exit 0 diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts new file mode 100644 index 00000000000000..1c82782b1f4d8d --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-nor.dts @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + /delete-property/ cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + compatible = "denx,fit"; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-snand.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-snand.dts new file mode 100644 index 00000000000000..2ca865d6e6f871 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-emmc-snand.dts @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + /delete-property/ cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-nor.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-nor.dts new file mode 100644 index 00000000000000..f597b869abc80d --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-nor.dts @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + compatible = "denx,fit"; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-snand.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-snand.dts new file mode 100644 index 00000000000000..e29ea2adb03df4 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3-snand.dts @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + nand-flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts new file mode 100644 index 00000000000000..2d9b0ac3b1b342 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-bananapi-bpi-r3.dts @@ -0,0 +1,540 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + led-boot = &led_status_green; + led-failsafe = &led_status_green; + led-running = &led_status_green; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory { + label = "reset"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_green: green { + label = "green:status"; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led_status_blue: blue { + label = "blue:status"; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; + }; + }; + + /* SFP1 cage (WAN) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* SFP2 cage (LAN) */ + i2c_sfp2: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port5: port@5 { + reg = <5>; + label = "sfp2"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&mmc0 { + //sdcard + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&wmac { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; +}; + +&pio { + /* don't mess around with GPIO 419, 450, 451, 498, 510 in sysfs system will freeze. */ + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; //"pcie_wake" is unused + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&wmac { + mediatek,eeprom-data = <0x86790900 0xc4326 0x60000000 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000000 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x800 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 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b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 9168e4d3991989..13afc2a3dcfe40 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -12,6 +12,10 @@ mediatek_setup_interfaces() mediatek,mt7986b-rfb) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; + bananapi,bpi-r3) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" + ucidef_set_interface_macaddr "wan" "$(macaddr_add $(cat /sys/class/net/eth0/address) 1)" + ;; *) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index bdb3309faa0d43..13b5b64fb69801 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -5,8 +5,26 @@ platform_do_upgrade() { local file_type=$(identify $1) case "$board" in + bananapi,bpi-r3) + export_bootdevice + export_partdevice rootdev 0 + case "$rootdev" in + mmc*) + CI_ROOTDEV="$rootdev" + CI_KERNPART="production" + emmc_do_upgrade "$1" + ;; + mtdblock*) + PART_NAME="fit" + default_do_upgrade "$1" + ;; + ubiblock*) + CI_KERNPART="fit" + nand_do_upgrade "$1" + ;; + esac + ;; *) - nand_do_upgrade "$1" ;; esac } @@ -20,6 +38,13 @@ platform_check_image() { [ "$#" -gt 1 ] && return 1 case "$board" in + bananapi,bpi-r3) + [ "$magic" != "d00dfeed" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; *) nand_do_platform_check "$board" "$1" return 0 @@ -28,3 +53,17 @@ platform_check_image() { return 0 } + +platform_copy_config() { + case "$(board_name)" in + bananapi,bpi-r3) + export_bootdevice + export_partdevice rootdev 0 + case "$rootdev" in + mmc*) + emmc_copy_config + ;; + esac + ;; + esac +} diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index dfa7f092cfbd39..dfc71bbb14155a 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -8,6 +8,77 @@ define Image/Prepare echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark endef +define Build/bl2 + cat $(STAGING_DIR_IMAGE)/mt7986-$1-bl2.img >> $@ +endef + +define Build/bl31-uboot + cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@ +endef + +define Build/mt7986-gpt + cp $@ $@.tmp 2>/dev/null || true + ptgen -g -o $@.tmp -a 1 -l 1024 \ + $(if $(findstring sdmmc,$1), \ + -H \ + -t 0x83 -N bl2 -r -p 4079k@17k \ + ) \ + -t 0x83 -N ubootenv -r -p 512k@4M \ + -t 0x83 -N factory -r -p 2M@4608k \ + -t 0xef -N fip -r -p 4M@6656k \ + -N recovery -r -p 32M@12M \ + $(if $(findstring sdmmc,$1), \ + -N install -r -p 20M@44M \ + -t 0x2e -N production -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@64M \ + ) \ + $(if $(findstring emmc,$1), \ + -t 0x2e -N production -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@64M \ + ) + cat $@.tmp >> $@ + rm $@.tmp +endef + +define Device/bananapi_bpi-r3 + DEVICE_VENDOR := Bananapi + DEVICE_MODEL := BPi-R3 + DEVICE_DTS := mt7986a-bananapi-bpi-r3 + DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3 + DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-emmc-nor mt7986a-bananapi-bpi-r3-emmc-snand mt7986a-bananapi-bpi-r3-snand + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-btmtkuart kmod-usb3 kmod-i2c-gpio kmod-sfp e2fsprogs f2fsck mkf2fs + IMAGES := sysupgrade.itb + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + ARTIFACTS := \ + emmc-preloader.bin emmc-bl31-uboot.fip \ + nor-preloader.bin nor-bl31-uboot.fip \ + sdcard.img.gz \ + snand-preloader.bin snand-bl31-uboot.fip + ARTIFACT/emmc-preloader.bin := bl2 emmc-ddr4 + ARTIFACT/emmc-bl31-uboot.fip := bl31-uboot bananapi_bpi-r3-emmc + ARTIFACT/nor-preloader.bin := bl2 nor-ddr4 + ARTIFACT/nor-bl31-uboot.fip := bl31-uboot bananapi_bpi-r3-nor + ARTIFACT/snand-preloader.bin := bl2 spim-nand-ddr4 + ARTIFACT/snand-bl31-uboot.fip := bl31-uboot bananapi_bpi-r3-snand + ARTIFACT/sdcard.img.gz := mt7986-gpt sdmmc |\ + pad-to 17k | bl2 sdmmc-ddr4 |\ + pad-to 6656k | bl31-uboot bananapi_bpi-r3-sdmmc |\ + pad-to 12M | append-image-stage initramfs-recovery.itb |\ + pad-to 44M | bl2 spim-nand-ddr4 |\ + pad-to 45M | bl31-uboot bananapi_bpi-r3-snand |\ + pad-to 49M | bl2 nor-ddr4 |\ + pad-to 50M | bl31-uboot bananapi_bpi-r3-nor |\ + pad-to 51M | bl2 emmc-ddr4 |\ + pad-to 52M | bl31-uboot bananapi_bpi-r3-emmc |\ + pad-to 56M | mt7986-gpt emmc |\ + pad-to 64M | append-image squashfs-sysupgrade.itb | gzip + KERNEL := kernel-bin | gzip + KERNEL_INITRAMFS := kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata + DTC_FLAGS += -@ --space 32768 +endef +TARGET_DEVICES += bananapi_bpi-r3 + define Device/mediatek_mt7986a-rfb DEVICE_VENDOR := MediaTek DEVICE_MODEL := MTK7986 rfba AP From 0ea329fec4c693443066faffe864edba17facc27 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 31 Aug 2022 13:31:02 +0100 Subject: [PATCH 06/91] uboot-mediatek: replace patches with updated versions Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle --- ...ONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch | 494 ++++++++++++++++++ ...-add-support-for-MediaTek-MT7986-SoC.patch | 36 +- ...-add-support-for-MediaTek-MT7981-SoC.patch | 36 +- ...mediatek-add-MT7986-reference-boards.patch | 6 +- ...mediatek-add-MT7981-reference-boards.patch | 6 +- ...-support-for-MediaTek-MT7891-MT7986-.patch | 6 +- ...-a-struct-to-cover-variations-of-all.patch | 6 +- ...p-using-bitfileds-for-DMA-descriptor.patch | 6 +- ...net-mediatek-add-support-for-PDMA-v2.patch | 6 +- ...d-support-for-MediaTek-MT7981-MT7986.patch | 6 +- ...upport-for-using-dynamic-baud-clock-.patch | 8 +- ...t7622-force-high-speed-mode-for-uart.patch | 6 +- ...-add-support-for-MediaTek-MT7986-SoC.patch | 6 +- ...-add-support-for-MediaTek-MT7981-SoC.patch | 6 +- ...pport-for-MediaTek-MT7981-MT7986-SoC.patch | 6 +- ...k-add-support-for-MediaTek-MT7986-So.patch | 6 +- ...port-for-MediaTek-spi-mem-controller.patch | 6 +- ...d-support-for-MediaTek-I2C-interface.patch | 6 +- ...-0018-arm-dts-mt7622-add-i2c-support.patch | 6 +- ...trl-mediatek-add-a-header-for-common.patch | 6 +- ...ek-add-pinctrl-driver-for-MT7981-SoC.patch | 6 +- ...ek-add-pinctrl-driver-for-MT7986-SoC.patch | 6 +- ...-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch | 24 +- ...-support-to-configure-clock-driver-p.patch | 30 +- ...iatek-add-infrasys-clock-mux-support.patch | 23 +- ...dd-CLK_XTAL-support-for-clock-driver.patch | 10 +- ...-clock-driver-support-for-MediaTek-M.patch | 7 +- ...-clock-driver-support-for-MediaTek-M.patch | 7 +- ...ic-cpu-driver-for-MediaTek-ARM-chips.patch | 133 +++++ ...plit-gfh-header-verification-into-a.patch} | 6 +- ...plit-the-code-of-generating-NAND-he.patch} | 6 +- ...dd-support-for-nand-headers-used-by.patch} | 6 +- ...e-maintainer-for-MediaTek-ARM-platf.patch} | 13 +- ...dd-support-for-booting-from-SPI-NAND.patch | 2 +- ...7622-generic-reset-button-ignore-env.patch | 2 +- .../patches/430-add-bpi-r3.patch | 4 + 36 files changed, 791 insertions(+), 164 deletions(-) create mode 100644 package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch create mode 100644 package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch rename package/boot/uboot-mediatek/patches/{002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch => 002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch} (93%) rename package/boot/uboot-mediatek/patches/{002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch => 002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch} (99%) rename package/boot/uboot-mediatek/patches/{002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch => 002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch} (99%) rename package/boot/uboot-mediatek/patches/{002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch => 002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch} (74%) diff --git a/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch b/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch new file mode 100644 index 00000000000000..a94ea18dd5e084 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch @@ -0,0 +1,494 @@ +From b62450cf229c50ad2ce819dd02a09726909cc89a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 27 May 2022 22:15:24 +0200 +Subject: [PATCH] serial: Replace CONFIG_DEBUG_UART_BASE by + CONFIG_VAL(DEBUG_UART_BASE) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +CONFIG_VAL(DEBUG_UART_BASE) expands to CONFIG_DEBUG_UART_BASE or +CONFIG_SPL_DEBUG_UART_BASE or CONFIG_TPL_DEBUG_UART_BASE and allows boards +to set different values for SPL, TPL and U-Boot Proper. + +For ns16550 driver this support is there since commit d293759d55cc +("serial: ns16550: Add support for SPL_DEBUG_UART_BASE"). + +Signed-off-by: Pali Rohár +--- + arch/arm/mach-uniphier/debug-uart/debug-uart.c | 4 ++-- + arch/x86/cpu/apollolake/cpu_common.c | 2 +- + board/eets/pdu001/board.c | 2 +- + drivers/serial/altera_jtag_uart.c | 2 +- + drivers/serial/altera_uart.c | 4 ++-- + drivers/serial/atmel_usart.c | 4 ++-- + drivers/serial/serial_ar933x.c | 4 ++-- + drivers/serial/serial_arc.c | 4 ++-- + drivers/serial/serial_bcm6345.c | 4 ++-- + drivers/serial/serial_linflexuart.c | 4 ++-- + drivers/serial/serial_meson.c | 2 +- + drivers/serial/serial_msm_geni.c | 6 +++--- + drivers/serial/serial_mt7620.c | 4 ++-- + drivers/serial/serial_mtk.c | 4 ++-- + drivers/serial/serial_mvebu_a3700.c | 4 ++-- + drivers/serial/serial_mxc.c | 4 ++-- + drivers/serial/serial_omap.c | 4 ++-- + drivers/serial/serial_pic32.c | 4 ++-- + drivers/serial/serial_pl01x.c | 4 ++-- + drivers/serial/serial_s5p.c | 4 ++-- + drivers/serial/serial_sifive.c | 4 ++-- + drivers/serial/serial_stm32.c | 4 ++-- + drivers/serial/serial_xuartlite.c | 4 ++-- + drivers/serial/serial_zynq.c | 4 ++-- + 24 files changed, 45 insertions(+), 45 deletions(-) + +--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c ++++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c +@@ -18,7 +18,7 @@ + + static void _debug_uart_putc(int c) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) + ; +@@ -57,7 +57,7 @@ void sg_set_iectrl(unsigned int pin) + void _debug_uart_init(void) + { + #ifdef CONFIG_SPL_BUILD +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + unsigned int divisor; + + switch (uniphier_get_soc_id()) { +--- a/arch/x86/cpu/apollolake/cpu_common.c ++++ b/arch/x86/cpu/apollolake/cpu_common.c +@@ -72,7 +72,7 @@ static void pch_uart_init(void) + } + + #ifdef CONFIG_DEBUG_UART +- apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE); ++ apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE)); + #endif + } + +--- a/board/eets/pdu001/board.c ++++ b/board/eets/pdu001/board.c +@@ -273,7 +273,7 @@ void board_debug_uart_init(void) + setup_early_clocks(); + + /* done by pin controller driver if not debugging */ +- enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); ++ enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE)); + } + #endif + +--- a/drivers/serial/altera_jtag_uart.c ++++ b/drivers/serial/altera_jtag_uart.c +@@ -134,7 +134,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (1) { + u32 st = readl(®s->control); +--- a/drivers/serial/altera_uart.c ++++ b/drivers/serial/altera_uart.c +@@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = { + + static inline void _debug_uart_init(void) + { +- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 div; + + div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1; +@@ -132,7 +132,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (1) { + u32 st = readl(®s->status); +--- a/drivers/serial/atmel_usart.c ++++ b/drivers/serial/atmel_usart.c +@@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = { + #ifdef CONFIG_DEBUG_UART_ATMEL + static inline void _debug_uart_init(void) + { +- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; ++ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); + + _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } + + static inline void _debug_uart_putc(int ch) + { +- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; ++ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(&usart->csr) & USART3_BIT(TXRDY))) + ; +--- a/drivers/serial/serial_ar933x.c ++++ b/drivers/serial/serial_ar933x.c +@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 val, scale, step; + + /* +@@ -227,7 +227,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 data; + + do { +--- a/drivers/serial/serial_arc.c ++++ b/drivers/serial/serial_arc.c +@@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = { + + static inline void _debug_uart_init(void) + { +- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; ++ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); + int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1; + + writeb(arc_console_baud & 0xff, ®s->baudl); +@@ -146,7 +146,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; ++ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readb(®s->status) & UART_TXEMPTY)) + ; +--- a/drivers/serial/serial_bcm6345.c ++++ b/drivers/serial/serial_bcm6345.c +@@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = { + #ifdef CONFIG_DEBUG_UART_BCM6345 + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } +@@ -285,7 +285,7 @@ static inline void wait_xfered(void __io + + static inline void _debug_uart_putc(int ch) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + wait_xfered(base); + writel(ch, base + UART_FIFO_REG); +--- a/drivers/serial/serial_linflexuart.c ++++ b/drivers/serial/serial_linflexuart.c +@@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = { + + static inline void _debug_uart_init(void) + { +- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; ++ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); + + linflex_serial_init_internal(base); + } + + static inline void _debug_uart_putc(int ch) + { +- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; ++ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); + + /* XXX: Is this OK? Should this use the non-DM version? */ + _linflex_serial_putc(base, ch); +--- a/drivers/serial/serial_meson.c ++++ b/drivers/serial/serial_meson.c +@@ -182,7 +182,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE; ++ struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + while (readl(®s->status) & AML_UART_TX_FULL) + ; +--- a/drivers/serial/serial_msm_geni.c ++++ b/drivers/serial/serial_msm_geni.c +@@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = { + #ifdef CONFIG_DEBUG_UART_MSM_GENI + + static struct msm_serial_data init_serial_data = { +- .base = CONFIG_DEBUG_UART_BASE ++ .base = CONFIG_VAL(DEBUG_UART_BASE) + }; + + /* Serial dumb device, to reuse driver code */ +@@ -587,7 +587,7 @@ static struct udevice init_dev = { + + static inline void _debug_uart_init(void) + { +- phys_addr_t base = CONFIG_DEBUG_UART_BASE; ++ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + + geni_serial_init(&init_dev); + geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); +@@ -596,7 +596,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- phys_addr_t base = CONFIG_DEBUG_UART_BASE; ++ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + + writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); + qcom_geni_serial_setup_tx(base, 1); +--- a/drivers/serial/serial_mt7620.c ++++ b/drivers/serial/serial_mt7620.c +@@ -220,7 +220,7 @@ static inline void _debug_uart_init(void + { + struct mt7620_serial_plat plat; + +- plat.regs = (void *)CONFIG_DEBUG_UART_BASE; ++ plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + plat.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &plat.regs->ier); +@@ -233,7 +233,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct mt7620_serial_regs __iomem *regs = +- (void *)CONFIG_DEBUG_UART_BASE; ++ (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_mtk.c ++++ b/drivers/serial/serial_mtk.c +@@ -426,7 +426,7 @@ static inline void _debug_uart_init(void + { + struct mtk_serial_priv priv; + +- priv.regs = (void *) CONFIG_DEBUG_UART_BASE; ++ priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); + priv.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &priv.regs->ier); +@@ -439,7 +439,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct mtk_serial_regs __iomem *regs = +- (void *) CONFIG_DEBUG_UART_BASE; ++ (void *) CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_mvebu_a3700.c ++++ b/drivers/serial/serial_mvebu_a3700.c +@@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + u32 parent_rate, divider; + + /* reset FIFOs */ +@@ -349,7 +349,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) + ; +--- a/drivers/serial/serial_mxc.c ++++ b/drivers/serial/serial_mxc.c +@@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = { + + static inline void _debug_uart_init(void) + { +- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; ++ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + _mxc_serial_init(base, false); + _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, +@@ -381,7 +381,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; ++ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(&base->ts) & UTS_TXEMPTY)) + WATCHDOG_RESET(); +--- a/drivers/serial/serial_omap.c ++++ b/drivers/serial/serial_omap.c +@@ -66,7 +66,7 @@ static inline int serial_in_shift(void * + + static inline void _debug_uart_init(void) + { +- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; ++ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); + int baud_divisor; + + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, +@@ -85,7 +85,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; ++ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_pic32.c ++++ b/drivers/serial/serial_pic32.c +@@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } + + static inline void _debug_uart_putc(int ch) + { +- writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); ++ writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR); + } + + DEBUG_UART_FUNCS +--- a/drivers/serial/serial_pl01x.c ++++ b/drivers/serial/serial_pl01x.c +@@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = { + static void _debug_uart_init(void) + { + #ifndef CONFIG_DEBUG_UART_SKIP_INIT +- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; ++ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); + enum pl01x_type type; + + if (IS_ENABLED(CONFIG_DEBUG_UART_PL011)) +@@ -419,7 +419,7 @@ static void _debug_uart_init(void) + + static inline void _debug_uart_putc(int ch) + { +- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; ++ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); + + while (pl01x_putc(regs, ch) == -EAGAIN) + ; +--- a/drivers/serial/serial_s5p.c ++++ b/drivers/serial/serial_s5p.c +@@ -276,7 +276,7 @@ static inline void _debug_uart_init(void + if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT)) + return; + +- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; ++ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + s5p_serial_init(uart); + #if CONFIG_IS_ENABLED(ARCH_APPLE) +@@ -288,7 +288,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; ++ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + #if CONFIG_IS_ENABLED(ARCH_APPLE) + while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL); +--- a/drivers/serial/serial_sifive.c ++++ b/drivers/serial/serial_sifive.c +@@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = { + static inline void _debug_uart_init(void) + { + struct uart_sifive *regs = +- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; ++ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); +@@ -222,7 +222,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct uart_sifive *regs = +- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; ++ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +--- a/drivers/serial/serial_stm32.c ++++ b/drivers/serial/serial_stm32.c +@@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_d + + static inline void _debug_uart_init(void) + { +- fdt_addr_t base = CONFIG_DEBUG_UART_BASE; ++ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + struct stm32_uart_info *uart_info = _debug_uart_info(); + + _stm32_serial_init(base, uart_info); +@@ -281,7 +281,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- fdt_addr_t base = CONFIG_DEBUG_UART_BASE; ++ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + struct stm32_uart_info *uart_info = _debug_uart_info(); + + while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN) +--- a/drivers/serial/serial_xuartlite.c ++++ b/drivers/serial/serial_xuartlite.c +@@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = { + + static inline void _debug_uart_init(void) + { +- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; ++ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); + int ret; + + uart_out32(®s->control, 0); +@@ -159,7 +159,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; ++ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); + + while (uart_in32(®s->status) & SR_TX_FIFO_FULL) + ; +--- a/drivers/serial/serial_zynq.c ++++ b/drivers/serial/serial_zynq.c +@@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = { + #ifdef CONFIG_DEBUG_UART_ZYNQ + static inline void _debug_uart_init(void) + { +- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; ++ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); + + _uart_zynq_serial_init(regs); + _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, +@@ -304,7 +304,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; ++ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); + + while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); diff --git a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch index 663f06c22c587b..07d7e4a6ae84f0 100644 --- a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From a299de45833df13d4ec28092201ea5fec0ba24fe Mon Sep 17 00:00:00 2001 +From 13d81db4723241e33316d7d134e4d279116e3158 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:17:58 +0800 -Subject: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:00:17 +0800 +Subject: [PATCH 01/32] arm: mediatek: add support for MediaTek MT7986 SoC This patch adds basic support for MediaTek MT7986 SoC. This include the file that will initialize the SoC after boot and its @@ -10,11 +10,11 @@ device tree. Signed-off-by: Weijie Gao --- arch/arm/dts/mt7986-u-boot.dtsi | 33 ++ - arch/arm/dts/mt7986.dtsi | 341 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 11 + + arch/arm/dts/mt7986.dtsi | 346 ++++++++++++++++++ + arch/arm/mach-mediatek/Kconfig | 12 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7986/Makefile | 4 + - arch/arm/mach-mediatek/mt7986/init.c | 51 +++ + arch/arm/mach-mediatek/mt7986/init.c | 45 +++ arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 ++ 7 files changed, 473 insertions(+) create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi @@ -61,7 +61,7 @@ Signed-off-by: Weijie Gao +}; --- /dev/null +++ b/arch/arm/dts/mt7986.dtsi -@@ -0,0 +1,341 @@ +@@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. @@ -118,6 +118,11 @@ Signed-off-by: Weijie Gao + u-boot,dm-pre-reloc; + }; + ++ hwver: hwver { ++ compatible = "mediatek,hwver"; ++ reg = <0x8000000 0x1000>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; @@ -405,13 +410,14 @@ Signed-off-by: Weijie Gao +}; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,14 @@ config TARGET_MT7629 +@@ -40,6 +40,15 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7986 + bool "MediaTek MT7986 SoC" + select ARM64 ++ select CPU + help + The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, @@ -420,7 +426,7 @@ Signed-off-by: Weijie Gao config TARGET_MT8183 bool "MediaTek MT8183 SoC" select ARM64 -@@ -84,6 +92,7 @@ config SYS_BOARD +@@ -84,6 +93,7 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -428,7 +434,7 @@ Signed-off-by: Weijie Gao default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 -@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME +@@ -99,6 +109,7 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -436,7 +442,7 @@ Signed-off-by: Weijie Gao default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 -@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO +@@ -113,6 +124,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 @@ -463,7 +469,7 @@ Signed-off-by: Weijie Gao +obj-y += lowlevel_init.o --- /dev/null +++ b/arch/arm/mach-mediatek/mt7986/init.c -@@ -0,0 +1,51 @@ +@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. @@ -477,12 +483,6 @@ Signed-off-by: Weijie Gao + +DECLARE_GLOBAL_DATA_PTR; + -+int print_cpuinfo(void) -+{ -+ printf("CPU: MediaTek MT7986\n"); -+ return 0; -+} -+ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); diff --git a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch index 93596af53d2f53..425f0de1b4975c 100644 --- a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 38faebb811868f9e6734dea7894d0fa5a61f3a22 Mon Sep 17 00:00:00 2001 +From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:58:11 +0800 -Subject: [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC +Date: Wed, 31 Aug 2022 19:00:20 +0800 +Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its @@ -9,11 +9,11 @@ device tree. Signed-off-by: Weijie Gao --- - arch/arm/dts/mt7981.dtsi | 288 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 12 +- + arch/arm/dts/mt7981.dtsi | 293 ++++++++++++++++++ + arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7981/Makefile | 4 + - arch/arm/mach-mediatek/mt7981/init.c | 51 ++++ + arch/arm/mach-mediatek/mt7981/init.c | 45 +++ arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++ 6 files changed, 387 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt7981.dtsi @@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao --- /dev/null +++ b/arch/arm/dts/mt7981.dtsi -@@ -0,0 +1,288 @@ +@@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. @@ -63,6 +63,11 @@ Signed-off-by: Weijie Gao + u-boot,dm-pre-reloc; + }; + ++ hwver: hwver { ++ compatible = "mediatek,hwver"; ++ reg = <0x8000000 0x1000>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; @@ -314,13 +319,14 @@ Signed-off-by: Weijie Gao +}; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,14 @@ config TARGET_MT7629 +@@ -40,6 +40,15 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7981 + bool "MediaTek MT7981 SoC" + select ARM64 ++ select CPU + help + The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, @@ -329,7 +335,7 @@ Signed-off-by: Weijie Gao config TARGET_MT7986 bool "MediaTek MT7986 SoC" select ARM64 -@@ -92,6 +100,7 @@ config SYS_BOARD +@@ -93,6 +102,7 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -337,7 +343,7 @@ Signed-off-by: Weijie Gao default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 -@@ -108,6 +117,7 @@ config SYS_CONFIG_NAME +@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -345,7 +351,7 @@ Signed-off-by: Weijie Gao default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 -@@ -123,7 +133,7 @@ config MTK_BROM_HEADER_INFO +@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 @@ -373,7 +379,7 @@ Signed-off-by: Weijie Gao +obj-y += lowlevel_init.o --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/init.c -@@ -0,0 +1,51 @@ +@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. @@ -387,12 +393,6 @@ Signed-off-by: Weijie Gao + +DECLARE_GLOBAL_DATA_PTR; + -+int print_cpuinfo(void) -+{ -+ printf("CPU: MediaTek MT7981\n"); -+ return 0; -+} -+ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); diff --git a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch index 8cbd57459d496b..2c1d50481b4e6b 100644 --- a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch +++ b/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch @@ -1,7 +1,7 @@ -From ab3f81920b4e47bd2894388540363700d5b1e59c Mon Sep 17 00:00:00 2001 +From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:26:31 +0800 -Subject: [PATCH 03/31] board: mediatek: add MT7986 reference boards +Date: Wed, 31 Aug 2022 19:00:22 +0800 +Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards Add general board files based on MT7986 SoCs. diff --git a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch index 6e08843bdcbea3..401aa11cdac167 100644 --- a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch +++ b/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch @@ -1,7 +1,7 @@ -From 89a31bfa05c384a2b4e56ddb9814633325b7feab Mon Sep 17 00:00:00 2001 +From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 16:02:37 +0800 -Subject: [PATCH 04/31] board: mediatek: add MT7981 reference boards +Date: Wed, 31 Aug 2022 19:00:25 +0800 +Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards This patch adds general board files based on MT7981 SoCs. diff --git a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch b/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch index 281c289c6a40bb..aa9adf40ffe4e6 100644 --- a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch +++ b/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch @@ -1,7 +1,7 @@ -From 3831266fedf14ef415791a93dd03a9e637eb8b5e Mon Sep 17 00:00:00 2001 +From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 26 Jul 2022 09:24:13 +0800 -Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 +Date: Wed, 31 Aug 2022 19:04:12 +0800 +Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs diff --git a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch b/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch index 2a1f5892d8a856..08cad1bb530fe1 100644 --- a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch +++ b/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch @@ -1,7 +1,7 @@ -From 5c5af768c4cceaa9d7497c3e5bfbc9d1ea8b279c Mon Sep 17 00:00:00 2001 +From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 26 Jul 2022 10:44:57 +0800 -Subject: [PATCH 06/31] net: mediatek: use a struct to cover variations of all +Date: Wed, 31 Aug 2022 19:04:19 +0800 +Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all SoCs Using a single soc id to control different initialization and TX/RX flow diff --git a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch b/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch index 3cf45b7f3e1d41..41f5ce63354275 100644 --- a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch +++ b/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch @@ -1,7 +1,7 @@ -From b978c067075fddbac341bf551ebef29e78767b75 Mon Sep 17 00:00:00 2001 +From 5f6f3600a334398e27802de33a6a8726aacbe88c Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 09:32:29 +0800 -Subject: [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors +Date: Wed, 31 Aug 2022 19:04:23 +0800 +Subject: [PATCH 07/32] net: mediatek: stop using bitfileds for DMA descriptors This patch is a preparation for adding a new version of PDMA of which the DMA descriptor fields has changed. Using bitfields will result in a complex diff --git a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch b/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch index 0fc0f4cafb6ecc..043e9a91d48128 100644 --- a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch +++ b/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch @@ -1,7 +1,7 @@ -From 2f53795aac940d960bc5f3b08a730c4d480fc5f6 Mon Sep 17 00:00:00 2001 +From 72241607b955639a51b79297776991de7dd59915 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 09:56:30 +0800 -Subject: [PATCH 08/31] net: mediatek: add support for PDMA v2 +Date: Wed, 31 Aug 2022 19:04:27 +0800 +Subject: [PATCH 08/32] net: mediatek: add support for PDMA v2 This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the DMA descriptor to 8-words, and some of its fields have changed comparing diff --git a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch b/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch index 7afd49d4574b9b..e2a16e2d6d5e5e 100644 --- a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch +++ b/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch @@ -1,7 +1,7 @@ -From 5e06e9a78bbc81f64fdb4c8502a8e7175d8b6216 Mon Sep 17 00:00:00 2001 +From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 10:03:17 +0800 -Subject: [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986 +Date: Wed, 31 Aug 2022 19:04:29 +0800 +Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986 This patch adds support for MediaTek MT7981 and MT7986. Both chips uses PDMA v2. diff --git a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch b/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch index ff7f66f0675a6a..d2f28f2bc9f7a0 100644 --- a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch +++ b/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch @@ -1,7 +1,7 @@ -From 55ed87efb110d13fce6d1a7ee6cb04fac1a2c08a Mon Sep 17 00:00:00 2001 +From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 10:28:05 +0800 -Subject: [PATCH 10/31] serial: mtk: add support for using dynamic baud clock +Date: Wed, 31 Aug 2022 19:04:32 +0800 +Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock souce The baud clock on some platform may change due to assigned-clock-parent @@ -187,7 +187,7 @@ Signed-off-by: Weijie Gao @@ -427,13 +441,13 @@ static inline void _debug_uart_init(void struct mtk_serial_priv priv; - priv.regs = (void *) CONFIG_DEBUG_UART_BASE; + priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); - priv.clock = CONFIG_DEBUG_UART_CLOCK; + priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; diff --git a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch index 7ed6083c8956e6..0777848f01b172 100644 --- a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch +++ b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch @@ -1,7 +1,7 @@ -From 893368e64049fd770e55fffcc8758d2619dc337d Mon Sep 17 00:00:00 2001 +From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Mon, 25 Jul 2022 16:33:13 +0800 -Subject: [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart +Date: Wed, 31 Aug 2022 19:04:34 +0800 +Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart The input clock for uart is too slow (25MHz) which introduces frequent data error on both receiving and transmitting even if the baudrate is 115200. diff --git a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch index a19b69a53cbfd4..da5f53f49c23a8 100644 --- a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From 63acbf4ffe328809ca479e5c7d344882810d412c Mon Sep 17 00:00:00 2001 +From d7dae84aad997f4f9b5d039f7ab180bd1f54fa37 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:00:15 +0800 -Subject: [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:35 +0800 +Subject: [PATCH 12/32] pwm: mtk: add support for MediaTek MT7986 SoC This patch adds PWM support for MediaTek MT7986 SoC. diff --git a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch index 2da5b960a3b01c..cd8ecd59179813 100644 --- a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001 +From 230003c14f7beedf4042bf2258b04e2cd5aac270 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:01:34 +0800 -Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC +Date: Wed, 31 Aug 2022 19:04:38 +0800 +Subject: [PATCH 13/32] pwm: mtk: add support for MediaTek MT7981 SoC This patch adds PWM support for MediaTek MT7981 SoC. MT7981 uses a different register offset so we have to add a version field diff --git a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch index 78894019315e52..d02841951da38a 100644 --- a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From 7860bc58c43dfa939d2664be518c28aea591aeef Mon Sep 17 00:00:00 2001 +From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:38:33 +0800 -Subject: [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs +Date: Wed, 31 Aug 2022 19:04:40 +0800 +Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs This patch add general-purpose timer support for MediaTek MT7981/MT7986. These two SoCs uses a newer version of timer with its register definition diff --git a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch b/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch index 09ffc5c7d9a117..3215d17050cdca 100644 --- a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch +++ b/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch @@ -1,7 +1,7 @@ -From ec7e5d3e4d6e9239f3d7ac861f07ca4a52bec9fa Mon Sep 17 00:00:00 2001 +From 18f761770d7aa53abf187fa64bbd92f0682d154c Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:47:50 +0800 -Subject: [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:42 +0800 +Subject: [PATCH 15/32] watchdog: mediatek: add support for MediaTek MT7986 SoC Add watchdog support for MediaTek MT7986 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch b/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch index 04c2df3b48afaf..0e0d72d5eba0de 100644 --- a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch +++ b/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch @@ -1,7 +1,7 @@ -From f85493e3c2d1e4fd411061540b4f4943c09114df Mon Sep 17 00:00:00 2001 +From e6b225ff8990635dc2d6d8dbd72e78dec1f36c62 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 16:58:38 +0800 -Subject: [PATCH 16/31] spi: add support for MediaTek spi-mem controller +Date: Wed, 31 Aug 2022 19:04:45 +0800 +Subject: [PATCH 16/32] spi: add support for MediaTek spi-mem controller This patch adds support for spi-mem controller found on newer MediaTek SoCs This controller supports Single/Dual/Quad SPI mode. diff --git a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch b/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch index c2bc33cdaaf024..a9abefa9403709 100644 --- a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch +++ b/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch @@ -1,7 +1,7 @@ -From de6f2293ab087f405dbcf7b8df45d1f9b03fc091 Mon Sep 17 00:00:00 2001 +From 987dc8d079cd399e753e10fce12d526b42f90ed0 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 17:16:38 +0800 -Subject: [PATCH 17/31] i2c: add support for MediaTek I2C interface +Date: Wed, 31 Aug 2022 19:04:47 +0800 +Subject: [PATCH 17/32] i2c: add support for MediaTek I2C interface This patch adds support for MediaTek I2C interface diff --git a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch b/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch index 378078882e5a2b..c87f17f6ef1235 100644 --- a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch +++ b/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch @@ -1,7 +1,7 @@ -From 9ae337317d5634569bda83dfc5e0658fce34b1e2 Mon Sep 17 00:00:00 2001 +From ceb4b900586299b12e2c8edffecef1d09b57eb30 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Mon, 25 Jul 2022 16:30:30 +0800 -Subject: [PATCH 18/31] arm: dts: mt7622: add i2c support +Date: Wed, 31 Aug 2022 19:04:49 +0800 +Subject: [PATCH 18/32] arm: dts: mt7622: add i2c support Add both hardware and software i2c support for mt7622. diff --git a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch b/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch index 385ec1395bc36e..b4b38f26a4cad5 100644 --- a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch +++ b/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch @@ -1,7 +1,7 @@ -From 920ba7b9ba1787fd03dad7a5bdc894073936c197 Mon Sep 17 00:00:00 2001 +From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 09:37:26 +0800 -Subject: [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common +Date: Wed, 31 Aug 2022 19:04:51 +0800 +Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters This patch adds a pinctrl header for common pinconf parameters such as diff --git a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch index 809b3cbc9b37b6..f4bc27f93dfd10 100644 --- a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 49e7b1e01cf80437c7e22f8b6579d4a81e7f8a3a Mon Sep 17 00:00:00 2001 +From 95df7f4bfacf810be4f94112ab2a4215f6de288d Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 09:57:58 +0800 -Subject: [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC +Date: Wed, 31 Aug 2022 19:04:55 +0800 +Subject: [PATCH 20/32] pinctrl: mediatek: add pinctrl driver for MT7981 SoC This patch adds pinctrl and gpio support for MT7981 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch index d0675ed4f88860..56bb68c8b6b23a 100644 --- a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From a018800db986d63cf95b0779ebb33b5e246072a7 Mon Sep 17 00:00:00 2001 +From 201880cacf1498dd4c6749780163157148d0445d Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 10:01:00 +0800 -Subject: [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:57 +0800 +Subject: [PATCH 21/32] pinctrl: mediatek: add pinctrl driver for MT7986 SoC This patch adds pinctrl and gpio support for MT7986 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch index c26fc8090ebfda..b9f0954401ed01 100644 --- a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch +++ b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch @@ -1,7 +1,7 @@ -From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001 +From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 10:43:39 +0800 -Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow +Date: Wed, 31 Aug 2022 19:04:59 +0800 +Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock The mtk clock framework in u-boot uses array index for searching clock @@ -22,26 +22,20 @@ with ID=0 to call mtk_topckgen_get_mux_rate. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- - drivers/clk/mediatek/clk-mtk.c | 5 ++++- + drivers/clk/mediatek/clk-mtk.c | 4 +++- drivers/clk/mediatek/clk-mtk.h | 6 ++++++ - 2 files changed, 10 insertions(+), 1 deletion(-) + 2 files changed, 9 insertions(+), 1 deletion(-) --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c -@@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; -+ u32 flag = 0; - - index = readl(priv->base + mux->mux_reg); +@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift; - if (mux->parent[index]) -+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) -+ flag = 1; -+ if (mux->parent[index] > 0 || flag == 1) ++ if (mux->parent[index] > 0 || ++ (mux->parent[index] == CLK_XTAL && ++ priv->tree->flags & CLK_BYPASS_XTAL)) return mtk_clk_find_parent_rate(clk, mux->parent[index], NULL); diff --git a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch b/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch index 41600a96b5bbbe..c8af7e3191825d 100644 --- a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch +++ b/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch @@ -1,7 +1,7 @@ -From cd4d6be5ed0488de2e0df9c388d89ad93d781caa Mon Sep 17 00:00:00 2001 +From 50859bea6a3334834b8250e7e5406507f0d0918a Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 10:57:05 +0800 -Subject: [PATCH 23/31] clk: mediatek: add support to configure clock driver +Date: Wed, 31 Aug 2022 19:05:06 +0800 +Subject: [PATCH 23/32] clk: mediatek: add support to configure clock driver parent This patch adds support for a clock node to configure its parent clock @@ -50,14 +50,14 @@ Signed-off-by: Weijie Gao break; case CLK_PARENT_TOPCKGEN: rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); -@@ -322,9 +316,18 @@ static ulong mtk_topckgen_get_mux_rate(s +@@ -321,9 +315,18 @@ static ulong mtk_topckgen_get_mux_rate(s - if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) - flag = 1; -- if (mux->parent[index] > 0 || flag == 1) + if (mux->parent[index] > 0 || + (mux->parent[index] == CLK_XTAL && +- priv->tree->flags & CLK_BYPASS_XTAL)) - return mtk_clk_find_parent_rate(clk, mux->parent[index], - NULL); -+ if (mux->parent[index] > 0 || flag == 1) { ++ priv->tree->flags & CLK_BYPASS_XTAL)) { + switch (mux->flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + return mtk_clk_find_parent_rate(clk, mux->parent[index], @@ -72,7 +72,7 @@ Signed-off-by: Weijie Gao return priv->tree->xtal_rate; } -@@ -343,7 +346,7 @@ static ulong mtk_topckgen_get_rate(struc +@@ -342,7 +345,7 @@ static ulong mtk_topckgen_get_rate(struc priv->tree->muxes_offs); } @@ -81,7 +81,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; -@@ -376,7 +379,7 @@ static int mtk_topckgen_enable(struct cl +@@ -375,7 +378,7 @@ static int mtk_topckgen_enable(struct cl return 0; } @@ -90,7 +90,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; -@@ -402,7 +405,7 @@ static int mtk_topckgen_disable(struct c +@@ -401,7 +404,7 @@ static int mtk_topckgen_disable(struct c return 0; } @@ -99,7 +99,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -474,19 +477,7 @@ static ulong mtk_clk_gate_get_rate(struc +@@ -473,19 +476,7 @@ static ulong mtk_clk_gate_get_rate(struc struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate = &priv->gates[clk->id]; @@ -120,7 +120,7 @@ Signed-off-by: Weijie Gao } const struct clk_ops mtk_clk_apmixedsys_ops = { -@@ -497,10 +488,10 @@ const struct clk_ops mtk_clk_apmixedsys_ +@@ -496,10 +487,10 @@ const struct clk_ops mtk_clk_apmixedsys_ }; const struct clk_ops mtk_clk_topckgen_ops = { @@ -134,7 +134,7 @@ Signed-off-by: Weijie Gao }; const struct clk_ops mtk_clk_gate_ops = { -@@ -513,11 +504,22 @@ int mtk_common_clk_init(struct udevice * +@@ -512,11 +503,22 @@ int mtk_common_clk_init(struct udevice * const struct mtk_clk_tree *tree) { struct mtk_clk_priv *priv = dev_get_priv(dev); @@ -157,7 +157,7 @@ Signed-off-by: Weijie Gao priv->tree = tree; return 0; -@@ -528,11 +530,22 @@ int mtk_common_clk_gate_init(struct udev +@@ -527,11 +529,22 @@ int mtk_common_clk_gate_init(struct udev const struct mtk_gate *gates) { struct mtk_cg_priv *priv = dev_get_priv(dev); diff --git a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch index f84fdec2b40ad1..6475dde38861f4 100644 --- a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch +++ b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch @@ -1,16 +1,16 @@ -From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001 +From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:14:33 +0800 -Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support +Date: Wed, 31 Aug 2022 19:05:09 +0800 +Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support This patch adds infrasys clock mux support for mediatek clock drivers. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- - drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 4 +- - 2 files changed, 75 insertions(+), 1 deletion(-) + 2 files changed, 74 insertions(+), 1 deletion(-) --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s +@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s return priv->tree->xtal_rate; } @@ -48,15 +48,14 @@ Signed-off-by: Weijie Gao + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + u32 index; -+ u32 flag; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + -+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) -+ flag = 1; -+ if (mux->parent[index] > 0 || flag == 1) { ++ if (mux->parent[index] > 0 || ++ (mux->parent[index] == CLK_XTAL && ++ priv->tree->flags & CLK_BYPASS_XTAL)) { + switch (mux->flags & CLK_PARENT_MASK) { + case CLK_PARENT_TOPCKGEN: + return mtk_clk_find_parent_rate(clk, mux->parent[index], @@ -74,7 +73,7 @@ Signed-off-by: Weijie Gao static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc +@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc priv->tree->muxes_offs); } @@ -100,7 +99,7 @@ Signed-off-by: Weijie Gao static int mtk_clk_mux_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op +@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op .set_parent = mtk_common_clk_set_parent, }; diff --git a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch b/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch index 37619d22f0b085..b03ca7384fa0f6 100644 --- a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch +++ b/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch @@ -1,10 +1,10 @@ -From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001 +From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:15:35 +0800 -Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver +Date: Wed, 31 Aug 2022 19:05:11 +0800 +Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver -This add CLK_XTAL macro and flag to mediatek clock driver common part, -to make thi SoC that has clock directlly connect to XTAL working. +This adds the CLK_XTAL macro/flag to allow modeling clocks which are +directly connected to the xtal clock. Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch index f42e497141cec9..da2506d93e6299 100644 --- a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ b/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch @@ -1,11 +1,12 @@ -From ba4acf55044a8a11fc7e11a558a8a93e3c126391 Mon Sep 17 00:00:00 2001 +From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:21:59 +0800 -Subject: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek +Date: Wed, 31 Aug 2022 19:05:13 +0800 +Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek MT7986 SoC This patch adds clock driver support for MediaTek MT7986 SoC +Reviewed-by: Sean Anderson Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch index 26084a6535a727..cc90fa1944caf6 100644 --- a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ b/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch @@ -1,11 +1,12 @@ -From 79bca945dbfafcd08d71437b11e8ee57d64b4305 Mon Sep 17 00:00:00 2001 +From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:22:51 +0800 -Subject: [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek +Date: Wed, 31 Aug 2022 19:05:16 +0800 +Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek MT7981 SoC This patch adds clock driver support for MediaTek MT7981 SoC +Reviewed-by: Sean Anderson Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch b/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch new file mode 100644 index 00000000000000..01871781f05239 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch @@ -0,0 +1,133 @@ +From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:20 +0800 +Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips + +Add basic CPU driver used to retrieve CPU model information. + +Signed-off-by: Weijie Gao +--- + drivers/cpu/Makefile | 1 + + drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 107 insertions(+) + create mode 100644 drivers/cpu/mtk_cpu.c + +--- a/drivers/cpu/Makefile ++++ b/drivers/cpu/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o + obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o + obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o + obj-$(CONFIG_ARCH_AT91) += at91_cpu.o ++obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o + obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o + obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o + obj-$(CONFIG_SANDBOX) += cpu_sandbox.o +--- /dev/null ++++ b/drivers/cpu/mtk_cpu.c +@@ -0,0 +1,106 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. All rights reserved. ++ * ++ * Author: Weijie Gao ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++struct mtk_cpu_plat { ++ void __iomem *hwver_base; ++}; ++ ++static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size) ++{ ++ struct mtk_cpu_plat *plat = dev_get_plat(dev); ++ ++ snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base)); ++ ++ return 0; ++} ++ ++static int mtk_cpu_get_count(const struct udevice *dev) ++{ ++ return 1; ++} ++ ++static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size) ++{ ++ snprintf(buf, size, "MediaTek"); ++ ++ return 0; ++} ++ ++static int mtk_cpu_probe(struct udevice *dev) ++{ ++ struct mtk_cpu_plat *plat = dev_get_plat(dev); ++ const void *fdt = gd->fdt_blob, *reg; ++ int offset, parent, len, na, ns; ++ u64 addr; ++ ++ if (!fdt) ++ return -ENODEV; ++ ++ offset = fdt_path_offset(fdt, "/hwver"); ++ if (offset < 0) ++ return -ENODEV; ++ ++ parent = fdt_parent_offset(fdt, offset); ++ if (parent < 0) ++ return -ENODEV; ++ ++ na = fdt_address_cells(fdt, parent); ++ if (na < 1) ++ return -ENODEV; ++ ++ ns = fdt_size_cells(gd->fdt_blob, parent); ++ if (ns < 0) ++ return -ENODEV; ++ ++ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); ++ if (!reg) ++ return -ENODEV; ++ ++ if (ns) ++ addr = fdt_translate_address(fdt, offset, reg); ++ else ++ addr = fdt_read_number(reg, na); ++ ++ plat->hwver_base = map_sysmem(addr, 0); ++ if (!plat->hwver_base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct cpu_ops mtk_cpu_ops = { ++ .get_desc = mtk_cpu_get_desc, ++ .get_count = mtk_cpu_get_count, ++ .get_vendor = mtk_cpu_get_vendor, ++}; ++ ++static const struct udevice_id mtk_cpu_ids[] = { ++ { .compatible = "arm,cortex-a7" }, ++ { .compatible = "arm,cortex-a53" }, ++ { .compatible = "arm,cortex-a73" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(cpu_mtk) = { ++ .name = "mtk-cpu", ++ .id = UCLASS_CPU, ++ .of_match = mtk_cpu_ids, ++ .ops = &mtk_cpu_ops, ++ .probe = mtk_cpu_probe, ++ .plat_auto = sizeof(struct mtk_cpu_plat), ++ .flags = DM_FLAG_PRE_RELOC, ++}; diff --git a/package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch similarity index 93% rename from package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch rename to package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch index c8747ae1547e62..54c92eaaf778de 100644 --- a/package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch @@ -1,7 +1,7 @@ -From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001 +From 1c9174cbf57ddc75bb5a25b2563333d974fd1a55 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 2 Aug 2022 17:21:34 +0800 -Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a +Date: Wed, 31 Aug 2022 19:05:22 +0800 +Subject: [PATCH 29/32] tools: mtk_image: split gfh header verification into a new function The verification code of gfh header for NAND and non-NAND are identical. diff --git a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch similarity index 99% rename from package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch rename to package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch index 9a5332f6950bcb..2f5c9353563291 100644 --- a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch @@ -1,7 +1,7 @@ -From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001 +From 8867a5e66369d4a7da667e0f505597e1ac91209e Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 2 Aug 2022 17:23:57 +0800 -Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND +Date: Wed, 31 Aug 2022 19:05:24 +0800 +Subject: [PATCH 30/32] tools: mtk_image: split the code of generating NAND header into a new file The predefined NAND headers take too much spaces in the mtk_image.c. diff --git a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch similarity index 99% rename from package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch rename to package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch index 0ce095998f417e..c20dffdb36d34a 100644 --- a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ b/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch @@ -1,7 +1,7 @@ -From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001 +From d459092aca25e081401606e18b7097f33b575188 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 3 Aug 2022 11:14:36 +0800 -Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by +Date: Wed, 31 Aug 2022 19:05:26 +0800 +Subject: [PATCH 31/32] tools: mtk_image: add support for nand headers used by newer chips This patch adds more nand headers in two new types: diff --git a/package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch b/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch similarity index 74% rename from package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch rename to package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch index 227fa0752778ba..5b0b263fd553f4 100644 --- a/package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch +++ b/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch @@ -1,7 +1,7 @@ -From ca90c165157c19af9bf46a69dcf719b8aab636b1 Mon Sep 17 00:00:00 2001 +From 180f8ce7cac9277406ee702ea9390a6f78981bda Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 4 Aug 2022 09:50:40 +0800 -Subject: [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM +Date: Wed, 31 Aug 2022 19:05:28 +0800 +Subject: [PATCH 32/32] MAINTAINERS: update maintainer for MediaTek ARM platform Add new files for MediaTek ARM platform @@ -9,15 +9,16 @@ Add new files for MediaTek ARM platform Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- - MAINTAINERS | 5 +++++ - 1 file changed, 5 insertions(+) + MAINTAINERS | 6 ++++++ + 1 file changed, 6 insertions(+) --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -340,20 +340,25 @@ F: doc/device-tree-bindings/phy/phy-mtk- +@@ -340,20 +340,26 @@ F: doc/device-tree-bindings/phy/phy-mtk- F: doc/device-tree-bindings/usb/mediatek,* F: doc/README.mediatek F: drivers/clk/mediatek/ ++F: drivers/cpu/mtk_cpu.c +F: drivers/i2c/mtk_i2c.c F: drivers/mmc/mtk-sd.c F: drivers/phy/phy-mtk-* diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index b6243db9c2d902..571b883fb99a42 100644 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -89,7 +89,7 @@ Signed-off-by: Weijie Gao reg = <0x11014000 0x1000>; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -131,9 +131,11 @@ config SYS_CONFIG_NAME +@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 9fae6d056f6077..63301fd5351317 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -40,7 +40,7 @@ } --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -138,4 +138,8 @@ config MTK_BROM_HEADER_INFO +@@ -140,4 +140,8 @@ config MTK_BROM_HEADER_INFO source "board/mediatek/mt7629/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch index 48835e43af72fb..d48de66064c5a5 100644 --- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -51,6 +51,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -246,6 +247,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -442,6 +444,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -637,6 +640,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y From 11a6021866a4e5c688dde0d1ea5841f10fc739be Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 31 Aug 2022 21:10:39 +0100 Subject: [PATCH 07/91] arm-trusted-firmware-mediatek: update to sources of 2022-08-31 Drop downstream patches which have been replaced with equivalent upstream changes. Signed-off-by: Daniel Golle --- .../arm-trusted-firmware-mediatek/Makefile | 6 +-- ...-spi-nor-add-more-Winbond-device-IDs.patch | 32 --------------- ...2-initialize-watchdog-after-DDR-init.patch | 40 ------------------- 3 files changed, 3 insertions(+), 75 deletions(-) delete mode 100644 package/boot/arm-trusted-firmware-mediatek/patches/0001-spi-nor-add-more-Winbond-device-IDs.patch delete mode 100644 package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-mt7622-initialize-watchdog-after-DDR-init.patch diff --git a/package/boot/arm-trusted-firmware-mediatek/Makefile b/package/boot/arm-trusted-firmware-mediatek/Makefile index 583517b8668504..c54373f6bdffee 100644 --- a/package/boot/arm-trusted-firmware-mediatek/Makefile +++ b/package/boot/arm-trusted-firmware-mediatek/Makefile @@ -13,9 +13,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git -PKG_SOURCE_DATE:=2022-08-18 -PKG_SOURCE_VERSION:=9c9c49945c24634e4ae6cd924dbb88cf85c7926d -PKG_MIRROR_HASH:=26b474f40c02da12b7bed56597aeef209757ad1b40a4f0a652794954018b2198 +PKG_SOURCE_DATE:=2022-08-31 +PKG_SOURCE_VERSION:=7539348480af57c6d0db95aba6381f3ee7483779 +PKG_MIRROR_HASH:=125090124d77753acc379b3b124100978c1ecb3da37c4983ba9644b433b7eb08 PKG_MAINTAINER:=Daniel Golle diff --git a/package/boot/arm-trusted-firmware-mediatek/patches/0001-spi-nor-add-more-Winbond-device-IDs.patch b/package/boot/arm-trusted-firmware-mediatek/patches/0001-spi-nor-add-more-Winbond-device-IDs.patch deleted file mode 100644 index d0e2f8a2c3fe4d..00000000000000 --- a/package/boot/arm-trusted-firmware-mediatek/patches/0001-spi-nor-add-more-Winbond-device-IDs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From daaac60b504e6d5e77156ad0dc3dceca8b786e2d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 27 Aug 2022 03:41:57 +0100 -Subject: [PATCH] spi-nor: add more Winbond device IDs - -Add device IDs for Winbond W25Q256 and W25Q512 variants. - -Signed-off-by: Daniel Golle ---- - drivers/mtd/nor/spi_nor.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/nor/spi_nor.c -+++ b/drivers/mtd/nor/spi_nor.c -@@ -327,8 +327,15 @@ int spi_nor_read(unsigned int offset, ui - - struct nor_device_info nor_flash_info_table[] = { - {"MX25L51245G", {0xC2, 0x20, 0x1A}, 0x4000000, 0}, -- {"W25Q256JW",{0xEF,0x80, 0x19}, 0x2000000, 0}, -- {"MX25U25635",{0xC2, 0x25, 0x39}, 0x2000000, 0} -+ {"W25Q256JV-IM", {0xEF, 0x70, 0x19}, 0x2000000, 0}, -+ {"W25Q256JV-IQ", {0xEF, 0x40, 0x19}, 0x2000000, 0}, -+ {"W25Q256JW", {0xEF, 0x60, 0x19}, 0x2000000, 0}, -+ {"W25Q256JW-IM", {0xEF, 0x80, 0x19}, 0x2000000, 0}, -+ {"W25Q512JV-IM", {0xEF, 0x70, 0x20}, 0x4000000, 0}, -+ {"W25Q512JV-IQ", {0xEF, 0x40, 0x20}, 0x4000000, 0}, -+ {"W25Q512NW-IM", {0xEF, 0x80, 0x20}, 0x4000000, 0}, -+ {"W25Q512NW-IQ/IN", {0xEF, 0x60, 0x20}, 0x4000000, 0}, -+ {"MX25U25635", {0xC2, 0x25, 0x39}, 0x2000000, 0} - }; - - diff --git a/package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-mt7622-initialize-watchdog-after-DDR-init.patch b/package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-mt7622-initialize-watchdog-after-DDR-init.patch deleted file mode 100644 index d8905986e2f943..00000000000000 --- a/package/boot/arm-trusted-firmware-mediatek/patches/0002-mediatek-mt7622-initialize-watchdog-after-DDR-init.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 2a012775b3ab6e72091c8be1c2d4bf5972407eb5 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 27 Aug 2022 21:38:33 +0100 -Subject: [PATCH] mediatek: mt7622: initialize watchdog after DDR init - -Initializing the WDT before memory calibration breaks reboot at least -on some MT7622 boards like the Bananapi BPi-R64: -NOTICE: BL2: v2.7(release):OpenWrt v2022-08-18-9c9c4994-2 (mt7622-emmc-2ddr) -NOTICE: BL2: Built : 04:00:25, Aug 27 2022 -ERROR: Cannot find any pass-window -ERROR: no DATLAT taps pass, DATLAT calibration fail! -ERROR: DATLAT calibration fail, write back to 20! -ERROR: EMI: complex R/W mem test failed: -2 - -Move watchdog initialization to happen only after memory initialization -has completed to avoid the problem. - -Signed-off-by: Daniel Golle ---- - plat/mediatek/mt7622/bl2_plat_setup.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/plat/mediatek/mt7622/bl2_plat_setup.c -+++ b/plat/mediatek/mt7622/bl2_plat_setup.c -@@ -277,7 +277,6 @@ void bl2_platform_setup(void) - plat_mt_cpuxgpt_init(); - generic_delay_timer_init(); - -- mtk_wdt_init(); - mtk_pin_init(); - #ifndef USING_BL2PL - mtk_pll_init(); -@@ -285,6 +284,7 @@ void bl2_platform_setup(void) - mtk_pwrap_init(); - mtk_pmic_init(); - mtk_mem_init(); -+ mtk_wdt_init(); - - mtk_io_setup(); - } From e0753c5d5cef5b03c60601364188afb262ccd02e Mon Sep 17 00:00:00 2001 From: John Audia Date: Mon, 29 Aug 2022 11:30:27 -0400 Subject: [PATCH 08/91] kernel: bump 5.10 to 5.10.139 All patches automatically rebased. Signed-off-by: John Audia --- include/kernel-5.10 | 4 +- .../300-mips-add-rtl838x-platform.patch | 2 +- .../318-add-rtl83xx-clk-support.patch | 46 ++++++++----------- 3 files changed, 23 insertions(+), 29 deletions(-) diff --git a/include/kernel-5.10 b/include/kernel-5.10 index 4143799e89705a..8933b1de8378a7 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .138 -LINUX_KERNEL_HASH-5.10.138 = 29a003bb8e0e3a45942f703370fb0b3460e6fdcbbad37424423c9cf831ab5ba8 +LINUX_VERSION-5.10 = .139 +LINUX_KERNEL_HASH-5.10.139 = 1c002ac275a44934a280a158a136735bf6665b26a42d344023b4648a7898bef1 diff --git a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch index 476afba6a80aeb..87ab1a7543739d 100644 --- a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch +++ b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch @@ -73,7 +73,7 @@ source "arch/mips/alchemy/Kconfig" source "arch/mips/ath25/Kconfig" source "arch/mips/ath79/Kconfig" -@@ -1097,6 +1147,9 @@ config CEVT_GT641XX +@@ -1097,6 +1151,9 @@ config CEVT_GT641XX config CEVT_R4K bool diff --git a/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch b/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch index 5215a7508748c5..285b7489f2c523 100644 --- a/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch +++ b/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch @@ -1,26 +1,20 @@ -diff -rpN x/drivers/clk/Kconfig y/drivers/clk/Kconfig -*** x/drivers/clk/Kconfig 2022-07-29 14:28:59.704481188 +0200 ---- y/drivers/clk/Kconfig 2022-07-29 14:29:56.886053322 +0200 -*************** source "drivers/clk/mediatek/Kconfig" -*** 372,377 **** ---- 372,378 ---- - source "drivers/clk/meson/Kconfig" - source "drivers/clk/mvebu/Kconfig" - source "drivers/clk/qcom/Kconfig" -+ source "drivers/clk/realtek/Kconfig" - source "drivers/clk/renesas/Kconfig" - source "drivers/clk/rockchip/Kconfig" - source "drivers/clk/samsung/Kconfig" -diff -rpN x/drivers/clk/Makefile y/drivers/clk/Makefile -*** x/drivers/clk/Makefile 2022-07-29 13:34:36.638231518 +0200 ---- y/drivers/clk/Makefile 2022-07-29 13:34:19.105060958 +0200 -*************** obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ -*** 100,105 **** ---- 100,106 ---- - obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ - obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ - obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ -+ obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ - obj-y += renesas/ - obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ - obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig" + source "drivers/clk/meson/Kconfig" + source "drivers/clk/mvebu/Kconfig" + source "drivers/clk/qcom/Kconfig" ++source "drivers/clk/realtek/Kconfig" + source "drivers/clk/renesas/Kconfig" + source "drivers/clk/rockchip/Kconfig" + source "drivers/clk/samsung/Kconfig" +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ + obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ + obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ + obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ ++obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ + obj-y += renesas/ + obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ + obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ From 6ff21c436dd93646f924efdd73c4b3fc59501ad3 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Tue, 30 Aug 2022 16:44:02 +0200 Subject: [PATCH 09/91] realtek: fix PLL register inconsistencies Some devices have wrong/empty values in the PLL registers. Work around that by reporting the default values. Signed-off-by: Markus Stockhausen --- .../linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c index c3eb270f6e935d..9b8183fbebd6bc 100644 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c +++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c @@ -366,6 +366,9 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra switch (rtcl_ccu->soc) { case SOC_RTL838X: + if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB)) + return 200000000; + cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; break; From 78c0fb69275be14c7f46e97c0df3932807c0dd56 Mon Sep 17 00:00:00 2001 From: Markus Stockhausen Date: Tue, 30 Aug 2022 16:48:46 +0200 Subject: [PATCH 10/91] realtek: Fix missing clock module CONFIG setting Since introduction of clock driver we have a new kernel config setting. Provide an initial value for the 930x targets. Signed-off-by: Markus Stockhausen --- target/linux/realtek/rtl930x/config-5.10 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/realtek/rtl930x/config-5.10 b/target/linux/realtek/rtl930x/config-5.10 index 5afe90f23675ec..9984533c067b17 100644 --- a/target/linux/realtek/rtl930x/config-5.10 +++ b/target/linux/realtek/rtl930x/config-5.10 @@ -14,6 +14,7 @@ CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_BOSTON=y +# CONFIG_COMMON_CLK_REALTEK is not set CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 CONFIG_CPU_BIG_ENDIAN=y From f8f9d6901c6a7c85e6b18fba665175646fb53ec7 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Tue, 30 Aug 2022 08:51:37 +0200 Subject: [PATCH 11/91] kernel: fix typo for tegra crypto-sha1 module Fixes: e889489bedfd2830411bd0cf6564b8272aa9c254 ("kernel: build arm/neon-optimized sha1/512 modules") Signed-off-by: Josef Schlehofer --- package/kernel/linux/modules/crypto.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk index a5b018aa1e82b9..5b52eacf109e60 100644 --- a/package/kernel/linux/modules/crypto.mk +++ b/package/kernel/linux/modules/crypto.mk @@ -858,7 +858,7 @@ define KernelPackage/crypto-sha1/octeon AUTOLOAD+=$(call AutoLoad,09,octeon-sha1) endef -KernelPackage/crypto-sha1/tegra=$(KernelPakcage/crypto-sha1/arm) +KernelPackage/crypto-sha1/tegra=$(KernelPackage/crypto-sha1/arm) define KernelPackage/crypto-sha1/x86/64 FILES+=$(LINUX_DIR)/arch/x86/crypto/sha1-ssse3.ko From f15137c455f050f089b60269744ee1ba077b6386 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 08:25:03 +0200 Subject: [PATCH 12/91] readline: update to 8.1.2 Update to latest version. Signed-off-by: Nick Hainke --- package/libs/readline/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/libs/readline/Makefile b/package/libs/readline/Makefile index 9cf061a648c66c..a6ceec1fce8391 100644 --- a/package/libs/readline/Makefile +++ b/package/libs/readline/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=readline -PKG_VERSION:=8.1 +PKG_VERSION:=8.1.2 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/readline -PKG_HASH:=f8ceb4ee131e3232226a17f51b164afc46cd0b9e6cef344be87c65962cb82b02 +PKG_HASH:=7589a2381a8419e68654a47623ce7dfcb756815c8fee726b98f90bf668af7bc6 PKG_LICENSE:=GPL-3.0-or-later PKG_LICENSE_FILES:=COPYING From bae87942bcfb461d2882dd7e593b6aa2d75f63b1 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 08:08:40 +0200 Subject: [PATCH 13/91] nettle: update to 3.8.1 Release Notes: https://lists.gnu.org/archive/html/info-gnu/2022-07/msg00010.html Signed-off-by: Nick Hainke --- package/libs/nettle/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/libs/nettle/Makefile b/package/libs/nettle/Makefile index 0c06205ec2c8de..8e4b987512b577 100644 --- a/package/libs/nettle/Makefile +++ b/package/libs/nettle/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=nettle -PKG_VERSION:=3.8 +PKG_VERSION:=3.8.1 PKG_RELEASE:=$(AUTORELEASE) PKG_USE_MIPS16:=0 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@GNU/nettle -PKG_HASH:=7576c68481c198f644b08c160d1a4850ba9449e308069455b5213319f234e8e6 +PKG_HASH:=364f3e2b77cd7dcde83fd7c45219c834e54b0c75e428b6f894a23d12dd41cbfe PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=COPYING From ab31ffc425b59afc102f8a3275791c153f39c8f4 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Thu, 1 Sep 2022 12:37:58 +0200 Subject: [PATCH 14/91] firewall4: update to latest Git HEAD f5fcdcf cli: introduce test mode and refuse firewall restart on errors a540f6d fw4: fix cosmetic issue with per-ruleset and per-table include paths 695e821 doc: fix swapped include positions in nftables.d README Signed-off-by: Jo-Philipp Wich --- package/network/config/firewall4/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/network/config/firewall4/Makefile b/package/network/config/firewall4/Makefile index 82ba304e43238f..87510d59af649b 100644 --- a/package/network/config/firewall4/Makefile +++ b/package/network/config/firewall4/Makefile @@ -9,9 +9,9 @@ PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git -PKG_SOURCE_DATE:=2022-08-12 -PKG_SOURCE_VERSION:=a4484d4612931800583a7219271b63224491244c -PKG_MIRROR_HASH:=f23799cf619395eab0c46050bb52b0a177e37056ff11dc146be6a358af367ae2 +PKG_SOURCE_DATE:=2022-09-01 +PKG_SOURCE_VERSION:=f5fcdcf2c51f6f0a4b116c352000c4fe0523be77 +PKG_MIRROR_HASH:=57ef6f161abdd323019c026c959ab875fdfd3c972b8dc7767623634b1c259138 PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=ISC From 23a7188ab47907a631951c18d93cf3fee0055a79 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 31 Aug 2022 13:29:32 +0200 Subject: [PATCH 15/91] unetd: fix handling of connect/tunnel list change the type to array, so that uci lists can be used Signed-off-by: Felix Fietkau --- package/network/services/unetd/files/unetd.sh | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/package/network/services/unetd/files/unetd.sh b/package/network/services/unetd/files/unetd.sh index 8e56fbd8694c4c..581eeb95fa147c 100644 --- a/package/network/services/unetd/files/unetd.sh +++ b/package/network/services/unetd/files/unetd.sh @@ -16,8 +16,8 @@ proto_unet_init_config() { proto_config_add_string file proto_config_add_int keepalive proto_config_add_string domain - proto_config_add_string "tunnels:list(string)" - proto_config_add_string "connect:list(string)" + proto_config_add_array "tunnels:list(string)" + proto_config_add_array "connect:list(string)" no_device=1 available=1 no_proto_task=1 @@ -27,7 +27,9 @@ proto_unet_setup() { local config="$1" local device type key file keepalive domain tunnels - json_get_vars device type auth_key key file keepalive domain tunnels connect + json_get_vars device type auth_key key file keepalive domain + json_get_values tunnels tunnels + json_get_values connect connect device="${device:-$config}" [ -n "$auth_key" ] && type="${type:-dynamic}" From 90f55f5bf1d17dd19aac48ee1ca9bfeb7128703e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 1 Sep 2022 20:41:42 +0200 Subject: [PATCH 16/91] unetd: update to the latest version f5d02c32f811 pex: add support for sending endpoint notification from the wg port via raw socket c3b1127236a0 ubus: add support for querying active networks 8ad119715168 ubus: add support for adding auth_connect hosts at runtime 26dc52789d41 network: add support for configuring extra peers via a separate json file d7fb9e5b065b ubus: add reload command Signed-off-by: Felix Fietkau --- package/network/services/unetd/Makefile | 6 +++--- package/network/services/unetd/files/unetd.sh | 8 ++++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/package/network/services/unetd/Makefile b/package/network/services/unetd/Makefile index f692f26974dc9e..06e95b3326f0a6 100644 --- a/package/network/services/unetd/Makefile +++ b/package/network/services/unetd/Makefile @@ -10,9 +10,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=unetd PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/unetd.git -PKG_SOURCE_DATE:=2022-08-29 -PKG_SOURCE_VERSION:=0041fcacb62492653a1054098ec7d811d8eaacbf -PKG_MIRROR_HASH:=1aad05af0c4015dc7c07936e504a2c03ceacf676c5c15902c2049a63fab60428 +PKG_SOURCE_DATE:=2022-09-01 +PKG_SOURCE_VERSION:=d7fb9e5b065bf9eecb5bcbcf741b5f89695c5dcc +PKG_MIRROR_HASH:=a693c2b4b4bda5e1e44b493019e8e6e6d39c4048f417b581c801a9931e6b9b39 PKG_LICENSE:=GPL-2.0 PKG_MAINTAINER:=Felix Fietkau diff --git a/package/network/services/unetd/files/unetd.sh b/package/network/services/unetd/files/unetd.sh index 581eeb95fa147c..70a28f64826c8d 100644 --- a/package/network/services/unetd/files/unetd.sh +++ b/package/network/services/unetd/files/unetd.sh @@ -18,6 +18,7 @@ proto_unet_init_config() { proto_config_add_string domain proto_config_add_array "tunnels:list(string)" proto_config_add_array "connect:list(string)" + proto_config_add_array "peer_data:list(string)" no_device=1 available=1 no_proto_task=1 @@ -30,6 +31,7 @@ proto_unet_setup() { json_get_vars device type auth_key key file keepalive domain json_get_values tunnels tunnels json_get_values connect connect + json_get_values peer_data peer_data device="${device:-$config}" [ -n "$auth_key" ] && type="${type:-dynamic}" @@ -60,6 +62,12 @@ proto_unet_setup() { done json_close_array + json_add_array peer_data + for c in $peer_data; do + json_add_string "" "$c" + done + json_close_array + ip link del dev "$device" >/dev/null 2>&1 ip link add dev "$device" type wireguard || { echo "Could not create wireguard device $device" From 6c302b900979c3bad2a7764f72f23ccc2d2a33a4 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 1 Sep 2022 21:40:44 +0100 Subject: [PATCH 17/91] kernel: fix DSA mac_select_pcs backport Backport commit from Linux 5.18 fixing phylink with DSA drivers which do not provide mac_select_pcs yet. Fixes: aab466f422 ("kernel: backport generic phylink validate") Signed-off-by: Daniel Golle --- ...-fix-DSA-mac_select_pcs-introduction.patch | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch diff --git a/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch b/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch new file mode 100644 index 00000000000000..4ab90fafe1da76 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch @@ -0,0 +1,88 @@ +From 1054457006d4a14de4ae4132030e33d7eedaeba1 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 21 Feb 2022 17:10:52 +0000 +Subject: [PATCH] net: phy: phylink: fix DSA mac_select_pcs() introduction + +Vladimir Oltean reports that probing on DSA drivers that aren't yet +populating supported_interfaces now fails. Fix this by allowing +phylink to detect whether DSA actually provides an underlying +mac_select_pcs() implementation. + +Reported-by: Vladimir Oltean +Fixes: bde018222c6b ("net: dsa: add support for phylink mac_select_pcs()") +Signed-off-by: Russell King (Oracle) +Tested-by: Vladimir Oltean +Link: https://lore.kernel.org/r/E1nMCD6-00A0wC-FG@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/phylink.c | 14 +++++++++++--- + net/dsa/port.c | 2 +- + 2 files changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -74,6 +74,7 @@ struct phylink { + struct work_struct resolve; + + bool mac_link_dropped; ++ bool using_mac_select_pcs; + + struct sfp_bus *sfp_bus; + bool sfp_may_have_phy; +@@ -163,7 +164,7 @@ static int phylink_validate_mac_and_pcs( + int ret; + + /* Get the PCS for this interface mode */ +- if (pl->mac_ops->mac_select_pcs) { ++ if (pl->using_mac_select_pcs) { + pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); + if (IS_ERR(pcs)) + return PTR_ERR(pcs); +@@ -790,7 +791,7 @@ static void phylink_major_config(struct + + phylink_dbg(pl, "major config %s\n", phy_modes(state->interface)); + +- if (pl->mac_ops->mac_select_pcs) { ++ if (pl->using_mac_select_pcs) { + pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface); + if (IS_ERR(pcs)) { + phylink_err(pl, +@@ -1192,11 +1193,17 @@ struct phylink *phylink_create(struct ph + phy_interface_t iface, + const struct phylink_mac_ops *mac_ops) + { ++ bool using_mac_select_pcs = false; + struct phylink *pl; + int ret; + +- /* Validate the supplied configuration */ + if (mac_ops->mac_select_pcs && ++ mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) != ++ ERR_PTR(-EOPNOTSUPP)) ++ using_mac_select_pcs = true; ++ ++ /* Validate the supplied configuration */ ++ if (using_mac_select_pcs && + phy_interface_empty(config->supported_interfaces)) { + dev_err(config->dev, + "phylink: error: empty supported_interfaces but mac_select_pcs() method present\n"); +@@ -1220,6 +1227,7 @@ struct phylink *phylink_create(struct ph + return ERR_PTR(-EINVAL); + } + ++ pl->using_mac_select_pcs = using_mac_select_pcs; + pl->phy_state.interface = iface; + pl->link_interface = iface; + if (iface == PHY_INTERFACE_MODE_MOCA) +--- a/net/dsa/port.c ++++ b/net/dsa/port.c +@@ -1017,8 +1017,8 @@ dsa_port_phylink_mac_select_pcs(struct p + phy_interface_t interface) + { + struct dsa_port *dp = container_of(config, struct dsa_port, pl_config); ++ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); + struct dsa_switch *ds = dp->ds; +- struct phylink_pcs *pcs = NULL; + + if (ds->ops->phylink_mac_select_pcs) + pcs = ds->ops->phylink_mac_select_pcs(ds, dp->index, interface); From 9a49788008c18fd4fe6fefe9697962c102fb14c6 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 28 Jul 2022 13:12:34 +0300 Subject: [PATCH 18/91] uboot-at91: use sdmmc0 as booting media for sama5d27_som1_ek Commit adc69fe (""uboot-at91: changed som1 ek default defconfigs") changed the booting media to sdmmc1 as default booting w/o any reason. The Microchip releases for the rest of supported distributions (Buildroot, Yocto Project) uses sdmmc0 as default booting media for this board. Thus change it back to sdmmc0. With this remove references to sdmmc1 config. The initial commit cannot be cleanly reverted. Signed-off-by: Claudiu Beznea --- package/boot/uboot-at91/Makefile | 6 +++--- target/linux/at91/image/sama5.mk | 16 +++++----------- target/linux/at91/image/uboot-env.txt | 4 ++-- 3 files changed, 10 insertions(+), 16 deletions(-) diff --git a/package/boot/uboot-at91/Makefile b/package/boot/uboot-at91/Makefile index d75e3ba3aff9ee..f75a3878366814 100644 --- a/package/boot/uboot-at91/Makefile +++ b/package/boot/uboot-at91/Makefile @@ -107,8 +107,8 @@ define U-Boot/sama5d4_xplained_nandflash BUILD_DEVICES:=microchip_sama5d3-xplained endef -define U-Boot/sama5d27_som1_ek_mmc1 - NAME:=SAMA5D27 SOM1 Ek (SDCard1) +define U-Boot/sama5d27_som1_ek_mmc + NAME:=SAMA5D27 SOM1 Ek (SDCard0) BUILD_SUBTARGET:=sama5 BUILD_DEVICES:=microchip_sama5d27-som1-ek endef @@ -163,7 +163,7 @@ UBOOT_TARGETS := \ sama5d4_xplained_mmc \ sama5d4_xplained_spiflash \ sama5d4_xplained_nandflash\ - sama5d27_som1_ek_mmc1 \ + sama5d27_som1_ek_mmc \ sama5d27_som1_ek_qspiflash \ sama5d27_wlsom1_ek_mmc \ sama5d27_wlsom1_ek_qspiflash \ diff --git a/target/linux/at91/image/sama5.mk b/target/linux/at91/image/sama5.mk index 9078db525f9775..d108d27908eabc 100644 --- a/target/linux/at91/image/sama5.mk +++ b/target/linux/at91/image/sama5.mk @@ -15,23 +15,17 @@ define Build/at91-sdcard $(KDIR)/$(DEVICE_NAME)-fit-zImage.itb \ ::$(DEVICE_NAME)-fit.itb - $(if $(findstring sama5d27-som1-ek,$@), \ - mcopy -i $@.boot \ - $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc1/u-boot.bin \ - ::u-boot.bin - mcopy -i $@.boot \ - $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd1_uboot/at91bootstrap.bin \ - ::BOOT.bin, - mcopy -i $@.boot \ - $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \ - ::u-boot.bin + mcopy -i $@.boot \ + $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \ + ::u-boot.bin + $(if $(findstring sama5d4-xplained,$@), \ mcopy -i $@.boot \ $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot_secure/at91bootstrap.bin \ ::BOOT.bin, mcopy -i $@.boot \ $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot/at91bootstrap.bin \ - ::BOOT.bin)) + ::BOOT.bin) $(CP) uboot-env.txt $@-uboot-env.txt sed -i '2d;3d' $@-uboot-env.txt diff --git a/target/linux/at91/image/uboot-env.txt b/target/linux/at91/image/uboot-env.txt index 14f983d03920b7..c30bf42ec3aff1 100644 --- a/target/linux/at91/image/uboot-env.txt +++ b/target/linux/at91/image/uboot-env.txt @@ -6,8 +6,8 @@ bootargsd2=console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait root bootargsxx=console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait rootfstype=ext4 bootcmd=run setloadaddr; run setbootargs; run fatload_mmc; bootm ${loadaddr} bootdelay=1 -fatload_mmc=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then fatload mmc 1:1 ${loadaddr} ${board}-fit.itb; else fatload mmc 0:1 ${loadaddr} ${board}-fit.itb; fi -setbootargs=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then setenv bootargs ${bootargsd2}; else setenv bootargs ${bootargsxx}; fi +fatload_mmc=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = microchip,sama7g5ek; then fatload mmc 1:1 ${loadaddr} ${board}-fit.itb; else fatload mmc 0:1 ${loadaddr} ${board}-fit.itb; fi +setbootargs=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = microchip,sama7g5ek; then setenv bootargs ${bootargsd2}; else setenv bootargs ${bootargsxx}; fi setloadaddr=if test ${board_name} = microchip,sama7g5ek; then setenv loadaddr 0x63000000; else setenv loadaddr 0x21000000; fi ethact=gmac0 stderr=serial From e9f12931e60ee291cd7d2c8fd19a14682dae0197 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 28 Jul 2022 13:14:59 +0300 Subject: [PATCH 19/91] at91bootstrap: use sdmmc0 as booting media for sama5d27_som1_ek Commit 0b7c66c ("at91bootstrap: add sama5d27_som1_eksd1_uboot as default defconfig") changed default booting media for sama5d27_som1_ek board w/o any reason. Changed it back to sdmmc0 as it is for all the other Microchip supported distributions for this board (Buildroot, Yocto Project). The initial commit cannot be cleanly reverted. Signed-off-by: Claudiu Beznea --- package/boot/at91bootstrap/Makefile | 8 +------- target/linux/at91/image/sama5.mk | 4 ++-- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/package/boot/at91bootstrap/Makefile b/package/boot/at91bootstrap/Makefile index 1dd0f38fc2d218..efd42ecf5cc02c 100644 --- a/package/boot/at91bootstrap/Makefile +++ b/package/boot/at91bootstrap/Makefile @@ -136,12 +136,6 @@ define AT91Bootstrap/sama5d27_som1_eksd_uboot BUILD_DEVICES:=microchip_sama5d27-som1-ek endef -define AT91Bootstrap/sama5d27_som1_eksd1_uboot - TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (SDcard1) - BUILD_SUBTARGET:=sama5 - BUILD_DEVICES:=microchip_sama5d27-som1-ek -endef - define AT91Bootstrap/sama5d27_som1_ekqspi_uboot TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (QSPI Flash) BUILD_SUBTARGET:=sama5 @@ -193,7 +187,7 @@ AT91BOOTSTRAP_TARGETS := \ sama5d4_xplainednf_uboot_secure \ sama5d4_xplaineddf_uboot_secure \ sama5d4_xplainedsd_uboot_secure \ - sama5d27_som1_eksd1_uboot \ + sama5d27_som1_eksd_uboot \ sama5d27_som1_ekqspi_uboot \ sama5d27_wlsom1_eksd_uboot \ sama5d27_wlsom1_ekdf_qspi_uboot \ diff --git a/target/linux/at91/image/sama5.mk b/target/linux/at91/image/sama5.mk index d108d27908eabc..39db3e1cd022b3 100644 --- a/target/linux/at91/image/sama5.mk +++ b/target/linux/at91/image/sama5.mk @@ -19,8 +19,8 @@ define Build/at91-sdcard $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \ ::u-boot.bin - $(if $(findstring sama5d4-xplained,$@), \ - mcopy -i $@.boot \ + $(if $(findstring sama5d4-xplained,$@), \ + mcopy -i $@.boot \ $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot_secure/at91bootstrap.bin \ ::BOOT.bin, mcopy -i $@.boot \ From 7f4b4c29f3489697dca7495216460d0ed5023e02 Mon Sep 17 00:00:00 2001 From: Martin Kennedy Date: Mon, 29 Aug 2022 20:47:24 -0400 Subject: [PATCH 20/91] mpc85xx: Drop pci aliases to avoid domain changes As of upstream Linux commit 0fe1e96fef0a ("powerpc/pci: Prefer PCI domain assignment via DT 'linux,pci-domain' and alias"), the PCIe domain address is no longer numbered by the lowest 16 bits of the PCI register address after a fallthrough. Instead of the fallthrough, the enumeration process accepts the alias ID (as determined by `of_alias_scan()`). This causes e.g.: 9000:00:00.0 PCI bridge: Freescale Semiconductor Inc P1020E (rev 11) 9000:01:00.0 Network controller: Qualcomm Atheros AR958x 802.11abgn ... to become 0000:00:00.0 PCI bridge: Freescale Semiconductor Inc P1020E (rev 11) 0000:01:00.0 Network controller: Qualcomm Atheros AR958x 802.11abgn ... ... which then causes the sysfs path of the netdev to change, invalidating the `wifi_device.path`s enumerated in `/etc/config/wireless`. One other solution might be to migrate the uci configuration, as was done for mvebu in commit 0bd5aa89fcf2 ("mvebu: Migrate uci config to new PCIe path"). However, there are concerns that the sysfs path will change once again once some upstream patches[^2][^3] are merged and backported (and `CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT` is enabled). Instead, remove the aliases and allow the fallthrough to continue for now. We will provide a migration in a later release. This was first reported as a Github issue[^1]. [^1]: https://github.com/openwrt/openwrt/issues/10530 [^2]: https://lore.kernel.org/linuxppc-dev/20220706104308.5390-1-pali@kernel.org/t/#u [^3]: https://lore.kernel.org/linuxppc-dev/20220706101043.4867-1-pali@kernel.org/ Fixes: #10530 Tested-by: Martin Kennedy [Tested on the Aerohive HiveAP 330 and Extreme Networks WS-AP3825i] Signed-off-by: Martin Kennedy --- .../files/arch/powerpc/boot/dts/hiveap-330.dts | 13 +++++++++++++ .../mpc85xx/files/arch/powerpc/boot/dts/panda.dts | 14 ++++++++++++++ .../files/arch/powerpc/boot/dts/red-15w-rev1.dts | 14 ++++++++++++++ .../files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts | 13 +++++++++++++ .../files/arch/powerpc/boot/dts/ws-ap3710i.dts | 13 +++++++++++++ .../files/arch/powerpc/boot/dts/ws-ap3825i.dts | 13 +++++++++++++ 6 files changed, 80 insertions(+) diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts index ccf60eaeed0e10..d6a8da84ef66d1 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts @@ -300,3 +300,16 @@ }; }; /include/ "fsl/p1020si-post.dtsi" + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts index baaa4a43fd559c..9be822f7bb8acf 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts @@ -265,3 +265,17 @@ }; }; /include/ "fsl/p1020si-post.dtsi" + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; + diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts index 1fd6a4aa497133..db35602b94b5b7 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts @@ -214,3 +214,17 @@ }; /include/ "fsl/p1010si-post.dtsi" + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; + diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts index fbe1c0ee705d20..12281808aa5b60 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts @@ -302,3 +302,16 @@ /delete-node/ crypto@30000; /* Pulled in by p1010si-post */ }; }; + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts index c5588d80275e20..5d81da46864139 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts @@ -173,3 +173,16 @@ }; /include/ "fsl/p1020si-post.dtsi" + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts index 26f742b222c396..2ea67184681008 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts @@ -253,3 +253,16 @@ }; /include/ "fsl/p1020si-post.dtsi" + +/* + * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses + * aliases to determine PCI domain numbers, drop aliases so as not to + * change the sysfs path of our wireless netdevs. + */ + +/ { + aliases { + /delete-property/ pci0; + /delete-property/ pci1; + }; +}; From f87175b30398bd93fa603e90e3a6028c4ea12caf Mon Sep 17 00:00:00 2001 From: John Audia Date: Wed, 31 Aug 2022 12:26:53 -0400 Subject: [PATCH 21/91] kernel: bump 5.15 to 5.15.64 All patches automatically rebased Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia --- include/kernel-5.15 | 4 ++-- ...0-0032-smsx95xx-fix-crimes-against-truesize.patch | 6 +++--- ...Experimental-Enable-turbo_mode-and-packetsi.patch | 4 ++-- ...034-Allow-mac-address-to-be-set-in-smsc95xx.patch | 12 ++++++------ ...035-cgroup-Disable-cgroup-memory-by-default.patch | 8 ++++---- ...-nft_flow_offload-handle-netdevice-events-f.patch | 2 +- ...net-mtk_eth_soc-implement-flow-offloading-t.patch | 4 ++-- .../650-netfilter-add-xt_FLOWOFFLOAD-target.patch | 4 ++-- .../hack-5.15/721-net-add-packet-mangeling.patch | 10 +++++----- ...net-usb-r8152-add-LED-configuration-from-OF.patch | 8 ++++---- .../linux/generic/hack-5.15/902-debloat_proc.patch | 2 +- .../680-NET-skip-GRO-for-foreign-MAC-addresses.patch | 2 +- ...net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch | 4 ++-- 13 files changed, 35 insertions(+), 35 deletions(-) diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 4ce0e0ccd8472d..672f5bc15e6475 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .63 -LINUX_KERNEL_HASH-5.15.63 = 6dd3cd1e5a629d0002bc6c6ec7e8ea96710104f38664122dd56c83dfd4eb7341 +LINUX_VERSION-5.15 = .64 +LINUX_KERNEL_HASH-5.15.64 = c6a1d38c6fa3798341372d5cf0088ae806ccdc827e31ecbff8988e097ba5de50 diff --git a/target/linux/bcm27xx/patches-5.15/950-0032-smsx95xx-fix-crimes-against-truesize.patch b/target/linux/bcm27xx/patches-5.15/950-0032-smsx95xx-fix-crimes-against-truesize.patch index 14e3bea9e262f1..0d8ba7eef89b8b 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0032-smsx95xx-fix-crimes-against-truesize.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0032-smsx95xx-fix-crimes-against-truesize.patch @@ -14,7 +14,7 @@ Signed-off-by: Steve Glendinning --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c -@@ -76,6 +76,10 @@ static bool turbo_mode = true; +@@ -67,6 +67,10 @@ static bool turbo_mode = true; module_param(turbo_mode, bool, 0644); MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); @@ -25,7 +25,7 @@ Signed-off-by: Steve Glendinning static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data, int in_pm) { -@@ -1860,7 +1864,8 @@ static int smsc95xx_rx_fixup(struct usbn +@@ -1837,7 +1841,8 @@ static int smsc95xx_rx_fixup(struct usbn if (dev->net->features & NETIF_F_RXCSUM) smsc95xx_rx_csum_offload(skb); skb_trim(skb, skb->len - 4); /* remove fcs */ @@ -35,7 +35,7 @@ Signed-off-by: Steve Glendinning return 1; } -@@ -1878,7 +1883,8 @@ static int smsc95xx_rx_fixup(struct usbn +@@ -1855,7 +1860,8 @@ static int smsc95xx_rx_fixup(struct usbn if (dev->net->features & NETIF_F_RXCSUM) smsc95xx_rx_csum_offload(ax_skb); skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ diff --git a/target/linux/bcm27xx/patches-5.15/950-0033-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch b/target/linux/bcm27xx/patches-5.15/950-0033-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch index 7a914d5738adec..fe9efa305cb9d4 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0033-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0033-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch @@ -11,7 +11,7 @@ See: http://forum.kodi.tv/showthread.php?tid=285288 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c -@@ -80,6 +80,10 @@ static bool truesize_mode = false; +@@ -71,6 +71,10 @@ static bool truesize_mode = false; module_param(truesize_mode, bool, 0644); MODULE_PARM_DESC(truesize_mode, "Report larger truesize value"); @@ -22,7 +22,7 @@ See: http://forum.kodi.tv/showthread.php?tid=285288 static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data, int in_pm) { -@@ -932,13 +936,13 @@ static int smsc95xx_reset(struct usbnet +@@ -915,13 +919,13 @@ static int smsc95xx_reset(struct usbnet if (!turbo_mode) { burst_cap = 0; diff --git a/target/linux/bcm27xx/patches-5.15/950-0034-Allow-mac-address-to-be-set-in-smsc95xx.patch b/target/linux/bcm27xx/patches-5.15/950-0034-Allow-mac-address-to-be-set-in-smsc95xx.patch index fe7d0257664747..2983a0f1f061f2 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0034-Allow-mac-address-to-be-set-in-smsc95xx.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0034-Allow-mac-address-to-be-set-in-smsc95xx.patch @@ -10,15 +10,15 @@ Signed-off-by: popcornmix --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c -@@ -52,6 +52,7 @@ +@@ -50,6 +50,7 @@ #define SUSPEND_SUSPEND3 (0x08) #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \ SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3) +#define MAC_ADDR_LEN (6) - #define SMSC95XX_NR_IRQS (1) /* raise to 12 for GPIOs */ - #define PHY_HWIRQ (SMSC95XX_NR_IRQS - 1) -@@ -84,6 +85,10 @@ static int packetsize = 2560; + struct smsc95xx_priv { + u32 mac_cr; +@@ -75,6 +76,10 @@ static int packetsize = 2560; module_param(packetsize, int, 0644); MODULE_PARM_DESC(packetsize, "Override the RX URB packet size"); @@ -29,7 +29,7 @@ Signed-off-by: popcornmix static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data, int in_pm) { -@@ -788,6 +793,53 @@ static int smsc95xx_ioctl(struct net_dev +@@ -771,6 +776,53 @@ static int smsc95xx_ioctl(struct net_dev return phy_mii_ioctl(netdev->phydev, rq, cmd); } @@ -83,7 +83,7 @@ Signed-off-by: popcornmix static void smsc95xx_init_mac_address(struct usbnet *dev) { /* maybe the boot loader passed the MAC address in devicetree */ -@@ -810,6 +862,10 @@ static void smsc95xx_init_mac_address(st +@@ -793,6 +845,10 @@ static void smsc95xx_init_mac_address(st } } diff --git a/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch b/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch index 85f909847bee96..a2f7e2170860ee 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0035-cgroup-Disable-cgroup-memory-by-default.patch @@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c -@@ -5833,6 +5833,9 @@ int __init cgroup_init_early(void) +@@ -5834,6 +5834,9 @@ int __init cgroup_init_early(void) return 0; } @@ -27,7 +27,7 @@ Signed-off-by: Phil Elwell /** * cgroup_init - cgroup initialization * -@@ -5871,6 +5874,12 @@ int __init cgroup_init(void) +@@ -5872,6 +5875,12 @@ int __init cgroup_init(void) mutex_unlock(&cgroup_mutex); @@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell for_each_subsys(ss, ssid) { if (ss->early_init) { struct cgroup_subsys_state *css = -@@ -6455,6 +6464,10 @@ static int __init cgroup_disable(char *s +@@ -6456,6 +6465,10 @@ static int __init cgroup_disable(char *s strcmp(token, ss->legacy_name)) continue; @@ -51,7 +51,7 @@ Signed-off-by: Phil Elwell static_branch_disable(cgroup_subsys_enabled_key[i]); pr_info("Disabling %s control group subsystem\n", ss->name); -@@ -6473,6 +6486,31 @@ static int __init cgroup_disable(char *s +@@ -6474,6 +6487,31 @@ static int __init cgroup_disable(char *s } __setup("cgroup_disable=", cgroup_disable); diff --git a/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch index 19ec9d94092947..488c6a8d92c7dd 100644 --- a/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch +++ b/target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch @@ -10,7 +10,7 @@ Signed-off-by: Pablo Neira Ayuso --- a/net/netfilter/nf_flow_table_core.c +++ b/net/netfilter/nf_flow_table_core.c -@@ -608,13 +608,41 @@ void nf_flow_table_free(struct nf_flowta +@@ -613,13 +613,41 @@ void nf_flow_table_free(struct nf_flowta } EXPORT_SYMBOL_GPL(nf_flow_table_free); diff --git a/target/linux/generic/backport-5.15/702-v5.19-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch b/target/linux/generic/backport-5.15/702-v5.19-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch index 28b32521049a82..2f93518e157ab0 100644 --- a/target/linux/generic/backport-5.15/702-v5.19-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch +++ b/target/linux/generic/backport-5.15/702-v5.19-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch @@ -233,7 +233,7 @@ Signed-off-by: Felix Fietkau static inline void --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -849,6 +849,7 @@ enum net_device_path_type { +@@ -863,6 +863,7 @@ enum net_device_path_type { DEV_PATH_BRIDGE, DEV_PATH_PPPOE, DEV_PATH_DSA, @@ -241,7 +241,7 @@ Signed-off-by: Felix Fietkau }; struct net_device_path { -@@ -874,6 +875,12 @@ struct net_device_path { +@@ -888,6 +889,12 @@ struct net_device_path { int port; u16 proto; } dsa; diff --git a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch index f826d65a815687..8769876c4db21b 100644 --- a/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch +++ b/target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch @@ -822,7 +822,7 @@ Signed-off-by: Felix Fietkau } +EXPORT_SYMBOL_GPL(nf_flow_table_iterate); - static void nf_flow_offload_work_gc(struct work_struct *work) + void nf_flow_table_gc_run(struct nf_flowtable *flow_table) { --- /dev/null +++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h @@ -846,7 +846,7 @@ Signed-off-by: Felix Fietkau +#endif /* _XT_FLOWOFFLOAD_H */ --- a/include/net/netfilter/nf_flow_table.h +++ b/include/net/netfilter/nf_flow_table.h -@@ -275,6 +275,11 @@ void nf_flow_table_free(struct nf_flowta +@@ -276,6 +276,11 @@ void nf_flow_table_free(struct nf_flowta void flow_offload_teardown(struct flow_offload *flow); diff --git a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch index d7c7c20feedc9a..eab1ed92e493cd 100644 --- a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch +++ b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch @@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -1655,6 +1655,10 @@ enum netdev_priv_flags { +@@ -1669,6 +1669,10 @@ enum netdev_priv_flags { IFF_TX_SKB_NO_LINEAR = BIT_ULL(31), }; @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN #define IFF_EBRIDGE IFF_EBRIDGE #define IFF_BONDING IFF_BONDING -@@ -1687,6 +1691,7 @@ enum netdev_priv_flags { +@@ -1701,6 +1705,7 @@ enum netdev_priv_flags { #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER #define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK #define IFF_TX_SKB_NO_LINEAR IFF_TX_SKB_NO_LINEAR @@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau /* Specifies the type of the struct net_device::ml_priv pointer */ enum netdev_ml_priv_type { -@@ -1988,6 +1993,7 @@ struct net_device { +@@ -2002,6 +2007,7 @@ struct net_device { /* Read-mostly cache-line for fast-path access */ unsigned int flags; unsigned int priv_flags; @@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau const struct net_device_ops *netdev_ops; int ifindex; unsigned short gflags; -@@ -2048,6 +2054,11 @@ struct net_device { +@@ -2062,6 +2068,11 @@ struct net_device { const struct tlsdev_ops *tlsdev_ops; #endif @@ -58,7 +58,7 @@ Signed-off-by: Felix Fietkau const struct header_ops *header_ops; unsigned char operstate; -@@ -2122,6 +2133,10 @@ struct net_device { +@@ -2136,6 +2147,10 @@ struct net_device { struct mctp_dev __rcu *mctp_ptr; #endif diff --git a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch index c315dcf8ff4822..c54332f71c4aa2 100644 --- a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,7 +22,7 @@ Signed-off-by: David Bauer #include #include #include -@@ -6864,6 +6865,22 @@ static void rtl_tally_reset(struct r8152 +@@ -6861,6 +6862,22 @@ static void rtl_tally_reset(struct r8152 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); } @@ -45,7 +45,7 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -6905,6 +6922,8 @@ static void r8152b_init(struct r8152 *tp +@@ -6902,6 +6919,8 @@ static void r8152b_init(struct r8152 *tp ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); @@ -54,7 +54,7 @@ Signed-off-by: David Bauer } static void r8153_init(struct r8152 *tp) -@@ -7045,6 +7064,8 @@ static void r8153_init(struct r8152 *tp) +@@ -7042,6 +7061,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -7127,6 +7148,8 @@ static void r8153b_init(struct r8152 *tp +@@ -7124,6 +7145,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ diff --git a/target/linux/generic/hack-5.15/902-debloat_proc.patch b/target/linux/generic/hack-5.15/902-debloat_proc.patch index 33d637f13eae91..c58370eff115e3 100644 --- a/target/linux/generic/hack-5.15/902-debloat_proc.patch +++ b/target/linux/generic/hack-5.15/902-debloat_proc.patch @@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/sock.c +++ b/net/core/sock.c -@@ -3855,6 +3855,8 @@ static __net_initdata struct pernet_oper +@@ -3857,6 +3857,8 @@ static __net_initdata struct pernet_oper static int __init proto_init(void) { diff --git a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch index 1910174b4210bf..1d5975f626f81d 100644 --- a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch +++ b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -2075,6 +2075,8 @@ struct net_device { +@@ -2089,6 +2089,8 @@ struct net_device { struct netdev_hw_addr_list mc; struct netdev_hw_addr_list dev_addrs; diff --git a/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch index 8825b07cdb5817..efc35712c8f2ca 100644 --- a/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch +++ b/target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch @@ -24,7 +24,7 @@ Reviewed-by: Grant Grundler --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -771,6 +771,16 @@ struct xps_map { +@@ -785,6 +785,16 @@ struct xps_map { #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \ - sizeof(struct xps_map)) / sizeof(u16)) @@ -41,7 +41,7 @@ Reviewed-by: Grant Grundler /* * This structure holds all XPS maps for device. Maps are indexed by CPU. * -@@ -1477,6 +1487,9 @@ struct net_device_ops { +@@ -1491,6 +1501,9 @@ struct net_device_ops { const struct sk_buff *skb, u16 rxq_index, u32 flow_id); From d51e990ff81ad0335294749e8d2fc8e69ceb9179 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 2 Sep 2022 17:07:40 +0200 Subject: [PATCH 22/91] bcm4908: use upstream patches for Asus GT-AC5300 LEDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Rafał Miłecki --- ...-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch} | 5 ++++- ...m64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch} | 5 ++++- ...arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch} | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) rename target/linux/bcm4908/patches-5.10/{130-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch => 038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch} (91%) rename target/linux/bcm4908/patches-5.10/{130-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch => 038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch} (78%) rename target/linux/bcm4908/patches-5.10/{130-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch => 038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch} (88%) diff --git a/target/linux/bcm4908/patches-5.10/130-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch similarity index 91% rename from target/linux/bcm4908/patches-5.10/130-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch rename to target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch index be1efcde86015e..437249f2cb33ae 100644 --- a/target/linux/bcm4908/patches-5.10/130-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch +++ b/target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch @@ -1,5 +1,6 @@ +From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 13:16:05 +0200 +Date: Mon, 18 Jul 2022 15:20:58 +0200 Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -8,6 +9,8 @@ Content-Transfer-Encoding: 8bit Include all 32 pins. Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com +Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/target/linux/bcm4908/patches-5.10/130-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch similarity index 78% rename from target/linux/bcm4908/patches-5.10/130-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch rename to target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch index 0ba37457986b83..c8903408934192 100644 --- a/target/linux/bcm4908/patches-5.10/130-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch +++ b/target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch @@ -1,5 +1,6 @@ +From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 13:17:57 +0200 +Date: Mon, 18 Jul 2022 15:20:59 +0200 Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -9,6 +10,8 @@ BCM4908 includes LEDs controller that supports multiple brightness levels & hardware blinking. Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com +Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/linux/bcm4908/patches-5.10/130-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch similarity index 88% rename from target/linux/bcm4908/patches-5.10/130-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch rename to target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch index 796395a017cda8..3888efb66bbff1 100644 --- a/target/linux/bcm4908/patches-5.10/130-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch +++ b/target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch @@ -1,5 +1,6 @@ +From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 13:21:54 +0200 +Date: Mon, 18 Jul 2022 15:21:00 +0200 Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -8,6 +9,8 @@ Content-Transfer-Encoding: 8bit There are 5 software-controllable LEDs on PCB. Signed-off-by: Rafał Miłecki +Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com +Signed-off-by: Florian Fainelli --- .../bcm4908/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) From 3d88f26d74f7771b808082cef541ed8286c40491 Mon Sep 17 00:00:00 2001 From: Ivan Pavlov Date: Wed, 31 Aug 2022 08:04:42 +0300 Subject: [PATCH 23/91] wolfssl: bump to 5.5.0 Remove upstreamed: 101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch Some low severity vulnerabilities fixed OpenVPN compatibility fixed (broken in 5.4.0) Other fixes && improvements Signed-off-by: Ivan Pavlov --- package/libs/wolfssl/Makefile | 4 ++-- .../patches/100-disable-hardening-check.patch | 2 +- ...prime-s-preprocessor-gating-to-match.patch | 23 ------------------- .../libs/wolfssl/patches/200-ecc-rng.patch | 4 ++-- 4 files changed, 5 insertions(+), 28 deletions(-) delete mode 100644 package/libs/wolfssl/patches/101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch diff --git a/package/libs/wolfssl/Makefile b/package/libs/wolfssl/Makefile index 4554bce5df1aa2..ee07081cfd8d17 100644 --- a/package/libs/wolfssl/Makefile +++ b/package/libs/wolfssl/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=wolfssl -PKG_VERSION:=5.4.0-stable +PKG_VERSION:=5.5.0-stable PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION) -PKG_HASH:=dc36cc19dad197253e5c2ecaa490c7eef579ad448706e55d73d79396e814098b +PKG_HASH:=c34b74b5f689fac7becb05583b044e84d3b10d39f38709f0095dd5d423ded67f PKG_FIXUP:=libtool libtool-abiver PKG_INSTALL:=1 diff --git a/package/libs/wolfssl/patches/100-disable-hardening-check.patch b/package/libs/wolfssl/patches/100-disable-hardening-check.patch index d3ad2e27bc3e35..01bb5974ba3385 100644 --- a/package/libs/wolfssl/patches/100-disable-hardening-check.patch +++ b/package/libs/wolfssl/patches/100-disable-hardening-check.patch @@ -1,6 +1,6 @@ --- a/wolfssl/wolfcrypt/settings.h +++ b/wolfssl/wolfcrypt/settings.h -@@ -2442,7 +2442,7 @@ extern void uITRON4_free(void *p) ; +@@ -2445,7 +2445,7 @@ extern void uITRON4_free(void *p) ; #endif /* warning for not using harden build options (default with ./configure) */ diff --git a/package/libs/wolfssl/patches/101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch b/package/libs/wolfssl/patches/101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch deleted file mode 100644 index 4b56c1568afe5c..00000000000000 --- a/package/libs/wolfssl/patches/101-update-sp_rand_prime-s-preprocessor-gating-to-match.patch +++ /dev/null @@ -1,23 +0,0 @@ -From dc92ec2aa9cb76b782bdba3fc5203267ebf39994 Mon Sep 17 00:00:00 2001 -From: Kareem -Date: Fri, 22 Jul 2022 11:07:46 -0700 -Subject: [PATCH] Update sp_rand_prime's preprocessor gating to match - wolfSSL_BN_generate_prime_ex's. - ---- - wolfcrypt/src/sp_int.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/wolfcrypt/src/sp_int.c -+++ b/wolfcrypt/src/sp_int.c -@@ -15647,8 +15647,8 @@ int sp_radix_size(sp_int* a, int radix, - * Prime number generation and checking. - ***************************************/ - --#if defined(WOLFSSL_KEY_GEN) && (!defined(NO_DH) || !defined(NO_DSA)) && \ -- !defined(WC_NO_RNG) -+#if defined(WOLFSSL_KEY_GEN) && (!defined(NO_RSA) || !defined(NO_DH) || \ -+ !defined(NO_DSA)) && !defined(WC_NO_RNG) - /* Generate a random prime for RSA only. - * - * @param [out] r SP integer to hold result. diff --git a/package/libs/wolfssl/patches/200-ecc-rng.patch b/package/libs/wolfssl/patches/200-ecc-rng.patch index 2e09e6d273e39e..d68ef7f3853a44 100644 --- a/package/libs/wolfssl/patches/200-ecc-rng.patch +++ b/package/libs/wolfssl/patches/200-ecc-rng.patch @@ -11,7 +11,7 @@ RNG regardless of the built settings for wolfssl. --- a/wolfcrypt/src/ecc.c +++ b/wolfcrypt/src/ecc.c -@@ -12288,21 +12288,21 @@ void wc_ecc_fp_free(void) +@@ -12348,21 +12348,21 @@ void wc_ecc_fp_free(void) #endif /* FP_ECC */ @@ -37,7 +37,7 @@ RNG regardless of the built settings for wolfssl. --- a/wolfssl/wolfcrypt/ecc.h +++ b/wolfssl/wolfcrypt/ecc.h -@@ -650,10 +650,8 @@ WOLFSSL_API +@@ -650,10 +650,8 @@ WOLFSSL_ABI WOLFSSL_API void wc_ecc_fp_free(void); WOLFSSL_LOCAL void wc_ecc_fp_init(void); From 728740fe7818ebd3264fcd98b78a0e12239e73aa Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 14:21:18 +0200 Subject: [PATCH 24/91] toolchain: gdb: update to 12.1 Release Notes: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=gdb/NEWS;hb=gdb-12.1-release Refreshed patch: - 120-fix-compile-flag-mismatch.patch Signed-off-by: Nick Hainke --- toolchain/gdb/Makefile | 4 ++-- toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/toolchain/gdb/Makefile b/toolchain/gdb/Makefile index 6ed3b190ce584e..d69217f6ca20c7 100644 --- a/toolchain/gdb/Makefile +++ b/toolchain/gdb/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=gdb -PKG_VERSION:=11.2 +PKG_VERSION:=12.1 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@GNU/gdb -PKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32 +PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed GDB_DIR:=$(PKG_NAME)-$(PKG_VERSION) HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(GDB_DIR) diff --git a/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch b/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch index 99c91a0304ed34..118bebe3c82bba 100644 --- a/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch +++ b/toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch @@ -1,6 +1,6 @@ --- a/gdbserver/configure +++ b/gdbserver/configure -@@ -2661,7 +2661,7 @@ $as_echo "$as_me: error: \`$ac_var' was +@@ -2664,7 +2664,7 @@ $as_echo "$as_me: error: \`$ac_var' was ac_cache_corrupted=: ;; ,);; *) From 392febc6f6925903d7367ed870cb97a711554bd5 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 27 Aug 2022 19:53:17 +0200 Subject: [PATCH 25/91] gdb: update to 12.1 Release Notes: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=gdb/NEWS;hb=gdb-12.1-release Refresh patches: - 110-shared_libgcc.patch - 130-gdb-ctrl-c.patch Signed-off-by: Nick Hainke --- package/devel/gdb/Makefile | 4 ++-- package/devel/gdb/patches/110-shared_libgcc.patch | 12 ++++++------ package/devel/gdb/patches/130-gdb-ctrl-c.patch | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/package/devel/gdb/Makefile b/package/devel/gdb/Makefile index dd1df7af8551f9..7acf26d60b9678 100644 --- a/package/devel/gdb/Makefile +++ b/package/devel/gdb/Makefile @@ -8,12 +8,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=gdb -PKG_VERSION:=11.2 +PKG_VERSION:=12.1 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=@GNU/gdb -PKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32 +PKG_HASH:=0e1793bf8f2b54d53f46dea84ccfd446f48f81b297b28c4f7fc017b818d69fed PKG_BUILD_PARALLEL:=1 PKG_INSTALL:=1 diff --git a/package/devel/gdb/patches/110-shared_libgcc.patch b/package/devel/gdb/patches/110-shared_libgcc.patch index 3979ccd26ba7cd..f1602bc69506e7 100644 --- a/package/devel/gdb/patches/110-shared_libgcc.patch +++ b/package/devel/gdb/patches/110-shared_libgcc.patch @@ -1,6 +1,6 @@ --- a/configure.ac +++ b/configure.ac -@@ -1300,13 +1300,13 @@ if test -z "$LD"; then +@@ -1314,13 +1314,13 @@ if test -z "$LD"; then fi fi @@ -17,7 +17,7 @@ AC_LANG_PUSH(C++) AC_LINK_IFELSE([AC_LANG_SOURCE([ #if (__GNUC__ < 4) || (__GNUC__ == 4 && __GNUC_MINOR__ < 5) -@@ -1705,7 +1705,7 @@ AC_ARG_WITH(stage1-ldflags, +@@ -1719,7 +1719,7 @@ AC_ARG_WITH(stage1-ldflags, # trust that they are doing what they want. if test "$with_static_standard_libraries" = yes -a "$stage1_libs" = "" \ -a "$have_static_libs" = yes; then @@ -26,7 +26,7 @@ fi]) AC_SUBST(stage1_ldflags) -@@ -1734,7 +1734,7 @@ AC_ARG_WITH(boot-ldflags, +@@ -1748,7 +1748,7 @@ AC_ARG_WITH(boot-ldflags, # statically. But if the user explicitly specified the libraries to # use, trust that they are doing what they want. if test "$poststage1_libs" = ""; then @@ -37,7 +37,7 @@ --- a/configure +++ b/configure -@@ -5257,14 +5257,14 @@ if test -z "$LD"; then +@@ -5275,14 +5275,14 @@ if test -z "$LD"; then fi fi @@ -56,7 +56,7 @@ ac_ext=cpp ac_cpp='$CXXCPP $CPPFLAGS' ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' -@@ -6149,7 +6149,7 @@ else +@@ -6167,7 +6167,7 @@ else # trust that they are doing what they want. if test "$with_static_standard_libraries" = yes -a "$stage1_libs" = "" \ -a "$have_static_libs" = yes; then @@ -65,7 +65,7 @@ fi fi -@@ -6185,7 +6185,7 @@ else +@@ -6203,7 +6203,7 @@ else # statically. But if the user explicitly specified the libraries to # use, trust that they are doing what they want. if test "$poststage1_libs" = ""; then diff --git a/package/devel/gdb/patches/130-gdb-ctrl-c.patch b/package/devel/gdb/patches/130-gdb-ctrl-c.patch index 72b7273434d20e..f793a71cae0222 100644 --- a/package/devel/gdb/patches/130-gdb-ctrl-c.patch +++ b/package/devel/gdb/patches/130-gdb-ctrl-c.patch @@ -24,7 +24,7 @@ Signed-off-by: Khem Raj --- a/gdbserver/linux-low.cc +++ b/gdbserver/linux-low.cc -@@ -5733,7 +5733,7 @@ linux_process_target::request_interrupt +@@ -5496,7 +5496,7 @@ linux_process_target::request_interrupt { /* Send a SIGINT to the process group. This acts just like the user typed a ^C on the controlling terminal. */ From 3a702f8733ff371f30e9e3ba1e1aed5f4686b6b4 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Tue, 30 Aug 2022 09:02:32 +0200 Subject: [PATCH 26/91] kernel: build crypto md5/sha1/sha256 modules for powerpc This builds and enables kernel optimized modules for mpc85xx target: - CONFIG_CRYPTO_MD5_PPC [1] - CONFIG_CRYPTO_SHA1_PPC_SPE [2] - CONFIG_CRYPTO_SHA256_PPC_SPE [3] Where it was possible, then use Signal Processing Engine, because CONFIG_SPE is already enabled in mpc85xx config. [1] https://cateee.net/lkddb/web-lkddb/CRYPTO_MD5_PPC.html [2] https://cateee.net/lkddb/web-lkddb/CRYPTO_SHA1_PPC.html [3] https://cateee.net/lkddb/web-lkddb/CRYPTO_SHA256_PPC_SPE.html Signed-off-by: Josef Schlehofer --- package/kernel/linux/modules/crypto.mk | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/crypto.mk b/package/kernel/linux/modules/crypto.mk index 5b52eacf109e60..35113e12d069ab 100644 --- a/package/kernel/linux/modules/crypto.mk +++ b/package/kernel/linux/modules/crypto.mk @@ -622,7 +622,8 @@ define KernelPackage/crypto-md5 DEPENDS:=+kmod-crypto-hash KCONFIG:= \ CONFIG_CRYPTO_MD5 \ - CONFIG_CRYPTO_MD5_OCTEON + CONFIG_CRYPTO_MD5_OCTEON \ + CONFIG_CRYPTO_MD5_PPC FILES:=$(LINUX_DIR)/crypto/md5.ko AUTOLOAD:=$(call AutoLoad,09,md5) $(call AddDepends/crypto) @@ -633,6 +634,11 @@ define KernelPackage/crypto-md5/octeon AUTOLOAD+=$(call AutoLoad,09,octeon-md5) endef +define KernelPackage/crypto-md5/mpc85xx + FILES+=$(LINUX_DIR)/arch/powerpc/crypto/md5-ppc.ko + AUTOLOAD+=$(call AutoLoad,09,md5-ppc) +endef + $(eval $(call KernelPackage,crypto-md5)) @@ -832,6 +838,7 @@ define KernelPackage/crypto-sha1 CONFIG_CRYPTO_SHA1_ARM \ CONFIG_CRYPTO_SHA1_ARM_NEON \ CONFIG_CRYPTO_SHA1_OCTEON \ + CONFIG_CRYPTO_SHA1_PPC_SPE \ CONFIG_CRYPTO_SHA1_SSSE3 FILES:=$(LINUX_DIR)/crypto/sha1_generic.ko AUTOLOAD:=$(call AutoLoad,09,sha1_generic) @@ -860,6 +867,11 @@ endef KernelPackage/crypto-sha1/tegra=$(KernelPackage/crypto-sha1/arm) +define KernelPackage/crypto-sha1/mpc85xx + FILES+=$(LINUX_DIR)/arch/powerpc/crypto/sha1-ppc-spe.ko + AUTOLOAD+=$(call AutoLoad,09,sha1-ppc-spe) +endef + define KernelPackage/crypto-sha1/x86/64 FILES+=$(LINUX_DIR)/arch/x86/crypto/sha1-ssse3.ko AUTOLOAD+=$(call AutoLoad,09,sha1-ssse3) @@ -874,6 +886,7 @@ define KernelPackage/crypto-sha256 KCONFIG:= \ CONFIG_CRYPTO_SHA256 \ CONFIG_CRYPTO_SHA256_OCTEON \ + CONFIG_CRYPTO_SHA256_PPC_SPE \ CONFIG_CRYPTO_SHA256_SSSE3 FILES:= \ $(LINUX_DIR)/crypto/sha256_generic.ko \ @@ -887,6 +900,11 @@ define KernelPackage/crypto-sha256/octeon AUTOLOAD+=$(call AutoLoad,09,octeon-sha256) endef +define KernelPackage/crypto-sha256/mpc85xx + FILES+=$(LINUX_DIR)/arch/powerpc/crypto/sha256-ppc-spe.ko + AUTOLOAD+=$(call AutoLoad,09,sha256-ppc-spe) +endef + define KernelPackage/crypto-sha256/x86/64 FILES+=$(LINUX_DIR)/arch/x86/crypto/sha256-ssse3.ko AUTOLOAD+=$(call AutoLoad,09,sha256-ssse3) From f1b5ed31432769ea5d585ecbca89908927388cf1 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 13:57:56 +0200 Subject: [PATCH 27/91] uboot-envtools: update to 2022.07 Update to latest version. Remove upstreamed patches: - 100-fw_env-make-flash_io-take-buffer-as-an-argument.patch - 101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch - 102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch Signed-off-by: Nick Hainke --- package/boot/uboot-envtools/Makefile | 4 +- ...-flash_io-take-buffer-as-an-argument.patch | 144 --------------- ...-logic-code-paths-in-the-fw_env_open.patch | 173 ------------------ ...llback-to-Linux-s-NVMEM-based-access.patch | 110 ----------- 4 files changed, 2 insertions(+), 429 deletions(-) delete mode 100644 package/boot/uboot-envtools/patches/100-fw_env-make-flash_io-take-buffer-as-an-argument.patch delete mode 100644 package/boot/uboot-envtools/patches/101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch delete mode 100644 package/boot/uboot-envtools/patches/102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile index 8bbe1eb9912960..6840b9c586be1b 100644 --- a/package/boot/uboot-envtools/Makefile +++ b/package/boot/uboot-envtools/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=uboot-envtools PKG_DISTNAME:=u-boot -PKG_VERSION:=2022.01 +PKG_VERSION:=2022.07 PKG_RELEASE:=$(AUTORELEASE) PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2 @@ -17,7 +17,7 @@ PKG_SOURCE_URL:= \ https://ftp.denx.de/pub/u-boot \ https://mirror.cyberbits.eu/u-boot \ ftp://ftp.denx.de/pub/u-boot -PKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413 +PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION) PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION) diff --git a/package/boot/uboot-envtools/patches/100-fw_env-make-flash_io-take-buffer-as-an-argument.patch b/package/boot/uboot-envtools/patches/100-fw_env-make-flash_io-take-buffer-as-an-argument.patch deleted file mode 100644 index c3b20edbdd60fb..00000000000000 --- a/package/boot/uboot-envtools/patches/100-fw_env-make-flash_io-take-buffer-as-an-argument.patch +++ /dev/null @@ -1,144 +0,0 @@ -From f178f7c9550c4fd9c644f79a1eb2dafa5bcdce25 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 12 Jan 2022 12:47:05 +0100 -Subject: [PATCH] fw_env: make flash_io() take buffer as an argument -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's usually easier to understand code & follow it if all arguments are -passed explicitly. Many coding styles also discourage using global -variables. - -Behaviour of flash_io() was a bit unintuitive as it was writing to a -buffer referenced in a global struct. That required developers to -remember how it works and sometimes required hacking "environment" -global struct variable to read data into a proper buffer. - -Signed-off-by: Rafał Miłecki ---- - tools/env/fw_env.c | 32 ++++++++++++++++---------------- - 1 file changed, 16 insertions(+), 16 deletions(-) - ---- a/tools/env/fw_env.c -+++ b/tools/env/fw_env.c -@@ -346,7 +346,7 @@ static int ubi_write(int fd, const void - return 0; - } - --static int flash_io(int mode); -+static int flash_io(int mode, void *buf, size_t count); - static int parse_config(struct env_opts *opts); - - #if defined(CONFIG_FILE) -@@ -516,7 +516,7 @@ int fw_env_flush(struct env_opts *opts) - *environment.crc = crc32(0, (uint8_t *) environment.data, ENV_SIZE); - - /* write environment back to flash */ -- if (flash_io(O_RDWR)) { -+ if (flash_io(O_RDWR, environment.image, CUR_ENVSIZE)) { - fprintf(stderr, "Error: can't write fw_env to flash\n"); - return -1; - } -@@ -1185,7 +1185,8 @@ static int flash_flag_obsolete(int dev, - return rc; - } - --static int flash_write(int fd_current, int fd_target, int dev_target) -+static int flash_write(int fd_current, int fd_target, int dev_target, void *buf, -+ size_t count) - { - int rc; - -@@ -1212,11 +1213,10 @@ static int flash_write(int fd_current, i - if (IS_UBI(dev_target)) { - if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0) - return -1; -- return ubi_write(fd_target, environment.image, CUR_ENVSIZE); -+ return ubi_write(fd_target, buf, count); - } - -- rc = flash_write_buf(dev_target, fd_target, environment.image, -- CUR_ENVSIZE); -+ rc = flash_write_buf(dev_target, fd_target, buf, count); - if (rc < 0) - return rc; - -@@ -1235,17 +1235,17 @@ static int flash_write(int fd_current, i - return 0; - } - --static int flash_read(int fd) -+static int flash_read(int fd, void *buf, size_t count) - { - int rc; - - if (IS_UBI(dev_current)) { - DEVTYPE(dev_current) = MTD_ABSENT; - -- return ubi_read(fd, environment.image, CUR_ENVSIZE); -+ return ubi_read(fd, buf, count); - } - -- rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE, -+ rc = flash_read_buf(dev_current, fd, buf, count, - DEVOFFSET(dev_current)); - if (rc != CUR_ENVSIZE) - return -1; -@@ -1291,7 +1291,7 @@ err: - return rc; - } - --static int flash_io_write(int fd_current) -+static int flash_io_write(int fd_current, void *buf, size_t count) - { - int fd_target = -1, rc, dev_target; - const char *dname, *target_temp = NULL; -@@ -1322,7 +1322,7 @@ static int flash_io_write(int fd_current - fd_target = fd_current; - } - -- rc = flash_write(fd_current, fd_target, dev_target); -+ rc = flash_write(fd_current, fd_target, dev_target, buf, count); - - if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) { - fprintf(stderr, -@@ -1377,7 +1377,7 @@ static int flash_io_write(int fd_current - return rc; - } - --static int flash_io(int mode) -+static int flash_io(int mode, void *buf, size_t count) - { - int fd_current, rc; - -@@ -1391,9 +1391,9 @@ static int flash_io(int mode) - } - - if (mode == O_RDWR) { -- rc = flash_io_write(fd_current); -+ rc = flash_io_write(fd_current, buf, count); - } else { -- rc = flash_read(fd_current); -+ rc = flash_read(fd_current, buf, count); - } - - if (close(fd_current)) { -@@ -1455,7 +1455,7 @@ int fw_env_open(struct env_opts *opts) - } - - dev_current = 0; -- if (flash_io(O_RDONLY)) { -+ if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) { - ret = -EIO; - goto open_cleanup; - } -@@ -1490,7 +1490,7 @@ int fw_env_open(struct env_opts *opts) - * other pointers in environment still point inside addr0 - */ - environment.image = addr1; -- if (flash_io(O_RDONLY)) { -+ if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) { - ret = -EIO; - goto open_cleanup; - } diff --git a/package/boot/uboot-envtools/patches/101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch b/package/boot/uboot-envtools/patches/101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch deleted file mode 100644 index dbb71bd4337d22..00000000000000 --- a/package/boot/uboot-envtools/patches/101-fw_env-simplify-logic-code-paths-in-the-fw_env_open.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 07c79dd5fdeaefb39c9e7a97f3b66de63109a18d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 12 Jan 2022 12:47:06 +0100 -Subject: [PATCH] fw_env: simplify logic & code paths in the fw_env_open() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Environment variables can be stored in two formats: -1. Single entry with header containing CRC32 -2. Two entries with extra flags field in each entry header - -For that reason fw_env_open() has two main code paths and there are -pointers for CRC32/flags/data. - -Previous implementation was a bit hard to follow: -1. It was checking for used format twice (in reversed order each time) -2. It was setting "environment" global struct fields to some temporary - values that required extra comments explaining it - -This change simplifies that code: -1. It introduces two clear code paths -2. It sets "environment" global struct fields values only once it really - knows them - -To be fair there are *two* crc32() calls now and an extra pointer -variable but that should be cheap enough and worth it. - -Signed-off-by: Rafał Miłecki ---- - tools/env/fw_env.c | 77 +++++++++++++++++++--------------------------- - 1 file changed, 31 insertions(+), 46 deletions(-) - ---- a/tools/env/fw_env.c -+++ b/tools/env/fw_env.c -@@ -1421,9 +1421,6 @@ int fw_env_open(struct env_opts *opts) - - int ret; - -- struct env_image_single *single; -- struct env_image_redundant *redundant; -- - if (!opts) - opts = &default_opts; - -@@ -1439,40 +1436,37 @@ int fw_env_open(struct env_opts *opts) - goto open_cleanup; - } - -- /* read environment from FLASH to local buffer */ -- environment.image = addr0; -- -- if (have_redund_env) { -- redundant = addr0; -- environment.crc = &redundant->crc; -- environment.flags = &redundant->flags; -- environment.data = redundant->data; -- } else { -- single = addr0; -- environment.crc = &single->crc; -- environment.flags = NULL; -- environment.data = single->data; -- } -- - dev_current = 0; -- if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) { -+ if (flash_io(O_RDONLY, addr0, CUR_ENVSIZE)) { - ret = -EIO; - goto open_cleanup; - } - -- crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE); -- -- crc0_ok = (crc0 == *environment.crc); - if (!have_redund_env) { -+ struct env_image_single *single = addr0; -+ -+ crc0 = crc32(0, (uint8_t *)single->data, ENV_SIZE); -+ crc0_ok = (crc0 == single->crc); - if (!crc0_ok) { - fprintf(stderr, - "Warning: Bad CRC, using default environment\n"); -- memcpy(environment.data, default_environment, -+ memcpy(single->data, default_environment, - sizeof(default_environment)); - environment.dirty = 1; - } -+ -+ environment.image = addr0; -+ environment.crc = &single->crc; -+ environment.flags = NULL; -+ environment.data = single->data; - } else { -- flag0 = *environment.flags; -+ struct env_image_redundant *redundant0 = addr0; -+ struct env_image_redundant *redundant1; -+ -+ crc0 = crc32(0, (uint8_t *)redundant0->data, ENV_SIZE); -+ crc0_ok = (crc0 == redundant0->crc); -+ -+ flag0 = redundant0->flags; - - dev_current = 1; - addr1 = calloc(1, CUR_ENVSIZE); -@@ -1483,14 +1477,9 @@ int fw_env_open(struct env_opts *opts) - ret = -ENOMEM; - goto open_cleanup; - } -- redundant = addr1; -+ redundant1 = addr1; - -- /* -- * have to set environment.image for flash_read(), careful - -- * other pointers in environment still point inside addr0 -- */ -- environment.image = addr1; -- if (flash_io(O_RDONLY, environment.image, CUR_ENVSIZE)) { -+ if (flash_io(O_RDONLY, addr1, CUR_ENVSIZE)) { - ret = -EIO; - goto open_cleanup; - } -@@ -1518,18 +1507,12 @@ int fw_env_open(struct env_opts *opts) - goto open_cleanup; - } - -- crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE); -+ crc1 = crc32(0, (uint8_t *)redundant1->data, ENV_SIZE); - -- crc1_ok = (crc1 == redundant->crc); -- flag1 = redundant->flags; -+ crc1_ok = (crc1 == redundant1->crc); -+ flag1 = redundant1->flags; - -- /* -- * environment.data still points to ((struct -- * env_image_redundant *)addr0)->data. If the two -- * environments differ, or one has bad crc, force a -- * write-out by marking the environment dirty. -- */ -- if (memcmp(environment.data, redundant->data, ENV_SIZE) || -+ if (memcmp(redundant0->data, redundant1->data, ENV_SIZE) || - !crc0_ok || !crc1_ok) - environment.dirty = 1; - -@@ -1540,7 +1523,7 @@ int fw_env_open(struct env_opts *opts) - } else if (!crc0_ok && !crc1_ok) { - fprintf(stderr, - "Warning: Bad CRC, using default environment\n"); -- memcpy(environment.data, default_environment, -+ memcpy(redundant0->data, default_environment, - sizeof(default_environment)); - environment.dirty = 1; - dev_current = 0; -@@ -1586,13 +1569,15 @@ int fw_env_open(struct env_opts *opts) - */ - if (dev_current) { - environment.image = addr1; -- environment.crc = &redundant->crc; -- environment.flags = &redundant->flags; -- environment.data = redundant->data; -+ environment.crc = &redundant1->crc; -+ environment.flags = &redundant1->flags; -+ environment.data = redundant1->data; - free(addr0); - } else { - environment.image = addr0; -- /* Other pointers are already set */ -+ environment.crc = &redundant0->crc; -+ environment.flags = &redundant0->flags; -+ environment.data = redundant0->data; - free(addr1); - } - #ifdef DEBUG diff --git a/package/boot/uboot-envtools/patches/102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch b/package/boot/uboot-envtools/patches/102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch deleted file mode 100644 index da17350b40a3ec..00000000000000 --- a/package/boot/uboot-envtools/patches/102-fw_env-add-fallback-to-Linux-s-NVMEM-based-access.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 8142c4554ffaa927529f24427a35f7ee2861793a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Jun 2022 20:59:03 +0200 -Subject: [PATCH] fw_env: add fallback to Linux's NVMEM based access -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -A new DT binding for describing environment data block has been added in -Linux's commit 5db1c2dbc04c ("dt-bindings: nvmem: add U-Boot environment -variables binding"). Once we get a proper Linux NVMEM driver it'll be -possible to use Linux's binary interface for user-space as documented -in the: -https://www.kernel.org/doc/html/latest/driver-api/nvmem.html - -This commits makes fw_env fallback to looking for a compatible NVMEM -device in case config file isn't present. In a long term this may make -config files redundant and avoid code (info) duplication. - -Signed-off-by: Rafał Miłecki ---- - tools/env/fw_env.c | 70 ++++++++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 67 insertions(+), 3 deletions(-) - ---- a/tools/env/fw_env.c -+++ b/tools/env/fw_env.c -@@ -1713,6 +1713,67 @@ static int check_device_config(int dev) - return rc; - } - -+static int find_nvmem_device(void) -+{ -+ const char *path = "/sys/bus/nvmem/devices"; -+ struct dirent *dent; -+ char *nvmem = NULL; -+ char comp[256]; -+ char buf[32]; -+ int bytes; -+ DIR *dir; -+ -+ dir = opendir(path); -+ if (!dir) { -+ return -EIO; -+ } -+ -+ while (!nvmem && (dent = readdir(dir))) { -+ FILE *fp; -+ -+ if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) { -+ continue; -+ } -+ -+ bytes = snprintf(comp, sizeof(comp), "%s/%s/of_node/compatible", path, dent->d_name); -+ if (bytes < 0 || bytes == sizeof(comp)) { -+ continue; -+ } -+ -+ fp = fopen(comp, "r"); -+ if (!fp) { -+ continue; -+ } -+ -+ fread(buf, sizeof(buf), 1, fp); -+ -+ if (!strcmp(buf, "u-boot,env")) { -+ bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name); -+ if (bytes < 0) { -+ nvmem = NULL; -+ } -+ } -+ -+ fclose(fp); -+ } -+ -+ closedir(dir); -+ -+ if (nvmem) { -+ struct stat s; -+ -+ stat(nvmem, &s); -+ -+ DEVNAME(0) = nvmem; -+ DEVOFFSET(0) = 0; -+ ENVSIZE(0) = s.st_size; -+ -+ return 0; -+ } -+ -+ return -ENOENT; -+} -+ - static int parse_config(struct env_opts *opts) - { - int rc; -@@ -1723,9 +1784,12 @@ static int parse_config(struct env_opts - #if defined(CONFIG_FILE) - /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ - if (get_config(opts->config_file)) { -- fprintf(stderr, "Cannot parse config file '%s': %m\n", -- opts->config_file); -- return -1; -+ if (find_nvmem_device()) { -+ fprintf(stderr, "Cannot parse config file '%s': %m\n", -+ opts->config_file); -+ fprintf(stderr, "Failed to find NVMEM device\n"); -+ return -1; -+ } - } - #else - DEVNAME(0) = DEVICE1_NAME; From be555b9dd8618b8da68c42ae8dda493337519838 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 3 Sep 2022 02:24:14 +0100 Subject: [PATCH 28/91] mediatek: mt7622: fix DTS compatible of UniFi 6 LR variants Make sure the compatible string in DTS matches the now v1/v2 differentiated board name in target/linux/mediatek/image/mt7622.mk. Signed-off-by: Daniel Golle --- .../linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts | 2 +- target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts | 2 +- .../linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts index a22bc7018077dc..5b1fd1d9ba82da 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts @@ -4,7 +4,7 @@ / { model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)"; - compatible = "ubnt,unifi-6-lr-ubootmod", "mediatek,mt7622"; + compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622"; }; &nor_partitions { diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts index d0048d47158bc4..95f19af4cd9b69 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts @@ -4,7 +4,7 @@ / { model = "Ubiquiti UniFi 6 LR v1"; - compatible = "ubnt,unifi-6-lr", "mediatek,mt7622"; + compatible = "ubnt,unifi-6-lr-v1", "mediatek,mt7622"; }; &nor_partitions { diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts index 711d58d0e55bea..6a7b6868ce3787 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts @@ -4,7 +4,7 @@ / { model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)"; - compatible = "ubnt,unifi-6-lr-ubootmod-v2", "mediatek,mt7622"; + compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622"; }; &nor_partitions { From b8f8c6f2dd8d47216117cb5b78184531ab21dddd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sat, 3 Sep 2022 20:41:00 +0200 Subject: [PATCH 29/91] bcm4908: fix Asus GT-AX6000 image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. Include Linux DTB 2. Add 50991 variant (seems to differ by 1 PHY we don't support yet) Signed-off-by: Rafał Miłecki --- target/linux/bcm4908/config-5.10 | 1 + target/linux/bcm4908/image/bootfs-bcm4912.its | 35 +++++++++++++++++-- ...bcmbca-add-arch-bcmbca-machine-entry.patch | 31 ++++++++++++++++ 3 files changed, 65 insertions(+), 2 deletions(-) create mode 100644 target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch diff --git a/target/linux/bcm4908/config-5.10 b/target/linux/bcm4908/config-5.10 index 866fbaf105f162..4009f80038624a 100644 --- a/target/linux/bcm4908/config-5.10 +++ b/target/linux/bcm4908/config-5.10 @@ -1,5 +1,6 @@ CONFIG_64BIT=y CONFIG_ARCH_BCM4908=y +CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_ARCH_MMAP_RND_BITS=18 diff --git a/target/linux/bcm4908/image/bootfs-bcm4912.its b/target/linux/bcm4908/image/bootfs-bcm4912.its index 6f4548956c57cc..3d671f9d00ce14 100644 --- a/target/linux/bcm4908/image/bootfs-bcm4912.its +++ b/target/linux/bcm4908/image/bootfs-bcm4912.its @@ -12,9 +12,22 @@ data = /incbin/("${images_dir}/u-boot/u-boot-bcm4912.dtb"); }; - fdt_GTAX6000 { + fdt_uboot_GTAX6000 { description = "dtb"; data = /incbin/("${images_dir}/u-boot/GTAX6000.dtb"); + arch = "arm64"; + type = "flat_dt"; + compression = "none"; + + hash-1 { + algo = "sha256"; + }; + }; + + fdt_linux_GTAX6000 { + description = "dtb"; + data = /incbin/("${dts_dir}/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dtb"); + arch = "arm64"; type = "flat_dt"; compression = "none"; @@ -27,8 +40,26 @@ configurations { conf_ub_GTAX6000 { description = "GTAX6000"; - fdt = "fdt_GTAX6000"; + fdt = "fdt_uboot_GTAX6000"; + loadables = "atf", "uboot"; + }; + + conf_lx_GTAX6000 { + description = "BRCM 63xxx linux"; + kernel = "kernel"; + fdt = "fdt_linux_GTAX6000"; + }; + + conf_ub_GTAX6000_50991 { + description = "GTAX6000_50991"; + fdt = "fdt_uboot_GTAX6000"; loadables = "atf", "uboot"; }; + + conf_lx_GTAX6000_50991 { + description = "BRCM 63xxx linux"; + kernel = "kernel"; + fdt = "fdt_linux_GTAX6000"; + }; }; }; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch new file mode 100644 index 00000000000000..1b9a32e30ac9ca --- /dev/null +++ b/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch @@ -0,0 +1,31 @@ +From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001 +From: William Zhang +Date: Wed, 1 Jun 2022 15:56:50 -0700 +Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry + +Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets + +Signed-off-by: William Zhang +Signed-off-by: Florian Fainelli +--- + arch/arm64/Kconfig.platforms | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -59,6 +59,15 @@ config ARCH_BCM_IPROC + help + This enables support for Broadcom iProc based SoCs + ++config ARCH_BCMBCA ++ bool "Broadcom Broadband SoC" ++ help ++ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based ++ BCA chipset. ++ ++ This enables support for Broadcom BCA ARM-based broadband chipsets, ++ including the DSL, PON and Wireless family of chips. ++ + config ARCH_BERLIN + bool "Marvell Berlin SoC Family" + select DW_APB_ICTL From f1802b0db7e22f98e1718e2c8bec29b2842f5aea Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Sun, 4 Sep 2022 20:21:11 +0200 Subject: [PATCH 30/91] realtek: replace fix for spurious GPIO interrupts 8 and 16 bit writes to the GPIO peripheral are apparently not supported, and only worked most of the time. This resulted in garbabe writes to the interrupt mask registers, causing spurious unhandled interrupts, which could lead to CPU lock-ups as these kept retriggering. Instead of clearing these spurious interrupt when they occur, the upstream patch will just make sure all register writes have the intended result, so these don't happen at all. Signed-off-by: Sander Vanheule --- ...ealtek-otto-clear-spurious-interrups.patch | 30 -- ...io-realtek-otto-switch-to-32-bit-I-O.patch | 373 ++++++++++++++++++ 2 files changed, 373 insertions(+), 30 deletions(-) delete mode 100644 target/linux/realtek/patches-5.10/317-gpio-realtek-otto-clear-spurious-interrups.patch create mode 100644 target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch diff --git a/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-clear-spurious-interrups.patch b/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-clear-spurious-interrups.patch deleted file mode 100644 index 6e5957d13e1c8e..00000000000000 --- a/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-clear-spurious-interrups.patch +++ /dev/null @@ -1,30 +0,0 @@ -realtek: clear spurious GPIO interrupts - -The interrupt controller in the internal GPIO peripheral will sometimes -generate spurious interrupts. If these are not properly acknowledged, the -system will be held busy until reboot. These spurious interrupts are identified -by the fact that there is no system IRQ number associated, since the interrupt -line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have -also displayed this behaviour. - -Reported-by: Luiz Angelo Daros de Luca # DGS-1210-52 -Reported-by: Birger Koblitz # Netgear GS724TP v2 -Reported-by: Jan Hoffmann # HPE 1920-16G -Signed-off-by: Sander Vanheule ---- - drivers/gpio/gpio-realtek-otto.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -251,6 +251,10 @@ static void realtek_gpio_irq_handler(str - port_pin_count = min(gc->ngpio - lines_done, 8U); - for_each_set_bit(offset, &status, port_pin_count) { - irq = irq_find_mapping(gc->irq.domain, offset + lines_done); -+ if (unlikely(!irq)) { -+ realtek_gpio_clear_isr(ctrl, lines_done / 8, BIT(offset)); -+ continue; -+ } - generic_handle_irq(irq); - } - } diff --git a/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch b/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch new file mode 100644 index 00000000000000..9c043b71269e65 --- /dev/null +++ b/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch @@ -0,0 +1,373 @@ +From ee0175b3b44288c74d5292c2a9c2c154f6c0317e Mon Sep 17 00:00:00 2001 +From: Sander Vanheule +Date: Sun, 7 Aug 2022 21:21:15 +0200 +Subject: [PATCH] gpio: realtek-otto: switch to 32-bit I/O + +By using 16-bit I/O on the GPIO peripheral, which is apparently not safe +on MIPS, the IMR can end up containing garbage. This then results in +interrupt triggers for lines that don't have an interrupt handler +associated. The irq_desc lookup fails, and the ISR will not be cleared, +keeping the CPU busy until reboot, or until another IMR operation +restores the correct value. This situation appears to happen very +rarely, for < 0.5% of IMR writes. + +Instead of using 8-bit or 16-bit I/O operations on the 32-bit memory +mapped peripheral registers, switch to using 32-bit I/O only, operating +on the entire bank for all single bit line settings. For 2-bit line +settings, with 16-bit port values, stick to manual (un)packing. + +This issue has been seen on RTL8382M (HPE 1920-16G), RTL8391M (Netgear +GS728TP v2), and RTL8393M (D-Link DGS-1210-52 F3, Zyxel GS1900-48). + +Reported-by: Luiz Angelo Daros de Luca # DGS-1210-52 +Reported-by: Birger Koblitz # GS728TP +Reported-by: Jan Hoffmann # 1920-16G +Fixes: 0d82fb1127fb ("gpio: Add Realtek Otto GPIO support") +Signed-off-by: Sander Vanheule +Cc: Paul Cercueil +Reviewed-by: Linus Walleij +Signed-off-by: Bartosz Golaszewski + +Update patch for missing upstream changes: + - commit a01a40e33499 ("gpio: realtek-otto: Make the irqchip immutable") + - commit dbd1c54fc820 ("gpio: Bulk conversion to generic_handle_domain_irq()") +Signed-off-by: Sander Vanheule + +--- + drivers/gpio/gpio-realtek-otto.c | 166 ++++++++++++++++--------------- + 1 file changed, 85 insertions(+), 81 deletions(-) + +--- a/drivers/gpio/gpio-realtek-otto.c ++++ b/drivers/gpio/gpio-realtek-otto.c +@@ -46,10 +46,20 @@ + * @lock: Lock for accessing the IRQ registers and values + * @intr_mask: Mask for interrupts lines + * @intr_type: Interrupt type selection ++ * @bank_read: Read a bank setting as a single 32-bit value ++ * @bank_write: Write a bank setting as a single 32-bit value ++ * @imr_line_pos: Bit shift of an IRQ line's IMR value. ++ * ++ * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed ++ * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign) ++ * a value from (to) these registers. The IMR register consists of four 16-bit ++ * port values, packed into two 32-bit registers. Use @imr_line_pos to get the ++ * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than ++ * 32 overflow into the second register. + * + * Because the interrupt mask register (IMR) combines the function of IRQ type + * selection and masking, two extra values are stored. @intr_mask is used to +- * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store ++ * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store + * the selected interrupt types. The logical AND of these values is written to + * IMR on changes. + */ +@@ -59,10 +69,11 @@ struct realtek_gpio_ctrl { + void __iomem *cpumask_base; + struct cpumask cpu_irq_maskable; + raw_spinlock_t lock; +- u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; +- u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; +- unsigned int (*port_offset_u8)(unsigned int port); +- unsigned int (*port_offset_u16)(unsigned int port); ++ u8 intr_mask[REALTEK_GPIO_MAX]; ++ u8 intr_type[REALTEK_GPIO_MAX]; ++ u32 (*bank_read)(void __iomem *reg); ++ void (*bank_write)(void __iomem *reg, u32 value); ++ unsigned int (*line_imr_pos)(unsigned int line); + }; + + /* Expand with more flags as devices with other quirks are added */ +@@ -101,14 +112,22 @@ static struct realtek_gpio_ctrl *irq_dat + * port. The two interrupt mask registers store two bits per GPIO, so use u16 + * values. + */ +-static unsigned int realtek_gpio_port_offset_u8(unsigned int port) ++static u32 realtek_gpio_bank_read_swapped(void __iomem *reg) ++{ ++ return ioread32be(reg); ++} ++ ++static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value) + { +- return port; ++ iowrite32be(value, reg); + } + +-static unsigned int realtek_gpio_port_offset_u16(unsigned int port) ++static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line) + { +- return 2 * port; ++ unsigned int port_pin = line % 8; ++ unsigned int port = line / 8; ++ ++ return 2 * (8 * (port ^ 1) + port_pin); + } + + /* +@@ -119,64 +138,65 @@ static unsigned int realtek_gpio_port_of + * per GPIO, so use u16 values. The first register contains ports 1 and 0, the + * second ports 3 and 2. + */ +-static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) ++static u32 realtek_gpio_bank_read(void __iomem *reg) + { +- return 3 - port; ++ return ioread32(reg); + } + +-static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) ++static void realtek_gpio_bank_write(void __iomem *reg, u32 value) + { +- return 2 * (port ^ 1); ++ iowrite32(value, reg); + } + +-static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, +- unsigned int port, u16 irq_type, u16 irq_mask) ++static unsigned int realtek_gpio_line_imr_pos(unsigned int line) + { +- iowrite16(irq_type & irq_mask, +- ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); ++ return 2 * line; + } + +-static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, +- unsigned int port, u8 mask) ++static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask) + { +- iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); ++ ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask); + } + +-static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) ++static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl) + { +- return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); ++ return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR); + } + +-/* Set the rising and falling edge mask bits for a GPIO port pin */ +-static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) ++/* Set the rising and falling edge mask bits for a GPIO pin */ ++static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line) + { +- return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; ++ void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR; ++ unsigned int line_shift = ctrl->line_imr_pos(line); ++ unsigned int shift = line_shift % 32; ++ u32 irq_type = ctrl->intr_type[line]; ++ u32 irq_mask = ctrl->intr_mask[line]; ++ u32 reg_val; ++ ++ reg += 4 * (line_shift / 32); ++ reg_val = ioread32(reg); ++ reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift); ++ reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift; ++ iowrite32(reg_val, reg); + } + + static void realtek_gpio_irq_ack(struct irq_data *data) + { + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + irq_hw_number_t line = irqd_to_hwirq(data); +- unsigned int port = line / 8; +- unsigned int port_pin = line % 8; + +- realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); ++ realtek_gpio_clear_isr(ctrl, BIT(line)); + } + + static void realtek_gpio_irq_unmask(struct irq_data *data) + { + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + unsigned int line = irqd_to_hwirq(data); +- unsigned int port = line / 8; +- unsigned int port_pin = line % 8; + unsigned long flags; +- u16 m; + + raw_spin_lock_irqsave(&ctrl->lock, flags); +- m = ctrl->intr_mask[port]; +- m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); +- ctrl->intr_mask[port] = m; +- realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); ++ ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; ++ realtek_gpio_update_line_imr(ctrl, line); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); + } + +@@ -184,16 +204,11 @@ static void realtek_gpio_irq_mask(struct + { + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + unsigned int line = irqd_to_hwirq(data); +- unsigned int port = line / 8; +- unsigned int port_pin = line % 8; + unsigned long flags; +- u16 m; + + raw_spin_lock_irqsave(&ctrl->lock, flags); +- m = ctrl->intr_mask[port]; +- m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); +- ctrl->intr_mask[port] = m; +- realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); ++ ctrl->intr_mask[line] = 0; ++ realtek_gpio_update_line_imr(ctrl, line); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); + } + +@@ -201,10 +216,8 @@ static int realtek_gpio_irq_set_type(str + { + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + unsigned int line = irqd_to_hwirq(data); +- unsigned int port = line / 8; +- unsigned int port_pin = line % 8; + unsigned long flags; +- u16 type, t; ++ u8 type; + + switch (flow_type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: +@@ -223,11 +236,8 @@ static int realtek_gpio_irq_set_type(str + irq_set_handler_locked(data, handle_edge_irq); + + raw_spin_lock_irqsave(&ctrl->lock, flags); +- t = ctrl->intr_type[port]; +- t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); +- t |= realtek_gpio_imr_bits(port_pin, type); +- ctrl->intr_type[port] = t; +- realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); ++ ctrl->intr_type[line] = type; ++ realtek_gpio_update_line_imr(ctrl, line); + raw_spin_unlock_irqrestore(&ctrl->lock, flags); + + return 0; +@@ -238,31 +248,24 @@ static void realtek_gpio_irq_handler(str + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); + struct irq_chip *irq_chip = irq_desc_get_chip(desc); +- unsigned int lines_done; +- unsigned int port_pin_count; + unsigned int irq; + unsigned long status; + int offset; + + chained_irq_enter(irq_chip, desc); + +- for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { +- status = realtek_gpio_read_isr(ctrl, lines_done / 8); +- port_pin_count = min(gc->ngpio - lines_done, 8U); +- for_each_set_bit(offset, &status, port_pin_count) { +- irq = irq_find_mapping(gc->irq.domain, offset + lines_done); +- generic_handle_irq(irq); +- } ++ status = realtek_gpio_read_isr(ctrl); ++ for_each_set_bit(offset, &status, gc->ngpio) { ++ irq = irq_find_mapping(gc->irq.domain, offset); ++ generic_handle_irq(irq); + } + + chained_irq_exit(irq_chip, desc); + } + +-static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, +- unsigned int port, int cpu) ++static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu) + { +- return ctrl->cpumask_base + ctrl->port_offset_u8(port) + +- REALTEK_GPIO_PORTS_PER_BANK * cpu; ++ return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu; + } + + static int realtek_gpio_irq_set_affinity(struct irq_data *data, +@@ -270,12 +273,10 @@ static int realtek_gpio_irq_set_affinity + { + struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); + unsigned int line = irqd_to_hwirq(data); +- unsigned int port = line / 8; +- unsigned int port_pin = line % 8; + void __iomem *irq_cpu_mask; + unsigned long flags; + int cpu; +- u8 v; ++ u32 v; + + if (!ctrl->cpumask_base) + return -ENXIO; +@@ -283,15 +284,15 @@ static int realtek_gpio_irq_set_affinity + raw_spin_lock_irqsave(&ctrl->lock, flags); + + for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { +- irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); +- v = ioread8(irq_cpu_mask); ++ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); ++ v = ctrl->bank_read(irq_cpu_mask); + + if (cpumask_test_cpu(cpu, dest)) +- v |= BIT(port_pin); ++ v |= BIT(line); + else +- v &= ~BIT(port_pin); ++ v &= ~BIT(line); + +- iowrite8(v, irq_cpu_mask); ++ ctrl->bank_write(irq_cpu_mask, v); + } + + raw_spin_unlock_irqrestore(&ctrl->lock, flags); +@@ -305,22 +306,23 @@ static int realtek_gpio_irq_init(struct + { + struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); + void __iomem *irq_cpu_mask; +- unsigned int port; ++ u32 mask_all = GENMASK(gc->ngpio - 1, 0); ++ unsigned int line; + int cpu; + +- for (port = 0; (port * 8) < gc->ngpio; port++) { +- realtek_gpio_write_imr(ctrl, port, 0, 0); +- realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); +- +- /* +- * Uniprocessor builds assume a mask always contains one CPU, +- * so only start the loop if we have at least one maskable CPU. +- */ +- if(!cpumask_empty(&ctrl->cpu_irq_maskable)) { +- for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { +- irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); +- iowrite8(GENMASK(7, 0), irq_cpu_mask); +- } ++ for (line = 0; line < gc->ngpio; line++) ++ realtek_gpio_update_line_imr(ctrl, line); ++ ++ realtek_gpio_clear_isr(ctrl, mask_all); ++ ++ /* ++ * Uniprocessor builds assume a mask always contains one CPU, ++ * so only start the loop if we have at least one maskable CPU. ++ */ ++ if(!cpumask_empty(&ctrl->cpu_irq_maskable)) { ++ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { ++ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); ++ ctrl->bank_write(irq_cpu_mask, mask_all); + } + } + +@@ -393,12 +395,14 @@ static int realtek_gpio_probe(struct pla + + if (dev_flags & GPIO_PORTS_REVERSED) { + bgpio_flags = 0; +- ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; +- ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; ++ ctrl->bank_read = realtek_gpio_bank_read; ++ ctrl->bank_write = realtek_gpio_bank_write; ++ ctrl->line_imr_pos = realtek_gpio_line_imr_pos; + } else { + bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; +- ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; +- ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; ++ ctrl->bank_read = realtek_gpio_bank_read_swapped; ++ ctrl->bank_write = realtek_gpio_bank_write_swapped; ++ ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; + } + + err = bgpio_init(&ctrl->gc, dev, 4, From f32085fc0b87049491b07e198d924d738a1a2834 Mon Sep 17 00:00:00 2001 From: Daniel Danzberger Date: Wed, 3 Aug 2022 17:31:03 +0200 Subject: [PATCH 31/91] airoha: Add new target platform Airoha is a new ARM platform based on Cortex-A53 which has recently been merged into linux-next. Due to BootROM limitations on this platform, the Cortex-A53 can't run in Aarch64 mode and code must be compiled for 32-Bit ARM. This support is based mostly on those linux-next commits backported for kernel 5.15. Patches: 1 - platform support = linux-next 2 - clock driver = linux-next 3 - gpio driver = linux-next 4 - linux,usable-memory-range dts support = linux-next 5 - mtd spinand driver 6 - spi driver 7 - pci driver (kconfig only, uses mediatek PCI) = linux-next Still missing: - Ethernet driver - Sysupgrade support A.t.m there exists one subtarget EN7523 with only one evaluation board. The initramfs can be run with the following commands from u-boot: - u-boot> setenv bootfile \ openwrt-airoha-airoha_en7523-evb-initramfs-kernel.bin u-boot> tftpboot u-boot> bootm 0x81800000 - Signed-off-by: Daniel Danzberger --- target/linux/airoha/Makefile | 15 + target/linux/airoha/config-5.15 | 271 ++++++++++++++ target/linux/airoha/dts/en7523-evb.dts | 73 ++++ target/linux/airoha/dts/en7523.dtsi | 219 +++++++++++ .../files/arch/arm/mach-airoha/Makefile | 2 + .../files/arch/arm/mach-airoha/airoha.c | 16 + .../airoha/files/drivers/clk/clk-en7523.c | 351 ++++++++++++++++++ .../airoha/files/drivers/gpio/gpio-en7523.c | 137 +++++++ .../include/dt-bindings/clock/en7523-clk.h | 17 + target/linux/airoha/image/Makefile | 37 ++ target/linux/airoha/image/en7523.mk | 0 .../0001-add-airoha-platform.patch | 35 ++ .../0002-add-airoha-en7523-clk-driver.patch | 32 ++ .../0003-add-airoha-en7523-gpio-driver.patch | 33 ++ ...press-Parse-linux-usable-memory-rang.patch | 111 ++++++ ...for-the-Airoha-EN7523-SoC-SPI-contro.patch | 346 +++++++++++++++++ ...iatek-Allow-building-for-ARCH_AIROHA.patch | 35 ++ ...nd-Add-support-for-Etron-EM73D044VCx.patch | 137 +++++++ 18 files changed, 1867 insertions(+) create mode 100644 target/linux/airoha/Makefile create mode 100644 target/linux/airoha/config-5.15 create mode 100644 target/linux/airoha/dts/en7523-evb.dts create mode 100644 target/linux/airoha/dts/en7523.dtsi create mode 100644 target/linux/airoha/files/arch/arm/mach-airoha/Makefile create mode 100644 target/linux/airoha/files/arch/arm/mach-airoha/airoha.c create mode 100644 target/linux/airoha/files/drivers/clk/clk-en7523.c create mode 100644 target/linux/airoha/files/drivers/gpio/gpio-en7523.c create mode 100644 target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h create mode 100644 target/linux/airoha/image/Makefile create mode 100644 target/linux/airoha/image/en7523.mk create mode 100644 target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch create mode 100644 target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch create mode 100644 target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch create mode 100644 target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch create mode 100644 target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch create mode 100644 target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch create mode 100644 target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch diff --git a/target/linux/airoha/Makefile b/target/linux/airoha/Makefile new file mode 100644 index 00000000000000..723bec8cd434dc --- /dev/null +++ b/target/linux/airoha/Makefile @@ -0,0 +1,15 @@ +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=airoha +BOARDNAME:=Airoha ARM +CPU_TYPE:=cortex-a7 +FEATURES:=dt squashfs nand ramdisk gpio source-only + +KERNEL_PATCHVER:=5.15 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=Image dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/airoha/config-5.15 b/target/linux/airoha/config-5.15 new file mode 100644 index 00000000000000..0fbf8a49959d35 --- /dev/null +++ b/target/linux/airoha/config-5.15 @@ -0,0 +1,271 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_AIROHA=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_CACHE_L2X0=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_EN7523=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_MISC=y +CONFIG_DMA_OPS=y +CONFIG_DMA_REMAP=y +CONFIG_DTC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_EN7523=y +CONFIG_GPIO_GENERIC=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND_CORE=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NLS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_AIROHA_EN7523=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UBIFS_FS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USE_OF=y +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XXHASH=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/airoha/dts/en7523-evb.dts b/target/linux/airoha/dts/en7523-evb.dts new file mode 100644 index 00000000000000..f311c840e0f975 --- /dev/null +++ b/target/linux/airoha/dts/en7523-evb.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7523.dtsi" + +/ { + model = "Airoha EN7523 Evaluation Board"; + compatible = "airoha,en7523-evb", "airoha,en7523"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x80200000 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x7C000>; + read-only; + }; + + partition@1 { + label = "u-boot-env"; + reg = <0x7C000 0x4000>; + }; + + partition@2 { + label = "art"; + reg = <0x80000 0x40000>; + read-only; + }; + + partition@3 { + label = "firmware"; + reg = <0xC0000 0xDF40000>; + }; + }; +}; diff --git a/target/linux/airoha/dts/en7523.dtsi b/target/linux/airoha/dts/en7523.dtsi new file mode 100644 index 00000000000000..72478b225cbb07 --- /dev/null +++ b/target/linux/airoha/dts/en7523.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + npu_binary@84000000 { + no-map; + reg = <0x84000000 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x84B00000 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x85000000 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x86B00000 0x100000>; + }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x86D00000 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x09000000 0x20000>, + <0x09080000 0x80000>, + <0x09400000 0x2000>, + <0x09500000 0x2000>, + <0x09600000 0x20000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + status = "okay"; + }; + + gpio0: gpio@1fbf0200 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0204 0x4>, + <0x1fbf0200 0x4>, + <0x1fbf0220 0x4>, + <0x1fbf0214 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@1fbf0270 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0270 0x4>, + <0x1fbf0260 0x4>, + <0x1fbf0264 0x4>, + <0x1fbf0278 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + pcie0: pcie@1fa91000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa91000 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1fa92000 { + compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0x1fa92000 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + interrupt-names = "pcie_irq"; + clocks = <&scu EN7523_CLK_PCIE>; + clock-names = "sys_ck1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + spi_ctrl: spi_controller@1fa10000 { + compatible = "airoha,en7523-spi"; + reg = <0x1fa10000 0x140>; + #address-cells = <1>; + #size-cells = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + + nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + nand-ecc-engine = <&nand>; + }; + }; +}; diff --git a/target/linux/airoha/files/arch/arm/mach-airoha/Makefile b/target/linux/airoha/files/arch/arm/mach-airoha/Makefile new file mode 100644 index 00000000000000..a5857d0d02ebf9 --- /dev/null +++ b/target/linux/airoha/files/arch/arm/mach-airoha/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += airoha.o diff --git a/target/linux/airoha/files/arch/arm/mach-airoha/airoha.c b/target/linux/airoha/files/arch/arm/mach-airoha/airoha.c new file mode 100644 index 00000000000000..ea23b5abb478e3 --- /dev/null +++ b/target/linux/airoha/files/arch/arm/mach-airoha/airoha.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree support for Airoha SoCs + * + * Copyright (c) 2022 Felix Fietkau + */ +#include + +static const char * const airoha_board_dt_compat[] = { + "airoha,en7523", + NULL, +}; + +DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)") + .dt_compat = airoha_board_dt_compat, +MACHINE_END diff --git a/target/linux/airoha/files/drivers/clk/clk-en7523.c b/target/linux/airoha/files/drivers/clk/clk-en7523.c new file mode 100644 index 00000000000000..29f0126cbd05bc --- /dev/null +++ b/target/linux/airoha/files/drivers/clk/clk-en7523.c @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#define REG_PCI_CONTROL 0x88 +#define REG_PCI_CONTROL_PERSTOUT BIT(29) +#define REG_PCI_CONTROL_PERSTOUT1 BIT(26) +#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22) +#define REG_GSW_CLK_DIV_SEL 0x1b4 +#define REG_EMI_CLK_DIV_SEL 0x1b8 +#define REG_BUS_CLK_DIV_SEL 0x1bc +#define REG_SPI_CLK_DIV_SEL 0x1c4 +#define REG_SPI_CLK_FREQ_SEL 0x1c8 +#define REG_NPU_CLK_DIV_SEL 0x1fc +#define REG_CRYPTO_CLKSRC 0x200 +#define REG_RESET_CONTROL 0x834 +#define REG_RESET_CONTROL_PCIEHB BIT(29) +#define REG_RESET_CONTROL_PCIE1 BIT(27) +#define REG_RESET_CONTROL_PCIE2 BIT(26) + +struct en_clk_desc { + int id; + const char *name; + u32 base_reg; + u8 base_bits; + u8 base_shift; + union { + const unsigned int *base_values; + unsigned int base_value; + }; + size_t n_base_values; + + u16 div_reg; + u8 div_bits; + u8 div_shift; + u16 div_val0; + u8 div_step; +}; + +struct en_clk_gate { + void __iomem *base; + struct clk_hw hw; +}; + +static const u32 gsw_base[] = { 400000000, 500000000 }; +static const u32 emi_base[] = { 333000000, 400000000 }; +static const u32 bus_base[] = { 500000000, 540000000 }; +static const u32 slic_base[] = { 100000000, 3125000 }; +static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; + +static const struct en_clk_desc en7523_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu_base, + .n_base_values = ARRAY_SIZE(npu_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC, + .base_bits = 1, + .base_shift = 8, + .base_values = emi_base, + .n_base_values = ARRAY_SIZE(emi_base), + } +}; + +static const struct of_device_id of_match_clk_en7523[] = { + { .compatible = "airoha,en7523-scu", }, + { /* sentinel */ } +}; + +static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val; + + if (!desc->base_bits) + return desc->base_value; + + val = readl(base + desc->base_reg); + val >>= desc->base_shift; + val &= (1 << desc->base_bits) - 1; + + if (val >= desc->n_base_values) + return 0; + + return desc->base_values[val]; +} + +static u32 en7523_get_div(void __iomem *base, int i) +{ + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg, val; + + if (!desc->div_bits) + return 1; + + reg = desc->div_reg ? desc->div_reg : desc->base_reg; + val = readl(base + reg); + val >>= desc->div_shift; + val &= (1 << desc->div_bits) - 1; + + if (!val && desc->div_val0) + return desc->div_val0; + + return (val + 1) * desc->div_step; +} + +static int en7523_pci_is_enabled(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + + return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); +} + +static int en7523_pci_prepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val, mask; + + /* Need to pull device low before reset */ + val = readl(np_base + REG_PCI_CONTROL); + val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT); + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Enable PCIe port 1 */ + val |= REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + + /* Reset to default */ + val = readl(np_base + REG_RESET_CONTROL); + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | + REG_RESET_CONTROL_PCIEHB; + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_RESET_CONTROL); + msleep(100); + writel(val & ~mask, np_base + REG_RESET_CONTROL); + usleep_range(5000, 10000); + + /* Release device */ + mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT; + val = readl(np_base + REG_PCI_CONTROL); + writel(val & ~mask, np_base + REG_PCI_CONTROL); + usleep_range(1000, 2000); + writel(val | mask, np_base + REG_PCI_CONTROL); + msleep(250); + + return 0; +} + +static void en7523_pci_unprepare(struct clk_hw *hw) +{ + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); + void __iomem *np_base = cg->base; + u32 val; + + val = readl(np_base + REG_PCI_CONTROL); + val &= ~REG_PCI_CONTROL_REFCLK_EN1; + writel(val, np_base + REG_PCI_CONTROL); +} + +static struct clk_hw *en7523_register_pcie_clk(struct device *dev, + void __iomem *np_base) +{ + static const struct clk_ops pcie_gate_ops = { + .is_enabled = en7523_pci_is_enabled, + .prepare = en7523_pci_prepare, + .unprepare = en7523_pci_unprepare, + }; + struct clk_init_data init = { + .name = "pcie", + .ops = &pcie_gate_ops, + }; + struct en_clk_gate *cg; + + cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); + if (!cg) + return NULL; + + cg->base = np_base; + cg->hw.init = &init; + en7523_pci_unprepare(&cg->hw); + + if (clk_hw_register(dev, &cg->hw)) + return NULL; + + return &cg->hw; +} + +static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + void __iomem *base, void __iomem *np_base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + + rate = en7523_get_base_rate(base, i); + rate /= en7523_get_div(base, i); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + +static int en7523_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base, *np_base; + int r; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + clk_data = devm_kzalloc(&pdev->dev, + struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_en7523_drv = { + .probe = en7523_clk_probe, + .driver = { + .name = "clk-en7523", + .of_match_table = of_match_clk_en7523, + .suppress_bind_attrs = true, + }, +}; + +static int __init clk_en7523_init(void) +{ + return platform_driver_register(&clk_en7523_drv); +} + +arch_initcall(clk_en7523_init); diff --git a/target/linux/airoha/files/drivers/gpio/gpio-en7523.c b/target/linux/airoha/files/drivers/gpio/gpio-en7523.c new file mode 100644 index 00000000000000..f836a8db4c1d21 --- /dev/null +++ b/target/linux/airoha/files/drivers/gpio/gpio-en7523.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AIROHA_GPIO_MAX 32 + +/** + * airoha_gpio_ctrl - Airoha GPIO driver data + * @gc: Associated gpio_chip instance. + * @data: The data register. + * @dir0: The direction register for the lower 16 pins. + * @dir1: The direction register for the higher 16 pins. + * @output: The output enable register. + */ +struct airoha_gpio_ctrl { + struct gpio_chip gc; + void __iomem *data; + void __iomem *dir[2]; + void __iomem *output; +}; + +static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc) +{ + return container_of(gc, struct airoha_gpio_ctrl, gc); +} + +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, + int val, int out) +{ + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); + u32 dir = ioread32(ctrl->dir[gpio / 16]); + u32 output = ioread32(ctrl->output); + u32 mask = BIT((gpio % 16) * 2); + + if (out) { + dir |= mask; + output |= BIT(gpio); + } else { + dir &= ~mask; + output &= ~BIT(gpio); + } + + iowrite32(dir, ctrl->dir[gpio / 16]); + + if (out) + gc->set(gc, gpio, val); + + iowrite32(output, ctrl->output); + + return 0; +} + +static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio, + int val) +{ + return airoha_dir_set(gc, gpio, val, 1); +} + +static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio) +{ + return airoha_dir_set(gc, gpio, 0, 0); +} + +static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio) +{ + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); + u32 dir = ioread32(ctrl->dir[gpio / 16]); + u32 mask = BIT((gpio % 16) * 2); + + return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int airoha_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct airoha_gpio_ctrl *ctrl; + int err; + + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->data = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ctrl->data)) + return PTR_ERR(ctrl->data); + + ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ctrl->dir[0])) + return PTR_ERR(ctrl->dir[0]); + + ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(ctrl->dir[1])) + return PTR_ERR(ctrl->dir[1]); + + ctrl->output = devm_platform_ioremap_resource(pdev, 3); + if (IS_ERR(ctrl->output)) + return PTR_ERR(ctrl->output); + + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL, + NULL, NULL, NULL, 0); + if (err) + return dev_err_probe(dev, err, "unable to init generic GPIO"); + + ctrl->gc.ngpio = AIROHA_GPIO_MAX; + ctrl->gc.owner = THIS_MODULE; + ctrl->gc.direction_output = airoha_dir_out; + ctrl->gc.direction_input = airoha_dir_in; + ctrl->gc.get_direction = airoha_get_dir; + + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); +} + +static const struct of_device_id airoha_gpio_of_match[] = { + { .compatible = "airoha,en7523-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, airoha_gpio_of_match); + +static struct platform_driver airoha_gpio_driver = { + .driver = { + .name = "airoha-gpio", + .of_match_table = airoha_gpio_of_match, + }, + .probe = airoha_gpio_probe, +}; +module_platform_driver(airoha_gpio_driver); + +MODULE_DESCRIPTION("Airoha GPIO support"); +MODULE_AUTHOR("John Crispin "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h b/target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h new file mode 100644 index 00000000000000..717d23a5e5aef0 --- /dev/null +++ b/target/linux/airoha/files/include/dt-bindings/clock/en7523-clk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ +#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ + +#define EN7523_CLK_GSW 0 +#define EN7523_CLK_EMI 1 +#define EN7523_CLK_BUS 2 +#define EN7523_CLK_SLIC 3 +#define EN7523_CLK_SPI 4 +#define EN7523_CLK_NPU 5 +#define EN7523_CLK_CRYPTO 6 +#define EN7523_CLK_PCIE 7 + +#define EN7523_NUM_CLOCKS 8 + +#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */ diff --git a/target/linux/airoha/image/Makefile b/target/linux/airoha/image/Makefile new file mode 100644 index 00000000000000..c6def5ad653b6a --- /dev/null +++ b/target/linux/airoha/image/Makefile @@ -0,0 +1,37 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +KERNEL_LOADADDR := 0x80208000 + +define Target/Description + Build firmware images for Airoha EN7523 ARM based boards. +endef + +# default all platform image(fit) build +define Device/Default + PROFILES = Default $$(DEVICE_NAME) + KERNEL_NAME := Image + KERNEL = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb + KERNEL_INITRAMFS = kernel-bin | lzma | \ + fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd + FILESYSTEMS := squashfs + DEVICE_DTS_DIR := $(DTS_DIR) + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | \ + pad-rootfs | append-metadata +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) +endef + +define Device/airoha_en7523-evb + DEVICE_VENDOR := Airoha + DEVICE_MODEL := EN7523 Evaluation Board + DEVICE_DTS := en7523-evb + DEVICE_DTS_DIR := ../dts +endef +TARGET_DEVICES += airoha_en7523-evb + +$(eval $(call BuildImage)) diff --git a/target/linux/airoha/image/en7523.mk b/target/linux/airoha/image/en7523.mk new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch b/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch new file mode 100644 index 00000000000000..b1f88a6ac7b0f3 --- /dev/null +++ b/target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch @@ -0,0 +1,35 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 66f5d6c3..05cd3385 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -571,6 +571,18 @@ config ARCH_VIRT + select HAVE_ARM_ARCH_TIMER + select ARCH_SUPPORTS_BIG_ENDIAN + ++config ARCH_AIROHA ++ bool "Airoha SoC Support" ++ depends on ARCH_MULTI_V7 ++ select ARM_AMBA ++ select ARM_GIC ++ select ARM_GIC_V3 ++ select ARM_PSCI ++ select HAVE_ARM_ARCH_TIMER ++ select COMMON_CLK ++ help ++ Support for Airoha EN7523 SoCs ++ + # + # This is sorted alphabetically by mach-* pathname. However, plat-* + # Kconfigs may be included either alphabetically (according to the +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index fa45837b..c34f7463 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -156,6 +156,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 + # Machine directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. + machine-$(CONFIG_ARCH_ACTIONS) += actions ++machine-$(CONFIG_ARCH_AIROHA) += airoha + machine-$(CONFIG_ARCH_ALPINE) += alpine + machine-$(CONFIG_ARCH_ARTPEC) += artpec + machine-$(CONFIG_ARCH_ASPEED) += aspeed diff --git a/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch b/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch new file mode 100644 index 00000000000000..676e0f40bbc89b --- /dev/null +++ b/target/linux/airoha/patches-5.15/0002-add-airoha-en7523-clk-driver.patch @@ -0,0 +1,32 @@ +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index c5b3dc97..c973ac1a 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP + help + If you say yes here you get support for the CS2000 clock multiplier. + ++config COMMON_CLK_EN7523 ++ bool "Clock driver for Airoha EN7523 SoC system clocks" ++ depends on OF ++ depends on ARCH_AIROHA || COMPILE_TEST ++ default ARCH_AIROHA ++ help ++ This driver provides the fixed clocks and gates present on Airoha ++ ARM silicon. ++ + config COMMON_CLK_FSL_FLEXSPI + tristate "Clock driver for FlexSPI on Layerscape SoCs" + depends on ARCH_LAYERSCAPE || COMPILE_TEST +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index e4231212..be11d88c 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o + obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o ++obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o + obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o + obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o + obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch b/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch new file mode 100644 index 00000000000000..1d95e6b2c82713 --- /dev/null +++ b/target/linux/airoha/patches-5.15/0003-add-airoha-en7523-gpio-driver.patch @@ -0,0 +1,33 @@ +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +index cbfb6f13..b3106df6 100644 +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -247,6 +247,16 @@ config GPIO_EM + help + Say yes here to support GPIO on Renesas Emma Mobile SoCs. + ++config GPIO_EN7523 ++ tristate "Airoha GPIO support" ++ depends on ARCH_AIROHA ++ default ARCH_AIROHA ++ select GPIO_GENERIC ++ select GPIOLIB_IRQCHIP ++ help ++ Say Y or M here to support the GPIO controller block on the ++ Airoha EN7523 SoC. It supports two banks of 32 GPIOs. ++ + config GPIO_EP93XX + def_bool y + depends on ARCH_EP93XX +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +index 61202717..4c73ce82 100644 +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o + obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o + obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o + obj-$(CONFIG_GPIO_EM) += gpio-em.o ++obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o + obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o + obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o + obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o diff --git a/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch b/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch new file mode 100644 index 00000000000000..f13ab2b0ed2c33 --- /dev/null +++ b/target/linux/airoha/patches-5.15/0004-ARM-9124-1-uncompress-Parse-linux-usable-memory-rang.patch @@ -0,0 +1,111 @@ +From 48342ae751c797ac73ac9c894b3f312df18ffd21 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Wed, 15 Sep 2021 13:46:20 +0100 +Subject: [PATCH] ARM: 9124/1: uncompress: Parse "linux,usable-memory-range" DT + property + +Add support for parsing the "linux,usable-memory-range" DT property. +This property is used to describe the usable memory reserved for the +crash dump kernel, and thus makes the memory reservation explicit. +If present, Linux no longer needs to mask the program counter, and rely +on the "mem=" kernel parameter to obtain the start and size of usable +memory. + +For backwards compatibility, the traditional method to derive the start +of memory is still used if "linux,usable-memory-range" is absent. + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Russell King (Oracle) +Signed-off-by: Daniel Danzberger +--- + .../arm/boot/compressed/fdt_check_mem_start.c | 48 ++++++++++++++++--- + 1 file changed, 42 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/boot/compressed/fdt_check_mem_start.c b/arch/arm/boot/compressed/fdt_check_mem_start.c +index 62450d824c3c..9291a2661bdf 100644 +--- a/arch/arm/boot/compressed/fdt_check_mem_start.c ++++ b/arch/arm/boot/compressed/fdt_check_mem_start.c +@@ -55,16 +55,17 @@ static uint64_t get_val(const fdt32_t *cells, uint32_t ncells) + * DTB, and, if out-of-range, replace it by the real start address. + * To preserve backwards compatibility (systems reserving a block of memory + * at the start of physical memory, kdump, ...), the traditional method is +- * always used if it yields a valid address. ++ * used if it yields a valid address, unless the "linux,usable-memory-range" ++ * property is present. + * + * Return value: start address of physical memory to use + */ + uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) + { +- uint32_t addr_cells, size_cells, base; ++ uint32_t addr_cells, size_cells, usable_base, base; + uint32_t fdt_mem_start = 0xffffffff; +- const fdt32_t *reg, *endp; +- uint64_t size, end; ++ const fdt32_t *usable, *reg, *endp; ++ uint64_t size, usable_end, end; + const char *type; + int offset, len; + +@@ -80,6 +81,27 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) + if (addr_cells > 2 || size_cells > 2) + return mem_start; + ++ /* ++ * Usable memory in case of a crash dump kernel ++ * This property describes a limitation: memory within this range is ++ * only valid when also described through another mechanism ++ */ ++ usable = get_prop(fdt, "/chosen", "linux,usable-memory-range", ++ (addr_cells + size_cells) * sizeof(fdt32_t)); ++ if (usable) { ++ size = get_val(usable + addr_cells, size_cells); ++ if (!size) ++ return mem_start; ++ ++ if (addr_cells > 1 && fdt32_ld(usable)) { ++ /* Outside 32-bit address space */ ++ return mem_start; ++ } ++ ++ usable_base = fdt32_ld(usable + addr_cells - 1); ++ usable_end = usable_base + size; ++ } ++ + /* Walk all memory nodes and regions */ + for (offset = fdt_next_node(fdt, -1, NULL); offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { +@@ -107,7 +129,20 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) + + base = fdt32_ld(reg + addr_cells - 1); + end = base + size; +- if (mem_start >= base && mem_start < end) { ++ if (usable) { ++ /* ++ * Clip to usable range, which takes precedence ++ * over mem_start ++ */ ++ if (base < usable_base) ++ base = usable_base; ++ ++ if (end > usable_end) ++ end = usable_end; ++ ++ if (end <= base) ++ continue; ++ } else if (mem_start >= base && mem_start < end) { + /* Calculated address is valid, use it */ + return mem_start; + } +@@ -123,7 +158,8 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) + } + + /* +- * The calculated address is not usable. ++ * The calculated address is not usable, or was overridden by the ++ * "linux,usable-memory-range" property. + * Use the lowest usable physical memory address from the DTB instead, + * and make sure this is a multiple of 2 MiB for phys/virt patching. + */ +-- +2.35.1 diff --git a/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch b/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch new file mode 100644 index 00000000000000..e368acc0cf7fde --- /dev/null +++ b/target/linux/airoha/patches-5.15/0005-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch @@ -0,0 +1,346 @@ +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 83e352b0..5f7defe4 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -308,6 +308,12 @@ config SPI_DLN2 + This driver can also be built as a module. If so, the module + will be called spi-dln2. + ++config SPI_AIROHA_EN7523 ++ bool "Airoha EN7523 SPI controller support" ++ depends on ARCH_AIROHA ++ help ++ This enables SPI controller support for the Airoha EN7523 SoC. ++ + config SPI_EP93XX + tristate "Cirrus Logic EP93xx SPI controller" + depends on ARCH_EP93XX || COMPILE_TEST +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 699db95c..6c9460f7 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.o + obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o + obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o + obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o ++obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o + obj-$(CONFIG_SPI_FALCON) += spi-falcon.o + obj-$(CONFIG_SPI_FSI) += spi-fsi.o + obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o +diff --git a/drivers/spi/spi-en7523.c b/drivers/spi/spi-en7523.c +new file mode 100644 +index 00000000..322bf2eb +--- /dev/null ++++ b/drivers/spi/spi-en7523.c +@@ -0,0 +1,311 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++ ++ ++#define ENSPI_READ_IDLE_EN 0x0004 ++#define ENSPI_MTX_MODE_TOG 0x0014 ++#define ENSPI_RDCTL_FSM 0x0018 ++#define ENSPI_MANUAL_EN 0x0020 ++#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024 ++#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028 ++#define ENSPI_MANUAL_OPFIFO_FULL 0x002C ++#define ENSPI_MANUAL_OPFIFO_WR 0x0030 ++#define ENSPI_MANUAL_DFIFO_FULL 0x0034 ++#define ENSPI_MANUAL_DFIFO_WDATA 0x0038 ++#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C ++#define ENSPI_MANUAL_DFIFO_RD 0x0040 ++#define ENSPI_MANUAL_DFIFO_RDATA 0x0044 ++#define ENSPI_IER 0x0090 ++#define ENSPI_NFI2SPI_EN 0x0130 ++ ++// TODO not in spi block ++#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4) ++ ++#define OP_CSH 0x00 ++#define OP_CSL 0x01 ++#define OP_CK 0x02 ++#define OP_OUTS 0x08 ++#define OP_OUTD 0x09 ++#define OP_OUTQ 0x0A ++#define OP_INS 0x0C ++#define OP_INS0 0x0D ++#define OP_IND 0x0E ++#define OP_INQ 0x0F ++#define OP_OS2IS 0x10 ++#define OP_OS2ID 0x11 ++#define OP_OS2IQ 0x12 ++#define OP_OD2IS 0x13 ++#define OP_OD2ID 0x14 ++#define OP_OD2IQ 0x15 ++#define OP_OQ2IS 0x16 ++#define OP_OQ2ID 0x17 ++#define OP_OQ2IQ 0x18 ++#define OP_OSNIS 0x19 ++#define OP_ODNID 0x1A ++ ++#define MATRIX_MODE_AUTO 1 ++#define CONF_MTX_MODE_AUTO 0 ++#define MANUALEN_AUTO 0 ++#define MATRIX_MODE_MANUAL 0 ++#define CONF_MTX_MODE_MANUAL 9 ++#define MANUALEN_MANUAL 1 ++ ++#define _ENSPI_MAX_XFER 0x1ff ++ ++#define REG(x) (iobase + x) ++ ++ ++static void __iomem *iobase; ++ ++ ++static void opfifo_write(u32 cmd, u32 len) ++{ ++ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff); ++ ++ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA)); ++ ++ /* Wait for room in OPFIFO */ ++ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL))) ++ ; ++ ++ /* Shift command into OPFIFO */ ++ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR)); ++ ++ /* Wait for command to finish */ ++ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY))) ++ ; ++} ++ ++static void set_cs(int state) ++{ ++ if (state) ++ opfifo_write(OP_CSH, 1); ++ else ++ opfifo_write(OP_CSL, 1); ++} ++ ++static void manual_begin_cmd(void) ++{ ++ /* Disable read idle state */ ++ writel(0, REG(ENSPI_READ_IDLE_EN)); ++ ++ /* Wait for FSM to reach idle state */ ++ while (readl(REG(ENSPI_RDCTL_FSM))) ++ ; ++ ++ /* Set SPI core to manual mode */ ++ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN)); ++} ++ ++static void manual_end_cmd(void) ++{ ++ /* Set SPI core to auto mode */ ++ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG)); ++ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN)); ++ ++ /* Enable read idle state */ ++ writel(1, REG(ENSPI_READ_IDLE_EN)); ++} ++ ++static void dfifo_read(u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for requested data to show up in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY))) ++ ; ++ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA)); ++ /* Queue up next byte */ ++ writel(1, REG(ENSPI_MANUAL_DFIFO_RD)); ++ } ++} ++ ++static void dfifo_write(const u8 *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ /* Wait for room in DFIFO */ ++ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL))) ++ ; ++ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA)); ++ } ++} ++ ++static void set_spi_clock_speed(int freq_mhz) ++{ ++ u32 tmp, val; ++ ++ tmp = readl(ENSPI_CLOCK_DIVIDER); ++ tmp &= 0xffff0000; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++ ++ val = (400 / (freq_mhz * 2)); ++ tmp |= (val << 8) | 1; ++ writel(tmp, ENSPI_CLOCK_DIVIDER); ++} ++ ++static void init_hw(void) ++{ ++ /* Disable manual/auto mode clash interrupt */ ++ writel(0, REG(ENSPI_IER)); ++ ++ // TODO via clk framework ++ // set_spi_clock_speed(50); ++ ++ /* Disable DMA */ ++ writel(0, REG(ENSPI_NFI2SPI_EN)); ++} ++ ++static int xfer_read(struct spi_transfer *xfer) ++{ ++ int opcode; ++ uint8_t *buf = xfer->rx_buf; ++ ++ switch (xfer->rx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_INS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_IND; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_INQ; ++ break; ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_read(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx) ++{ ++ int opcode; ++ const uint8_t *buf = xfer->tx_buf; ++ ++ if (next_xfer_is_rx) { ++ /* need to use Ox2Ix opcode to set the core to input afterwards */ ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OS2IS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OS2ID; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OS2IQ; ++ break; ++ } ++ } else { ++ switch (xfer->tx_nbits) { ++ case SPI_NBITS_SINGLE: ++ opcode = OP_OUTS; ++ break; ++ case SPI_NBITS_DUAL: ++ opcode = OP_OUTD; ++ break; ++ case SPI_NBITS_QUAD: ++ opcode = OP_OUTQ; ++ break; ++ } ++ } ++ ++ opfifo_write(opcode, xfer->len); ++ dfifo_write(buf, xfer->len); ++ ++ return xfer->len; ++} ++ ++size_t max_transfer_size(struct spi_device *spi) ++{ ++ return _ENSPI_MAX_XFER; ++} ++ ++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg) ++{ ++ struct spi_transfer *xfer; ++ int next_xfer_is_rx = 0; ++ ++ manual_begin_cmd(); ++ set_cs(0); ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (xfer->tx_buf) { ++ if (!list_is_last(&xfer->transfer_list, &msg->transfers) ++ && list_next_entry(xfer, transfer_list)->rx_buf != NULL) ++ next_xfer_is_rx = 1; ++ else ++ next_xfer_is_rx = 0; ++ msg->actual_length += xfer_write(xfer, next_xfer_is_rx); ++ } else if (xfer->rx_buf) { ++ msg->actual_length += xfer_read(xfer); ++ } ++ } ++ set_cs(1); ++ manual_end_cmd(); ++ ++ msg->status = 0; ++ spi_finalize_current_message(ctrl); ++ ++ return 0; ++} ++ ++static int spi_probe(struct platform_device *pdev) ++{ ++ struct spi_controller *ctrl; ++ int err; ++ ++ ctrl = devm_spi_alloc_master(&pdev->dev, 0); ++ if (!ctrl) { ++ dev_err(&pdev->dev, "Error allocating SPI controller\n"); ++ return -ENOMEM; ++ } ++ ++ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); ++ if (IS_ERR(iobase)) { ++ dev_err(&pdev->dev, "Could not map SPI register address"); ++ return -ENOMEM; ++ } ++ ++ init_hw(); ++ ++ ctrl->dev.of_node = pdev->dev.of_node; ++ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; ++ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL; ++ ctrl->max_transfer_size = max_transfer_size; ++ ctrl->transfer_one_message = transfer_one_message; ++ err = devm_spi_register_controller(&pdev->dev, ctrl); ++ if (err) { ++ dev_err(&pdev->dev, "Could not register SPI controller\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id spi_of_ids[] = { ++ { .compatible = "airoha,en7523-spi" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spi_of_ids); ++ ++static struct platform_driver spi_driver = { ++ .probe = spi_probe, ++ .driver = { ++ .name = "airoha-en7523-spi", ++ .of_match_table = spi_of_ids, ++ }, ++}; ++ ++module_platform_driver(spi_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Bert Vermeulen "); ++MODULE_DESCRIPTION("Airoha EN7523 SPI driver"); diff --git a/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch b/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch new file mode 100644 index 00000000000000..9f51f281bcf8f8 --- /dev/null +++ b/target/linux/airoha/patches-5.15/0006-PCI-mediatek-Allow-building-for-ARCH_AIROHA.patch @@ -0,0 +1,35 @@ +From b3b76fc86f0fb4d98918f48c784138bfa950dff6 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 15 Jun 2022 14:53:34 +0200 +Subject: [PATCH] PCI: mediatek: Allow building for ARCH_AIROHA + +Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the +Airoha EN7523 SoC uses the same controller as MT7622. + +The driver itself is not modified. The PCIe controller DT node should use +mediatek,mt7622-pcie after airoha,en7523-pcie. + +Link: https://lore.kernel.org/r/20220615125335.96089-2-nbd@nbd.name +Signed-off-by: Felix Fietkau +Signed-off-by: Bjorn Helgaas +Acked-by: Lorenzo Pieralisi +Signed-off-by: Daniel Danzberger +--- + drivers/pci/controller/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index b8d96d38064d..2f6806dc2a20 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -237,7 +237,7 @@ config PCIE_ROCKCHIP_EP + + config PCIE_MEDIATEK + tristate "MediaTek PCIe controller" +- depends on ARCH_MEDIATEK || COMPILE_TEST ++ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + help +-- +2.35.1 diff --git a/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch b/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch new file mode 100644 index 00000000000000..a48e02fc083bca --- /dev/null +++ b/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch @@ -0,0 +1,137 @@ +diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile +index 9c64d9fc..5f99ea72 100644 +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c +index 9839ee44..9ab44217 100644 +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -898,6 +898,7 @@ static const struct nand_ops spinand_ops = { + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &esmt_c8_spinand_manufacturer, + &gigadevice_spinand_manufacturer, ++ &etron_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, + ¶gon_spinand_manufacturer, +diff --git a/drivers/mtd/nand/spi/etron.c b/drivers/mtd/nand/spi/etron.c +new file mode 100644 +index 00000000..653092be +--- /dev/null ++++ b/drivers/mtd/nand/spi/etron.c +@@ -0,0 +1,98 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_ETRON 0xd5 ++ ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int etron_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 72; ++ oobregion->length = 56; ++ ++ return 0; ++} ++ ++static int etron_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobregion) ++{ ++ if (section) ++ return -ERANGE; ++ ++ oobregion->offset = 1; ++ oobregion->length = 71; ++ ++ return 0; ++} ++ ++static int etron_ecc_get_status(struct spinand_device *spinand, u8 status) ++{ ++ switch (status & STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case STATUS_ECC_HAS_BITFLIPS: ++ /* Between 1-7 bitflips were corrected */ ++ return 7; ++ ++ case STATUS_ECC_MASK: ++ /* Maximum bitflips were corrected */ ++ return 8; ++ ++ case STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ } ++ ++ return -EINVAL; ++} ++ ++static const struct mtd_ooblayout_ops etron_ooblayout = { ++ .ecc = etron_ooblayout_ecc, ++ .free = etron_ooblayout_free, ++}; ++ ++static const struct spinand_info etron_spinand_table[] = { ++ SPINAND_INFO("EM73D044VCx", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x1f), ++ // bpc, pagesize, oobsize, pagesperblock, bperlun, maxbadplun, ppl, lpt, #t ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer etron_spinand_manufacturer = { ++ .id = SPINAND_MFR_ETRON, ++ .name = "Etron", ++ .chips = etron_spinand_table, ++ .nchips = ARRAY_SIZE(etron_spinand_table), ++ .ops = &etron_spinand_manuf_ops, ++}; +diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h +index 2066962d..11d38d2f 100644 +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -261,6 +261,7 @@ struct spinand_manufacturer { + + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; ++extern const struct spinand_manufacturer etron_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; From faf2b2193e28ecf4237c263ce58897cb9170d477 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 28 Aug 2022 20:35:03 +0200 Subject: [PATCH 32/91] build: export STAGING_DIR_HOST in toplevel make code Fixes ncurses pkg-config check for menuconfig Signed-off-by: Felix Fietkau --- include/toplevel.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/include/toplevel.mk b/include/toplevel.mk index ce744bc92ccf67..455fc9c4da0b3c 100644 --- a/include/toplevel.mk +++ b/include/toplevel.mk @@ -60,6 +60,7 @@ endif SCAN_COOKIE?=$(shell echo $$$$) export SCAN_COOKIE +export STAGING_DIR_HOST=$(TOPDIR)/staging_dir/host SUBMAKE:=umask 022; $(SUBMAKE) From 0c8e5c35c7b37a45a7146a2857ffe2f4cf496898 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 5 Sep 2022 11:45:00 +0200 Subject: [PATCH 33/91] mediatek: fix fallout after etron spinand backport Signed-off-by: Felix Fietkau --- ...-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch index 4a5d814b3ba112..823630b3c42339 100644 --- a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -18,8 +18,8 @@ Signed-off-by: Davide Fioravanti +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o esmt.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o +-spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -29,8 +29,8 @@ Signed-off-by: Davide Fioravanti &esmt_c8_spinand_manufacturer, + &fidelix_spinand_manufacturer, &gigadevice_spinand_manufacturer, + &etron_spinand_manufacturer, ¯onix_spinand_manufacturer, - µn_spinand_manufacturer, --- /dev/null +++ b/drivers/mtd/nand/spi/fidelix.c @@ -0,0 +1,76 @@ @@ -112,10 +112,10 @@ Signed-off-by: Davide Fioravanti +}; --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -261,6 +261,7 @@ struct spinand_manufacturer { - +@@ -262,6 +262,7 @@ struct spinand_manufacturer { /* SPI NAND manufacturers */ extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; + extern const struct spinand_manufacturer etron_spinand_manufacturer; +extern const struct spinand_manufacturer fidelix_spinand_manufacturer; extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; From ee035de0fd4cf674dccc455cdb10dfa414f378c7 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 5 Sep 2022 14:04:17 +0100 Subject: [PATCH 34/91] kernel: fix mvneta Ethernet after generic phylink validate Import patches from Linux v5.16 and v5.17 to get 2500Base-X SFP working again with mvneta driver after the generic phylink validate backport. Fixes: aab466f422 ("kernel: backport generic phylink validate") Signed-off-by: Daniel Golle --- ...-users-of-bitmap_foo-to-linkmode_foo.patch | 948 ++++++++++++++++++ ...populate-supported_interfaces-member.patch | 48 + ...e-interface-checks-in-mvneta_validat.patch | 35 + ...op-use-of-phylink_helper_basex_speed.patch | 55 + ...-mvneta-use-phylink_generic_validate.patch | 72 ++ ...ark-as-a-legacy_pre_march2020-driver.patch | 29 + ...3-Include-all-ports-in-enabled_ports.patch | 24 +- ...t-dsa-b53-Drop-unused-cpu_port-field.patch | 42 +- ...-dsa-mv88e6xxx-disable-ATU-violation.patch | 2 +- ...equest-assisted-learning-on-CPU-port.patch | 2 +- 10 files changed, 1222 insertions(+), 35 deletions(-) create mode 100644 target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch create mode 100644 target/linux/generic/backport-5.15/703-16-v5.16-net-mvneta-populate-supported_interfaces-member.patch create mode 100644 target/linux/generic/backport-5.15/703-17-v5.16-net-mvneta-remove-interface-checks-in-mvneta_validat.patch create mode 100644 target/linux/generic/backport-5.15/703-18-v5.16-net-mvneta-drop-use-of-phylink_helper_basex_speed.patch create mode 100644 target/linux/generic/backport-5.15/703-19-v5.17-net-mvneta-use-phylink_generic_validate.patch create mode 100644 target/linux/generic/backport-5.15/703-20-v5.17-net-mvneta-mark-as-a-legacy_pre_march2020-driver.patch diff --git a/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch new file mode 100644 index 00000000000000..eb1bc503673fb7 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch @@ -0,0 +1,948 @@ +From 4973056cceacc70966396039fae99867dfafd796 Mon Sep 17 00:00:00 2001 +From: Sean Anderson +Date: Fri, 22 Oct 2021 18:41:04 -0400 +Subject: [PATCH] net: convert users of bitmap_foo() to linkmode_foo() + +This converts instances of + bitmap_foo(args..., __ETHTOOL_LINK_MODE_MASK_NBITS) +to + linkmode_foo(args...) + +I manually fixed up some lines to prevent them from being excessively +long. Otherwise, this change was generated with the following semantic +patch: + +// Generated with +// echo linux/linkmode.h > includes +// git grep -Flf includes include/ | cut -f 2- -d / | cat includes - \ +// | sort | uniq | tee new_includes | wc -l && mv new_includes includes +// and repeating until the number stopped going up +@i@ +@@ + +( + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +| + #include +) + +@depends on i@ +expression list args; +@@ + +( +- bitmap_zero(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_zero(args) +| +- bitmap_copy(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_copy(args) +| +- bitmap_and(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_and(args) +| +- bitmap_or(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_or(args) +| +- bitmap_empty(args, ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_empty(args) +| +- bitmap_andnot(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_andnot(args) +| +- bitmap_equal(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_equal(args) +| +- bitmap_intersects(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_intersects(args) +| +- bitmap_subset(args, __ETHTOOL_LINK_MODE_MASK_NBITS) ++ linkmode_subset(args) +) + +Add missing linux/mii.h include to mellanox. -DaveM + +Signed-off-by: Sean Anderson +Signed-off-by: David S. Miller +--- + drivers/net/dsa/b53/b53_common.c | 6 ++---- + drivers/net/dsa/bcm_sf2.c | 8 +++---- + drivers/net/dsa/hirschmann/hellcreek.c | 6 ++---- + drivers/net/dsa/lantiq_gswip.c | 14 ++++++------- + drivers/net/dsa/microchip/ksz8795.c | 8 +++---- + drivers/net/dsa/mv88e6xxx/chip.c | 5 ++--- + drivers/net/dsa/ocelot/felix_vsc9959.c | 8 +++---- + drivers/net/dsa/ocelot/seville_vsc9953.c | 8 +++---- + drivers/net/dsa/qca/ar9331.c | 10 ++++----- + drivers/net/dsa/sja1105/sja1105_main.c | 7 +++---- + drivers/net/dsa/xrs700x/xrs700x.c | 8 +++---- + drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c | 8 +++---- + drivers/net/ethernet/atheros/ag71xx.c | 8 +++---- + drivers/net/ethernet/cadence/macb_main.c | 11 +++++----- + .../net/ethernet/freescale/enetc/enetc_pf.c | 8 +++---- + .../net/ethernet/huawei/hinic/hinic_ethtool.c | 10 ++++----- + .../net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 5 ++--- + drivers/net/ethernet/marvell/mvneta.c | 10 ++++----- + .../net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 +++---- + .../marvell/octeontx2/nic/otx2_ethtool.c | 5 ++--- + drivers/net/ethernet/marvell/pxa168_eth.c | 3 +-- + .../net/ethernet/mellanox/mlx4/en_ethtool.c | 21 +++++++------------ + .../microchip/sparx5/sparx5_phylink.c | 7 +++---- + drivers/net/ethernet/mscc/ocelot_net.c | 7 +++---- + .../ethernet/pensando/ionic/ionic_ethtool.c | 3 +-- + .../net/ethernet/xilinx/xilinx_axienet_main.c | 8 +++---- + drivers/net/pcs/pcs-xpcs.c | 2 +- + drivers/net/phy/sfp-bus.c | 2 +- + net/ethtool/ioctl.c | 7 +++---- + 29 files changed, 87 insertions(+), 133 deletions(-) + +--- a/drivers/net/dsa/b53/b53_common.c ++++ b/drivers/net/dsa/b53/b53_common.c +@@ -1349,10 +1349,8 @@ void b53_phylink_validate(struct dsa_swi + phylink_set(mask, 100baseT_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + phylink_helper_basex_speed(state); + } +--- a/drivers/net/dsa/bcm_sf2.c ++++ b/drivers/net/dsa/bcm_sf2.c +@@ -686,7 +686,7 @@ static void bcm_sf2_sw_validate(struct d + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_MOCA) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + if (port != core_readl(priv, CORE_IMP0_PRT_ID)) + dev_err(ds->dev, + "Unsupported interface: %d for port %d\n", +@@ -714,10 +714,8 @@ static void bcm_sf2_sw_validate(struct d + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port, +--- a/drivers/net/dsa/hirschmann/hellcreek.c ++++ b/drivers/net/dsa/hirschmann/hellcreek.c +@@ -1476,10 +1476,8 @@ static void hellcreek_phylink_validate(s + else + phylink_set(mask, 1000baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static int +--- a/drivers/net/dsa/lantiq_gswip.c ++++ b/drivers/net/dsa/lantiq_gswip.c +@@ -1452,10 +1452,8 @@ static void gswip_phylink_set_capab(unsi + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, +@@ -1483,7 +1481,7 @@ static void gswip_xrx200_phylink_validat + goto unsupported; + break; + default: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported port: %i\n", port); + return; + } +@@ -1493,7 +1491,7 @@ static void gswip_xrx200_phylink_validat + return; + + unsupported: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", + phy_modes(state->interface), port); + } +@@ -1523,7 +1521,7 @@ static void gswip_xrx300_phylink_validat + goto unsupported; + break; + default: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported port: %i\n", port); + return; + } +@@ -1533,7 +1531,7 @@ static void gswip_xrx300_phylink_validat + return; + + unsupported: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", + phy_modes(state->interface), port); + } +--- a/drivers/net/dsa/microchip/ksz8795.c ++++ b/drivers/net/dsa/microchip/ksz8795.c +@@ -1542,15 +1542,13 @@ static void ksz8_validate(struct dsa_swi + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + return; + + unsupported: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported interface: %s, port: %d\n", + phy_modes(state->interface), port); + } +--- a/drivers/net/dsa/mv88e6xxx/chip.c ++++ b/drivers/net/dsa/mv88e6xxx/chip.c +@@ -683,9 +683,8 @@ static void mv88e6xxx_validate(struct ds + if (chip->info->ops->phylink_validate) + chip->info->ops->phylink_validate(chip, port, mask, state); + +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + /* We can only operate at 2500BaseX or 1000BaseX. If requested + * to advertise both, only report advertising at 2500BaseX. +--- a/drivers/net/dsa/ocelot/felix_vsc9959.c ++++ b/drivers/net/dsa/ocelot/felix_vsc9959.c +@@ -944,7 +944,7 @@ static void vsc9959_phylink_validate(str + + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != ocelot_port->phy_mode) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -966,10 +966,8 @@ static void vsc9959_phylink_validate(str + phylink_set(mask, 2500baseX_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, +--- a/drivers/net/dsa/ocelot/seville_vsc9953.c ++++ b/drivers/net/dsa/ocelot/seville_vsc9953.c +@@ -1000,7 +1000,7 @@ static void vsc9953_phylink_validate(str + + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != ocelot_port->phy_mode) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -1019,10 +1019,8 @@ static void vsc9953_phylink_validate(str + phylink_set(mask, 2500baseX_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static int vsc9953_prevalidate_phy_mode(struct ocelot *ocelot, int port, +--- a/drivers/net/dsa/qca/ar9331.c ++++ b/drivers/net/dsa/qca/ar9331.c +@@ -522,7 +522,7 @@ static void ar9331_sw_phylink_validate(s + goto unsupported; + break; + default: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported port: %i\n", port); + return; + } +@@ -536,15 +536,13 @@ static void ar9331_sw_phylink_validate(s + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + return; + + unsupported: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported interface: %d, port: %d\n", + state->interface, port); + } +--- a/drivers/net/dsa/sja1105/sja1105_main.c ++++ b/drivers/net/dsa/sja1105/sja1105_main.c +@@ -1360,7 +1360,7 @@ static void sja1105_phylink_validate(str + */ + if (state->interface != PHY_INTERFACE_MODE_NA && + sja1105_phy_mode_mismatch(priv, port, state->interface)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -1380,9 +1380,8 @@ static void sja1105_phylink_validate(str + phylink_set(mask, 2500baseX_Full); + } + +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static int +--- a/drivers/net/dsa/xrs700x/xrs700x.c ++++ b/drivers/net/dsa/xrs700x/xrs700x.c +@@ -456,7 +456,7 @@ static void xrs700x_phylink_validate(str + phylink_set(mask, 1000baseT_Full); + break; + default: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + dev_err(ds->dev, "Unsupported port: %i\n", port); + return; + } +@@ -467,10 +467,8 @@ static void xrs700x_phylink_validate(str + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Full); + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void xrs700x_mac_link_up(struct dsa_switch *ds, int port, +--- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c +@@ -369,9 +369,8 @@ static int xgbe_set_link_ksettings(struc + __ETHTOOL_LINK_MODE_MASK_NBITS, cmd->link_modes.advertising, + __ETHTOOL_LINK_MODE_MASK_NBITS, lks->link_modes.supported); + +- bitmap_and(advertising, +- cmd->link_modes.advertising, lks->link_modes.supported, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(advertising, cmd->link_modes.advertising, ++ lks->link_modes.supported); + + if ((cmd->base.autoneg == AUTONEG_ENABLE) && + bitmap_empty(advertising, __ETHTOOL_LINK_MODE_MASK_NBITS)) { +@@ -384,8 +383,7 @@ static int xgbe_set_link_ksettings(struc + pdata->phy.autoneg = cmd->base.autoneg; + pdata->phy.speed = speed; + pdata->phy.duplex = cmd->base.duplex; +- bitmap_copy(lks->link_modes.advertising, advertising, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_copy(lks->link_modes.advertising, advertising); + + if (cmd->base.autoneg == AUTONEG_ENABLE) + XGBE_SET_ADV(lks, Autoneg); +--- a/drivers/net/ethernet/atheros/ag71xx.c ++++ b/drivers/net/ethernet/atheros/ag71xx.c +@@ -1082,14 +1082,12 @@ static void ag71xx_mac_validate(struct p + phylink_set(mask, 1000baseX_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + return; + unsupported: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + } + + static void ag71xx_mac_pcs_get_state(struct phylink_config *config, +--- a/drivers/net/ethernet/cadence/macb_main.c ++++ b/drivers/net/ethernet/cadence/macb_main.c +@@ -523,21 +523,21 @@ static void macb_validate(struct phylink + state->interface != PHY_INTERFACE_MODE_SGMII && + state->interface != PHY_INTERFACE_MODE_10GBASER && + !phy_interface_mode_is_rgmii(state->interface)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + + if (!macb_is_gem(bp) && + (state->interface == PHY_INTERFACE_MODE_GMII || + phy_interface_mode_is_rgmii(state->interface))) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + + if (state->interface == PHY_INTERFACE_MODE_10GBASER && + !(bp->caps & MACB_CAPS_HIGH_SPEED && + bp->caps & MACB_CAPS_PCS)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -576,9 +576,8 @@ static void macb_validate(struct phylink + phylink_set(mask, 1000baseT_Half); + } + out: +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, +--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c ++++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c +@@ -940,7 +940,7 @@ static void enetc_pl_mac_validate(struct + state->interface != PHY_INTERFACE_MODE_2500BASEX && + state->interface != PHY_INTERFACE_MODE_USXGMII && + !phy_interface_mode_is_rgmii(state->interface)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -963,10 +963,8 @@ static void enetc_pl_mac_validate(struct + phylink_set(mask, 2500baseX_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void enetc_pl_mac_config(struct phylink_config *config, +--- a/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c ++++ b/drivers/net/ethernet/huawei/hinic/hinic_ethtool.c +@@ -322,12 +322,10 @@ static int hinic_get_link_ksettings(stru + } + } + +- bitmap_copy(link_ksettings->link_modes.supported, +- (unsigned long *)&settings.supported, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_copy(link_ksettings->link_modes.advertising, +- (unsigned long *)&settings.advertising, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_copy(link_ksettings->link_modes.supported, ++ (unsigned long *)&settings.supported); ++ linkmode_copy(link_ksettings->link_modes.advertising, ++ (unsigned long *)&settings.advertising); + + return 0; + } +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +@@ -467,9 +467,8 @@ static int ixgbe_set_link_ksettings(stru + * this function does not support duplex forcing, but can + * limit the advertising of the adapter to the specified speed + */ +- if (!bitmap_subset(cmd->link_modes.advertising, +- cmd->link_modes.supported, +- __ETHTOOL_LINK_MODE_MASK_NBITS)) ++ if (!linkmode_subset(cmd->link_modes.advertising, ++ cmd->link_modes.supported)) + return -EINVAL; + + /* only allow one speed at a time if no autoneg */ +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -3835,14 +3835,14 @@ static void mvneta_validate(struct phyli + */ + if (phy_interface_mode_is_8023z(state->interface)) { + if (!phylink_test(state->advertising, Autoneg)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + } else if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_SGMII && + !phy_interface_mode_is_rgmii(state->interface)) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -3871,10 +3871,8 @@ static void mvneta_validate(struct phyli + phylink_set(mask, 100baseT_Full); + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + /* We can only operate at 2500BaseX or 1000BaseX. If requested + * to advertise both, only report advertising at 2500BaseX. +--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c ++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +@@ -6347,15 +6347,14 @@ static void mvpp2_phylink_validate(struc + goto empty_set; + } + +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + + phylink_helper_basex_speed(state); + return; + + empty_set: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + } + + static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, +--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c ++++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +@@ -1168,9 +1168,8 @@ static int otx2_set_link_ksettings(struc + otx2_get_link_ksettings(netdev, &cur_ks); + + /* Check requested modes against supported modes by hardware */ +- if (!bitmap_subset(cmd->link_modes.advertising, +- cur_ks.link_modes.supported, +- __ETHTOOL_LINK_MODE_MASK_NBITS)) ++ if (!linkmode_subset(cmd->link_modes.advertising, ++ cur_ks.link_modes.supported)) + return -EINVAL; + + mutex_lock(&mbox->lock); +--- a/drivers/net/ethernet/marvell/pxa168_eth.c ++++ b/drivers/net/ethernet/marvell/pxa168_eth.c +@@ -977,8 +977,7 @@ static int pxa168_init_phy(struct net_de + cmd.base.phy_address = pep->phy_addr; + cmd.base.speed = pep->phy_speed; + cmd.base.duplex = pep->phy_duplex; +- bitmap_copy(cmd.link_modes.advertising, PHY_BASIC_FEATURES, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_copy(cmd.link_modes.advertising, PHY_BASIC_FEATURES); + cmd.base.autoneg = AUTONEG_ENABLE; + + if (cmd.base.speed != 0) +--- a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c ++++ b/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + + #include "mlx4_en.h" + #include "en_port.h" +@@ -643,10 +644,8 @@ static unsigned long *ptys2ethtool_link_ + unsigned int i; \ + cfg = &ptys2ethtool_map[reg_]; \ + cfg->speed = speed_; \ +- bitmap_zero(cfg->supported, \ +- __ETHTOOL_LINK_MODE_MASK_NBITS); \ +- bitmap_zero(cfg->advertised, \ +- __ETHTOOL_LINK_MODE_MASK_NBITS); \ ++ linkmode_zero(cfg->supported); \ ++ linkmode_zero(cfg->advertised); \ + for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ + __set_bit(modes[i], cfg->supported); \ + __set_bit(modes[i], cfg->advertised); \ +@@ -702,10 +701,8 @@ static void ptys2ethtool_update_link_mod + int i; + for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { + if (eth_proto & MLX4_PROT_MASK(i)) +- bitmap_or(link_modes, link_modes, +- ptys2ethtool_link_mode(&ptys2ethtool_map[i], +- report), +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_or(link_modes, link_modes, ++ ptys2ethtool_link_mode(&ptys2ethtool_map[i], report)); + } + } + +@@ -716,11 +713,9 @@ static u32 ethtool2ptys_link_modes(const + u32 ptys_modes = 0; + + for (i = 0; i < MLX4_LINK_MODES_SZ; i++) { +- if (bitmap_intersects( +- ptys2ethtool_link_mode(&ptys2ethtool_map[i], +- report), +- link_modes, +- __ETHTOOL_LINK_MODE_MASK_NBITS)) ++ ulong *map_mode = ptys2ethtool_link_mode(&ptys2ethtool_map[i], ++ report); ++ if (linkmode_intersects(map_mode, link_modes)) + ptys_modes |= 1 << i; + } + return ptys_modes; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c +@@ -92,12 +92,11 @@ static void sparx5_phylink_validate(stru + } + break; + default: +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void sparx5_phylink_mac_config(struct phylink_config *config, +--- a/drivers/net/ethernet/mscc/ocelot_net.c ++++ b/drivers/net/ethernet/mscc/ocelot_net.c +@@ -1509,7 +1509,7 @@ static void vsc7514_phylink_validate(str + + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != ocelot_port->phy_mode) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + +@@ -1528,9 +1528,8 @@ static void vsc7514_phylink_validate(str + phylink_set(mask, 2500baseT_Full); + phylink_set(mask, 2500baseX_Full); + +- bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void vsc7514_phylink_mac_config(struct phylink_config *config, +--- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c ++++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c +@@ -228,8 +228,7 @@ static int ionic_get_link_ksettings(stru + break; + } + +- bitmap_copy(ks->link_modes.advertising, ks->link_modes.supported, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported); + + ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER); + ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS); +--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c ++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +@@ -1565,7 +1565,7 @@ static void axienet_validate(struct phyl + netdev_warn(ndev, "Cannot use PHY mode %s, supported: %s\n", + phy_modes(state->interface), + phy_modes(lp->phy_mode)); +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(supported); + return; + } + } +@@ -1598,10 +1598,8 @@ static void axienet_validate(struct phyl + break; + } + +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_and(supported, supported, mask); ++ linkmode_and(state->advertising, state->advertising, mask); + } + + static void axienet_mac_pcs_get_state(struct phylink_config *config, +--- a/drivers/net/pcs/pcs-xpcs.c ++++ b/drivers/net/pcs/pcs-xpcs.c +@@ -646,7 +646,7 @@ void xpcs_validate(struct dw_xpcs *xpcs, + if (state->interface == PHY_INTERFACE_MODE_NA) + return; + +- bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(xpcs_supported); + + compat = xpcs_find_compat(xpcs->id, state->interface); + +--- a/drivers/net/phy/sfp-bus.c ++++ b/drivers/net/phy/sfp-bus.c +@@ -379,7 +379,7 @@ void sfp_parse_support(struct sfp_bus *b + if (bus->sfp_quirk) + bus->sfp_quirk->modes(id, modes); + +- bitmap_or(support, support, modes, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_or(support, support, modes); + + phylink_set(support, Autoneg); + phylink_set(support, Pause); +--- a/net/ethtool/ioctl.c ++++ b/net/ethtool/ioctl.c +@@ -335,7 +335,7 @@ EXPORT_SYMBOL(ethtool_intersect_link_mas + void ethtool_convert_legacy_u32_to_link_mode(unsigned long *dst, + u32 legacy_u32) + { +- bitmap_zero(dst, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(dst); + dst[0] = legacy_u32; + } + EXPORT_SYMBOL(ethtool_convert_legacy_u32_to_link_mode); +@@ -350,11 +350,10 @@ bool ethtool_convert_link_mode_to_legacy + if (__ETHTOOL_LINK_MODE_MASK_NBITS > 32) { + __ETHTOOL_DECLARE_LINK_MODE_MASK(ext); + +- bitmap_zero(ext, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ linkmode_zero(ext); + bitmap_fill(ext, 32); + bitmap_complement(ext, ext, __ETHTOOL_LINK_MODE_MASK_NBITS); +- if (bitmap_intersects(ext, src, +- __ETHTOOL_LINK_MODE_MASK_NBITS)) { ++ if (linkmode_intersects(ext, src)) { + /* src mask goes beyond bit 31 */ + retval = false; + } diff --git a/target/linux/generic/backport-5.15/703-16-v5.16-net-mvneta-populate-supported_interfaces-member.patch b/target/linux/generic/backport-5.15/703-16-v5.16-net-mvneta-populate-supported_interfaces-member.patch new file mode 100644 index 00000000000000..f21fa4b2778ec7 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-16-v5.16-net-mvneta-populate-supported_interfaces-member.patch @@ -0,0 +1,48 @@ +From fdedb695e6a8657302341cda81d519ef04f9acaa Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Wed, 27 Oct 2021 10:03:43 +0100 +Subject: [PATCH] net: mvneta: populate supported_interfaces member + +Populate the phy_interface_t bitmap for the Marvell mvneta driver with +interfaces modes supported by the MAC. + +Signed-off-by: Russell King +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/marvell/mvneta.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -5180,6 +5180,31 @@ static int mvneta_probe(struct platform_ + + pp->phylink_config.dev = &dev->dev; + pp->phylink_config.type = PHYLINK_NETDEV; ++ phy_interface_set_rgmii(pp->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_QSGMII, ++ pp->phylink_config.supported_interfaces); ++ if (comphy) { ++ /* If a COMPHY is present, we can support any of the serdes ++ * modes and switch between them. ++ */ ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ pp->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_1000BASEX, ++ pp->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ pp->phylink_config.supported_interfaces); ++ } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { ++ /* No COMPHY, with only 2500BASE-X mode supported */ ++ __set_bit(PHY_INTERFACE_MODE_2500BASEX, ++ pp->phylink_config.supported_interfaces); ++ } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || ++ phy_mode == PHY_INTERFACE_MODE_SGMII) { ++ /* No COMPHY, we can switch between 1000BASE-X and SGMII */ ++ __set_bit(PHY_INTERFACE_MODE_1000BASEX, ++ pp->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_SGMII, ++ pp->phylink_config.supported_interfaces); ++ } + + phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, + phy_mode, &mvneta_phylink_ops); diff --git a/target/linux/generic/backport-5.15/703-17-v5.16-net-mvneta-remove-interface-checks-in-mvneta_validat.patch b/target/linux/generic/backport-5.15/703-17-v5.16-net-mvneta-remove-interface-checks-in-mvneta_validat.patch new file mode 100644 index 00000000000000..e287e39d6a4ea7 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-17-v5.16-net-mvneta-remove-interface-checks-in-mvneta_validat.patch @@ -0,0 +1,35 @@ +From d9ca72807ecb236f679b960c70ef5b7d4a5f0222 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 27 Oct 2021 10:03:48 +0100 +Subject: [PATCH] net: mvneta: remove interface checks in mvneta_validate() + +As phylink checks the interface mode against the supported_interfaces +bitmap, we no longer need to validate the interface mode in the +validation function. Remove this to simplify it. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/marvell/mvneta.c | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -3833,15 +3833,8 @@ static void mvneta_validate(struct phyli + * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... + * When = 1 (1000BASE-X) this field must be set to 1." + */ +- if (phy_interface_mode_is_8023z(state->interface)) { +- if (!phylink_test(state->advertising, Autoneg)) { +- linkmode_zero(supported); +- return; +- } +- } else if (state->interface != PHY_INTERFACE_MODE_NA && +- state->interface != PHY_INTERFACE_MODE_QSGMII && +- state->interface != PHY_INTERFACE_MODE_SGMII && +- !phy_interface_mode_is_rgmii(state->interface)) { ++ if (phy_interface_mode_is_8023z(state->interface) && ++ !phylink_test(state->advertising, Autoneg)) { + linkmode_zero(supported); + return; + } diff --git a/target/linux/generic/backport-5.15/703-18-v5.16-net-mvneta-drop-use-of-phylink_helper_basex_speed.patch b/target/linux/generic/backport-5.15/703-18-v5.16-net-mvneta-drop-use-of-phylink_helper_basex_speed.patch new file mode 100644 index 00000000000000..9121612bf82942 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-18-v5.16-net-mvneta-drop-use-of-phylink_helper_basex_speed.patch @@ -0,0 +1,55 @@ +From 099cbfa286ab937d8213c2dc5c0b401969b78042 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Wed, 27 Oct 2021 10:03:53 +0100 +Subject: [PATCH] net: mvneta: drop use of phylink_helper_basex_speed() + +Now that we have a better method to select SFP interface modes, we +no longer need to use phylink_helper_basex_speed() in a driver's +validation function, and we can also get rid of our hack to indicate +both 1000base-X and 2500base-X if the comphy is present to make that +work. Remove this hack and use of phylink_helper_basex_speed(). + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/marvell/mvneta.c | 12 +++--------- + 1 file changed, 3 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -3824,8 +3824,6 @@ static void mvneta_validate(struct phyli + unsigned long *supported, + struct phylink_link_state *state) + { +- struct net_device *ndev = to_net_dev(config->dev); +- struct mvneta_port *pp = netdev_priv(ndev); + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + /* We only support QSGMII, SGMII, 802.3z and RGMII modes. +@@ -3847,11 +3845,12 @@ static void mvneta_validate(struct phyli + phylink_set(mask, Pause); + + /* Half-duplex at speeds higher than 100Mbit is unsupported */ +- if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { ++ if (state->interface != PHY_INTERFACE_MODE_2500BASEX) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + } +- if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { ++ ++ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) { + phylink_set(mask, 2500baseT_Full); + phylink_set(mask, 2500baseX_Full); + } +@@ -3866,11 +3865,6 @@ static void mvneta_validate(struct phyli + + linkmode_and(supported, supported, mask); + linkmode_and(state->advertising, state->advertising, mask); +- +- /* We can only operate at 2500BaseX or 1000BaseX. If requested +- * to advertise both, only report advertising at 2500BaseX. +- */ +- phylink_helper_basex_speed(state); + } + + static void mvneta_mac_pcs_get_state(struct phylink_config *config, diff --git a/target/linux/generic/backport-5.15/703-19-v5.17-net-mvneta-use-phylink_generic_validate.patch b/target/linux/generic/backport-5.15/703-19-v5.17-net-mvneta-use-phylink_generic_validate.patch new file mode 100644 index 00000000000000..209dfbc0de93f3 --- /dev/null +++ b/target/linux/generic/backport-5.15/703-19-v5.17-net-mvneta-use-phylink_generic_validate.patch @@ -0,0 +1,72 @@ +From 02a0988b98930491db95966fb8086072e47dabb6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 15 Nov 2021 10:00:32 +0000 +Subject: [PATCH] net: mvneta: use phylink_generic_validate() + +Convert mvneta to use phylink_generic_validate() for the bulk of its +validate() implementation. This network adapter has a restriction +that for 802.3z links, autonegotiation must be enabled. + +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/marvell/mvneta.c | 34 ++++----------------------- + 1 file changed, 4 insertions(+), 30 deletions(-) + +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -3824,8 +3824,6 @@ static void mvneta_validate(struct phyli + unsigned long *supported, + struct phylink_link_state *state) + { +- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +- + /* We only support QSGMII, SGMII, 802.3z and RGMII modes. + * When in 802.3z mode, we must have AN enabled: + * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... +@@ -3837,34 +3835,7 @@ static void mvneta_validate(struct phyli + return; + } + +- /* Allow all the expected bits */ +- phylink_set(mask, Autoneg); +- phylink_set_port_modes(mask); +- +- /* Asymmetric pause is unsupported */ +- phylink_set(mask, Pause); +- +- /* Half-duplex at speeds higher than 100Mbit is unsupported */ +- if (state->interface != PHY_INTERFACE_MODE_2500BASEX) { +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 1000baseX_Full); +- } +- +- if (state->interface == PHY_INTERFACE_MODE_2500BASEX) { +- phylink_set(mask, 2500baseT_Full); +- phylink_set(mask, 2500baseX_Full); +- } +- +- if (!phy_interface_mode_is_8023z(state->interface)) { +- /* 10M and 100M are only supported in non-802.3z mode */ +- phylink_set(mask, 10baseT_Half); +- phylink_set(mask, 10baseT_Full); +- phylink_set(mask, 100baseT_Half); +- phylink_set(mask, 100baseT_Full); +- } +- +- linkmode_and(supported, supported, mask); +- linkmode_and(state->advertising, state->advertising, mask); ++ phylink_generic_validate(config, supported, state); + } + + static void mvneta_mac_pcs_get_state(struct phylink_config *config, +@@ -5167,6 +5138,9 @@ static int mvneta_probe(struct platform_ + + pp->phylink_config.dev = &dev->dev; + pp->phylink_config.type = PHYLINK_NETDEV; ++ pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | ++ MAC_100 | MAC_1000FD | MAC_2500FD; ++ + phy_interface_set_rgmii(pp->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, + pp->phylink_config.supported_interfaces); diff --git a/target/linux/generic/backport-5.15/703-20-v5.17-net-mvneta-mark-as-a-legacy_pre_march2020-driver.patch b/target/linux/generic/backport-5.15/703-20-v5.17-net-mvneta-mark-as-a-legacy_pre_march2020-driver.patch new file mode 100644 index 00000000000000..31717565bf175c --- /dev/null +++ b/target/linux/generic/backport-5.15/703-20-v5.17-net-mvneta-mark-as-a-legacy_pre_march2020-driver.patch @@ -0,0 +1,29 @@ +From 2106be4fdf3223d9c5bd485e6ef094139e3197ba Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Sun, 12 Dec 2021 13:01:21 +0000 +Subject: [PATCH] net: mvneta: mark as a legacy_pre_march2020 driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mvneta provides mac_an_restart and mac_pcs_get_state methods, so needs +to be marked as a legacy driver. Marek spotted that mvneta had stopped +working in 2500base-X mode - thanks for reporting. + +Reported-by: Marek Behún +Signed-off-by: Russell King (Oracle) +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/marvell/mvneta.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/ethernet/marvell/mvneta.c ++++ b/drivers/net/ethernet/marvell/mvneta.c +@@ -5138,6 +5138,7 @@ static int mvneta_probe(struct platform_ + + pp->phylink_config.dev = &dev->dev; + pp->phylink_config.type = PHYLINK_NETDEV; ++ pp->phylink_config.legacy_pre_march2020 = true; + pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | + MAC_100 | MAC_1000FD | MAC_2500FD; + diff --git a/target/linux/generic/backport-5.15/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch b/target/linux/generic/backport-5.15/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch index eb84b45b5c45c8..dc149a742b1af4 100644 --- a/target/linux/generic/backport-5.15/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch +++ b/target/linux/generic/backport-5.15/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch @@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c -@@ -2302,7 +2302,7 @@ static const struct b53_chip_data b53_sw +@@ -2300,7 +2300,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5325_DEVICE_ID, .dev_name = "BCM5325", .vlans = 16, @@ -31,7 +31,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 2, .arl_buckets = 1024, .imp_port = 5, -@@ -2313,7 +2313,7 @@ static const struct b53_chip_data b53_sw +@@ -2311,7 +2311,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5365_DEVICE_ID, .dev_name = "BCM5365", .vlans = 256, @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 2, .arl_buckets = 1024, .imp_port = 5, -@@ -2324,7 +2324,7 @@ static const struct b53_chip_data b53_sw +@@ -2322,7 +2322,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5389_DEVICE_ID, .dev_name = "BCM5389", .vlans = 4096, @@ -49,7 +49,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2338,7 +2338,7 @@ static const struct b53_chip_data b53_sw +@@ -2336,7 +2336,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5395_DEVICE_ID, .dev_name = "BCM5395", .vlans = 4096, @@ -58,7 +58,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2352,7 +2352,7 @@ static const struct b53_chip_data b53_sw +@@ -2350,7 +2350,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5397_DEVICE_ID, .dev_name = "BCM5397", .vlans = 4096, @@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2366,7 +2366,7 @@ static const struct b53_chip_data b53_sw +@@ -2364,7 +2364,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM5398_DEVICE_ID, .dev_name = "BCM5398", .vlans = 4096, @@ -76,7 +76,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2380,7 +2380,7 @@ static const struct b53_chip_data b53_sw +@@ -2378,7 +2378,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM53115_DEVICE_ID, .dev_name = "BCM53115", .vlans = 4096, @@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .vta_regs = B53_VTA_REGS, -@@ -2394,7 +2394,7 @@ static const struct b53_chip_data b53_sw +@@ -2392,7 +2392,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM53125_DEVICE_ID, .dev_name = "BCM53125", .vlans = 4096, @@ -94,7 +94,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2436,7 +2436,7 @@ static const struct b53_chip_data b53_sw +@@ -2434,7 +2434,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM53010_DEVICE_ID, .dev_name = "BCM53010", .vlans = 4096, @@ -103,7 +103,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2478,7 +2478,7 @@ static const struct b53_chip_data b53_sw +@@ -2476,7 +2476,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM53018_DEVICE_ID, .dev_name = "BCM53018", .vlans = 4096, @@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2492,7 +2492,7 @@ static const struct b53_chip_data b53_sw +@@ -2490,7 +2490,7 @@ static const struct b53_chip_data b53_sw .chip_id = BCM53019_DEVICE_ID, .dev_name = "BCM53019", .vlans = 4096, @@ -121,7 +121,7 @@ Signed-off-by: Jakub Kicinski .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, -@@ -2634,7 +2634,6 @@ static int b53_switch_init(struct b53_de +@@ -2632,7 +2632,6 @@ static int b53_switch_init(struct b53_de dev->cpu_port = 5; } diff --git a/target/linux/generic/backport-5.15/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch b/target/linux/generic/backport-5.15/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch index 746a1e39782370..07d0ec03cf1792 100644 --- a/target/linux/generic/backport-5.15/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch +++ b/target/linux/generic/backport-5.15/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c -@@ -2300,7 +2300,6 @@ static const struct b53_chip_data b53_sw +@@ -2298,7 +2298,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 2, .arl_buckets = 1024, .imp_port = 5, @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski .duplex_reg = B53_DUPLEX_STAT_FE, }, { -@@ -2311,7 +2310,6 @@ static const struct b53_chip_data b53_sw +@@ -2309,7 +2308,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 2, .arl_buckets = 1024, .imp_port = 5, @@ -35,7 +35,7 @@ Signed-off-by: Jakub Kicinski .duplex_reg = B53_DUPLEX_STAT_FE, }, { -@@ -2322,7 +2320,6 @@ static const struct b53_chip_data b53_sw +@@ -2320,7 +2318,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -43,7 +43,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2336,7 +2333,6 @@ static const struct b53_chip_data b53_sw +@@ -2334,7 +2331,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -51,7 +51,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2350,7 +2346,6 @@ static const struct b53_chip_data b53_sw +@@ -2348,7 +2344,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -59,7 +59,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS_9798, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2364,7 +2359,6 @@ static const struct b53_chip_data b53_sw +@@ -2362,7 +2357,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS_9798, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2379,7 +2373,6 @@ static const struct b53_chip_data b53_sw +@@ -2377,7 +2371,6 @@ static const struct b53_chip_data b53_sw .arl_buckets = 1024, .vta_regs = B53_VTA_REGS, .imp_port = 8, @@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, .jumbo_size_reg = B53_JUMBO_MAX_SIZE, -@@ -2392,7 +2385,6 @@ static const struct b53_chip_data b53_sw +@@ -2390,7 +2383,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2406,7 +2398,6 @@ static const struct b53_chip_data b53_sw +@@ -2404,7 +2396,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2420,7 +2411,6 @@ static const struct b53_chip_data b53_sw +@@ -2418,7 +2409,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS_63XX, .duplex_reg = B53_DUPLEX_STAT_63XX, .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, -@@ -2434,7 +2424,6 @@ static const struct b53_chip_data b53_sw +@@ -2432,7 +2422,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2448,7 +2437,6 @@ static const struct b53_chip_data b53_sw +@@ -2446,7 +2435,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2462,7 +2450,6 @@ static const struct b53_chip_data b53_sw +@@ -2460,7 +2448,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2476,7 +2463,6 @@ static const struct b53_chip_data b53_sw +@@ -2474,7 +2461,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -131,7 +131,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2490,7 +2476,6 @@ static const struct b53_chip_data b53_sw +@@ -2488,7 +2474,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -139,7 +139,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2504,7 +2489,6 @@ static const struct b53_chip_data b53_sw +@@ -2502,7 +2487,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2518,7 +2502,6 @@ static const struct b53_chip_data b53_sw +@@ -2516,7 +2500,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -155,7 +155,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2547,7 +2530,6 @@ static const struct b53_chip_data b53_sw +@@ -2545,7 +2528,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 1024, .imp_port = 8, @@ -163,7 +163,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2561,7 +2543,6 @@ static const struct b53_chip_data b53_sw +@@ -2559,7 +2541,6 @@ static const struct b53_chip_data b53_sw .arl_bins = 4, .arl_buckets = 256, .imp_port = 8, @@ -171,7 +171,7 @@ Signed-off-by: Jakub Kicinski .vta_regs = B53_VTA_REGS, .duplex_reg = B53_DUPLEX_STAT_GE, .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2587,7 +2568,6 @@ static int b53_switch_init(struct b53_de +@@ -2585,7 +2566,6 @@ static int b53_switch_init(struct b53_de dev->vta_regs[2] = chip->vta_regs[2]; dev->jumbo_pm_reg = chip->jumbo_pm_reg; dev->imp_port = chip->imp_port; @@ -179,7 +179,7 @@ Signed-off-by: Jakub Kicinski dev->num_vlans = chip->vlans; dev->num_arl_bins = chip->arl_bins; dev->num_arl_buckets = chip->arl_buckets; -@@ -2619,13 +2599,6 @@ static int b53_switch_init(struct b53_de +@@ -2617,13 +2597,6 @@ static int b53_switch_init(struct b53_de break; #endif } diff --git a/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch index 8f2e6e0e0e8a16..ffa44f09607ccd 100644 --- a/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch +++ b/target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch @@ -9,7 +9,7 @@ Subject: [PATCH] net/dsa/mv88e6xxx: disable ATU violation --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2981,6 +2981,9 @@ static int mv88e6xxx_setup_port(struct m +@@ -2980,6 +2980,9 @@ static int mv88e6xxx_setup_port(struct m else reg = 1 << port; diff --git a/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch index 662b956e4c07e6..8a718a02f213ec 100644 --- a/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch +++ b/target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch @@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -6320,6 +6320,7 @@ static int mv88e6xxx_register_switch(str +@@ -6319,6 +6319,7 @@ static int mv88e6xxx_register_switch(str ds->ops = &mv88e6xxx_switch_ops; ds->ageing_time_min = chip->info->age_time_coeff; ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; From 4d8b42d8a7774070ac0439915f8de1430db9a8e3 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Thu, 25 Aug 2022 20:26:11 +0200 Subject: [PATCH 35/91] ipq40xx: point to externally compiled dtbs in recipes Adjusting dts will cause a rebuild of whole kernel as the buildroot considers this a part of kernel source. It's a royal PITA when trying to prepare support for new device, since this takes a lot of time on slower systems. As it stands, buildroot itself, with own rule, also compiles dtbs and the results are $(KDIR)/image-$(DEVICE_DTS).dtb. With setting DEVICE_DTS_DIR to directory holding the device dts (similarly to some other targets), buildroot doesn't consider changed dts as part of kernel source and rebuilds only dtb. This really speeds up development. And since the kernel built dts are no longer used, drop the paches adding dtses to its build. Signed-off-by: Tomasz Maciej Nowak Reviewed-by: Robert Marko --- target/linux/ipq40xx/image/chromium.mk | 2 +- target/linux/ipq40xx/image/generic.mk | 20 ++-- .../901-arm-boot-add-dts-files.patch | 92 ------------------- .../901-arm-boot-add-dts-files.patch | 91 ------------------ 4 files changed, 11 insertions(+), 194 deletions(-) delete mode 100644 target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch diff --git a/target/linux/ipq40xx/image/chromium.mk b/target/linux/ipq40xx/image/chromium.mk index 567a5e7ca5c7af..2abd2df02ae4dd 100644 --- a/target/linux/ipq40xx/image/chromium.mk +++ b/target/linux/ipq40xx/image/chromium.mk @@ -26,7 +26,7 @@ define Device/google_wifi DEVICE_MODEL := WiFi (Gale) SOC := qcom-ipq4019 KERNEL_SUFFIX := -fit-zImage.itb.vboot - KERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb | cros-vboot + KERNEL = kernel-bin | fit none $$(KDIR)/image-$$(DEVICE_DTS).dtb | cros-vboot KERNEL_NAME := zImage IMAGES += factory.bin IMAGE/factory.bin := cros-gpt | append-kernel-part | append-rootfs diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 792122f7a1ae18..6daebd5ed0f5ec 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -5,19 +5,19 @@ DEVICE_VARS += WRGG_DEVNAME WRGG_SIGNATURE define Device/FitImage KERNEL_SUFFIX := -fit-uImage.itb - KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb KERNEL_NAME := Image endef define Device/FitImageLzma KERNEL_SUFFIX := -fit-uImage.itb - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb KERNEL_NAME := Image endef define Device/FitzImage KERNEL_SUFFIX := -fit-zImage.itb - KERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | fit none $$(KDIR)/image-$$(DEVICE_DTS).dtb KERNEL_NAME := zImage endef @@ -308,8 +308,8 @@ TARGET_DEVICES += buffalo_wtr-m2133hp define Device/cellc_rtl30vw KERNEL_SUFFIX := -fit-zImage.itb - KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb - KERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb | uImage lzma | pad-to 2048 + KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb + KERNEL = kernel-bin | fit none $$(KDIR)/image-$$(DEVICE_DTS).dtb | uImage lzma | pad-to 2048 KERNEL_NAME := zImage KERNEL_IN_UBI := IMAGES := nand-factory.bin nand-sysupgrade.bin @@ -376,7 +376,7 @@ define Device/devolo_magic-2-wifi-next # If the bootloader sees 0xDEADC0DE and this trailer at the 64k boundary of a TFTP image # it will bootm it, just like we want for the initramfs. - KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to 64k |\ + KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to 64k |\ append-string -e '\xDE\xAD\xC0\xDE{"fl_initramfs":""}\x00' IMAGE_SIZE := 26624k @@ -832,7 +832,7 @@ define Device/openmesh_a42 SOC := qcom-ipq4018 DEVICE_DTS_CONFIG := config@om.a42 BLOCKSIZE := 64k - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) IMAGE_SIZE := 15616k IMAGES += factory.bin IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42 @@ -847,7 +847,7 @@ define Device/openmesh_a62 SOC := qcom-ipq4019 DEVICE_DTS_CONFIG := config@om.a62 BLOCKSIZE := 64k - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) IMAGE_SIZE := 15552k IMAGES += factory.bin IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A62 @@ -889,7 +889,7 @@ define Device/plasmacloud_pa1200 SOC := qcom-ipq4018 DEVICE_DTS_CONFIG := config@pc.pa1200 BLOCKSIZE := 64k - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) IMAGE_SIZE := 15616k IMAGES += factory.bin IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA1200 @@ -904,7 +904,7 @@ define Device/plasmacloud_pa2200 SOC := qcom-ipq4019 DEVICE_DTS_CONFIG := config@pc.pa2200 BLOCKSIZE := 64k - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE) IMAGE_SIZE := 15552k IMAGES += factory.bin IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA2200 diff --git a/target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch deleted file mode 100644 index 952092d1f729ad..00000000000000 --- a/target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,92 +0,0 @@ -From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 11:03:18 +0100 -Subject: [PATCH] arm: boot: add dts files - -Signed-off-by: John Crispin ---- - arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -904,11 +904,79 @@ dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ -+ qcom-ipq4018-a42.dtb \ -+ qcom-ipq4018-ap120c-ac.dtb \ -+ qcom-ipq4018-dap-2610.dtb \ -+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \ -+ qcom-ipq4018-magic-2-wifi-next.dtb \ -+ qcom-ipq4018-ea6350v3.dtb \ -+ qcom-ipq4018-eap1300.dtb \ -+ qcom-ipq4018-ecw5211.dtb \ -+ qcom-ipq4018-emd1.dtb \ -+ qcom-ipq4018-emr3500.dtb \ -+ qcom-ipq4018-ens620ext.dtb \ -+ qcom-ipq4018-ex6100v2.dtb \ -+ qcom-ipq4018-ex6150v2.dtb \ -+ qcom-ipq4018-fritzbox-4040.dtb \ -+ qcom-ipq4018-gl-ap1300.dtb \ -+ qcom-ipq4018-jalapeno.dtb \ -+ qcom-ipq4018-meshpoint-one.dtb \ -+ qcom-ipq4018-cap-ac.dtb \ -+ qcom-ipq4018-hap-ac2.dtb \ -+ qcom-ipq4018-sxtsq-5-ac.dtb \ -+ qcom-ipq4018-nbg6617.dtb \ -+ qcom-ipq4019-oap100.dtb \ -+ qcom-ipq4018-pa1200.dtb \ -+ qcom-ipq4018-rt-ac58u.dtb \ -+ qcom-ipq4018-rutx10.dtb \ -+ qcom-ipq4018-wac510.dtb \ -+ qcom-ipq4018-wap-ac.dtb \ -+ qcom-ipq4018-whw01-v1.dtb \ -+ qcom-ipq4018-wre6606.dtb \ -+ qcom-ipq4018-wrtq-329acn.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ -+ qcom-ipq4019-a62.dtb \ -+ qcom-ipq4019-cm520-79f.dtb \ -+ qcom-ipq4019-e2600ac-c1.dtb \ -+ qcom-ipq4019-e2600ac-c2.dtb \ -+ qcom-ipq4019-ea8300.dtb \ -+ qcom-ipq4019-eap2200.dtb \ -+ qcom-ipq4019-fritzbox-7530.dtb \ -+ qcom-ipq4019-fritzrepeater-1200.dtb \ -+ qcom-ipq4019-fritzrepeater-3000.dtb \ -+ qcom-ipq4019-habanero-dvk.dtb \ -+ qcom-ipq4019-hap-ac3.dtb \ -+ qcom-ipq4019-map-ac2200.dtb \ -+ qcom-ipq4019-lhgg-60ad.dtb \ -+ qcom-ipq4019-mf286d.dtb \ -+ qcom-ipq4019-mr8300.dtb \ -+ qcom-ipq4019-pa2200.dtb \ -+ qcom-ipq4019-r619ac-64m.dtb \ -+ qcom-ipq4019-r619ac-128m.dtb \ -+ qcom-ipq4019-rbr50.dtb \ -+ qcom-ipq4019-rbs50.dtb \ -+ qcom-ipq4019-rt-ac42u.dtb \ -+ qcom-ipq4019-rtl30vw.dtb \ -+ qcom-ipq4019-srr60.dtb \ -+ qcom-ipq4019-srs60.dtb \ -+ qcom-ipq4019-u4019-32m.dtb \ -+ qcom-ipq4019-wifi.dtb \ -+ qcom-ipq4019-wpj419.dtb \ -+ qcom-ipq4019-wtr-m2133hp.dtb \ -+ qcom-ipq4019-x1pro.dtb \ -+ qcom-ipq4028-wpj428.dtb \ -+ qcom-ipq4029-ap-303.dtb \ -+ qcom-ipq4029-ap-303h.dtb \ -+ qcom-ipq4029-ap-365.dtb \ -+ qcom-ipq4029-gl-b1300.dtb \ -+ qcom-ipq4019-gl-b2200.dtb \ -+ qcom-ipq4029-gl-s1300.dtb \ -+ qcom-ipq4029-mr33.dtb \ -+ qcom-ipq4029-mr74.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-ipq8064-rb3011.dtb \ - qcom-msm8660-surf.dtb \ diff --git a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch b/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch deleted file mode 100644 index 78b97393d565c8..00000000000000 --- a/target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch +++ /dev/null @@ -1,91 +0,0 @@ -From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 11:03:18 +0100 -Subject: [PATCH] arm: boot: add dts files - -Signed-off-by: John Crispin ---- - arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -952,11 +952,78 @@ dtb-$(CONFIG_ARCH_QCOM) += \ - qcom-ipq4018-ap120c-ac.dtb \ - qcom-ipq4018-ap120c-ac-bit.dtb \ - qcom-ipq4018-jalapeno.dtb \ -+ qcom-ipq4018-a42.dtb \ -+ qcom-ipq4018-ap120c-ac.dtb \ -+ qcom-ipq4018-dap-2610.dtb \ -+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \ -+ qcom-ipq4018-magic-2-wifi-next.dtb \ -+ qcom-ipq4018-ea6350v3.dtb \ -+ qcom-ipq4018-eap1300.dtb \ -+ qcom-ipq4018-ecw5211.dtb \ -+ qcom-ipq4018-emd1.dtb \ -+ qcom-ipq4018-emr3500.dtb \ -+ qcom-ipq4018-ens620ext.dtb \ -+ qcom-ipq4018-ex6100v2.dtb \ -+ qcom-ipq4018-ex6150v2.dtb \ -+ qcom-ipq4018-fritzbox-4040.dtb \ -+ qcom-ipq4018-gl-ap1300.dtb \ -+ qcom-ipq4018-meshpoint-one.dtb \ -+ qcom-ipq4018-cap-ac.dtb \ -+ qcom-ipq4018-hap-ac2.dtb \ -+ qcom-ipq4018-sxtsq-5-ac.dtb \ -+ qcom-ipq4018-nbg6617.dtb \ -+ qcom-ipq4019-oap100.dtb \ -+ qcom-ipq4018-pa1200.dtb \ -+ qcom-ipq4018-rt-ac58u.dtb \ -+ qcom-ipq4018-rutx10.dtb \ -+ qcom-ipq4018-wac510.dtb \ -+ qcom-ipq4018-wap-ac.dtb \ -+ qcom-ipq4018-whw01-v1.dtb \ -+ qcom-ipq4018-wre6606.dtb \ -+ qcom-ipq4018-wrtq-329acn.dtb \ - qcom-ipq4019-ap.dk01.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c1.dtb \ - qcom-ipq4019-ap.dk04.1-c3.dtb \ - qcom-ipq4019-ap.dk07.1-c1.dtb \ - qcom-ipq4019-ap.dk07.1-c2.dtb \ -+ qcom-ipq4019-a62.dtb \ -+ qcom-ipq4019-cm520-79f.dtb \ -+ qcom-ipq4019-e2600ac-c1.dtb \ -+ qcom-ipq4019-e2600ac-c2.dtb \ -+ qcom-ipq4019-ea8300.dtb \ -+ qcom-ipq4019-eap2200.dtb \ -+ qcom-ipq4019-fritzbox-7530.dtb \ -+ qcom-ipq4019-fritzrepeater-1200.dtb \ -+ qcom-ipq4019-fritzrepeater-3000.dtb \ -+ qcom-ipq4019-habanero-dvk.dtb \ -+ qcom-ipq4019-hap-ac3.dtb \ -+ qcom-ipq4019-map-ac2200.dtb \ -+ qcom-ipq4019-lhgg-60ad.dtb \ -+ qcom-ipq4019-mf286d.dtb \ -+ qcom-ipq4019-mr8300.dtb \ -+ qcom-ipq4019-pa2200.dtb \ -+ qcom-ipq4019-r619ac-64m.dtb \ -+ qcom-ipq4019-r619ac-128m.dtb \ -+ qcom-ipq4019-rbr50.dtb \ -+ qcom-ipq4019-rbs50.dtb \ -+ qcom-ipq4019-rt-ac42u.dtb \ -+ qcom-ipq4019-rtl30vw.dtb \ -+ qcom-ipq4019-srr60.dtb \ -+ qcom-ipq4019-srs60.dtb \ -+ qcom-ipq4019-u4019-32m.dtb \ -+ qcom-ipq4019-wifi.dtb \ -+ qcom-ipq4019-wpj419.dtb \ -+ qcom-ipq4019-wtr-m2133hp.dtb \ -+ qcom-ipq4019-x1pro.dtb \ -+ qcom-ipq4028-wpj428.dtb \ -+ qcom-ipq4029-ap-303.dtb \ -+ qcom-ipq4029-ap-303h.dtb \ -+ qcom-ipq4029-ap-365.dtb \ -+ qcom-ipq4029-gl-b1300.dtb \ -+ qcom-ipq4019-gl-b2200.dtb \ -+ qcom-ipq4029-gl-s1300.dtb \ -+ qcom-ipq4029-mr33.dtb \ -+ qcom-ipq4029-mr74.dtb \ - qcom-ipq8064-ap148.dtb \ - qcom-ipq8064-rb3011.dtb \ - qcom-msm8226-samsung-s3ve3g.dtb \ From 02f81494bb5c05ffc16025198792f99bdeac8a77 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 29 Aug 2022 17:36:46 +0200 Subject: [PATCH 36/91] ipq-wifi: add Extreme Networks WS-AP3915i Signed-off-by: David Bauer --- package/firmware/ipq-wifi/Makefile | 2 ++ .../board-extreme-networks_ws-ap3915i.qca4019 | Bin 0 -> 24348 bytes 2 files changed, 2 insertions(+) create mode 100644 package/firmware/ipq-wifi/board-extreme-networks_ws-ap3915i.qca4019 diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index ebd10cd2ecc28b..44d6e2a086d86f 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -29,6 +29,7 @@ ALLWIFIBOARDS:= \ devolo_magic-2-wifi-next \ edgecore_ecw5410 \ edgecore_oap100 \ + extreme-networks_ws-ap3915i \ glinet_gl-ap1300 \ glinet_gl-s1300 \ linksys_ea8300 \ @@ -100,6 +101,7 @@ $(eval $(call generate-ipq-wifi-package,aruba_ap-365,Aruba AP-365)) $(eval $(call generate-ipq-wifi-package,devolo_magic-2-wifi-next,devolo Magic 2 WiFi next)) $(eval $(call generate-ipq-wifi-package,edgecore_ecw5410,Edgecore ECW5410)) $(eval $(call generate-ipq-wifi-package,edgecore_oap100,Edgecore OAP100)) +$(eval $(call generate-ipq-wifi-package,extreme-networks_ws-ap3915i,Edgecore OAP100)) $(eval $(call generate-ipq-wifi-package,glinet_gl-ap1300,GL.iNet GL-AP1300)) $(eval $(call generate-ipq-wifi-package,glinet_gl-s1300,GL.iNet GL-S1300)) $(eval $(call generate-ipq-wifi-package,linksys_ea8300,Linksys EA8300)) diff --git a/package/firmware/ipq-wifi/board-extreme-networks_ws-ap3915i.qca4019 b/package/firmware/ipq-wifi/board-extreme-networks_ws-ap3915i.qca4019 new file mode 100644 index 0000000000000000000000000000000000000000..8aeedf07cba67bba50e00446f9867afbcc9cdb83 GIT binary patch literal 24348 zcmeHPdr(tX8b1jj>SE!BfCzXAAv}T*AfN_`@{|ThfubS-7J&+qXaoY`Vd#P#9~2@Y zPz#0#S_b9O6p?Z90kK$HJEQFWv48CBA8ltJ-I;aQcCC;l$_@>xDv$^Zj#uv9TT>}15*G!h7FAZ4N{&_pAKVul zn;sq+wp|GOCc*w_uy0xjuY^PbHuaQoqmO*XKD*OdE)eyy63z)L9b*lcaqs?X3`TXzH}X|W(S!4^2p zzO+ZM7`6I*8U6YZ&vyc~jdSDDfaV1oX}TsJx*v5el%}v$W{G=${ z;gNqJn7pAl2S<1-DRS}?=pe!!`e7#}*(sa=*j-y~S#|~|bk@ONKfYJgYN5QsME@}1 zppS>~+G;?__{>&TYhQCgb!3r$rf14jyQDr*%sS)}H!)b=m3THl;+Eevl+zV?mR8|h z(BD)bjV$!rw>9Zr>+!n1!k`?NJ)aNMewcQaRk8J*J44l7Z#4&3dlrwKE2-I2#LPq@ z??Sr-5i7@e&$WJGC$DK+wMWVAkE?n@>b=UG^H&y1M6_B2?CdxEYLg@4?6P@_$5!nJ zzD|jK#{QhZe&7WWmXXP15|-Q8z^~w3V4$C$roq}Yd;$g;f+9#P8jFOX zVMv+uME$AvTiQDpDu6pH_smi#D1}9NOhMdHca}Tf33Wo;&^R=X756v}Nk)@d$@~~J z2H~M>l+9v4W+S`MU94UFP&5?bpmRYeuNqh9V&Zb=q9W7<=VvjHIHS(boDmPygXO`G zN8_KxBPnPKD}^79hCd5OqR=Q-6kl@^baQ+t4fM;NW6QSeedVxj@?E0ne6<)=4c;nC zs;-7>QeqB^Spoz~1WG0lAeM#+VDy^TBuaV+5ETLe0s#U60s#U60)aJ*z-IPl#EbGK z`%NT`vXi|NiKeXA3dksIyE^(nH`m_!n^!IzV}n*KHpUu0g~Zg&MBv2&F|&i^GS_D< zm>y-ZcBXr<$|L;T68YE@0AN`o?;U$$Sh9kHf`S4A7&O#6H5goAV1OTt&q_5I-fVnU zsafTs)CnpEAi()sW&;3Wzz_0sydWEh0jW@Qn6R>y5(emWPfxmmbinq7t#o>BI|Fbz zB=AEi03G%SDJBAdfb|IA0EwiOI_gA1sH+Wumm>~TGWjsvfq=Wq zWZU&0Lb(D(JI`?_OKIb0!4KEou`f-P{(ioUUovTS?lgOKn%y~m`u?ok{KF;k){f5Z z-oER@BV*$epFaHZiTMX~_VLWSa$Paj0N)4YQyR59q4*vsKdw=`3ySZ5^4X2r9Z>T@ zH0iPW(OogiV08t$m_6gv%)H{3iILMiAXAC2YUyyhmw5>doAok`#q;ESIRAp zxg7j3vpM)azax<#0l%gdXN0@-LWJ@mm)pJpDmbV6=Q;R-W#i!A!~@XDewKr;W2dja znuCubx*i%Xy!|>GJKH%nJOH;|noG?$%E8wi2>bsA9kBrSpGu_yENR8n)fHe#D`wU= zLD9OtZb=90Ot{8Sd#S&t-glw7rn@${j?71C!rrj?pBnkhuwB32-90_s-Rt0>Pmj^J zF{idBw|0q1FJ_5YAxeu0+cGvtBLMs02ej0U46glwgr_sGJo60+)G)|kaF`5+z9)kx z<2K+K*A_TV*n;TYb^vj)v9q^K2t+Rg0t5nU4uN?Ny)h2{fBx~;Z@&Kej}R3NFCXLJ zzx>zV|NQjn-(Z_54nCI~5vt+v&&>S$d&~3kjdAcpLRc&;VS5kQujq7q7h>sJ&^G)> zc{h%^l~x`5VtQs4nLB6kYbcM#mx3ptbBdwsv*-_n5v!3cfEt3;W@F z;)(tp#(d4#`$f0yt5J1_vPzaI2>I%^TA{3yFazP@;S3RoglgmT`jwkki zWB2a+2LR~Mu9V6S2w2l2stfW`QHFq{8dLU)M1oXKkovdEHknuu$Dv^k6I1^F05=oK zGG&?5cU0YSsc4^Ir|ORUqDaC^;IN@XyX=_OVRFi!38wF~>M0n~^lg5@qWDIDhXE!8EtM3ly3U=E*7F(FDf)m_R8d7dm`dK@0C zkmZV!VVGASmN6U@9_?0Ei{g1(aEFI*4(5mzUg{GeE#?FgC=n=`Kwvd24HHu%n%67> zoukLEMRx=@dQ@Fe{aTT5-oI|k@yd&dr2QCLUx>vnXFgQ~EQA|rf-R2UxBK34wrOUxhdv6aE zw(Y8?9d*h1?6zz$P2qpiRjj%py&Ba-uc91k>PkBkQROCZ;N2WL^a1BRFR@Erze?DX zaGoYb@&|@0l-$$wawox9kEA8OE=cT}@#vG}=Ahaw#ZCtYMvn9*wlPjni#rF8Uyg3_ ztDzQL>k>BZkp>=dPU*j1dMWCZkA#|cX`rAhw%NOalGo8Myu>}@Q{kL@uI1pn5h8jH zC1!N6qC53mK($-Znq4@=#0dme0Rl^XA_sgf*1Qx|9;^ZS_=LKi;ZCfexiv$z$gL>DEKc7%oa-kv9z5*7;CNi zN)A5u;2HP>`0NvC2yK<2Vg2h}!@c)|ESf&}1WJYjOppZ=13CE{`AETIy|(?A4i@;*`j7{ Date: Mon, 29 Aug 2022 14:30:01 +0200 Subject: [PATCH 37/91] ipq40xx: add support for Extreme Networks WS-AP3915i Hardware -------- Qualcomm IPQ4029 WiSoC 2T2R 802.11 abgn 2T2R 802.11 nac Macronix MX25L25635E SPI-NOR (32M) 512M DDR3 RAM 1x Gigabit LAN 1x Cisco RJ-45 Console port Settings: 115200 8N1 Installation ------------ 1. Attach to the Console port. Power up the device and press the s key to interrupt autoboot. 2. The default username / password to the bootloader is admin / new2day 3. Update the bootcommand to allow loading OpenWrt. $ setenv ramboot_openwrt "setenv serverip 192.168.1.66; setenv ipaddr 192.168.1.1; tftpboot 0x86000000 openwrt-3915.bin; bootm" $ setenv boot_openwrt "sf probe; sf read 0x88000000 0x280000 0xc00000; bootm 0x88000000" $ setenv bootcmd "run boot_openwrt" $ saveenv 4. Download the OpenWrt initramfs image. Serve it using a TFTP server as "openwrt-3915.bin" at 192.1681.66. 5. Download & boot the OpenWrt initramfs image on the access point. $ run ramboot_openwrt 6. Wait for OpenWrt to start. 7. Download and transfer the sysupgrade image to the device using e.g. SCP. 8. Install OpenWrt to the device using "sysupgrade" $ sysupgrade -n /path/to/openwrt.bin Signed-off-by: David Bauer --- .../ipq40xx/base-files/etc/board.d/02_network | 1 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 8 + .../lib/preinit/05_set_iface_mac_ipq40xx.sh | 3 + .../arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts | 272 ++++++++++++++++++ target/linux/ipq40xx/image/generic.mk | 12 + 5 files changed, 296 insertions(+) create mode 100644 target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index 5843987627b0ba..a468c62b3c5c81 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -28,6 +28,7 @@ ipq40xx_setup_interfaces() dlink,dap-2610 |\ engenius,eap1300|\ engenius,emd1|\ + extreme-networks,ws-ap3915i|\ meraki,mr33|\ meraki,mr74|\ mikrotik,lhgg-60ad|\ diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index f1c424a28d2252..b488bf5ddb1de7 100644 --- a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -104,6 +104,10 @@ case "$FIRMWARE" in caldata_extract "ART" 0x1000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2) ;; + extreme-networks,ws-ap3915i) + caldata_extract "ART" 0x1000 0x2f20 + ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR0) + ;; linksys,ea8300 |\ linksys,mr8300) caldata_extract "ART" 0x1000 0x2f20 @@ -186,6 +190,10 @@ case "$FIRMWARE" in caldata_extract "ART" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 3) ;; + extreme-networks,ws-ap3915i) + caldata_extract "ART" 0x5000 0x2f20 + ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR1) + ;; linksys,ea8300 |\ linksys,mr8300) caldata_extract "ART" 0x5000 0x2f20 diff --git a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh index ba1c1963980ecc..940af0528d513f 100644 --- a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh +++ b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh @@ -15,6 +15,9 @@ preinit_set_mac_address() { base_mac=$(cat /sys/class/net/eth0/address) ip link set dev eth1 address $(macaddr_add "$base_mac" 1) ;; + extreme-networks,ws-ap3915i) + ip link set dev eth0 address $(mtd_get_mac_ascii CFG1 ethaddr) + ;; linksys,ea8300|\ linksys,mr8300) base_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts new file mode 100644 index 00000000000000..c14023559be098 --- /dev/null +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap3915i.dts @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include "qcom-ipq4019.dtsi" +#include +#include +#include + +/ { + model = "Extreme Networks WS-AP3915i"; + compatible = "extreme-networks,ws-ap3915i"; + + aliases { + led-boot = &led_system_green; + led-failsafe = &led_system_amber; + led-running = &led_system_green; + led-upgrade = &led_system_amber; + label-mac-device = &gmac0; + }; + + soc { + rng@22000 { + status = "okay"; + }; + + mdio@90000 { + status = "okay"; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + }; + + ess-psgmii@98000 { + status = "okay"; + }; + + tcsr@1949000 { + compatible = "qcom,tcsr"; + reg = <0x1949000 0x100>; + qcom,wifi_glb_cfg = ; + }; + + ess_tcsr@1953000 { + compatible = "qcom,tcsr"; + reg = <0x1953000 0x1000>; + qcom,ess-interface-select = ; + }; + + tcsr@1957000 { + compatible = "qcom,tcsr"; + reg = <0x1957000 0x100>; + qcom,wifi_noc_memtype_m0_m2 = ; + }; + + crypto@8e3a000 { + status = "okay"; + }; + + watchdog@b017000 { + status = "okay"; + }; + + ess-switch@c000000 { + status = "okay"; + switch_lan_bmp = <0x20>; + switch_wan_bmp = <0x00>; + }; + + edma@c080000 { + status = "okay"; + qcom,num_gmac = <1>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system_green: system_green { + label = "green:system"; + gpios = <&tlmm 49 GPIO_ACTIVE_LOW>; + }; + + led_system_amber: system_amber { + label = "amber:system"; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + }; + + led_wlan24_green: wlan24_green { + label = "green:wlan24"; + gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + led_wlan24_amber: wlan24_amber { + label = "amber:wlan24"; + gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + }; + + led_wlan5_green: wlan5_green { + label = "green:wlan5"; + gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + led_wlan5_amber: wlan5_amber { + label = "amber:wlan5"; + gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + }; + + iot { + label = "blue:iot"; + gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_uart1 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&tlmm { + mdio_pins: mdio_pinmux { + mux_1 { + pins = "gpio6"; + function = "mdio"; + bias-pull-up; + }; + mux_2 { + pins = "gpio7"; + function = "mdc"; + bias-pull-up; + }; + }; + + spi_0_pins: spi_0_pinmux { + pin { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + drive-strength = <12>; + bias-disable; + }; + pin_cs { + function = "gpio"; + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + serial_pins: serial_0_pinmux { + mux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; +}; + +&wifi0 { + status = "okay"; + qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i"; +}; + +&wifi1 { + status = "okay"; + qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i"; +}; + +&blsp1_spi1 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Layout for 0x0 - 0xe0000 unknown */ + + partition@e0000 { + label = "CFG1"; + reg = <0xe0000 0x10000>; + read-only; + }; + + partition@f0000 { + label = "BootBAK"; + reg = <0xf0000 0x70000>; + read-only; + }; + + partition@160000 { + label = "WINGCFG1"; + reg = <0x160000 0x10000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x170000 0x10000>; + read-only; + }; + + partition@180000 { + label = "BootPRI"; + reg = <0x180000 0x70000>; + read-only; + }; + + partition@1f0000 { + label = "WINGCFG2"; + reg = <0x1f0000 0x10000>; + read-only; + }; + + partition@200000 { + label = "FS"; + reg = <0x200000 0x80000>; + read-only; + }; + + partition@280000 { + label = "firmware"; + reg = <0x280000 0x1d60000>; + }; + + partition@1fe0000 { + label = "CFG2"; + reg = <0x1fe0000 0x10000>; + read-only; + }; + }; + }; +}; + +&gmac0 { + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <1>; + qcom,forced_speed = <1000>; + qcom,forced_duplex = <1>; + vlan_tag = <1 0x20>; +}; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 6daebd5ed0f5ec..e8f8fa27b94027 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -519,6 +519,18 @@ define Device/engenius_ens620ext endef TARGET_DEVICES += engenius_ens620ext +define Device/extreme-networks_ws-ap3915i + $(call Device/FitImage) + DEVICE_VENDOR := Extreme Networks + DEVICE_MODEL := WS-AP3915i + IMAGE_SIZE := 30080k + SOC := qcom-ipq4029 + BLOCKSIZE := 128k + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata + DEVICE_PACKAGES := ipq-wifi-extreme-networks_ws-ap3915i +endef +TARGET_DEVICES += extreme-networks_ws-ap3915i + define Device/ezviz_cs-w3-wd1200g-eup $(call Device/FitImage) DEVICE_VENDOR := EZVIZ From f54ac98f8cec676761e5144ae06640b8007b4b04 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Fri, 19 Aug 2022 18:59:36 +0200 Subject: [PATCH 38/91] ath79: add low_mem to tiny image Devices with SMALL_FLASH enabled have "SQUASHFS_BLOCK_SIZE=1024" in their config. This significantly increases the cache memory required by squashfs [0]. This commit enables low_mem leading to a much better performance because the SQUASHFS_BLOCK_SIZE is reduced to 256. Example Nanostation M5 (XM): The image size increases by 128 KiB. However, the memory statisitcs look much better: Default tiny build: ------ MemTotal: 26020 kB MemFree: 5648 kB MemAvailable: 6112 kB Buffers: 0 kB Cached: 3044 kB low_mem enabled: ----- MemTotal: 26976 kB MemFree: 6748 kB MemAvailable: 11504 kB Buffers: 0 kB Cached: 7204 kB [0] - https://github.com/freifunk-gluon/gluon/commit/7e8af99cf504ca1dc389f282a0c94f4a911571be Signed-off-by: Nick Hainke --- target/linux/ath79/tiny/target.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ath79/tiny/target.mk b/target/linux/ath79/tiny/target.mk index 91f135b56eda45..28e02f7a674c43 100644 --- a/target/linux/ath79/tiny/target.mk +++ b/target/linux/ath79/tiny/target.mk @@ -1,5 +1,5 @@ BOARDNAME:=Devices with small flash -FEATURES += small_flash +FEATURES += low_mem small_flash DEFAULT_PACKAGES += wpad-basic-wolfssl From ae6bfb7d67c12a4e9d2c1e3f6366de5cef7b61e3 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 23 Aug 2022 18:44:21 +0200 Subject: [PATCH 39/91] ath79: tiny: add 5.15 support for tiny subtarget Tested on Ubiquiti Nanostation M5 XM with low_mem. Signed-off-by: Nick Hainke --- target/linux/ath79/tiny/target.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/ath79/tiny/target.mk b/target/linux/ath79/tiny/target.mk index 28e02f7a674c43..8241aacd3a75fe 100644 --- a/target/linux/ath79/tiny/target.mk +++ b/target/linux/ath79/tiny/target.mk @@ -3,6 +3,8 @@ FEATURES += low_mem small_flash DEFAULT_PACKAGES += wpad-basic-wolfssl +KERNEL_TESTING_PATCHVER:=5.15 + define Target/Description Build firmware images for Atheros AR71xx/AR913x/AR934x based boards with small flash endef From 431526be7c3a9a1ee981c99496f610c23d6ea73d Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Tue, 23 Aug 2022 19:14:47 +0200 Subject: [PATCH 40/91] ath79: move 5.15 testing kernel to common Makefile All subtargets are using now 5.15 as testing kernel. Move KERNEL_TESTING_PATCHVER:=5.15 to the common Makefile. Signed-off-by: Nick Hainke --- target/linux/ath79/Makefile | 1 + target/linux/ath79/generic/target.mk | 2 -- target/linux/ath79/mikrotik/target.mk | 2 -- target/linux/ath79/nand/target.mk | 2 -- target/linux/ath79/tiny/target.mk | 2 -- 5 files changed, 1 insertion(+), 8 deletions(-) diff --git a/target/linux/ath79/Makefile b/target/linux/ath79/Makefile index dd57d9fed9311a..20dae789af19f4 100644 --- a/target/linux/ath79/Makefile +++ b/target/linux/ath79/Makefile @@ -9,6 +9,7 @@ SUBTARGETS:=generic mikrotik nand tiny FEATURES:=ramdisk squashfs usbgadget KERNEL_PATCHVER:=5.10 +KERNEL_TESTING_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/ath79/generic/target.mk b/target/linux/ath79/generic/target.mk index af330b09b8d68d..4e53c8926053dc 100644 --- a/target/linux/ath79/generic/target.mk +++ b/target/linux/ath79/generic/target.mk @@ -2,8 +2,6 @@ BOARDNAME:=Generic DEFAULT_PACKAGES += wpad-basic-wolfssl -KERNEL_TESTING_PATCHVER:=5.15 - define Target/Description Build firmware images for generic Atheros AR71xx/AR913x/AR934x based boards. endef diff --git a/target/linux/ath79/mikrotik/target.mk b/target/linux/ath79/mikrotik/target.mk index 697aa003c82c8b..f5df9044875060 100644 --- a/target/linux/ath79/mikrotik/target.mk +++ b/target/linux/ath79/mikrotik/target.mk @@ -5,8 +5,6 @@ IMAGES_DIR := ../../.. DEFAULT_PACKAGES += wpad-basic-wolfssl -KERNEL_TESTING_PATCHVER:=5.15 - define Target/Description Build firmware images for MikroTik devices based on Qualcomm Atheros MIPS SoCs (AR71xx, AR72xx, AR91xx, AR93xx, QCA95xx). diff --git a/target/linux/ath79/nand/target.mk b/target/linux/ath79/nand/target.mk index 12694b6013e758..7ea9b57f45d5fb 100644 --- a/target/linux/ath79/nand/target.mk +++ b/target/linux/ath79/nand/target.mk @@ -4,8 +4,6 @@ FEATURES += nand DEFAULT_PACKAGES += wpad-basic-wolfssl -KERNEL_TESTING_PATCHVER:=5.15 - define Target/Description Firmware for boards using Qualcomm Atheros, MIPS-based SoCs in the ar72xx and subsequent series, with support for NAND flash diff --git a/target/linux/ath79/tiny/target.mk b/target/linux/ath79/tiny/target.mk index 8241aacd3a75fe..28e02f7a674c43 100644 --- a/target/linux/ath79/tiny/target.mk +++ b/target/linux/ath79/tiny/target.mk @@ -3,8 +3,6 @@ FEATURES += low_mem small_flash DEFAULT_PACKAGES += wpad-basic-wolfssl -KERNEL_TESTING_PATCHVER:=5.15 - define Target/Description Build firmware images for Atheros AR71xx/AR913x/AR934x based boards with small flash endef From 5788b494f9fb6f7182f7f7ca265751e1a5631652 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 6 Sep 2022 03:27:16 +0100 Subject: [PATCH 41/91] mediatek: fix sysupgrade on MTK7986 rfba AP A line in platform.sh was accidentally removed when adding support for the Bananapi BPi-R3. Re-add it to fix sysupgrade on the MTK7986 rfba AP. Fixes: a96382c1bb ("mediatek: add support for Bananapi BPi-R3") Signed-off-by: Daniel Golle --- target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 13b5b64fb69801..811e5133f2e469 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -25,6 +25,7 @@ platform_do_upgrade() { esac ;; *) + nand_do_upgrade "$1" ;; esac } From 2117d04a3aaad3394c0afec799d9c43f8a09c2cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 30 Aug 2022 08:31:42 +0200 Subject: [PATCH 42/91] scripts: add xxdi.pl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit xxdi.pl is a Perl script that implements vim's 'xxd -i' mode so that packages do not have to use all of vim just to get this functionality. References: #10555 Source: https://github.com/gregkh/xxdi/blob/97a6bd5cee05d1b15851981ec38ef5a460ddfcb1/xxdi.pl Signed-off-by: Petr Štetiar --- scripts/xxdi.pl | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100755 scripts/xxdi.pl diff --git a/scripts/xxdi.pl b/scripts/xxdi.pl new file mode 100755 index 00000000000000..acc974c4b3cc83 --- /dev/null +++ b/scripts/xxdi.pl @@ -0,0 +1,50 @@ +#!/usr/bin/env perl +# +# xxdi.pl - perl implementation of 'xxd -i' mode +# +# Copyright 2013 Greg Kroah-Hartman +# Copyright 2013 Linux Foundation +# +# Released under the GPLv2. +# +# Implements the "basic" functionality of 'xxd -i' in perl to keep build +# systems from having to build/install/rely on vim-core, which not all +# distros want to do. But everyone has perl, so use it instead. +# + +use strict; +use warnings; +use File::Slurp qw(slurp); + +my $indata = slurp(@ARGV ? $ARGV[0] : \*STDIN); +my $len_data = length($indata); +my $num_digits_per_line = 12; +my $var_name; +my $outdata; + +# Use the variable name of the file we read from, converting '/' and '. +# to '_', or, if this is stdin, just use "stdin" as the name. +if (@ARGV) { + $var_name = $ARGV[0]; + $var_name =~ s/\//_/g; + $var_name =~ s/\./_/g; +} else { + $var_name = "stdin"; +} + +$outdata .= "unsigned char $var_name\[] = {"; + +# trailing ',' is acceptable, so instead of duplicating the logic for +# just the last character, live with the extra ','. +for (my $key= 0; $key < $len_data; $key++) { + if ($key % $num_digits_per_line == 0) { + $outdata .= "\n\t"; + } + $outdata .= sprintf("0x%.2x, ", ord(substr($indata, $key, 1))); +} + +$outdata .= "\n};\nunsigned int $var_name\_len = $len_data;\n"; + +binmode STDOUT; +print {*STDOUT} $outdata; + From 8b278a76d90e3724815a5fde32be59f7796be1d8 Mon Sep 17 00:00:00 2001 From: Jo-Philipp Wich Date: Tue, 30 Aug 2022 18:20:04 +0200 Subject: [PATCH 43/91] scripts: xxdi.pl: remove File::Slurp dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to make it more portable. Signed-off-by: Jo-Philipp Wich Signed-off-by: Petr Štetiar --- scripts/xxdi.pl | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/scripts/xxdi.pl b/scripts/xxdi.pl index acc974c4b3cc83..1f960902beffd5 100755 --- a/scripts/xxdi.pl +++ b/scripts/xxdi.pl @@ -14,9 +14,24 @@ use strict; use warnings; -use File::Slurp qw(slurp); -my $indata = slurp(@ARGV ? $ARGV[0] : \*STDIN); +my $indata; + +{ + local $/; + my $fh; + + if (@ARGV) { + open($fh, '<:raw', $ARGV[0]) || die("Unable to open $ARGV[0]: $!\n"); + } else { + $fh = \*STDIN; + } + + $indata = readline $fh; + + close $fh; +} + my $len_data = length($indata); my $num_digits_per_line = 12; my $var_name; From 06e01e817ec6643a35beb9e6946689e9cc7d020a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 30 Aug 2022 08:34:26 +0200 Subject: [PATCH 44/91] scripts: xxdi.pl: add xxd -i compat mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So it can serve as a standalone drop in replacement for xxd utility used currently mostly in U-Boot packages with `xxd -i` mode which outputs C include file style, with aim for byte to byte identical output, so the eventual difference in the generated output is easily spottable. Fixes: #10555 Signed-off-by: Petr Štetiar Signed-off-by: Jo-Philipp Wich [perl-fu] --- scripts/xxdi.pl | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/scripts/xxdi.pl b/scripts/xxdi.pl index 1f960902beffd5..f7bb3c2f9ca1a0 100755 --- a/scripts/xxdi.pl +++ b/scripts/xxdi.pl @@ -16,15 +16,21 @@ use warnings; my $indata; +my $var_name = "stdin"; +my $full_output = (@ARGV > 0 && $ARGV[0] eq '-i') ? shift @ARGV : undef; { local $/; my $fh; if (@ARGV) { - open($fh, '<:raw', $ARGV[0]) || die("Unable to open $ARGV[0]: $!\n"); - } else { + $var_name = $ARGV[0]; + open($fh, '<:raw', $var_name) || die("xxdi.pl: Unable to open $var_name: $!\n"); + } elsif (! -t STDIN) { $fh = \*STDIN; + undef $full_output; + } else { + die "usage: xxdi.pl [-i] [infile]\n"; } $indata = readline $fh; @@ -34,32 +40,27 @@ my $len_data = length($indata); my $num_digits_per_line = 12; -my $var_name; -my $outdata; +my $outdata = ""; # Use the variable name of the file we read from, converting '/' and '. # to '_', or, if this is stdin, just use "stdin" as the name. -if (@ARGV) { - $var_name = $ARGV[0]; - $var_name =~ s/\//_/g; - $var_name =~ s/\./_/g; -} else { - $var_name = "stdin"; -} +$var_name =~ s/\//_/g; +$var_name =~ s/\./_/g; +$var_name = "__$var_name" if $var_name =~ /^\d/; -$outdata .= "unsigned char $var_name\[] = {"; +$outdata = "unsigned char $var_name\[] = { " if $full_output; -# trailing ',' is acceptable, so instead of duplicating the logic for -# just the last character, live with the extra ','. for (my $key= 0; $key < $len_data; $key++) { if ($key % $num_digits_per_line == 0) { - $outdata .= "\n\t"; + $outdata = substr($outdata, 0, -1)."\n "; } $outdata .= sprintf("0x%.2x, ", ord(substr($indata, $key, 1))); } -$outdata .= "\n};\nunsigned int $var_name\_len = $len_data;\n"; +$outdata = substr($outdata, 0, -2); +$outdata .= "\n"; -binmode STDOUT; -print {*STDOUT} $outdata; +$outdata .= "};\nunsigned int $var_name\_len = $len_data;\n" if $full_output; +binmode STDOUT; +print $outdata; From eae2fb8027cb892e42181e471ba344aa5d26bf7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 30 Aug 2022 08:45:39 +0200 Subject: [PATCH 45/91] build: provide xxd -i with scripts/xxdi.pl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Dependency on xxd was added in commit c4dd2441e787 ("tools: add xxd (from vim)") as U-Boot requires xxd to create the default environment from an external file. Later in commit 2b94aac7a128 ("tools: xxd: use more convenient source tarball"), xxd from another source was used instead, but that source is currently unavailable, so let's fix it by using simple xxdi.pl Perl script instead. Fixes: #10555 Signed-off-by: Petr Štetiar --- include/prereq-build.mk | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 6c45327f013b7a..0a023c2c6f6ece 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -202,7 +202,10 @@ $(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c mkdir -p $(dir $@) $(CC) -O2 -I$(TOPDIR)/tools/include -o $@ $< -prereq: $(STAGING_DIR_HOST)/bin/mkhash +$(STAGING_DIR_HOST)/bin/xxd: $(SCRIPT_DIR)/xxdi.pl + $(LN) $< $@ + +prereq: $(STAGING_DIR_HOST)/bin/mkhash $(STAGING_DIR_HOST)/bin/xxd # Install ldconfig stub $(eval $(call TestHostCommand,ldconfig-stub,Failed to install stub, \ From 88c9056a70901577489ecdc7a25207a9b7576d6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petr=20=C5=A0tetiar?= Date: Tue, 30 Aug 2022 08:41:07 +0200 Subject: [PATCH 46/91] tools: remove xxd package MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It shouldn't be needed anymore as we've now `scripts/xxdi.pl`, which should be self contained and fully compatible `xxd -i` replacement. Fixes: #10555 Signed-off-by: Petr Štetiar --- tools/Makefile | 2 +- tools/xxd/Makefile | 19 ------------------- 2 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 tools/xxd/Makefile diff --git a/tools/Makefile b/tools/Makefile index 0d6e675d4ceb16..3f505459e9731d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -25,7 +25,7 @@ tools-y += autoconf autoconf-archive automake bc bison cmake cpio dosfstools tools-y += e2fsprogs fakeroot findutils firmware-utils flex gengetopt tools-y += libressl libtool lzma m4 make-ext4fs meson missing-macros mkimage tools-y += mklibs mtd-utils mtools ninja padjffs2 patch-image -tools-y += patchelf pkgconf quilt squashfskit4 sstrip xxd zip zlib zstd +tools-y += patchelf pkgconf quilt squashfskit4 sstrip zip zlib zstd tools-$(BUILD_B43_TOOLS) += b43-tools tools-$(BUILD_ISL) += isl tools-$(BUILD_TOOLCHAIN) += expat gmp mpc mpfr diff --git a/tools/xxd/Makefile b/tools/xxd/Makefile deleted file mode 100644 index c3cc6863cc89a8..00000000000000 --- a/tools/xxd/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later - -include $(TOPDIR)/rules.mk - -PKG_NAME:=xxd -PKG_VERSION:=1.10 -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=http://grail.cba.csuohio.edu/~somos/ -PKG_HASH:=9bf05c19b9084973e3cc877696a7f9881a5c87fa5a9fa438d9962519726559f9 -PKG_CPE_ID:=cpe:/a:vim:vim - -include $(INCLUDE_DIR)/host-build.mk - -define Host/Install - $(INSTALL_DIR) $(STAGING_DIR_HOST)/bin - $(INSTALL_BIN) $(HOST_BUILD_DIR)/xxd $(STAGING_DIR_HOST)/bin/ -endef - -$(eval $(call HostBuild)) From 09ea1db93b53d2c1e4a081f20fbbddd4bffd451d Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 6 Sep 2022 12:12:12 +0200 Subject: [PATCH 47/91] hostapd: rename hostapd multicast_to_unicast option to multicast_to_unicast_all There are two feature currently altered by the multicast_to_unicast option. 1. bridge level multicast_to_unicast via IGMP snooping 2. hostapd/mac80211 config multicast_to_unicast setting The hostapd/mac80211 setting has the side effect of converting *all* multicast or broadcast traffic into per-station duplicated unicast traffic, which can in some cases break expectations of various protocols. It also has been observed to cause ARP lookup failure between stations connected to the same interface. The bridge level feature is much more useful, since it only covers actual multicast traffic managed by IGMP, and it implicitly defaults to 1 already. Renaming the hostapd/mac80211 option to multicast_to_unicast_all should avoid unintentionally enabling this feature Signed-off-by: Felix Fietkau --- package/network/services/hostapd/files/hostapd.sh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/package/network/services/hostapd/files/hostapd.sh b/package/network/services/hostapd/files/hostapd.sh index e3b4b1df91d79f..7eeb74e9846cac 100644 --- a/package/network/services/hostapd/files/hostapd.sh +++ b/package/network/services/hostapd/files/hostapd.sh @@ -361,7 +361,7 @@ hostapd_common_add_bss_config() { config_add_array airtime_sta_weight config_add_int airtime_bss_weight airtime_bss_limit - config_add_boolean multicast_to_unicast proxy_arp per_sta_vif + config_add_boolean multicast_to_unicast multicast_to_unicast_all proxy_arp per_sta_vif config_add_array hostapd_bss_options config_add_boolean default_disabled @@ -547,7 +547,7 @@ hostapd_set_bss_options() { bss_load_update_period chan_util_avg_period sae_require_mfp sae_pwe \ multi_ap multi_ap_backhaul_ssid multi_ap_backhaul_key skip_inactivity_poll \ ppsk airtime_bss_weight airtime_bss_limit airtime_sta_weight \ - multicast_to_unicast proxy_arp per_sta_vif \ + multicast_to_unicast_all proxy_arp per_sta_vif \ eap_server eap_user_file ca_cert server_cert private_key private_key_passwd server_id \ vendor_elements fils ocv @@ -1130,9 +1130,9 @@ hostapd_set_bss_options() { [ -n "$server_id" ] && append bss_conf "server_id=$server_id" "$N" fi - set_default multicast_to_unicast 0 - if [ "$multicast_to_unicast" -gt 0 ]; then - append bss_conf "multicast_to_unicast=$multicast_to_unicast" "$N" + set_default multicast_to_unicast_all 0 + if [ "$multicast_to_unicast_all" -gt 0 ]; then + append bss_conf "multicast_to_unicast=$multicast_to_unicast_all" "$N" fi set_default proxy_arp 0 if [ "$proxy_arp" -gt 0 ]; then From 7e94a02cbe84701d2638d243b328d53ce27f2474 Mon Sep 17 00:00:00 2001 From: Josef Schlehofer Date: Fri, 26 Aug 2022 16:21:44 +0200 Subject: [PATCH 48/91] kernel: add support for HALNy HL-GSFP and other related fixes It was reported on Turris forum [1] that HALNy HL-GSFP module does not work as it should with kernel 5.15. Russell King prepared this patch series, which fixes broken SFP module to work. Compile and run tested with Turris Omnia. [1] https://forum.turris.cz/t/hbl-turrisos-6-0-alpha2-halny-hl-gsfp-sfp-gpon-stick-problems/17547 Signed-off-by: Josef Schlehofer --- ...t-sfp-move-quirk-handling-into-sfp.c.patch | 290 ++++++++++++++++++ ...move-Alcatel-Lucent-3FE46541AA-fixup.patch | 68 ++++ ...72-net-sfp-move-Huawei-MA5671A-fixup.patch | 47 +++ ...t-sfp-add-support-for-HALNy-GPON-SFP.patch | 86 ++++++ ...774--net-sfp-redo-soft-state-polling.patch | 79 +++++ ...change-HALNy-to-ignore-hardware-pins.patch | 35 +++ 6 files changed, 605 insertions(+) create mode 100644 target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch create mode 100644 target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch create mode 100644 target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch create mode 100644 target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch create mode 100644 target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch create mode 100644 target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch diff --git a/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch b/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch new file mode 100644 index 00000000000000..8d43ccb3e922d1 --- /dev/null +++ b/target/linux/generic/pending-5.15/770-net-sfp-move-quirk-handling-into-sfp.c.patch @@ -0,0 +1,290 @@ +From a4648a1957cd79bc389538aa0472db39a56e3df6 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:43:30 +0100 +Subject: [PATCH 1/6] net: sfp: move quirk handling into sfp.c + +We need to handle more quirks than just those which affect the link +modes of the module. Move the quirk lookup into sfp.c, and pass the +quirk to sfp-bus.c + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp-bus.c | 98 ++------------------------------------- + drivers/net/phy/sfp.c | 94 ++++++++++++++++++++++++++++++++++++- + drivers/net/phy/sfp.h | 9 +++- + 3 files changed, 104 insertions(+), 97 deletions(-) + +--- a/drivers/net/phy/sfp-bus.c ++++ b/drivers/net/phy/sfp-bus.c +@@ -10,12 +10,6 @@ + + #include "sfp.h" + +-struct sfp_quirk { +- const char *vendor; +- const char *part; +- void (*modes)(const struct sfp_eeprom_id *id, unsigned long *modes); +-}; +- + /** + * struct sfp_bus - internal representation of a sfp bus + */ +@@ -38,93 +32,6 @@ struct sfp_bus { + bool started; + }; + +-static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, +- unsigned long *modes) +-{ +- phylink_set(modes, 2500baseX_Full); +-} +- +-static void sfp_quirk_ubnt_uf_instant(const struct sfp_eeprom_id *id, +- unsigned long *modes) +-{ +- /* Ubiquiti U-Fiber Instant module claims that support all transceiver +- * types including 10G Ethernet which is not truth. So clear all claimed +- * modes and set only one mode which module supports: 1000baseX_Full. +- */ +- phylink_zero(modes); +- phylink_set(modes, 1000baseX_Full); +-} +- +-static const struct sfp_quirk sfp_quirks[] = { +- { +- // Alcatel Lucent G-010S-P can operate at 2500base-X, but +- // incorrectly report 2500MBd NRZ in their EEPROM +- .vendor = "ALCATELLUCENT", +- .part = "G010SP", +- .modes = sfp_quirk_2500basex, +- }, { +- // Alcatel Lucent G-010S-A can operate at 2500base-X, but +- // report 3.2GBd NRZ in their EEPROM +- .vendor = "ALCATELLUCENT", +- .part = "3FE46541AA", +- .modes = sfp_quirk_2500basex, +- }, { +- // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd +- // NRZ in their EEPROM +- .vendor = "HUAWEI", +- .part = "MA5671A", +- .modes = sfp_quirk_2500basex, +- }, { +- // Lantech 8330-262D-E can operate at 2500base-X, but +- // incorrectly report 2500MBd NRZ in their EEPROM +- .vendor = "Lantech", +- .part = "8330-262D-E", +- .modes = sfp_quirk_2500basex, +- }, { +- .vendor = "UBNT", +- .part = "UF-INSTANT", +- .modes = sfp_quirk_ubnt_uf_instant, +- }, +-}; +- +-static size_t sfp_strlen(const char *str, size_t maxlen) +-{ +- size_t size, i; +- +- /* Trailing characters should be filled with space chars */ +- for (i = 0, size = 0; i < maxlen; i++) +- if (str[i] != ' ') +- size = i + 1; +- +- return size; +-} +- +-static bool sfp_match(const char *qs, const char *str, size_t len) +-{ +- if (!qs) +- return true; +- if (strlen(qs) != len) +- return false; +- return !strncmp(qs, str, len); +-} +- +-static const struct sfp_quirk *sfp_lookup_quirk(const struct sfp_eeprom_id *id) +-{ +- const struct sfp_quirk *q; +- unsigned int i; +- size_t vs, ps; +- +- vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); +- ps = sfp_strlen(id->base.vendor_pn, ARRAY_SIZE(id->base.vendor_pn)); +- +- for (i = 0, q = sfp_quirks; i < ARRAY_SIZE(sfp_quirks); i++, q++) +- if (sfp_match(q->vendor, id->base.vendor_name, vs) && +- sfp_match(q->part, id->base.vendor_pn, ps)) +- return q; +- +- return NULL; +-} +- + /** + * sfp_parse_port() - Parse the EEPROM base ID, setting the port type + * @bus: a pointer to the &struct sfp_bus structure for the sfp module +@@ -786,12 +693,13 @@ void sfp_link_down(struct sfp_bus *bus) + } + EXPORT_SYMBOL_GPL(sfp_link_down); + +-int sfp_module_insert(struct sfp_bus *bus, const struct sfp_eeprom_id *id) ++int sfp_module_insert(struct sfp_bus *bus, const struct sfp_eeprom_id *id, ++ const struct sfp_quirk *quirk) + { + const struct sfp_upstream_ops *ops = sfp_get_upstream_ops(bus); + int ret = 0; + +- bus->sfp_quirk = sfp_lookup_quirk(id); ++ bus->sfp_quirk = quirk; + + if (ops && ops->module_insert) + ret = ops->module_insert(bus->upstream, id); +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -252,6 +252,8 @@ struct sfp { + unsigned int module_t_start_up; + bool tx_fault_ignore; + ++ const struct sfp_quirk *quirk; ++ + #if IS_ENABLED(CONFIG_HWMON) + struct sfp_diag diag; + struct delayed_work hwmon_probe; +@@ -308,6 +310,93 @@ static const struct of_device_id sfp_of_ + }; + MODULE_DEVICE_TABLE(of, sfp_of_match); + ++static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, ++ unsigned long *modes) ++{ ++ linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, modes); ++} ++ ++static void sfp_quirk_ubnt_uf_instant(const struct sfp_eeprom_id *id, ++ unsigned long *modes) ++{ ++ /* Ubiquiti U-Fiber Instant module claims that support all transceiver ++ * types including 10G Ethernet which is not truth. So clear all claimed ++ * modes and set only one mode which module supports: 1000baseX_Full. ++ */ ++ linkmode_zero(modes); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, modes); ++} ++ ++static const struct sfp_quirk sfp_quirks[] = { ++ { ++ // Alcatel Lucent G-010S-P can operate at 2500base-X, but ++ // incorrectly report 2500MBd NRZ in their EEPROM ++ .vendor = "ALCATELLUCENT", ++ .part = "G010SP", ++ .modes = sfp_quirk_2500basex, ++ }, { ++ // Alcatel Lucent G-010S-A can operate at 2500base-X, but ++ // report 3.2GBd NRZ in their EEPROM ++ .vendor = "ALCATELLUCENT", ++ .part = "3FE46541AA", ++ .modes = sfp_quirk_2500basex, ++ }, { ++ // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd ++ // NRZ in their EEPROM ++ .vendor = "HUAWEI", ++ .part = "MA5671A", ++ .modes = sfp_quirk_2500basex, ++ }, { ++ // Lantech 8330-262D-E can operate at 2500base-X, but ++ // incorrectly report 2500MBd NRZ in their EEPROM ++ .vendor = "Lantech", ++ .part = "8330-262D-E", ++ .modes = sfp_quirk_2500basex, ++ }, { ++ .vendor = "UBNT", ++ .part = "UF-INSTANT", ++ .modes = sfp_quirk_ubnt_uf_instant, ++ }, ++}; ++ ++static size_t sfp_strlen(const char *str, size_t maxlen) ++{ ++ size_t size, i; ++ ++ /* Trailing characters should be filled with space chars */ ++ for (i = 0, size = 0; i < maxlen; i++) ++ if (str[i] != ' ') ++ size = i + 1; ++ ++ return size; ++} ++ ++static bool sfp_match(const char *qs, const char *str, size_t len) ++{ ++ if (!qs) ++ return true; ++ if (strlen(qs) != len) ++ return false; ++ return !strncmp(qs, str, len); ++} ++ ++static const struct sfp_quirk *sfp_lookup_quirk(const struct sfp_eeprom_id *id) ++{ ++ const struct sfp_quirk *q; ++ unsigned int i; ++ size_t vs, ps; ++ ++ vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); ++ ps = sfp_strlen(id->base.vendor_pn, ARRAY_SIZE(id->base.vendor_pn)); ++ ++ for (i = 0, q = sfp_quirks; i < ARRAY_SIZE(sfp_quirks); i++, q++) ++ if (sfp_match(q->vendor, id->base.vendor_name, vs) && ++ sfp_match(q->part, id->base.vendor_pn, ps)) ++ return q; ++ ++ return NULL; ++} ++ + static unsigned long poll_jiffies; + + static unsigned int sfp_gpio_get_state(struct sfp *sfp) +@@ -1952,6 +2041,8 @@ static int sfp_sm_mod_probe(struct sfp * + else + sfp->tx_fault_ignore = false; + ++ sfp->quirk = sfp_lookup_quirk(&id); ++ + return 0; + } + +@@ -2063,7 +2154,8 @@ static void sfp_sm_module(struct sfp *sf + break; + + /* Report the module insertion to the upstream device */ +- err = sfp_module_insert(sfp->sfp_bus, &sfp->id); ++ err = sfp_module_insert(sfp->sfp_bus, &sfp->id, ++ sfp->quirk); + if (err < 0) { + sfp_sm_mod_next(sfp, SFP_MOD_ERROR, 0); + break; +--- a/drivers/net/phy/sfp.h ++++ b/drivers/net/phy/sfp.h +@@ -6,6 +6,12 @@ + + struct sfp; + ++struct sfp_quirk { ++ const char *vendor; ++ const char *part; ++ void (*modes)(const struct sfp_eeprom_id *id, unsigned long *modes); ++}; ++ + struct sfp_socket_ops { + void (*attach)(struct sfp *sfp); + void (*detach)(struct sfp *sfp); +@@ -23,7 +29,8 @@ int sfp_add_phy(struct sfp_bus *bus, str + void sfp_remove_phy(struct sfp_bus *bus); + void sfp_link_up(struct sfp_bus *bus); + void sfp_link_down(struct sfp_bus *bus); +-int sfp_module_insert(struct sfp_bus *bus, const struct sfp_eeprom_id *id); ++int sfp_module_insert(struct sfp_bus *bus, const struct sfp_eeprom_id *id, ++ const struct sfp_quirk *quirk); + void sfp_module_remove(struct sfp_bus *bus); + int sfp_module_start(struct sfp_bus *bus); + void sfp_module_stop(struct sfp_bus *bus); diff --git a/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch b/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch new file mode 100644 index 00000000000000..f285561ebba111 --- /dev/null +++ b/target/linux/generic/pending-5.15/771-net-sfp-move-Alcatel-Lucent-3FE46541AA-fixup.patch @@ -0,0 +1,68 @@ +From 21fdd8281de3022aee35dd5bfccc892bd46529a3 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:43:35 +0100 +Subject: [PATCH 2/6] net: sfp: move Alcatel Lucent 3FE46541AA fixup + +Add a new fixup mechanism to the SFP quirks, and use it for this +module. + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp.c | 14 +++++++++----- + drivers/net/phy/sfp.h | 1 + + 2 files changed, 10 insertions(+), 5 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -310,6 +310,11 @@ static const struct of_device_id sfp_of_ + }; + MODULE_DEVICE_TABLE(of, sfp_of_match); + ++static void sfp_fixup_long_startup(struct sfp *sfp) ++{ ++ sfp->module_t_start_up = T_START_UP_BAD_GPON; ++} ++ + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, + unsigned long *modes) + { +@@ -340,6 +345,7 @@ static const struct sfp_quirk sfp_quirks + .vendor = "ALCATELLUCENT", + .part = "3FE46541AA", + .modes = sfp_quirk_2500basex, ++ .fixup = sfp_fixup_long_startup, + }, { + // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd + // NRZ in their EEPROM +@@ -2029,11 +2035,7 @@ static int sfp_sm_mod_probe(struct sfp * + if (ret < 0) + return ret; + +- if (!memcmp(id.base.vendor_name, "ALCATELLUCENT ", 16) && +- !memcmp(id.base.vendor_pn, "3FE46541AA ", 16)) +- sfp->module_t_start_up = T_START_UP_BAD_GPON; +- else +- sfp->module_t_start_up = T_START_UP; ++ sfp->module_t_start_up = T_START_UP; + + if (!memcmp(id.base.vendor_name, "HUAWEI ", 16) && + !memcmp(id.base.vendor_pn, "MA5671A ", 16)) +@@ -2042,6 +2044,8 @@ static int sfp_sm_mod_probe(struct sfp * + sfp->tx_fault_ignore = false; + + sfp->quirk = sfp_lookup_quirk(&id); ++ if (sfp->quirk && sfp->quirk->fixup) ++ sfp->quirk->fixup(sfp); + + return 0; + } +--- a/drivers/net/phy/sfp.h ++++ b/drivers/net/phy/sfp.h +@@ -10,6 +10,7 @@ struct sfp_quirk { + const char *vendor; + const char *part; + void (*modes)(const struct sfp_eeprom_id *id, unsigned long *modes); ++ void (*fixup)(struct sfp *sfp); + }; + + struct sfp_socket_ops { diff --git a/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch b/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch new file mode 100644 index 00000000000000..dfd08af671846d --- /dev/null +++ b/target/linux/generic/pending-5.15/772-net-sfp-move-Huawei-MA5671A-fixup.patch @@ -0,0 +1,47 @@ +From 4c9d8c654827ef42da702c5b6c3392e8ac0bc60a Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:43:40 +0100 +Subject: [PATCH 3/6] net: sfp: move Huawei MA5671A fixup + +Move this module over to the new fixup mechanism. + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -315,6 +315,11 @@ static void sfp_fixup_long_startup(struc + sfp->module_t_start_up = T_START_UP_BAD_GPON; + } + ++static void sfp_fixup_ignore_tx_fault(struct sfp *sfp) ++{ ++ sfp->tx_fault_ignore = true; ++} ++ + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, + unsigned long *modes) + { +@@ -352,6 +357,7 @@ static const struct sfp_quirk sfp_quirks + .vendor = "HUAWEI", + .part = "MA5671A", + .modes = sfp_quirk_2500basex, ++ .fixup = sfp_fixup_ignore_tx_fault, + }, { + // Lantech 8330-262D-E can operate at 2500base-X, but + // incorrectly report 2500MBd NRZ in their EEPROM +@@ -2037,11 +2043,7 @@ static int sfp_sm_mod_probe(struct sfp * + + sfp->module_t_start_up = T_START_UP; + +- if (!memcmp(id.base.vendor_name, "HUAWEI ", 16) && +- !memcmp(id.base.vendor_pn, "MA5671A ", 16)) +- sfp->tx_fault_ignore = true; +- else +- sfp->tx_fault_ignore = false; ++ sfp->tx_fault_ignore = false; + + sfp->quirk = sfp_lookup_quirk(&id); + if (sfp->quirk && sfp->quirk->fixup) diff --git a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch b/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch new file mode 100644 index 00000000000000..9ec47812734834 --- /dev/null +++ b/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch @@ -0,0 +1,86 @@ +From 43ac680124bc57951a6d0356b41498c2324388bf Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:43:45 +0100 +Subject: [PATCH 4/6] net: sfp: add support for HALNy GPON SFP + +Add a quirk for the HALNy HL-GSFP module, which appears to have an +inverted RX_LOS signal, and possibly uses TX_FAULT as an inverted +host-link status signal. As we can't be certain about the modules +use of TX_FAULT, we ignore it. + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp-bus.c | 2 +- + drivers/net/phy/sfp.c | 29 ++++++++++++++++++++++++++--- + 2 files changed, 27 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/sfp-bus.c ++++ b/drivers/net/phy/sfp-bus.c +@@ -283,7 +283,7 @@ void sfp_parse_support(struct sfp_bus *b + phylink_set(modes, 2500baseX_Full); + } + +- if (bus->sfp_quirk) ++ if (bus->sfp_quirk && bus->sfp_quirk->modes) + bus->sfp_quirk->modes(id, modes); + + bitmap_or(support, support, modes, __ETHTOOL_LINK_MODE_MASK_NBITS); +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -320,6 +320,23 @@ static void sfp_fixup_ignore_tx_fault(st + sfp->tx_fault_ignore = true; + } + ++static void sfp_fixup_inverted_los(struct sfp *sfp) ++{ ++ const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); ++ const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); ++ ++ sfp->id.ext.options &= ~los_normal; ++ sfp->id.ext.options |= los_inverted; ++} ++ ++static void sfp_fixup_halny_gsfp(struct sfp *sfp) ++{ ++ /* LOS is inverted */ ++ sfp_fixup_inverted_los(sfp); ++ /* TX fault might be inverted, but we don't know for certain. */ ++ sfp_fixup_ignore_tx_fault(sfp); ++} ++ + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, + unsigned long *modes) + { +@@ -352,6 +369,10 @@ static const struct sfp_quirk sfp_quirks + .modes = sfp_quirk_2500basex, + .fixup = sfp_fixup_long_startup, + }, { ++ .vendor = "HALNy", ++ .part = "HL-GSFP", ++ .fixup = sfp_fixup_halny_gsfp, ++ }, { + // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd + // NRZ in their EEPROM + .vendor = "HUAWEI", +@@ -368,16 +389,18 @@ static const struct sfp_quirk sfp_quirks + .vendor = "UBNT", + .part = "UF-INSTANT", + .modes = sfp_quirk_ubnt_uf_instant, +- }, ++ } + }; + + static size_t sfp_strlen(const char *str, size_t maxlen) + { + size_t size, i; + +- /* Trailing characters should be filled with space chars */ ++ /* Trailing characters should be filled with space chars, but ++ * some manufacturers can't read SFF-8472 and use NUL. ++ */ + for (i = 0, size = 0; i < maxlen; i++) +- if (str[i] != ' ') ++ if (str[i] != ' ' && str[i] != '\0') + size = i + 1; + + return size; diff --git a/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch b/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch new file mode 100644 index 00000000000000..3aa51deb3c74bb --- /dev/null +++ b/target/linux/generic/pending-5.15/774--net-sfp-redo-soft-state-polling.patch @@ -0,0 +1,79 @@ +From 9a84d699ddde0d4e272aa919ad8fd50271a3f932 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:48:20 +0100 +Subject: [PATCH 5/6] net: sfp: redo soft state polling + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp.c | 35 ++++++++++++++++++++++++----------- + 1 file changed, 24 insertions(+), 11 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -234,6 +234,7 @@ struct sfp { + bool need_poll; + + struct mutex st_mutex; /* Protects state */ ++ unsigned int state_ignore_hw_mask; + unsigned int state_soft_mask; + unsigned int state; + struct delayed_work poll; +@@ -623,17 +624,18 @@ static void sfp_soft_set_state(struct sf + static void sfp_soft_start_poll(struct sfp *sfp) + { + const struct sfp_eeprom_id *id = &sfp->id; ++ unsigned int mask = 0; + + sfp->state_soft_mask = 0; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE && +- !sfp->gpio[GPIO_TX_DISABLE]) +- sfp->state_soft_mask |= SFP_F_TX_DISABLE; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT && +- !sfp->gpio[GPIO_TX_FAULT]) +- sfp->state_soft_mask |= SFP_F_TX_FAULT; +- if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS && +- !sfp->gpio[GPIO_LOS]) +- sfp->state_soft_mask |= SFP_F_LOS; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_DISABLE) ++ mask |= SFP_F_TX_DISABLE; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_TX_FAULT) ++ mask |= SFP_F_TX_FAULT; ++ if (id->ext.enhopts & SFP_ENHOPTS_SOFT_RX_LOS) ++ mask |= SFP_F_LOS; ++ ++ // Poll the soft state for hardware pins we want to ignore ++ sfp->state_soft_mask = sfp->state_ignore_hw_mask & mask; + + if (sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT) && + !sfp->need_poll) +@@ -647,10 +649,12 @@ static void sfp_soft_stop_poll(struct sf + + static unsigned int sfp_get_state(struct sfp *sfp) + { ++ unsigned int soft = sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT); + unsigned int state = sfp->get_state(sfp); + +- if (state & SFP_F_PRESENT && +- sfp->state_soft_mask & (SFP_F_LOS | SFP_F_TX_FAULT)) ++ state &= ~sfp->state_ignore_hw_mask; ++ ++ if (state & SFP_F_PRESENT && soft) + state |= sfp_soft_get_state(sfp); + + return state; +@@ -2064,6 +2068,15 @@ static int sfp_sm_mod_probe(struct sfp * + if (ret < 0) + return ret; + ++ /* Initialise state bits to ignore from hardware */ ++ sfp->state_ignore_hw_mask = 0; ++ if (!sfp->gpio[GPIO_TX_DISABLE]) ++ sfp->state_ignore_hw_mask |= SFP_F_TX_DISABLE; ++ if (!sfp->gpio[GPIO_TX_FAULT]) ++ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT; ++ if (!sfp->gpio[GPIO_LOS]) ++ sfp->state_ignore_hw_mask |= SFP_F_LOS; ++ + sfp->module_t_start_up = T_START_UP; + + sfp->tx_fault_ignore = false; diff --git a/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch b/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch new file mode 100644 index 00000000000000..7aa29cd722534e --- /dev/null +++ b/target/linux/generic/pending-5.15/775-net-sfp-change-HALNy-to-ignore-hardware-pins.patch @@ -0,0 +1,35 @@ +From 32a59a1c5dc8f6fa755bab9a5f9751fdb66bb234 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Fri, 26 Aug 2022 08:48:25 +0100 +Subject: [PATCH 6/6] net: sfp: change HALNy to ignore hardware pins + +Signed-off-by: Russell King (Oracle) +--- + drivers/net/phy/sfp.c | 14 +------------- + 1 file changed, 1 insertion(+), 13 deletions(-) + +--- a/drivers/net/phy/sfp.c ++++ b/drivers/net/phy/sfp.c +@@ -321,21 +321,9 @@ static void sfp_fixup_ignore_tx_fault(st + sfp->tx_fault_ignore = true; + } + +-static void sfp_fixup_inverted_los(struct sfp *sfp) +-{ +- const __be16 los_inverted = cpu_to_be16(SFP_OPTIONS_LOS_INVERTED); +- const __be16 los_normal = cpu_to_be16(SFP_OPTIONS_LOS_NORMAL); +- +- sfp->id.ext.options &= ~los_normal; +- sfp->id.ext.options |= los_inverted; +-} +- + static void sfp_fixup_halny_gsfp(struct sfp *sfp) + { +- /* LOS is inverted */ +- sfp_fixup_inverted_los(sfp); +- /* TX fault might be inverted, but we don't know for certain. */ +- sfp_fixup_ignore_tx_fault(sfp); ++ sfp->state_ignore_hw_mask |= SFP_F_TX_FAULT | SFP_F_LOS; + } + + static void sfp_quirk_2500basex(const struct sfp_eeprom_id *id, From 98e2501de56182768c11b018722f73caf6ddada9 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 5 Sep 2022 22:41:22 +0100 Subject: [PATCH 49/91] kernel: rework Huawei-compatible OEM SFP GE-T This patch was added in 09b086eecaa545cf7f30bc7e394a32751e25db65 ("kernel: add quirk for Huawei-compatible OEM SFP GE-T"). Add patch title, description and SoB to follow OpenWrt's developer guide for working patches to prepare it for being sent upstream. This patch should be discussed with Russell King and merged to Linux kernel. Co-authored-by: Josef Schlehofer Signed-off-by: Daniel Golle --- .../790-SFP-GE-T-ignore-TX_FAULT.patch | 80 ++++++++++++------- 1 file changed, 49 insertions(+), 31 deletions(-) diff --git a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch index bfb32d53816adc..d9835f88961036 100644 --- a/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch +++ b/target/linux/generic/hack-5.15/790-SFP-GE-T-ignore-TX_FAULT.patch @@ -1,36 +1,54 @@ +From 7cc39a6bedbd85f3ff7e16845f310e4ce8d9833f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 6 Sep 2022 00:31:19 +0100 +Subject: [PATCH] net: sfp: add quirk for ATS SFP-GE-T 1000Base-TX module +To: netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, + Russell King , + Andrew Lunn , + Heiner Kallweit +Cc: David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Josef Schlehofer + +This copper module comes with broken TX_FAULT indicator which must be +ignored for it to work. Implement ignoring TX_FAULT state bit also +during reset/insertion and mute the warning telling the user that the +module indicates TX_FAULT. + +Co-authored-by: Josef Schlehofer +Signed-off-by: Daniel Golle +--- + drivers/net/phy/sfp.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c -@@ -1803,6 +1803,7 @@ static int sfp_sm_mod_probe(struct sfp * - struct sfp_eeprom_id id; - bool cotsworks_sfbg; - bool cotsworks; -+ bool oem_ge_t; - u8 check; - int ret; - -@@ -1851,6 +1852,10 @@ static int sfp_sm_mod_probe(struct sfp * - } - } - -+ /* Some cheap SFP-GE-T modules always indicate TX fault */ -+ oem_ge_t = !memcmp(id.base.vendor_name, "OEM ", 16) && -+ !memcmp(id.base.vendor_pn, "SFP-GE-T ", 12); -+ - /* Cotsworks do not seem to update the checksums when they - * do the final programming with the final module part number, - * serial number and date code. -@@ -1946,8 +1951,8 @@ static int sfp_sm_mod_probe(struct sfp * - else - sfp->module_t_start_up = T_START_UP; - -- if (!memcmp(id.base.vendor_name, "HUAWEI ", 16) && -- !memcmp(id.base.vendor_pn, "MA5671A ", 16)) -+ if ((!memcmp(id.base.vendor_name, "HUAWEI ", 16) && -+ !memcmp(id.base.vendor_pn, "MA5671A ", 16)) || oem_ge_t) - sfp->tx_fault_ignore = true; - else - sfp->tx_fault_ignore = false; -@@ -2404,10 +2409,12 @@ static void sfp_check_state(struct sfp * +@@ -369,6 +369,11 @@ static const struct sfp_quirk sfp_quirks + .modes = sfp_quirk_2500basex, + .fixup = sfp_fixup_ignore_tx_fault, + }, { ++ // OEM SFP-GE-T is 1000Base-T module ++ .vendor = "OEM", ++ .part = "SFP-GE-T", ++ .fixup = sfp_fixup_ignore_tx_fault, ++ }, { + // Lantech 8330-262D-E can operate at 2500base-X, but + // incorrectly report 2500MBd NRZ in their EEPROM + .vendor = "Lantech", +@@ -2303,7 +2308,8 @@ static void sfp_sm_main(struct sfp *sfp, + * or t_start_up, so assume there is a fault. + */ + sfp_sm_fault(sfp, SFP_S_INIT_TX_FAULT, +- sfp->sm_fault_retries == N_FAULT_INIT); ++ !sfp->tx_fault_ignore && ++ (sfp->sm_fault_retries == N_FAULT_INIT)); + } else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) { + init_done: + sfp->sm_phy_retries = R_PHY_RETRY; +@@ -2526,10 +2532,12 @@ static void sfp_check_state(struct sfp * mutex_lock(&sfp->st_mutex); state = sfp_get_state(sfp); changed = state ^ sfp->state; From e7661c64c39becd3acca537f8cea43b67a1f1419 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 12:00:26 +0200 Subject: [PATCH 50/91] nettle: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/nettle/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/nettle/Makefile b/package/libs/nettle/Makefile index 8e4b987512b577..8825da4be7ffee 100644 --- a/package/libs/nettle/Makefile +++ b/package/libs/nettle/Makefile @@ -18,6 +18,7 @@ PKG_HASH:=364f3e2b77cd7dcde83fd7c45219c834e54b0c75e428b6f894a23d12dd41cbfe PKG_LICENSE:=GPL-2.0-or-later PKG_LICENSE_FILES:=COPYING +PKG_CPE_ID:=cpe:/a:nettle_project:nettle PKG_BUILD_PARALLEL:=1 PKG_CONFIG_DEPENDS := CONFIG_LIBNETTLE_MINI From f9a502c72191dc4d534f9550a926a569dd113a3b Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 12:13:36 +0200 Subject: [PATCH 51/91] libcap: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libcap/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libcap/Makefile b/package/libs/libcap/Makefile index 0e4ffc6e02839c..b3ca20fd8a5403 100644 --- a/package/libs/libcap/Makefile +++ b/package/libs/libcap/Makefile @@ -16,6 +16,7 @@ PKG_HASH:=73e350020cc31fe15360879d19384ffa3395a825f065fcf6bda3a5cdf965bebd PKG_MAINTAINER:=Paul Wassi PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=License +PKG_CPE_ID:=cpe:/a:libcap_project:libcap PKG_INSTALL:=1 PKG_BUILD_PARALLEL:=1 From 3f6d66d9840b671cd4cb5beff9353587defca34e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 17:38:43 +0200 Subject: [PATCH 52/91] tools/bc: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- tools/bc/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/bc/Makefile b/tools/bc/Makefile index 73dbdab49edffc..dc021024cd9035 100644 --- a/tools/bc/Makefile +++ b/tools/bc/Makefile @@ -17,6 +17,7 @@ PKG_SOURCE_URL:=https://alpha.gnu.org/gnu/bc \ PKG_HASH:=7ee4abbcfac03d8a6e1a8a3440558a3d239d6b858585063e745c760957725ecc PKG_FIXUP := autoreconf +PKG_CPE_ID:=cpe:/a:gnu:bc include $(INCLUDE_DIR)/host-build.mk From 5c238a44e976aad041bc3afd3f190614c6f20d47 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 17:42:56 +0200 Subject: [PATCH 53/91] ethtool: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/network/utils/ethtool/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/network/utils/ethtool/Makefile b/package/network/utils/ethtool/Makefile index 5e684ceedf7dc8..2c75dd19a4155b 100644 --- a/package/network/utils/ethtool/Makefile +++ b/package/network/utils/ethtool/Makefile @@ -18,6 +18,7 @@ PKG_HASH:=3b752a3329827907ac3812f2831dfecf51c8c41c55d2d69cfb9c53ca06449fc6 PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING +PKG_CPE_ID:=cpe:/a:kernel:ethtool PKG_FIXUP:=autoreconf PKG_INSTALL:=1 From 55c015ae4d115cf8ffb61ee2778d8355c224bd46 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 17:51:24 +0200 Subject: [PATCH 54/91] strace: replace PKG_CPE_ID Searching for strace in nvd.nist.gov/products/cpe/search [0] will result in "cpe:/a:strace_project:strace". Replace the current PKG_CPE_ID with it. [0] - https://nvd.nist.gov/products/cpe/search/results?namingFormat=2.2&keyword=strace Signed-off-by: Nick Hainke --- package/devel/strace/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/devel/strace/Makefile b/package/devel/strace/Makefile index 9d9db65c1777b1..71d79450038982 100644 --- a/package/devel/strace/Makefile +++ b/package/devel/strace/Makefile @@ -19,7 +19,7 @@ PKG_HASH:=aa3dc1c8e60e4f6ff3d396514aa247f3c7bf719d8a8dc4dd4fa793be786beca3 PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=LGPL-2.1-or-later PKG_LICENSE_FILES:=COPYING -PKG_CPE_ID:=cpe:/a:paul_kranenburg:strace +PKG_CPE_ID:=cpe:/a:strace_project:strace PKG_FIXUP:=autoreconf PKG_INSTALL:=1 From 8eca549bdc4a48fc2a9558e90bb338a3b8225449 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:00:30 +0200 Subject: [PATCH 55/91] lldpd: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/network/services/lldpd/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/network/services/lldpd/Makefile b/package/network/services/lldpd/Makefile index c9c66e8d933cb6..77b226a1e411dc 100644 --- a/package/network/services/lldpd/Makefile +++ b/package/network/services/lldpd/Makefile @@ -17,6 +17,7 @@ PKG_HASH:=0cb77fd7634401347b8311db1bf64d4fc3890acba90915e2cc2c5f79045ddbf0 PKG_MAINTAINER:=Stijn Tintel PKG_LICENSE:=ISC +PKG_CPE_ID:=cpe:/a:lldpd_project:lldpd PKG_FIXUP:=autoreconf PKG_BUILD_PARALLEL:=1 From 2091a76d343aeb60a6eeda9b67ac2cf0311080f8 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:02:34 +0200 Subject: [PATCH 56/91] libusb: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libusb/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libusb/Makefile b/package/libs/libusb/Makefile index 5e4046813ad343..5d89568937c780 100644 --- a/package/libs/libusb/Makefile +++ b/package/libs/libusb/Makefile @@ -20,6 +20,7 @@ PKG_HASH:=12ce7a61fc9854d1d2a1ffe095f7b5fac19ddba095c259e6067a46500381b5a5 PKG_MAINTAINER:= Felix Fietkau PKG_LICENSE:=LGPL-2.1-or-later PKG_LICENSE_FILES:=COPYING +PKG_CPE_ID:=cpe:/a:libusb:libusb PKG_INSTALL:=1 PKG_BUILD_PARALLEL:=1 From f93795cd9068457053ee384df27fe4ed63f0d746 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:04:57 +0200 Subject: [PATCH 57/91] jansson: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/jansson/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/jansson/Makefile b/package/libs/jansson/Makefile index 6de48c1d86a8d8..d8567ed79a4f11 100644 --- a/package/libs/jansson/Makefile +++ b/package/libs/jansson/Makefile @@ -17,6 +17,7 @@ PKG_HASH:=c739578bf6b764aa0752db9a2fdadcfe921c78f1228c7ec0bb47fa804c55d17b PKG_LICENSE:=MIT PKG_LICENSE_FILES:=LICENSE +PKG_CPE_ID:=cpe:/a:jansson_project:jansson include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/cmake.mk From 5bc8e5a5a94045f459b9c91040ed0ab56209e157 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:07:39 +0200 Subject: [PATCH 58/91] libnl: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libnl/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libnl/Makefile b/package/libs/libnl/Makefile index bb7a1e7fb12ec8..71b043a9e56507 100644 --- a/package/libs/libnl/Makefile +++ b/package/libs/libnl/Makefile @@ -15,6 +15,7 @@ PKG_HASH:=9fe43ccbeeea72c653bdcf8c93332583135cda46a79507bfd0a483bb57f65939 PKG_LICENSE:=LGPL-2.1 PKG_LICENSE_FILES:=COPYING +PKG_CPE_ID:=cpe:/a:libnl_project:libnl PKG_INSTALL:=1 PKG_FIXUP:=autoreconf From 91e65314a7cb26aec2fc74c40567ef190413cafd Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:11:51 +0200 Subject: [PATCH 59/91] f2fs-tools: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/utils/f2fs-tools/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/utils/f2fs-tools/Makefile b/package/utils/f2fs-tools/Makefile index 60f4b317c71c14..99d402af6ca552 100644 --- a/package/utils/f2fs-tools/Makefile +++ b/package/utils/f2fs-tools/Makefile @@ -18,6 +18,7 @@ PKG_HASH:=147d471040b44900283ce2c935f1d35d13d7f40008e7cb8fab2b69f54da01a4f PKG_MAINTAINER:=Felix Fietkau PKG_LICENSE:=GPL-2.0-only PKG_LICENSE_FILES:=COPYING +PKG_CPE_ID:=cpe:/a:f2fs-tools_project:f2fs-tools PKG_FIXUP:=autoreconf PKG_BUILD_PARALLEL:=1 From 7ea924d74ff39ba30921393054d0883231d71fe5 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:15:24 +0200 Subject: [PATCH 60/91] libmnl: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libmnl/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libmnl/Makefile b/package/libs/libmnl/Makefile index 2632cc2d946a9e..06f79d5384c589 100644 --- a/package/libs/libmnl/Makefile +++ b/package/libs/libmnl/Makefile @@ -22,6 +22,7 @@ PKG_MAINTAINER:=Jo-Philipp Wich PKG_FIXUP:=autoreconf PKG_INSTALL:=1 PKG_LICENSE:=LGPL-2.1+ +PKG_CPE_ID:=cpe:/a:netfilter:libmnl include $(INCLUDE_DIR)/package.mk From 79f3e6e2c151a07dd236db693e9b2f557c62f3f8 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:17:26 +0200 Subject: [PATCH 61/91] libnfnetlink: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libnfnetlink/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libnfnetlink/Makefile b/package/libs/libnfnetlink/Makefile index 57bb0cdb981d78..be1eba6517d852 100644 --- a/package/libs/libnfnetlink/Makefile +++ b/package/libs/libnfnetlink/Makefile @@ -18,6 +18,7 @@ PKG_SOURCE_URL:= \ PKG_HASH:=b064c7c3d426efb4786e60a8e6859b82ee2f2c5e49ffeea640cfe4fe33cbc376 PKG_MAINTAINER:=Jo-Philipp Wich PKG_LICENSE:=GPL-2.0+ +PKG_CPE_ID:=cpe:/a:netfilter:libnfnetlink PKG_FIXUP:=autoreconf From 45990ff76e209b72438575368cd29576f652778f Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sat, 3 Sep 2022 18:19:37 +0200 Subject: [PATCH 62/91] mtd-utils: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/utils/mtd-utils/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/utils/mtd-utils/Makefile b/package/utils/mtd-utils/Makefile index 74380022a52a5c..2f54b3ad0d036e 100644 --- a/package/utils/mtd-utils/Makefile +++ b/package/utils/mtd-utils/Makefile @@ -24,6 +24,7 @@ PKG_BUILD_DEPENDS:=util-linux PKG_LICENSE:=GPLv2 PKG_LICENSE_FILES:= +PKG_CPE_ID:=cpe:/a:mtd-utils_project:mtd-utils PKG_MAINTAINER:=John Crispin From 17dd8c7305b683d1287b90aecc1158252e808642 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 4 Sep 2022 15:13:59 +0200 Subject: [PATCH 63/91] libselinux: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libselinux/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libselinux/Makefile b/package/libs/libselinux/Makefile index 6bda72b5de0b20..7246d855668dd8 100644 --- a/package/libs/libselinux/Makefile +++ b/package/libs/libselinux/Makefile @@ -17,6 +17,7 @@ HOST_BUILD_DEPENDS:=libsepol/host pcre/host PKG_LICENSE:=libselinux-1.0 PKG_LICENSE_FILES:=LICENSE PKG_MAINTAINER:=Thomas Petazzoni +PKG_CPE_ID:=cpe:/a:selinuxproject:libselinux HOST_BUILD_DEPENDS:=libsepol/host musl-fts/host pcre/host From d40948b35d5e6f61aabab58d1cbd60080d9b920d Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 4 Sep 2022 15:15:13 +0200 Subject: [PATCH 64/91] libsepol: add PKG_CPE_ID Add CPE ID for tracking CVEs. Signed-off-by: Nick Hainke --- package/libs/libsepol/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/package/libs/libsepol/Makefile b/package/libs/libsepol/Makefile index 87f1ccd9177bc5..816b1397273e39 100644 --- a/package/libs/libsepol/Makefile +++ b/package/libs/libsepol/Makefile @@ -14,6 +14,7 @@ PKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PK PKG_HASH:=2d97df3eb8466169b389c3660acbb90c54200ac96e452eca9f41a9639f4f238b PKG_MAINTAINER:=Thomas Petazzoni +PKG_CPE_ID:=cpe:/a:selinuxproject:libsepol include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/host-build.mk From 33c11442b2fc60313a2d3196c9b01cf9b0931305 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 6 Sep 2022 22:44:43 +0200 Subject: [PATCH 65/91] mt76: update to the latest version d70546462b7b mt76: fix 5 GHz connection regression on mt76x0/mt76x2 Signed-off-by: Felix Fietkau --- package/kernel/mt76/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index ff58d27bc27032..998320ac5c804b 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -8,9 +8,9 @@ PKG_LICENSE_FILES:= PKG_SOURCE_URL:=https://github.com/openwrt/mt76 PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2022-08-26 -PKG_SOURCE_VERSION:=5ec78e1ec43d1e39edfea1efb9fd4541fa004af0 -PKG_MIRROR_HASH:=b96ec5199d423dc27e4fe7f0e94c8d5970f6db812237816235f3b735a5cb216a +PKG_SOURCE_DATE:=2022-09-06 +PKG_SOURCE_VERSION:=d70546462b7b51ebc2bcdd5c534fdf3465be62a4 +PKG_MIRROR_HASH:=3d6b68d70a78c0072ed10ab2548344b6b3a70ad99e4edc258fafa16886f4abf9 PKG_MAINTAINER:=Felix Fietkau PKG_USE_NINJA:=0 From 884e63fa68f717a3feb14c930cc0269f0450ef5a Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 7 Sep 2022 03:54:34 +0100 Subject: [PATCH 66/91] kernel: refresh patches The introduction of the new Airoha target has left the tree in an unfresh state. Refresh patches to improve that situation. Signed-off-by: Daniel Golle --- ...nd-Add-support-for-Etron-EM73D044VCx.patch | 23 ++++++------------- ...t-sfp-add-support-for-HALNy-GPON-SFP.patch | 2 +- ...lay-a-little-bit-the-dirmap-creation.patch | 4 ++-- ...te-direct-mapping-descriptors-for-EC.patch | 2 +- .../330-snand-mtk-bmt-support.patch | 6 ++--- 5 files changed, 14 insertions(+), 23 deletions(-) diff --git a/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch b/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch index a48e02fc083bca..c32e15d0c642d7 100644 --- a/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch +++ b/target/linux/generic/pending-5.15/487-mtd-spinand-Add-support-for-Etron-EM73D044VCx.patch @@ -1,5 +1,3 @@ -diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile -index 9c64d9fc..5f99ea72 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,3 @@ @@ -7,21 +5,16 @@ index 9c64d9fc..5f99ea72 100644 -spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o +spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o -diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c -index 9839ee44..9ab44217 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -898,6 +898,7 @@ static const struct nand_ops spinand_ops = { +@@ -898,6 +898,7 @@ static const struct nand_ops spinand_ops static const struct spinand_manufacturer *spinand_manufacturers[] = { - &esmt_c8_spinand_manufacturer, - &gigadevice_spinand_manufacturer, + &esmt_c8_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + &etron_spinand_manufacturer, - ¯onix_spinand_manufacturer, - µn_spinand_manufacturer, - ¶gon_spinand_manufacturer, -diff --git a/drivers/mtd/nand/spi/etron.c b/drivers/mtd/nand/spi/etron.c -new file mode 100644 -index 00000000..653092be + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, + ¶gon_spinand_manufacturer, --- /dev/null +++ b/drivers/mtd/nand/spi/etron.c @@ -0,0 +1,98 @@ @@ -123,12 +116,10 @@ index 00000000..653092be + .nchips = ARRAY_SIZE(etron_spinand_table), + .ops = &etron_spinand_manuf_ops, +}; -diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h -index 2066962d..11d38d2f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -261,6 +261,7 @@ struct spinand_manufacturer { - + /* SPI NAND manufacturers */ extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; +extern const struct spinand_manufacturer etron_spinand_manufacturer; diff --git a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch b/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch index 9ec47812734834..85c1d5b2031deb 100644 --- a/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch +++ b/target/linux/generic/pending-5.15/773-net-sfp-add-support-for-HALNy-GPON-SFP.patch @@ -24,7 +24,7 @@ Signed-off-by: Russell King (Oracle) + if (bus->sfp_quirk && bus->sfp_quirk->modes) bus->sfp_quirk->modes(id, modes); - bitmap_or(support, support, modes, __ETHTOOL_LINK_MODE_MASK_NBITS); + linkmode_or(support, support, modes); --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -320,6 +320,23 @@ static void sfp_fixup_ignore_tx_fault(st diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch index 192b1221edd751..0f69b30e947204 100644 --- a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch +++ b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch @@ -18,7 +18,7 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@b --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c -@@ -1210,14 +1210,6 @@ static int spinand_init(struct spinand_d +@@ -1211,14 +1211,6 @@ static int spinand_init(struct spinand_d if (ret) goto err_free_bufs; @@ -33,7 +33,7 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@b ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); if (ret) goto err_manuf_cleanup; -@@ -1252,6 +1244,14 @@ static int spinand_init(struct spinand_d +@@ -1253,6 +1245,14 @@ static int spinand_init(struct spinand_d mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch index 86df0270d8211c..1188872bd78731 100644 --- a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch +++ b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch @@ -87,7 +87,7 @@ Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@b --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h -@@ -391,6 +391,8 @@ struct spinand_info { +@@ -392,6 +392,8 @@ struct spinand_info { struct spinand_dirmap { struct spi_mem_dirmap_desc *wdesc; struct spi_mem_dirmap_desc *rdesc; diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch index 48bfb0d358153a..cd1745dd7a223f 100644 --- a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch +++ b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch @@ -8,7 +8,7 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { -@@ -1332,6 +1333,7 @@ static int spinand_probe(struct spi_mem +@@ -1333,6 +1334,7 @@ static int spinand_probe(struct spi_mem if (ret) return ret; @@ -16,7 +16,7 @@ ret = mtd_device_register(mtd, NULL, 0); if (ret) goto err_spinand_cleanup; -@@ -1339,6 +1341,7 @@ static int spinand_probe(struct spi_mem +@@ -1340,6 +1342,7 @@ static int spinand_probe(struct spi_mem return 0; err_spinand_cleanup: @@ -24,7 +24,7 @@ spinand_cleanup(spinand); return ret; -@@ -1357,6 +1360,7 @@ static int spinand_remove(struct spi_mem +@@ -1358,6 +1361,7 @@ static int spinand_remove(struct spi_mem if (ret) return ret; From 017aea00164edca28b87910ef725a18262bac1b2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 7 Sep 2022 03:50:42 +0100 Subject: [PATCH 67/91] kernel: mtk_eth_soc: fix hw hash reporting for MT7986 Import patch from Linux 6.0. Signed-off-by: Daniel Golle --- ..._eth_soc-fix-hw-hash-reporting-for-M.patch | 74 +++++++++++++++++++ ...net-mtk_eth_soc-enable-threaded-NAPI.patch | 6 +- ...mediatek-add-flow-offload-for-mt7623.patch | 2 +- ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 2 +- ...ethernet-mediatek-support-net-labels.patch | 4 +- ...y-simplify-phy_link_change-arguments.patch | 2 +- 6 files changed, 82 insertions(+), 8 deletions(-) create mode 100644 target/linux/generic/backport-5.15/710-v6.0-net-ethernet-mtk_eth_soc-fix-hw-hash-reporting-for-M.patch diff --git a/target/linux/generic/backport-5.15/710-v6.0-net-ethernet-mtk_eth_soc-fix-hw-hash-reporting-for-M.patch b/target/linux/generic/backport-5.15/710-v6.0-net-ethernet-mtk_eth_soc-fix-hw-hash-reporting-for-M.patch new file mode 100644 index 00000000000000..87941ef766a42c --- /dev/null +++ b/target/linux/generic/backport-5.15/710-v6.0-net-ethernet-mtk_eth_soc-fix-hw-hash-reporting-for-M.patch @@ -0,0 +1,74 @@ +From 0cf731f9ebb5bf6f252055bebf4463a5c0bd490b Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 23 Aug 2022 14:24:07 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix hw hash reporting for + MTK_NETSYS_V2 + +Properly report hw rx hash for mt7986 chipset accroding to the new dma +descriptor layout. + +Fixes: 197c9e9b17b11 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset") +Signed-off-by: Lorenzo Bianconi +Link: https://lore.kernel.org/r/091394ea4e705fbb35f828011d98d0ba33808f69.1661257293.git.lorenzo@kernel.org +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 +++++++++++---------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +++++ + 2 files changed, 17 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1469,10 +1469,19 @@ static int mtk_poll_rx(struct napi_struc + skb->dev = netdev; + skb_put(skb, pktlen); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; ++ if (hash != MTK_RXD5_FOE_ENTRY) ++ skb_set_hash(skb, jhash_1word(hash, 0), ++ PKT_HASH_TYPE_L4); + rxdcsum = &trxd.rxd3; +- else ++ } else { ++ hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; ++ if (hash != MTK_RXD4_FOE_ENTRY) ++ skb_set_hash(skb, jhash_1word(hash, 0), ++ PKT_HASH_TYPE_L4); + rxdcsum = &trxd.rxd4; ++ } + + if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) + skb->ip_summed = CHECKSUM_UNNECESSARY; +@@ -1481,16 +1490,9 @@ static int mtk_poll_rx(struct napi_struc + skb->protocol = eth_type_trans(skb, netdev); + bytes += pktlen; + +- hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; +- if (hash != MTK_RXD4_FOE_ENTRY) { +- hash = jhash_1word(hash, 0); +- skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); +- } +- + reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); + if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) +- mtk_ppe_check_skb(eth->ppe, skb, +- trxd.rxd4 & MTK_RXD4_FOE_ENTRY); ++ mtk_ppe_check_skb(eth->ppe, skb, hash); + + if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -307,6 +307,11 @@ + #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ + #define RX_DMA_SPECIAL_TAG BIT(22) + ++/* PDMA descriptor rxd5 */ ++#define MTK_RXD5_FOE_ENTRY GENMASK(14, 0) ++#define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18) ++#define MTK_RXD5_SRC_PORT GENMASK(29, 26) ++ + #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf) + #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7) + diff --git a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index e3e338bd4ffc65..298122375fd34d 100644 --- a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2381,8 +2381,8 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -2383,8 +2383,8 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -2394,8 +2394,8 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -2396,8 +2396,8 @@ static irqreturn_t mtk_handle_irq_tx(int eth->tx_events++; if (likely(napi_schedule_prep(ð->tx_napi))) { @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -3585,6 +3585,8 @@ static int mtk_probe(struct platform_dev +@@ -3587,6 +3587,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); diff --git a/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch b/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch index 4c0d1001e0fc3c..9b0d411bbacea5 100644 --- a/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch +++ b/target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch @@ -14,7 +14,7 @@ Signed-off-by: Frank Wunderlich --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3637,6 +3637,7 @@ static const struct mtk_soc_data mt2701_ +@@ -3639,6 +3639,7 @@ static const struct mtk_soc_data mt2701_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, diff --git a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch index de1079ffae5165..7544787701633d 100644 --- a/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ b/target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch @@ -113,7 +113,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -322,9 +322,12 @@ +@@ -327,9 +327,12 @@ #define PHY_IAC_ADDR_MASK GENMASK(24, 20) #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) #define PHY_IAC_CMD_MASK GENMASK(19, 18) diff --git a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch index 8a39c81e01774b..43526f3c4a76fa 100644 --- a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3228,6 +3228,7 @@ static const struct net_device_ops mtk_n +@@ -3230,6 +3230,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -3347,6 +3348,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -3349,6 +3350,9 @@ static int mtk_add_mac(struct mtk_eth *e else eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; diff --git a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index 063b317fd5ce24..94e99da015e1b8 100644 --- a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c phydev->mii_ts->link_state(phydev->mii_ts, phydev); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -1315,7 +1315,8 @@ void phylink_destroy(struct phylink *pl) +@@ -1323,7 +1323,8 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); From e12504a4d0180dd4c6d148c92e49b452a8c245b1 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 21 Aug 2022 23:04:58 +0200 Subject: [PATCH 68/91] tools/cmake: refresh patches Previous commit forgot to refresh the patches. This commit refreshes the patches: - 120-curl-fix-libressl-linking.patch - 130-bootstrap_parallel_make_flag.patch Fixes: 3b2f19271cc2 ("tools/cmake: update to 3.24.1") Signed-off-by: Nick Hainke --- tools/cmake/patches/120-curl-fix-libressl-linking.patch | 2 +- tools/cmake/patches/130-bootstrap_parallel_make_flag.patch | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/cmake/patches/120-curl-fix-libressl-linking.patch b/tools/cmake/patches/120-curl-fix-libressl-linking.patch index fd05d106c81e46..6ef37c22cb2531 100644 --- a/tools/cmake/patches/120-curl-fix-libressl-linking.patch +++ b/tools/cmake/patches/120-curl-fix-libressl-linking.patch @@ -20,7 +20,7 @@ Signed-off-by: Jo-Philipp Wich --- --- a/Utilities/cmcurl/CMakeLists.txt +++ b/Utilities/cmcurl/CMakeLists.txt -@@ -565,6 +565,14 @@ if(CMAKE_USE_OPENSSL) +@@ -594,6 +594,14 @@ if(CURL_USE_OPENSSL) endif() set(SSL_ENABLED ON) set(USE_OPENSSL ON) diff --git a/tools/cmake/patches/130-bootstrap_parallel_make_flag.patch b/tools/cmake/patches/130-bootstrap_parallel_make_flag.patch index dd66989c982e19..2b3ba361bd98a7 100644 --- a/tools/cmake/patches/130-bootstrap_parallel_make_flag.patch +++ b/tools/cmake/patches/130-bootstrap_parallel_make_flag.patch @@ -1,6 +1,6 @@ --- a/bootstrap +++ b/bootstrap -@@ -1423,7 +1423,10 @@ int main(){ printf("1%c", (char)0x0a); r +@@ -1441,7 +1441,10 @@ int main(){ printf("1%c", (char)0x0a); r ' > "test.c" cmake_original_make_flags="${cmake_make_flags}" if test "x${cmake_parallel_make}" != "x"; then From fed8550df744ebf4ab0e867f0f82357ca79db41e Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Sun, 28 Aug 2022 21:21:32 +0200 Subject: [PATCH 69/91] xdp-tools: update to v1.2.6 Release Notes: https://github.com/xdp-project/xdp-tools/releases/tag/v1.2.6 The update contains important fixes for cross-compilation. Signed-off-by: Nick Hainke --- package/network/utils/xdp-tools/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/network/utils/xdp-tools/Makefile b/package/network/utils/xdp-tools/Makefile index 7d831d0fece7d4..32f302543a1de8 100644 --- a/package/network/utils/xdp-tools/Makefile +++ b/package/network/utils/xdp-tools/Makefile @@ -2,8 +2,8 @@ include $(TOPDIR)/rules.mk PKG_NAME:=xdp-tools PKG_RELEASE:=$(AUTORELEASE) -PKG_VERSION:=1.2.5 -PKG_HASH:=140c9bdffe4f2b15bc2973b5f975d0fa5cc011f5a699c7bcdcb698b724b97d4d +PKG_VERSION:=1.2.6 +PKG_HASH:=e1bead15014adf404c1ae93b5bb24e6625840b4aadef6c1acfb47e0b99039f52 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://codeload.github.com/xdp-project/xdp-tools/tar.gz/v$(PKG_VERSION)? From 534e72ea0f8138b8581bb0618417dfe0e94bbbb4 Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 07:18:32 +0200 Subject: [PATCH 70/91] tools/pkgconf: update to 1.9.3 Release Notes: https://github.com/pkgconf/pkgconf/blob/pkgconf-1.9.3/NEWS Signed-off-by: Nick Hainke --- tools/pkgconf/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/pkgconf/Makefile b/tools/pkgconf/Makefile index d2f3252b12ef44..b5f241b7dce131 100644 --- a/tools/pkgconf/Makefile +++ b/tools/pkgconf/Makefile @@ -7,11 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=pkgconf -PKG_VERSION:=1.8.0 +PKG_VERSION:=1.9.3 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://distfiles.dereferenced.org/pkgconf -PKG_HASH:=ef9c7e61822b7cb8356e6e9e1dca58d9556f3200d78acab35e4347e9d4c2bbaf +PKG_HASH:=5fb355b487d54fb6d341e4f18d4e2f7e813a6622cf03a9e87affa6a40565699d include $(INCLUDE_DIR)/host-build.mk include $(INCLUDE_DIR)/meson.mk From 7b8f2dc6eca371a0edfcf3c14fb89983fcbe69eb Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 07:26:52 +0200 Subject: [PATCH 71/91] tools/bc: update to 1.07 Update to latest version. Replace mirror with @GNU/bc. Manually refresh: - 001-no_doc.patch Add patch found here: https://github.com/fivepiece/gnu-bc/commit/26f275502dd28114e78bc098fed81acde1d86d62 as 002-fix-libmath.patch to fix compilation. Add another patch found here: https://github.com/archlinux/svntogit-packages/commit/55b26eda94e1a9ff726ac458fccab5f3f3ad2114 as 003-bc-fix-hang.patch to prevent a hang when building the kernel. Signed-off-by: Nick Hainke --- tools/bc/Makefile | 11 ++++----- tools/bc/patches/001-no_doc.patch | 24 +++++++++---------- tools/bc/patches/002-fix-libmath.patch | 32 ++++++++++++++++++++++++++ tools/bc/patches/003-bc-fix-hang.patch | 11 +++++++++ 4 files changed, 58 insertions(+), 20 deletions(-) create mode 100644 tools/bc/patches/002-fix-libmath.patch create mode 100644 tools/bc/patches/003-bc-fix-hang.patch diff --git a/tools/bc/Makefile b/tools/bc/Makefile index dc021024cd9035..9e1b2ba3361758 100644 --- a/tools/bc/Makefile +++ b/tools/bc/Makefile @@ -7,14 +7,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=bc -PKG_VERSION:=1.06.95 +PKG_VERSION:=1.07 -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=https://alpha.gnu.org/gnu/bc \ - https://gnualpha.uib.no/bc/ \ - https://mirrors.fe.up.pt/pub/gnu-alpha/bc/ \ - https://www.nic.funet.fi/pub/gnu/alpha/gnu/bc/ -PKG_HASH:=7ee4abbcfac03d8a6e1a8a3440558a3d239d6b858585063e745c760957725ecc +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz +PKG_SOURCE_URL:=@GNU/bc +PKG_HASH:=55cf1fc33a728d7c3d386cc7b0cb556eb5bacf8e0cb5a3fcca7f109fc61205ad PKG_FIXUP := autoreconf PKG_CPE_ID:=cpe:/a:gnu:bc diff --git a/tools/bc/patches/001-no_doc.patch b/tools/bc/patches/001-no_doc.patch index 50deee8c89d03a..119f111f491169 100644 --- a/tools/bc/patches/001-no_doc.patch +++ b/tools/bc/patches/001-no_doc.patch @@ -1,6 +1,5 @@ -diff -urN bc-1.06.95/Makefile.am bc-1.06.95.new/Makefile.am ---- bc-1.06.95/Makefile.am 2005-05-27 01:05:41.000000000 +0100 -+++ bc-1.06.95.new/Makefile.am 2013-07-09 09:33:31.521490710 +0100 +--- a/Makefile.am ++++ b/Makefile.am @@ -1,6 +1,6 @@ ## Process this file with automake to produce Makefile.in @@ -8,16 +7,15 @@ diff -urN bc-1.06.95/Makefile.am bc-1.06.95.new/Makefile.am +SUBDIRS = lib bc dc MAINTAINERCLEANFILES = aclocal.m4 config.h.in configure Makefile.in \ - stamp-h $(distdir).tar.gz h/number.h depcomp missing -diff -urN bc-1.06.95/Makefile.in bc-1.06.95.new/Makefile.in ---- bc-1.06.95/Makefile.in 2006-09-05 03:39:30.000000000 +0100 -+++ bc-1.06.95.new/Makefile.in 2013-07-09 09:33:28.565490767 +0100 -@@ -149,7 +149,7 @@ - sharedstatedir = @sharedstatedir@ - sysconfdir = @sysconfdir@ - target_alias = @target_alias@ + stamp-h $(distdir).tar.gz h/number.h depcomp missing \ +--- a/Makefile.in ++++ b/Makefile.in +@@ -288,7 +288,7 @@ target_alias = @target_alias@ + top_build_prefix = @top_build_prefix@ + top_builddir = @top_builddir@ + top_srcdir = @top_srcdir@ -SUBDIRS = lib bc dc doc +SUBDIRS = lib bc dc MAINTAINERCLEANFILES = aclocal.m4 config.h.in configure Makefile.in \ - stamp-h $(distdir).tar.gz h/number.h depcomp missing - + stamp-h $(distdir).tar.gz h/number.h depcomp missing \ + bc/libmath.h diff --git a/tools/bc/patches/002-fix-libmath.patch b/tools/bc/patches/002-fix-libmath.patch new file mode 100644 index 00000000000000..1a8439542da0a1 --- /dev/null +++ b/tools/bc/patches/002-fix-libmath.patch @@ -0,0 +1,32 @@ +--- a/bc/fix-libmath_h ++++ b/bc/fix-libmath_h +@@ -1,9 +1,9 @@ +-ed libmath.h < Date: Mon, 29 Aug 2022 07:48:53 +0200 Subject: [PATCH 72/91] tools/expat: update to 2.4.8 Release Notes: https://github.com/libexpat/libexpat/blob/R_2_4_8/expat/Changes Signed-off-by: Nick Hainke --- tools/expat/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/expat/Makefile b/tools/expat/Makefile index fc339f818a32ce..7079dabcaf465a 100644 --- a/tools/expat/Makefile +++ b/tools/expat/Makefile @@ -9,10 +9,10 @@ include $(TOPDIR)/rules.mk PKG_NAME:=expat PKG_CPE_ID:=cpe:/a:libexpat:expat -PKG_VERSION:=2.4.7 +PKG_VERSION:=2.4.8 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_HASH:=e149bdd8b90254c62b3d195da53a09bd531a4d63a963b0d8a5268d48dd2f6a65 +PKG_HASH:=a247a7f6bbb21cf2ca81ea4cbb916bfb9717ca523631675f99b3d4a5678dcd16 PKG_SOURCE_URL:=https://github.com/libexpat/libexpat/releases/download/R_$(subst .,_,$(PKG_VERSION)) include $(INCLUDE_DIR)/host-build.mk From f94b67d893dd6ab388c7a13215b512335b2f86fb Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 07:55:14 +0200 Subject: [PATCH 73/91] tools/fakeroot: update to 1.29 Release Notes: https://salsa.debian.org/clint/fakeroot/-/commit/8dd9e34a2e54862a902040d76adbd1c1a42ffc35 Refresh patches: - 400-alpine-libc.musl-fix.patch - 600-macOS.patch Signed-off-by: Nick Hainke --- tools/fakeroot/Makefile | 4 ++-- tools/fakeroot/patches/400-alpine-libc.musl-fix.patch | 2 +- tools/fakeroot/patches/600-macOS.patch | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/fakeroot/Makefile b/tools/fakeroot/Makefile index c29f51e77f5e23..5d31e197819f1f 100644 --- a/tools/fakeroot/Makefile +++ b/tools/fakeroot/Makefile @@ -5,12 +5,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=fakeroot -PKG_VERSION:=1.28 +PKG_VERSION:=1.29 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).orig.tar.gz PKG_SOURCE_URL:=@DEBIAN/pool/main/f/fakeroot -PKG_HASH:=56d405e36ff685f83879be08fdd654255ab9aa38632b4605a98e896ad63990c2 +PKG_HASH:=8fbbafb780c9173e3ace4a04afbc1d900f337f3216883939f5c7db3431be7c20 PKG_LICENSE:=GPL-3.0-or-later PKG_LICENSE_FILES:=COPYING PKG_FIXUP:=autoreconf diff --git a/tools/fakeroot/patches/400-alpine-libc.musl-fix.patch b/tools/fakeroot/patches/400-alpine-libc.musl-fix.patch index 530c96842efbad..f740b120a14eac 100644 --- a/tools/fakeroot/patches/400-alpine-libc.musl-fix.patch +++ b/tools/fakeroot/patches/400-alpine-libc.musl-fix.patch @@ -21,7 +21,7 @@ Error relocating openwrt/staging_dir/host/lib/libfakeroot.so: SEND_GET_XATTR: sy #define SEND_GET_XATTR64(a,b,c) send_get_xattr64(a,b) #endif -@@ -140,8 +142,9 @@ +@@ -142,8 +144,9 @@ /* 10.10 uses id_t in getpriority/setpriority calls, so pretend id_t is used everywhere, just happens to be int on some OSes */ diff --git a/tools/fakeroot/patches/600-macOS.patch b/tools/fakeroot/patches/600-macOS.patch index f9d6d189b25a64..730367f07c7fad 100644 --- a/tools/fakeroot/patches/600-macOS.patch +++ b/tools/fakeroot/patches/600-macOS.patch @@ -36,7 +36,7 @@ posix_spawn;int;(pid_t * __restrict pid, const char * __restrict path, const posix_spawn_file_actions_t *file_actions, const posix_spawnattr_t * __restrict attrp, char *const argv[ __restrict], char *const envp[ __restrict]);(pid, path, file_actions, attrp, argv, envp) posix_spawnp;int;(pid_t * __restrict pid, const char * __restrict path, const posix_spawn_file_actions_t *file_actions, const posix_spawnattr_t * __restrict attrp, char *const argv[ __restrict], char *const envp[ __restrict]);(pid, path, file_actions, attrp, argv, envp) #endif -@@ -232,7 +234,7 @@ facl;int;(int fd, int cmd, int cnt, void +@@ -229,7 +231,7 @@ facl;int;(int fd, int cmd, int cnt, void #ifdef HAVE_FTS_READ fts_read;FTSENT *;(FTS *ftsp);(ftsp) #ifdef __APPLE__ @@ -45,7 +45,7 @@ fts_read$INODE64;FTSENT *;(FTS *ftsp);(ftsp) #endif #endif /* ifdef __APPLE__ */ -@@ -240,7 +242,7 @@ fts_read$INODE64;FTSENT *;(FTS *ftsp);(f +@@ -237,7 +239,7 @@ fts_read$INODE64;FTSENT *;(FTS *ftsp);(f #ifdef HAVE_FTS_CHILDREN fts_children;FTSENT *;(FTS *ftsp, int options);(ftsp, options) #ifdef __APPLE__ From da95084d3478226bede2aed04e21f47525b7e0ad Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 08:03:08 +0200 Subject: [PATCH 74/91] tools/meson: update to 0.63.1 Release Notes: - 0.62.0 https://mesonbuild.com/Release-notes-for-0-62-0.html - 0.63.0 https://mesonbuild.com/Release-notes-for-0-63-0.html - (other notes are not available) Signed-off-by: Nick Hainke --- tools/meson/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/meson/Makefile b/tools/meson/Makefile index d53ed897a3509a..13dcb114554798 100644 --- a/tools/meson/Makefile +++ b/tools/meson/Makefile @@ -1,11 +1,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=meson -PKG_VERSION:=0.61.5 +PKG_VERSION:=0.63.1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/mesonbuild/meson/releases/download/$(PKG_VERSION) -PKG_HASH:=5e9a0d65c1a51936362b9686d1c5e9e184a6fd245d57e7269750ce50c20f5d9a +PKG_HASH:=06fe13297213d6ff0121c5d5aab25a56ef938ffec57414ed6086fda272cb65e9 PKG_MAINTAINER:=Andre Heider PKG_LICENSE:=Apache-2.0 From 7cae91493901878167cc6e9af81e389214e405cc Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 08:17:58 +0200 Subject: [PATCH 75/91] libunwind: update to 1.6.2 Remove upstreamed: - 001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch Signed-off-by: Nick Hainke --- package/libs/libunwind/Makefile | 6 ++-- ...ce-exec_prefix-lib64-libdir-on-ppc64.patch | 29 ------------------- 2 files changed, 3 insertions(+), 32 deletions(-) delete mode 100644 package/libs/libunwind/patches/001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch diff --git a/package/libs/libunwind/Makefile b/package/libs/libunwind/Makefile index f129dafcbf3b96..c676d501bd5d91 100644 --- a/package/libs/libunwind/Makefile +++ b/package/libs/libunwind/Makefile @@ -9,12 +9,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=libunwind -PKG_VERSION:=1.5.0 -PKG_RELEASE:=2 +PKG_VERSION:=1.6.2 +PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@SAVANNAH/$(PKG_NAME) -PKG_HASH:=90337653d92d4a13de590781371c604f9031cdb50520366aa1e3a91e1efb1017 +PKG_HASH:=4a6aec666991fb45d0889c44aede8ad6eb108071c3554fcdff671f9c94794976 PKG_MAINTAINER:=Yousong Zhou PKG_LICENSE:=X11 diff --git a/package/libs/libunwind/patches/001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch b/package/libs/libunwind/patches/001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch deleted file mode 100644 index d6010ec0ae47fe..00000000000000 --- a/package/libs/libunwind/patches/001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0af7e7a53480ce8e1cf6cfb4e9fe071c1185ef31 Mon Sep 17 00:00:00 2001 -From: Matthias Diener -Date: Fri, 2 Jul 2021 12:36:10 -0500 -Subject: [PATCH] Don't force {exec_prefix}/lib64 libdir on ppc64 - ---- - configure.ac | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/configure.ac b/configure.ac -index 9fadc163..0dec4ca6 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -215,12 +215,6 @@ fi - AM_CONDITIONAL(USE_DWARF, [test x$use_dwarf = xyes]) - AC_MSG_RESULT([$use_dwarf]) - --if test x$target_arch = xppc64; then -- libdir='${exec_prefix}/lib64' -- AC_MSG_NOTICE([PowerPC64 detected, lib will be installed ${libdir}]); -- AC_SUBST([libdir]) --fi -- - AC_MSG_CHECKING([whether to restrict build to remote support]) - if test x$target_arch != x$host_arch; then - CPPFLAGS="${CPPFLAGS} -DUNW_REMOTE_ONLY" --- -2.32.0 - From 8ad03a2cd750301a4b60d2aee760b76e58afc88b Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Mon, 29 Aug 2022 13:35:06 +0200 Subject: [PATCH 76/91] tools/llvm: update to 14.0.6 Update to latest version. Signed-off-by: Nick Hainke --- tools/llvm-bpf/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/llvm-bpf/Makefile b/tools/llvm-bpf/Makefile index 527b3578242767..775e1af896be60 100644 --- a/tools/llvm-bpf/Makefile +++ b/tools/llvm-bpf/Makefile @@ -7,12 +7,12 @@ include $(TOPDIR)/rules.mk PKG_NAME:=llvm-project -PKG_VERSION:=13.0.0 +PKG_VERSION:=14.0.6 PKG_RELEASE:=1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).src.tar.xz PKG_SOURCE_URL:=https://github.com/llvm/llvm-project/releases/download/llvmorg-$(PKG_VERSION) -PKG_HASH:=6075ad30f1ac0e15f07c1bf062c1e1268c241d674f11bd32cdf0e040c71f2bf3 +PKG_HASH:=8b3cfd7bc695bd6cea0f37f53f0981f34f87496e79e2529874fd03a2f9dd3a8a HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION).src From 292146fda64cb8a72c986bb18edd48d5383fbefa Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 6 Sep 2022 21:16:06 +0100 Subject: [PATCH 77/91] arm-trusted-firmware-tools: update to v2.7 Update host build of fiptool and use the new python sptool.py instead of the previous sptool executable. Signed-off-by: Daniel Golle --- package/boot/arm-trusted-firmware-tools/Makefile | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/package/boot/arm-trusted-firmware-tools/Makefile b/package/boot/arm-trusted-firmware-tools/Makefile index a7112724c0f90d..81c8a99cbc21af 100644 --- a/package/boot/arm-trusted-firmware-tools/Makefile +++ b/package/boot/arm-trusted-firmware-tools/Makefile @@ -8,9 +8,9 @@ include $(TOPDIR)/rules.mk PKG_NAME:=arm-trusted-firmware-tools -PKG_VERSION:=2.4 +PKG_VERSION:=2.7 PKG_RELEASE:=1 -PKG_HASH:=bf3eb3617a74cddd7fb0e0eacbfe38c3258ee07d4c8ed730deef7a175cc3d55b +PKG_HASH:=53422dc649153838e03820330ba17cb10afe3e330ecde0db11e4d5f1361a33e6 PKG_MAINTAINER:=Daniel Golle PKG_HOST_ONLY:=1 @@ -34,23 +34,17 @@ define Host/Compile $(HOST_BUILD_DIR)/tools/fiptool \ CPPFLAGS="$(HOST_CFLAGS)" \ LDFLAGS="$(HOST_LDFLAGS)" - $(MAKE) -C \ - $(HOST_BUILD_DIR)/tools/sptool \ - CPPFLAGS="$(HOST_CFLAGS)" \ - LDFLAGS="$(HOST_LDFLAGS)" endef define Host/Install $(INSTALL_DIR) $(STAGING_DIR_HOST)/bin/ $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/ - $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sptool $(STAGING_DIR_HOST)/bin/ - $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sp_mk_generator.py $(STAGING_DIR_HOST)/bin/ + $(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sptool.py $(STAGING_DIR_HOST)/bin/ endef define Host/Clean rm -f $(STAGING_DIR_HOST)/bin/fiptool - rm -f $(STAGING_DIR_HOST)/bin/sptool - rm -f $(STAGING_DIR_HOST)/bin/sp_mk_generator.py + rm -f $(STAGING_DIR_HOST)/bin/sptool.py $(STAGING_DIR_HOST)/bin/sptool endef $(eval $(call BuildPackage,arm-trusted-firmware-tools)) From 3df72f69288a6234125cefd516bd75289794bb6b Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 7 Sep 2022 04:23:22 +0100 Subject: [PATCH 78/91] mediatek: remove redundant patch The patch 921-mt7986-add-mmc-support.patch introduced by commit dabcaac443 ("mediatek: add mt7986 soc support to the target") has never been applied in a way that it would have any effect as it actually created a file target/linux/generic/patches-5.15/... in the kernel tree and was probably a patch intended to be applied to openwrt.git instead of being put into kernel patches folder as a file. As an upstream commit from vanilla Linux also adding support for MT7986 to the mtk-sd driver has already been included we can remove that old patch. Signed-off-by: Daniel Golle --- .../921-mt7986-add-mmc-support.patch | 47 ------------------- 1 file changed, 47 deletions(-) delete mode 100644 target/linux/mediatek/patches-5.15/921-mt7986-add-mmc-support.patch diff --git a/target/linux/mediatek/patches-5.15/921-mt7986-add-mmc-support.patch b/target/linux/mediatek/patches-5.15/921-mt7986-add-mmc-support.patch deleted file mode 100644 index 18b6e97d06562c..00000000000000 --- a/target/linux/mediatek/patches-5.15/921-mt7986-add-mmc-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0f8a0dd620b2fb5f9c852844ce5f445bb0bd6d52 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Wed, 4 May 2022 10:27:43 +0800 -Subject: [PATCH 5/5] mediatek: add mt7986a mmc support - -Add mt7986a boot mmc support - -Signed-off-by: Sam Shih ---- - ...-mmc-mediatek-add-mt7986-mmc-support.patch | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - create mode 100644 target/linux/mediatek/patches-5.15/0704-mmc-mediatek-add-mt7986-mmc-support.patch - ---- /dev/null -+++ b/target/linux/mediatek/patches-5.15/0704-mmc-mediatek-add-mt7986-mmc-support.patch -@@ -0,0 +1,31 @@ -+diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c -+index 1ac9201..a32349c 100644 -+--- a/drivers/mmc/host/mtk-sd.c -++++ b/drivers/mmc/host/mtk-sd.c -+@@ -540,6 +540,18 @@ static const struct mtk_mmc_compatible mt7622_compat = { -+ .support_64g = false, -+ }; -+ -++static const struct mtk_mmc_compatible mt7986_compat = { -++ .clk_div_bits = 12, -++ .hs400_tune = false, -++ .pad_tune_reg = MSDC_PAD_TUNE0, -++ .async_fifo = true, -++ .data_tune = true, -++ .busy_check = true, -++ .stop_clk_fix = true, -++ .enhance_rx = true, -++ .support_64g = true, -++}; -++ -+ static const struct mtk_mmc_compatible mt8516_compat = { -+ .clk_div_bits = 12, -+ .recheck_sdio_irq = true, -+@@ -584,6 +596,7 @@ static const struct of_device_id msdc_of_ids[] = { -+ { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, -+ { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, -+ { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, -++ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, -+ { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, -+ { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, -+ { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, From a99707d14c029cfa2d09c936418bb10316f76540 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 7 Sep 2022 04:46:31 +0100 Subject: [PATCH 79/91] Revert "tools/meson: update to 0.63.1" This reverts commit da95084d3478226bede2aed04e21f47525b7e0ad. It was pulled by accident. Signed-off-by: Daniel Golle --- tools/meson/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/meson/Makefile b/tools/meson/Makefile index 13dcb114554798..d53ed897a3509a 100644 --- a/tools/meson/Makefile +++ b/tools/meson/Makefile @@ -1,11 +1,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=meson -PKG_VERSION:=0.63.1 +PKG_VERSION:=0.61.5 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=https://github.com/mesonbuild/meson/releases/download/$(PKG_VERSION) -PKG_HASH:=06fe13297213d6ff0121c5d5aab25a56ef938ffec57414ed6086fda272cb65e9 +PKG_HASH:=5e9a0d65c1a51936362b9686d1c5e9e184a6fd245d57e7269750ce50c20f5d9a PKG_MAINTAINER:=Andre Heider PKG_LICENSE:=Apache-2.0 From 6c4cd857851b010eab73fdefd4ada6b23f6eb048 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Mon, 29 Aug 2022 16:22:18 +0200 Subject: [PATCH 80/91] kernel: load FAT filesystem drivers before mount_root Devices using GPT usually have FAT filesystem on boot partition and that's where the intermediary backup of system configuration is stored on sysupgrade. Automatic restoring of OpenWrt configuration after sysupgrade will be inhibited if the driver is not loaded and file system type is not specified in mount command. Signed-off-by: Tomasz Maciej Nowak --- package/kernel/linux/modules/fs.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/fs.mk b/package/kernel/linux/modules/fs.mk index 0e4c0c091a5ad6..3ad458286f450e 100644 --- a/package/kernel/linux/modules/fs.mk +++ b/package/kernel/linux/modules/fs.mk @@ -601,7 +601,7 @@ define KernelPackage/fs-vfat FILES:= \ $(LINUX_DIR)/fs/fat/fat.ko \ $(LINUX_DIR)/fs/fat/vfat.ko - AUTOLOAD:=$(call AutoLoad,30,fat vfat) + AUTOLOAD:=$(call AutoLoad,30,fat vfat,1) $(call AddDepends/nls,cp437 iso8859-1 utf8) endef From 3b7948474f73b356a6d99b95f17aae93235f298d Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Mon, 29 Aug 2022 16:21:52 +0200 Subject: [PATCH 81/91] kernel: load loop driver before creating overlay Creating overlay will fail if there's no loop device. Signed-off-by: Tomasz Maciej Nowak --- package/kernel/linux/modules/block.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/kernel/linux/modules/block.mk b/package/kernel/linux/modules/block.mk index 40a14a9be2b173..8affa722963ee9 100644 --- a/package/kernel/linux/modules/block.mk +++ b/package/kernel/linux/modules/block.mk @@ -465,7 +465,7 @@ define KernelPackage/loop CONFIG_BLK_DEV_LOOP \ CONFIG_BLK_DEV_CRYPTOLOOP=n FILES:=$(LINUX_DIR)/drivers/block/loop.ko - AUTOLOAD:=$(call AutoLoad,30,loop) + AUTOLOAD:=$(call AutoLoad,30,loop,1) endef define KernelPackage/loop/description From 80baffd2aa91a1e95f818e7e9f7d668d3b64ed42 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Tue, 6 Sep 2022 15:32:33 +0200 Subject: [PATCH 82/91] ipq40xx: add support for Pakedge WR-1 Pakedge WR-1 is a dual-band wireless router. Specification SoC: Qualcomm Atheros IPQ4018 RAM: 256 MB DDR3 Flash: 32 MB SPI NOR WIFI: 2.4 GHz 2T2R integrated 5 GHz 2T2R integrated Ethernet: 5x 10/100/1000 Mbps QCA8075 USB: 1x 2.0 LEDS: 8x (3 GPIO controlled, 5 connected to switch) Buttons: 1x GPIO controlled UART: pin header J5 1. 3.3V, 2. GND, 3. TX, 4. RX baud: 115200, parity: none, flow control: none Installation 1. Rename initramfs image to: openwrt-ipq806x-qcom-ipq40xx-ap.dk01.1-c1-fit-uImage-initramfs.itb and copy it to USB flash drive with FAT32 file system. 2. Connect USB flash drive to the router and apply power while pressing reset button. Hold the button, on the lates bootloader version, when Power and WiFi-5 LEDs will start blinking release it. For the older bootloader holding it for 15 seconds should suffice. 3. Now the router boots the initramfs image, at some point (close to one minute) the Power LED will start blinking, when stops, router is fully booted. 4. Connect to one of LAN ports and use SSH to open the shell at 192.168.1.1. 5. ATTENTION! now backup the mtd8 and mtd9 partitions, it's necessary if, at some point, You want to go back to original firmware. The firmware provided by manufacturer on its site is encrypted and U-Boot accepts only decrypted factory images, so there's no way to restore original firmware. 6. If the backup is prepared, transfer the sysupgrade image to the router and use 'sysupgrade' command to flash it. 7. After successful flashing router will reboot. At some point the Power LED will start blinking, wait till it stops, then router is ready for configuration. Additional information U-Boot command line is password protected. Password is unknown. Signed-off-by: Tomasz Maciej Nowak --- package/boot/uboot-envtools/files/ipq40xx | 1 + .../ipq40xx/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 8 + .../arch/arm/boot/dts/qcom-ipq4018-wr-1.dts | 264 ++++++++++++++++++ target/linux/ipq40xx/image/generic.mk | 12 + 5 files changed, 292 insertions(+) create mode 100644 target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts diff --git a/package/boot/uboot-envtools/files/ipq40xx b/package/boot/uboot-envtools/files/ipq40xx index 1937f9d1ce0c99..e45e26dcc7f757 100644 --- a/package/boot/uboot-envtools/files/ipq40xx +++ b/package/boot/uboot-envtools/files/ipq40xx @@ -40,6 +40,7 @@ luma,wrtq-329acn|\ netgear,wac510|\ openmesh,a42|\ openmesh,a62|\ +pakedge,wr-1|\ plasmacloud,pa1200|\ plasmacloud,pa2200) ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x10000" "0x10000" diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index a468c62b3c5c81..db58eb9363bfc0 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -138,6 +138,11 @@ ipq40xx_setup_interfaces() "0u@eth0" "2:lan" "3:lan" "4:lan" ucidef_set_interface_wan "eth1" ;; + pakedge,wr-1) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" \ + "0u@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "0u@eth1" "5:wan" + ;; qxwlan,e2600ac-c1 |\ qxwlan,e2600ac-c2) ucidef_set_interfaces_lan_wan "eth0" "eth1" @@ -221,6 +226,8 @@ ipq40xx_setup_macs() lan_mac=$(cat /sys/firmware/mikrotik/hard_config/mac_base) label_mac="$lan_mac" ;; + pakedge,wr-1) + wan_mac=$(macaddr_add $(get_mac_label) 1) esac [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index b488bf5ddb1de7..a0280b7f225a99 100644 --- a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -134,6 +134,10 @@ case "$FIRMWARE" in caldata_extract_mmc "0:ART" 0x1000 0x2f20 ath10k_patch_mac $(mmc_get_mac_binary ARTMTD 0x0) ;; + pakedge,wr-1) + caldata_extract "0:ART" 0x1000 0x2f20 + ath10k_patch_mac $(macaddr_add $(get_mac_label) 2) + ;; zyxel,nbg6617 |\ zyxel,wre6606) caldata_extract "ART" 0x1000 0x2f20 @@ -221,6 +225,10 @@ case "$FIRMWARE" in caldata_extract_mmc "0:ART" 0x5000 0x2f20 ath10k_patch_mac $(mmc_get_mac_binary ARTMTD 0xc) ;; + pakedge,wr-1) + caldata_extract "0:ART" 0x5000 0x2f20 + ath10k_patch_mac $(macaddr_add $(get_mac_label) 4) + ;; zyxel,nbg6617 |\ zyxel,wre6606) caldata_extract "ART" 0x5000 0x2f20 diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts new file mode 100644 index 00000000000000..26a8b013aaad65 --- /dev/null +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq4019.dtsi" +#include +#include +#include +#include + +/ { + model = "Pakedge WR-1"; + compatible = "pakedge,wr-1"; + + aliases { + label-mac-device = &gmac0; + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&key_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "blue:power"; + gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&tlmm 1 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy1tpt"; + }; + }; + + soc { + ess-psgmii@98000 { + status = "okay"; + }; + + tcsr@1949000 { + compatible = "qcom,tcsr"; + reg = <0x1949000 0x100>; + qcom,wifi_glb_cfg = ; + }; + + tcsr@194b000 { + compatible = "qcom,tcsr"; + reg = <0x194b000 0x100>; + qcom,usb-hsphy-mode-select = ; + }; + + ess_tcsr@1953000 { + compatible = "qcom,tcsr"; + reg = <0x1953000 0x1000>; + qcom,ess-interface-select = ; + }; + + tcsr@1957000 { + compatible = "qcom,tcsr"; + reg = <0x1957000 0x100>; + qcom,wifi_noc_memtype_m0_m2 = ; + }; + + ess-switch@c000000 { + status = "okay"; + }; + + edma@c080000 { + status = "okay"; + }; + }; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_spi1 { + status = "okay"; + + cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0020000>; + read-only; + }; + + partition@60000 { + label = "0:QSEE"; + reg = <0x0060000 0x0060000>; + read-only; + }; + + partition@c0000 { + label = "0:CDT"; + reg = <0x00c0000 0x0010000>; + read-only; + }; + + partition@d0000 { + label = "0:DDRPARAMS"; + reg = <0x00d0000 0x0010000>; + read-only; + }; + + partition@e0000 { + label = "0:APPSBLENV"; + reg = <0x00e0000 0x0010000>; + read-only; + }; + + partition@f0000 { + label = "0:APPSBL"; + reg = <0x00f0000 0x0080000>; + read-only; + }; + + partition@170000 { + label = "0:ART"; + reg = <0x0170000 0x0010000>; + read-only; + }; + + partition@180000 { + label = "firmware"; + reg = <0x0180000 0x1e80000>; + }; + }; + }; +}; + +&blsp1_uart1 { + status = "okay"; + + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; +}; + +&crypto { + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&prng { + status = "okay"; +}; + +&tlmm { + key_pins: key_pinmux { + mux { + function = "gpio"; + pins = "gpio59"; + bias-pull-up; + }; + }; + + led_pins: led_pinmux { + mux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2"; + bias-none; + drive-strength = <2>; + output-low; + }; + }; + + serial_pins: serial_pinmux { + mux { + function = "blsp_uart0"; + pins = "gpio60", "gpio61"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + mux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + bias-disable; + drive-strength = <12>; + }; + + mux_cs { + function = "gpio"; + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + output-high; + }; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi0 { + status = "okay"; +}; + +&wifi1 { + status = "okay"; +}; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index e8f8fa27b94027..5652bf9414b990 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -894,6 +894,18 @@ define Device/p2w_r619ac-128m endef TARGET_DEVICES += p2w_r619ac-128m +define Device/pakedge_wr-1 + $(call Device/FitImageLzma) + DEVICE_VENDOR := Pakedge + DEVICE_MODEL := WR-1 + DEVICE_DTS_CONFIG := config@ap.dk01.1-c1 + SOC := qcom-ipq4018 + BLOCKSIZE := 64k + IMAGE_SIZE := 31232k + IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | append-metadata +endef +TARGET_DEVICES += pakedge_wr-1 + define Device/plasmacloud_pa1200 $(call Device/FitImageLzma) DEVICE_VENDOR := Plasma Cloud From 47306d47ef1873f11cbfb2cd24f4e12a83a31301 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Tue, 6 Sep 2022 15:32:34 +0200 Subject: [PATCH 83/91] ipq-wifi: add Pakedge WR-1 support Calibration variants: Pakedge-WR-1 ETSI, FCC and IC-2.4GHz Pakedge-WR-1-ACMA ACMA Pakedge-WR-1-IC IC-5GHz Pakedge-WR-1-SRRC SRRC Signed-off-by: Tomasz Maciej Nowak --- package/firmware/ipq-wifi/Makefile | 2 ++ .../ipq-wifi/board-pakedge_wr-1.qca4019 | Bin 0 -> 85076 bytes .../arch/arm/boot/dts/qcom-ipq4018-wr-1.dts | 4 ++++ target/linux/ipq40xx/image/generic.mk | 1 + 4 files changed, 7 insertions(+) create mode 100644 package/firmware/ipq-wifi/board-pakedge_wr-1.qca4019 diff --git a/package/firmware/ipq-wifi/Makefile b/package/firmware/ipq-wifi/Makefile index 44d6e2a086d86f..7b683ef0a2a29a 100644 --- a/package/firmware/ipq-wifi/Makefile +++ b/package/firmware/ipq-wifi/Makefile @@ -34,6 +34,7 @@ ALLWIFIBOARDS:= \ glinet_gl-s1300 \ linksys_ea8300 \ p2w_r619ac \ + pakedge_wr-1 \ qxwlan_e2600ac-c1 \ qxwlan_e2600ac-c2 \ teltonika_rutx @@ -106,6 +107,7 @@ $(eval $(call generate-ipq-wifi-package,glinet_gl-ap1300,GL.iNet GL-AP1300)) $(eval $(call generate-ipq-wifi-package,glinet_gl-s1300,GL.iNet GL-S1300)) $(eval $(call generate-ipq-wifi-package,linksys_ea8300,Linksys EA8300)) $(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC)) +$(eval $(call generate-ipq-wifi-package,pakedge_wr-1,Pakedge WR-1)) $(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac-c1,Qxwlan E2600AC C1)) $(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac-c2,Qxwlan E2600AC C2)) $(eval $(call generate-ipq-wifi-package,teltonika_rutx,Teltonika RUTX)) diff --git a/package/firmware/ipq-wifi/board-pakedge_wr-1.qca4019 b/package/firmware/ipq-wifi/board-pakedge_wr-1.qca4019 new file mode 100644 index 0000000000000000000000000000000000000000..967a45258055c8b02c9e1b9369484372710780fa GIT binary patch literal 85076 zcmeHQdr%Ztx<9*JmVTyqKMwl$(&bIU_#{Ra8_Uusw;?9-(JoE2*ho zTU=HWUs6$?@Jd;EWkUI`wMq0*$-d&MUDRRns`%RCs`BE!udm%w{95U*S4$JN<|iaq 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zcC;u_s>Tcbv=5RU8VhP*?(7wmvEAb?(Ud}!k&4Ly7WC|>AZE>2h-=S{&*&gr*!a|V_b%*^UDbqlpA=tGQJzq;uefSgLiw(>$pU)!HoW_S zT%vc6?|i6~=-p#9h~7O$f=xYgIhPEYodCj~8=@rKS*gzuy?dz3B459$ilH?7n~etz zyY-vkv!ljPFyjcgWnEF*ATsXqIYlmI^;ig!w+?&OZ=D0I_i-qSwldM2m(a!p6K0^R{=r5 zQxTZ13Wq<}ct9LFTBHe}RXC!fmGB=FI3l7VBNdSa$Zb?O2=AWf!jaINM!+HOUM#O& z>U?t=b;pBq#JjgB%z!AodwNpq(@R|+(Ytp%2Ope+=-odUpSgRM=-tm|z57;>R$|w% z7?0NZ>I4-g+Y=^A^h>aWlzR6dux{J<1zPVOzHniCg3-GdDlwzHdrG&;w!6KQN|uBt zD77rxHcUfc61Fi{^zNx~*kVP`D+y0f-wCp9V}$xi1_|2`vu4cY*9-aV%;|+6xWK*c zHTU#j-!#gN3;9y%-LqH6Wa9cPqQk@7xR5_J-aQQfGxPz*x8IA=yQimEKRpRPWPJPm I+~(c?Kfg#3Z~y=R literal 0 HcmV?d00001 diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts index 26a8b013aaad65..be2f619b39dcc6 100644 --- a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wr-1.dts @@ -257,8 +257,12 @@ &wifi0 { status = "okay"; + + qcom,ath10k-calibration-variant = "Pakedge-WR-1"; }; &wifi1 { status = "okay"; + + qcom,ath10k-calibration-variant = "Pakedge-WR-1"; }; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 5652bf9414b990..98a40349b22be7 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -899,6 +899,7 @@ define Device/pakedge_wr-1 DEVICE_VENDOR := Pakedge DEVICE_MODEL := WR-1 DEVICE_DTS_CONFIG := config@ap.dk01.1-c1 + DEVICE_PACKAGES := ipq-wifi-pakedge_wr-1 SOC := qcom-ipq4018 BLOCKSIZE := 64k IMAGE_SIZE := 31232k From 1a6f6a1e8cbc29042f63771d5f05bdbe622d9078 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 8 Sep 2022 02:34:28 +0100 Subject: [PATCH 84/91] mediatek: bpi-r3: make initramfs/recovery optional Only include recovery image in SD card image generated for the BananaPi BPi-R3 if building with CONFIG_TARGET_ROOTFS_INITRAMFS. This allows to build images larger than 32 MB (the limit for initramfs/recovery image) by deselecting initramfs. Signed-off-by: Daniel Golle --- target/linux/mediatek/image/filogic.mk | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index dfc71bbb14155a..e36666124007f3 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -62,7 +62,9 @@ define Device/bananapi_bpi-r3 ARTIFACT/sdcard.img.gz := mt7986-gpt sdmmc |\ pad-to 17k | bl2 sdmmc-ddr4 |\ pad-to 6656k | bl31-uboot bananapi_bpi-r3-sdmmc |\ - pad-to 12M | append-image-stage initramfs-recovery.itb |\ + $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ + pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\ + ) \ pad-to 44M | bl2 spim-nand-ddr4 |\ pad-to 45M | bl31-uboot bananapi_bpi-r3-snand |\ pad-to 49M | bl2 nor-ddr4 |\ @@ -70,7 +72,10 @@ define Device/bananapi_bpi-r3 pad-to 51M | bl2 emmc-ddr4 |\ pad-to 52M | bl31-uboot bananapi_bpi-r3-emmc |\ pad-to 56M | mt7986-gpt emmc |\ - pad-to 64M | append-image squashfs-sysupgrade.itb | gzip + $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ + pad-to 64M | append-image squashfs-sysupgrade.itb | check-size | gzip \ + ) + IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | \ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k From 50c892d67bb4af90861be9fbb6831c2eeb62de11 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 8 Sep 2022 02:44:30 +0100 Subject: [PATCH 85/91] mediatek: bpi-r64: make initramfs/recovery optional Only include recovery image in SD card image generated for the BananaPi BPi-R64 if building with CONFIG_TARGET_ROOTFS_INITRAMFS This allows to build images larger than 32 MB (the limit for initramfs/recovery image) by deselecting initramfs. Signed-off-by: Daniel Golle --- target/linux/mediatek/image/mt7622.mk | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 810645067a22d0..d92c72294a597f 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -86,13 +86,18 @@ define Device/bananapi_bpi-r64 ARTIFACT/sdcard.img.gz := mt7622-gpt sdmmc |\ pad-to 512k | bl2 sdmmc-2ddr |\ pad-to 2048k | bl31-uboot bananapi_bpi-r64-sdmmc |\ - pad-to 6144k | append-image-stage initramfs-recovery.itb |\ + $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ + pad-to 6144k | append-image-stage initramfs-recovery.itb | checksize 38912k |\ + ) \ pad-to 38912k | mt7622-gpt emmc |\ pad-to 39424k | bl2 emmc-2ddr |\ pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\ pad-to 43008k | bl2 snand-2ddr |\ pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\ - pad-to 46080k | append-image squashfs-sysupgrade.itb | gzip + $(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\ + pad-to 46080k | append-image squashfs-sysupgrade.itb | check-size | gzip \ + ) + IMAGE_SIZE := $$(shell expr 45 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m KERNEL := kernel-bin | gzip KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata From 1e1695f959e678868bb7911d059b847f38fc9cf4 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 5 Sep 2022 19:23:16 +0200 Subject: [PATCH 86/91] ath79: add support for ZTE MF281 Add support for the ZTE MF281 battery-powered WiFi router. Hardware -------- SoC: Qualcomm Atheros QCA9563 RAM: 128M DDR2 FLASH: 2M SPI-NOR (GigaDevice GD25Q16) 128M SPI-NAND (GigaDevice) WLAN: QCA9563 2T2R 802.11 abgn QCA9886 2T2R 802.11 nac WWAN: ASRMicro ASR1826 ETH: Qualcomm Atheros QCA8337 UART: 115200 8n1 Unpopulated connector next to SIM slot (SIM) GND - RX - TX - 3V3 Don't connect 3V3 BUTTON: Reset - WPS LED: 1x debug-LED (internal) LEDs on front of the device are controlled using the modem CPU and can not be controlled by OpenWrt Installation ------------ 1. Connect to the serial console. Power up the device and interrupt autoboot when prompted 2. Connect a TFTP server reachable at 192.168.1.66 to the ethernet port. Serve the OpenWrt initramfs image as "speedbox-2.bin" 3. Boot the initramfs image using U-Boot $ setenv serverip 192.168.1.66 $ setenv ipaddr 192.168.1.154 $ tftpboot 0x84000000 speedbox-2.bin $ bootm 4. Copy the OpenWrt factory image to the device using scp and write to the NAND flash $ mtd write /path/to/openwrt/factory.bin firmware WWAN ---- The WWAN card can be used with OpenWrt. Example configuration for connection with a unauthenticated dual-stack APN: network.lte=interface network.lte.proto='ncm' network.lte.device='/dev/ttyACM0' network.lte.pdptype='IPV4V6' network.lte.apn='internet.telekom' network.lte.ipv6='auto' network.lte.delay='10' The WWAN card is running a modified version of OpenWrt and handles power-management as well as the LED controller (AW9523). A root shell can be acquired by installing adb using opkg and executing "adb shell". Signed-off-by: David Bauer --- target/linux/ath79/dts/qca9563_zte_mf281.dts | 275 ++++++++++++++++++ target/linux/ath79/image/nand.mk | 21 +- .../nand/base-files/etc/board.d/02_network | 4 + 3 files changed, 296 insertions(+), 4 deletions(-) create mode 100644 target/linux/ath79/dts/qca9563_zte_mf281.dts diff --git a/target/linux/ath79/dts/qca9563_zte_mf281.dts b/target/linux/ath79/dts/qca9563_zte_mf281.dts new file mode 100644 index 00000000000000..2f4b7316bf919e --- /dev/null +++ b/target/linux/ath79/dts/qca9563_zte_mf281.dts @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +// Copyright (c) 2021 Cezary Jackiewicz +// Copyright (c) 2021, 2022 Lech Perczak +// Copyright (c) 2022 David Bauer + +#include "qca956x.dtsi" + +#include +#include +#include + +/ { + model = "ZTE MF281"; + compatible = "zte,mf281", "qca,qca9563"; + + aliases { + led-boot = &led_debug; + led-failsafe = &led_debug; + led-running = &led_debug; + led-upgrade = &led_debug; + label-mac-device = ð0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&enable_wlan_led_gpio>; + + /* Hidden SMD LED below signal strength LEDs. + * Visible through slits underside of the case. + */ + led_debug: debug { + label = "green:debug"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + /* This GPIO is used to reset whole board _including_ the modem */ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + active-delay = <3000>; + inactive-delay = <1000>; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xa0000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0xa0000 0x20000>; + read-only; + }; + }; + }; + + flash@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fota-flag"; + reg = <0x000000 0xa0000>; + read-only; + }; + + partition@a0000 { + label = "art"; + reg = <0xa0000 0x80000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + cal_caldata_1000: cal@1000 { + reg = <0x1000 0x440>; + }; + + cal_caldata_5000: cal@5000 { + reg = <0x5000 0x2f20>; + }; + }; + + partition@120000 { + label = "mac"; + reg = <0x120000 0x80000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_mac_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; + + partition@1a0000 { + label = "reserved2"; + reg = <0x1a0000 0xc0000>; + read-only; + }; + + partition@260000 { + label = "cfg-param"; + reg = <0x260000 0x400000>; + read-only; + }; + + partition@660000 { + label = "log"; + reg = <0x660000 0x400000>; + read-only; + }; + + partition@a60000 { + label = "oops"; + reg = <0xa60000 0xa0000>; + read-only; + }; + + partition@b00000 { + label = "reserved3"; + reg = <0xb00000 0x500000>; + read-only; + }; + + partition@1000000 { + label = "web"; + reg = <0x1000000 0x800000>; + read-only; + }; + + partition@1800000 { + label = "firmware"; + reg = <0x1800000 0x1d00000>; + + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x600000>; + }; + + partition@600000 { + label = "ubi"; + reg = <0x600000 0x1700000>; + }; + }; + + partition@3500000 { + label = "data"; + reg = <0x3500000 0x1900000>; + read-only; + }; + + partition@4e00000 { + label = "fota"; + reg = <0x4e00000 0x3200000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "sgmii"; + + qca,ar8327-initvals = < + 0x04 0x00080080 /* PORT0 PAD MODE CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&macaddr_mac_0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie { + status = "okay"; + + wifi@0,0 { + compatible = "qcom,ath10k"; + reg = <0x0 0 0 0 0>; + + nvmem-cells = <&macaddr_mac_0>, <&cal_caldata_5000>; + nvmem-cell-names = "mac-address", "pre-calibration"; + mac-address-increment = <1>; + }; +}; + +&pinmux { + enable_wlan_led_gpio: pinmux_wlan_led_gpio { + pinctrl-single,bits = <0x10 0x0 0xff000000>; + }; +}; + +&wmac { + status = "okay"; + + nvmem-cells = <&macaddr_mac_0>, <&cal_caldata_1000>; + nvmem-cell-names = "mac-address", "calibration"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/target/linux/ath79/image/nand.mk b/target/linux/ath79/image/nand.mk index 4e1ac216a58ae0..117f6e99cd6173 100644 --- a/target/linux/ath79/image/nand.mk +++ b/target/linux/ath79/image/nand.mk @@ -322,7 +322,7 @@ define Device/netgear_wndr4500-v3 endef TARGET_DEVICES += netgear_wndr4500-v3 -define Device/zte_mf286_common +define Device/zte_mf28x_common SOC := qca9563 DEVICE_VENDOR := ZTE DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct @@ -332,8 +332,21 @@ define Device/zte_mf286_common IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef +define Device/zte_mf281 + $(Device/zte_mf28x_common) + DEVICE_MODEL := MF281 + KERNEL_SIZE := 6144k + IMAGE_SIZE := 29696k + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \ + check-size + DEVICE_PACKAGES += ath10k-firmware-qca9888-ct kmod-usb-net-rndis \ + kmod-usb-acm comgt-ncm +endef +TARGET_DEVICES += zte_mf281 + define Device/zte_mf286 - $(Device/zte_mf286_common) + $(Device/zte_mf28x_common) DEVICE_MODEL := MF286 DEVICE_PACKAGES += ath10k-firmware-qca988x-ct kmod-usb-net-qmi-wwan \ kmod-usb-serial-option uqmi @@ -341,7 +354,7 @@ endef TARGET_DEVICES += zte_mf286 define Device/zte_mf286a - $(Device/zte_mf286_common) + $(Device/zte_mf28x_common) DEVICE_MODEL := MF286A DEVICE_PACKAGES += ath10k-firmware-qca9888-ct kmod-usb-net-qmi-wwan \ kmod-usb-serial-option uqmi @@ -349,7 +362,7 @@ endef TARGET_DEVICES += zte_mf286a define Device/zte_mf286r - $(Device/zte_mf286_common) + $(Device/zte_mf28x_common) DEVICE_MODEL := MF286R DEVICE_PACKAGES += ath10k-firmware-qca9888-ct kmod-usb-net-rndis kmod-usb-acm \ comgt-ncm diff --git a/target/linux/ath79/nand/base-files/etc/board.d/02_network b/target/linux/ath79/nand/base-files/etc/board.d/02_network index 01f26fb39d8c4a..b252d7d9e88fe3 100644 --- a/target/linux/ath79/nand/base-files/etc/board.d/02_network +++ b/target/linux/ath79/nand/base-files/etc/board.d/02_network @@ -53,6 +53,10 @@ ath79_setup_interfaces() ucidef_add_switch "switch0" \ "0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" ;; + zte,mf281) + ucidef_add_switch "switch0" \ + "0@eth0" "5:lan" + ;; zte,mf286|\ zte,mf286a|\ zte,mf286r) From 007c8809c1e888748af70c1b878f4d0105fe7531 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 8 Sep 2022 19:29:44 +0100 Subject: [PATCH 87/91] mediatek: fix typo in bpi-r64 image recipe Janusz Dziedzic reported a typo introduced by a recent commit. Fix it. Fixes: 50c892d67b ("mediatek: bpi-r64: make initramfs/recovery optional") Signed-off-by: Daniel Golle --- target/linux/mediatek/image/mt7622.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index d92c72294a597f..f9cd18fd418b27 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -87,7 +87,7 @@ define Device/bananapi_bpi-r64 pad-to 512k | bl2 sdmmc-2ddr |\ pad-to 2048k | bl31-uboot bananapi_bpi-r64-sdmmc |\ $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\ - pad-to 6144k | append-image-stage initramfs-recovery.itb | checksize 38912k |\ + pad-to 6144k | append-image-stage initramfs-recovery.itb | check-size 38912k |\ ) \ pad-to 38912k | mt7622-gpt emmc |\ pad-to 39424k | bl2 emmc-2ddr |\ From 545c6113c93bbf7de1b0e515141a4565f7e6cece Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= Date: Thu, 8 Sep 2022 19:35:34 +0200 Subject: [PATCH 88/91] realtek: fix RTL838x receive tag decoding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit dc9cc0d3e2a1 ("realtek: add QoS and rate control") replaced a 16 bit reserved field in the RTL83xx packet header with the initial cpu_tag word, shifting the real cpu_tag fields by one. Adjusting for this new shift was partially forgotten in the new RX tag decoders. This caused the switch to block IGMP, effectively blocking IPv4 multicast. The bug was partially fixed by commit 9d847244d9fd ("realtek: fix RTL839X receive tag decoding") Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value. Suggested-by: Jan Hoffmann Fixes: dc9cc0d3e2a1 ("realtek: add QoS and rate control") Signed-off-by: Bjørn Mork --- .../files-5.10/drivers/net/ethernet/rtl838x_eth.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c index 0eee06d803ad5d..d9ade6552698a6 100644 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c @@ -58,6 +58,7 @@ struct p_hdr { uint16_t size; /* buffer size */ uint16_t offset; uint16_t len; /* pkt len */ + /* cpu_tag[0] is a reserved uint16_t on RTL83xx */ uint16_t cpu_tag[10]; } __packed __aligned(1); @@ -262,13 +263,14 @@ struct dsa_tag { bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { - t->reason = h->cpu_tag[3] & 0xf; - t->queue = (h->cpu_tag[0] & 0xe0) >> 5; + /* cpu_tag[0] is reserved. Fields are off-by-one */ + t->reason = h->cpu_tag[4] & 0xf; + t->queue = (h->cpu_tag[1] & 0xe0) >> 5; t->port = h->cpu_tag[1] & 0x1f; t->crc_error = t->reason == 13; pr_debug("Reason: %d\n", t->reason); - if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP + if (t->reason != 6) // NIC_RX_REASON_SPECIAL_TRAP t->l2_offloaded = 1; else t->l2_offloaded = 0; @@ -278,6 +280,7 @@ bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) { + /* cpu_tag[0] is reserved. Fields are off-by-one */ t->reason = h->cpu_tag[5] & 0x1f; t->queue = (h->cpu_tag[3] & 0xe000) >> 13; t->port = h->cpu_tag[1] & 0x3f; From 3020d9f8b4d6651662ed22cc87e542ca3e66b887 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 9 Sep 2022 05:00:57 +0100 Subject: [PATCH 89/91] kernel: mtk_sgmii: re-organize PCS link status reporting Don't report speed in case link is down. Signed-off-by: Daniel Golle --- .../724-net-mtk_sgmii-implement-mtk_pcs_ops.patch | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch b/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch index 896f0169d2b945..cd97706658740a 100644 --- a/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch +++ b/target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch @@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c -@@ -122,10 +122,26 @@ static void mtk_pcs_link_up(struct phyli +@@ -122,10 +122,28 @@ static void mtk_pcs_link_up(struct phyli regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); } @@ -24,12 +24,14 @@ Signed-off-by: Daniel Golle + struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs); + unsigned int val; + -+ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); -+ state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000; -+ + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val); + state->an_complete = !!(val & SGMII_AN_COMPLETE); + state->link = !!(val & SGMII_LINK_STATYS); ++ if (!state->link) ++ return; ++ ++ regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val); ++ state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000; + state->duplex = DUPLEX_FULL; + state->pause = 0; +} From bd6783f4fb8f6171927e9067c0005a6d69fc13fe Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 9 Sep 2022 05:01:47 +0100 Subject: [PATCH 90/91] kernel: mt7530: add support for in-band managed link Add support for in-band managed link status to support SFP cage connected to port 5 of the MT7531 switch on the Bananapi BPi-R3. Signed-off-by: Daniel Golle --- ...-add-support-for-in-band-link-status.patch | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch diff --git a/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch b/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch new file mode 100644 index 00000000000000..8196f1954020bf --- /dev/null +++ b/target/linux/generic/pending-5.15/731-net-dsa-mt7530-add-support-for-in-band-link-status.patch @@ -0,0 +1,123 @@ +From 8e18c5fef75debfae3531fbd6901f3bf317d91ed Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 9 Sep 2022 04:28:43 +0100 +Subject: [PATCH] net: dsa: mt7530: add support for in-band link status +To: linux-mediatek@lists.infradead.org, + netdev@vger.kernel.org +Cc: Russell King , + Sean Wang , + Landen Chao , + DENG Qingfang , + Andrew Lunn , + Vivien Didelot , + Florian Fainelli , + Vladimir Oltean , + David S. Miller , + Eric Dumazet , + Jakub Kicinski , + Paolo Abeni , + Matthias Brugger , + Philipp Zabel + +Read link status from SGMII PCS for in-band managed 2500Base-X and +1000Base-X connection on a MAC port of the MT7531. This is needed to +get the SFP cage working which is connected to SGMII interface of +port 5 of the MT7531 switch IC on the Bananapi BPi-R3 board. + +Signed-off-by: Daniel Golle +--- + drivers/net/dsa/mt7530.c | 48 +++++++++++++++++++++++++++++----------- + 1 file changed, 35 insertions(+), 13 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2703,9 +2703,6 @@ mt7531_mac_config(struct dsa_switch *ds, + case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: +- if (phylink_autoneg_inband(mode)) +- return -EINVAL; +- + return mt7531_sgmii_setup_mode_force(priv, port, interface); + default: + return -EINVAL; +@@ -2781,13 +2778,6 @@ unsupported: + return; + } + +- if (phylink_autoneg_inband(mode) && +- state->interface != PHY_INTERFACE_MODE_SGMII) { +- dev_err(ds->dev, "%s: in-band negotiation unsupported\n", +- __func__); +- return; +- } +- + mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); + mcr_new = mcr_cur; + mcr_new &= ~PMCR_LINK_SETTINGS_MASK; +@@ -2924,6 +2914,9 @@ static void mt753x_phylink_get_caps(stru + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000FD; + ++ if ((priv->id == ID_MT7531) && mt753x_is_mac_port(port)) ++ config->mac_capabilities |= MAC_2500FD; ++ + /* This driver does not make use of the speed, duplex, pause or the + * advertisement in its mac_config, so it is safe to mark this driver + * as non-legacy. +@@ -3019,16 +3012,43 @@ mt7531_sgmii_pcs_get_state_an(struct mt7 + return 0; + } + ++static void ++mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port, ++ struct phylink_link_state *state) ++{ ++ unsigned int val; ++ ++ val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); ++ state->link = !!(val & MT7531_SGMII_LINK_STATUS); ++ if (!state->link) ++ return; ++ ++ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) ++ state->speed = SPEED_2500; ++ else ++ state->speed = SPEED_1000; ++ ++ state->duplex = DUPLEX_FULL; ++ state->pause = 0; ++} ++ + static void mt7531_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) + { + struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; + int port = pcs_to_mt753x_pcs(pcs)->port; ++ unsigned int val; + +- if (state->interface == PHY_INTERFACE_MODE_SGMII) ++ if (state->interface == PHY_INTERFACE_MODE_SGMII) { + mt7531_sgmii_pcs_get_state_an(priv, port, state); +- else +- state->link = false; ++ return; ++ } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) || ++ (state->interface == PHY_INTERFACE_MODE_2500BASEX)) { ++ mt7531_sgmii_pcs_get_state_inband(priv, port, state); ++ return; ++ } ++ ++ state->link = false; + } + + static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, +@@ -3069,6 +3089,8 @@ mt753x_setup(struct dsa_switch *ds) + priv->pcs[i].pcs.ops = priv->info->pcs_ops; + priv->pcs[i].priv = priv; + priv->pcs[i].port = i; ++ if (mt753x_is_mac_port(i)) ++ priv->pcs[i].pcs.poll = 1; + } + + ret = priv->info->sw_setup(ds); From 5f458e64a9bca6875d7974fd5b9cd570f5d2d40c Mon Sep 17 00:00:00 2001 From: Nick Hainke Date: Wed, 20 Jul 2022 20:39:09 +0200 Subject: [PATCH 91/91] ipq40xx: switch to 5.15 as default kernel The testing kernel received now multiple months of testing. Set 5.15 as default to give it a test with a broader audience. Tested on: - MikroTik SXTsq 5 AC - FritzBox 4040/7530 - ZyXEL NBG6617 Signed-off-by: Nick Hainke --- target/linux/ipq40xx/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile index 19b63cdd65853e..6eb9c0022328b3 100644 --- a/target/linux/ipq40xx/Makefile +++ b/target/linux/ipq40xx/Makefile @@ -8,8 +8,7 @@ CPU_TYPE:=cortex-a7 CPU_SUBTYPE:=neon-vfpv4 SUBTARGETS:=generic chromium mikrotik -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 KERNELNAME:=zImage Image dtbs