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MEMinst_syn.v
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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: MEMinst.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altsyncram ADDRESS_ACLR_A="NONE" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" DEVICE_FAMILY="Cyclone IV GX" ENABLE_RUNTIME_MOD="NO" INIT_FILE="Nivel1_code.mif" NUMWORDS_A=4096 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=32 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 address_a clock0 q_a
//VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = M9K 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module MEMinst_altsyncram
(
address_a,
clock0,
q_a) /* synthesis synthesis_clearbox=1 */;
input [11:0] address_a;
input clock0;
output [31:0] q_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_ram_block1a_0portadataout;
wire [0:0] wire_ram_block1a_1portadataout;
wire [0:0] wire_ram_block1a_2portadataout;
wire [0:0] wire_ram_block1a_3portadataout;
wire [0:0] wire_ram_block1a_4portadataout;
wire [0:0] wire_ram_block1a_5portadataout;
wire [0:0] wire_ram_block1a_6portadataout;
wire [0:0] wire_ram_block1a_7portadataout;
wire [0:0] wire_ram_block1a_8portadataout;
wire [0:0] wire_ram_block1a_9portadataout;
wire [0:0] wire_ram_block1a_10portadataout;
wire [0:0] wire_ram_block1a_11portadataout;
wire [0:0] wire_ram_block1a_12portadataout;
wire [0:0] wire_ram_block1a_13portadataout;
wire [0:0] wire_ram_block1a_14portadataout;
wire [0:0] wire_ram_block1a_15portadataout;
wire [0:0] wire_ram_block1a_16portadataout;
wire [0:0] wire_ram_block1a_17portadataout;
wire [0:0] wire_ram_block1a_18portadataout;
wire [0:0] wire_ram_block1a_19portadataout;
wire [0:0] wire_ram_block1a_20portadataout;
wire [0:0] wire_ram_block1a_21portadataout;
wire [0:0] wire_ram_block1a_22portadataout;
wire [0:0] wire_ram_block1a_23portadataout;
wire [0:0] wire_ram_block1a_24portadataout;
wire [0:0] wire_ram_block1a_25portadataout;
wire [0:0] wire_ram_block1a_26portadataout;
wire [0:0] wire_ram_block1a_27portadataout;
wire [0:0] wire_ram_block1a_28portadataout;
wire [0:0] wire_ram_block1a_29portadataout;
wire [0:0] wire_ram_block1a_30portadataout;
wire [0:0] wire_ram_block1a_31portadataout;
wire [11:0] address_a_wire;
cycloneiv_ram_block ram_block1a_0
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_0portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_0.clk0_core_clock_enable = "none",
ram_block1a_0.clk0_input_clock_enable = "none",
ram_block1a_0.connectivity_checking = "OFF",
ram_block1a_0.init_file = "Nivel1_code.mif",
ram_block1a_0.init_file_layout = "port_a",
ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
ram_block1a_0.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000301,
ram_block1a_0.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_0.operation_mode = "rom",
ram_block1a_0.port_a_address_clear = "none",
ram_block1a_0.port_a_address_width = 12,
ram_block1a_0.port_a_data_out_clear = "none",
ram_block1a_0.port_a_data_out_clock = "none",
ram_block1a_0.port_a_data_width = 1,
ram_block1a_0.port_a_first_address = 0,
ram_block1a_0.port_a_first_bit_number = 0,
ram_block1a_0.port_a_last_address = 4095,
ram_block1a_0.port_a_logical_ram_depth = 4096,
ram_block1a_0.port_a_logical_ram_width = 32,
ram_block1a_0.ram_block_type = "AUTO",
ram_block1a_0.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_1
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_1portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_1.clk0_core_clock_enable = "none",
ram_block1a_1.clk0_input_clock_enable = "none",
ram_block1a_1.connectivity_checking = "OFF",
ram_block1a_1.init_file = "Nivel1_code.mif",
ram_block1a_1.init_file_layout = "port_a",
ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
ram_block1a_1.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006C0,
ram_block1a_1.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_1.operation_mode = "rom",
ram_block1a_1.port_a_address_clear = "none",
ram_block1a_1.port_a_address_width = 12,
ram_block1a_1.port_a_data_out_clear = "none",
ram_block1a_1.port_a_data_out_clock = "none",
ram_block1a_1.port_a_data_width = 1,
ram_block1a_1.port_a_first_address = 0,
ram_block1a_1.port_a_first_bit_number = 1,
ram_block1a_1.port_a_last_address = 4095,
ram_block1a_1.port_a_logical_ram_depth = 4096,
ram_block1a_1.port_a_logical_ram_width = 32,
ram_block1a_1.ram_block_type = "AUTO",
ram_block1a_1.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_2
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_2portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_2.clk0_core_clock_enable = "none",
ram_block1a_2.clk0_input_clock_enable = "none",
ram_block1a_2.connectivity_checking = "OFF",
ram_block1a_2.init_file = "Nivel1_code.mif",
ram_block1a_2.init_file_layout = "port_a",
ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
ram_block1a_2.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002B48,
ram_block1a_2.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_2.operation_mode = "rom",
ram_block1a_2.port_a_address_clear = "none",
ram_block1a_2.port_a_address_width = 12,
ram_block1a_2.port_a_data_out_clear = "none",
ram_block1a_2.port_a_data_out_clock = "none",
ram_block1a_2.port_a_data_width = 1,
ram_block1a_2.port_a_first_address = 0,
ram_block1a_2.port_a_first_bit_number = 2,
ram_block1a_2.port_a_last_address = 4095,
ram_block1a_2.port_a_logical_ram_depth = 4096,
ram_block1a_2.port_a_logical_ram_width = 32,
ram_block1a_2.ram_block_type = "AUTO",
ram_block1a_2.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_3
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_3portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_3.clk0_core_clock_enable = "none",
ram_block1a_3.clk0_input_clock_enable = "none",
ram_block1a_3.connectivity_checking = "OFF",
ram_block1a_3.init_file = "Nivel1_code.mif",
ram_block1a_3.init_file_layout = "port_a",
ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
ram_block1a_3.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004410,
ram_block1a_3.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_3.operation_mode = "rom",
ram_block1a_3.port_a_address_clear = "none",
ram_block1a_3.port_a_address_width = 12,
ram_block1a_3.port_a_data_out_clear = "none",
ram_block1a_3.port_a_data_out_clock = "none",
ram_block1a_3.port_a_data_width = 1,
ram_block1a_3.port_a_first_address = 0,
ram_block1a_3.port_a_first_bit_number = 3,
ram_block1a_3.port_a_last_address = 4095,
ram_block1a_3.port_a_logical_ram_depth = 4096,
ram_block1a_3.port_a_logical_ram_width = 32,
ram_block1a_3.ram_block_type = "AUTO",
ram_block1a_3.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_4
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_4portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.clk0_core_clock_enable = "none",
ram_block1a_4.clk0_input_clock_enable = "none",
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.init_file = "Nivel1_code.mif",
ram_block1a_4.init_file_layout = "port_a",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800,
ram_block1a_4.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_4.operation_mode = "rom",
ram_block1a_4.port_a_address_clear = "none",
ram_block1a_4.port_a_address_width = 12,
ram_block1a_4.port_a_data_out_clear = "none",
ram_block1a_4.port_a_data_out_clock = "none",
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_first_address = 0,
ram_block1a_4.port_a_first_bit_number = 4,
ram_block1a_4.port_a_last_address = 4095,
ram_block1a_4.port_a_logical_ram_depth = 4096,
ram_block1a_4.port_a_logical_ram_width = 32,
ram_block1a_4.ram_block_type = "AUTO",
ram_block1a_4.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_5
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.clk0_core_clock_enable = "none",
ram_block1a_5.clk0_input_clock_enable = "none",
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.init_file = "Nivel1_code.mif",
ram_block1a_5.init_file_layout = "port_a",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003E0,
ram_block1a_5.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_5.operation_mode = "rom",
ram_block1a_5.port_a_address_clear = "none",
ram_block1a_5.port_a_address_width = 12,
ram_block1a_5.port_a_data_out_clear = "none",
ram_block1a_5.port_a_data_out_clock = "none",
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_first_address = 0,
ram_block1a_5.port_a_first_bit_number = 5,
ram_block1a_5.port_a_last_address = 4095,
ram_block1a_5.port_a_logical_ram_depth = 4096,
ram_block1a_5.port_a_logical_ram_width = 32,
ram_block1a_5.ram_block_type = "AUTO",
ram_block1a_5.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_6
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.clk0_core_clock_enable = "none",
ram_block1a_6.clk0_input_clock_enable = "none",
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.init_file = "Nivel1_code.mif",
ram_block1a_6.init_file_layout = "port_a",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_6.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_6.operation_mode = "rom",
ram_block1a_6.port_a_address_clear = "none",
ram_block1a_6.port_a_address_width = 12,
ram_block1a_6.port_a_data_out_clear = "none",
ram_block1a_6.port_a_data_out_clock = "none",
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_first_address = 0,
ram_block1a_6.port_a_first_bit_number = 6,
ram_block1a_6.port_a_last_address = 4095,
ram_block1a_6.port_a_logical_ram_depth = 4096,
ram_block1a_6.port_a_logical_ram_width = 32,
ram_block1a_6.ram_block_type = "AUTO",
ram_block1a_6.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_7
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.clk0_core_clock_enable = "none",
ram_block1a_7.clk0_input_clock_enable = "none",
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.init_file = "Nivel1_code.mif",
ram_block1a_7.init_file_layout = "port_a",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_7.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_7.operation_mode = "rom",
ram_block1a_7.port_a_address_clear = "none",
ram_block1a_7.port_a_address_width = 12,
ram_block1a_7.port_a_data_out_clear = "none",
ram_block1a_7.port_a_data_out_clock = "none",
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_first_address = 0,
ram_block1a_7.port_a_first_bit_number = 7,
ram_block1a_7.port_a_last_address = 4095,
ram_block1a_7.port_a_logical_ram_depth = 4096,
ram_block1a_7.port_a_logical_ram_width = 32,
ram_block1a_7.ram_block_type = "AUTO",
ram_block1a_7.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_8
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_8portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_8.clk0_core_clock_enable = "none",
ram_block1a_8.clk0_input_clock_enable = "none",
ram_block1a_8.connectivity_checking = "OFF",
ram_block1a_8.init_file = "Nivel1_code.mif",
ram_block1a_8.init_file_layout = "port_a",
ram_block1a_8.logical_ram_name = "ALTSYNCRAM",
ram_block1a_8.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_8.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_8.operation_mode = "rom",
ram_block1a_8.port_a_address_clear = "none",
ram_block1a_8.port_a_address_width = 12,
ram_block1a_8.port_a_data_out_clear = "none",
ram_block1a_8.port_a_data_out_clock = "none",
ram_block1a_8.port_a_data_width = 1,
ram_block1a_8.port_a_first_address = 0,
ram_block1a_8.port_a_first_bit_number = 8,
ram_block1a_8.port_a_last_address = 4095,
ram_block1a_8.port_a_logical_ram_depth = 4096,
ram_block1a_8.port_a_logical_ram_width = 32,
ram_block1a_8.ram_block_type = "AUTO",
ram_block1a_8.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_9
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_9portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_9.clk0_core_clock_enable = "none",
ram_block1a_9.clk0_input_clock_enable = "none",
ram_block1a_9.connectivity_checking = "OFF",
ram_block1a_9.init_file = "Nivel1_code.mif",
ram_block1a_9.init_file_layout = "port_a",
ram_block1a_9.logical_ram_name = "ALTSYNCRAM",
ram_block1a_9.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_9.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_9.operation_mode = "rom",
ram_block1a_9.port_a_address_clear = "none",
ram_block1a_9.port_a_address_width = 12,
ram_block1a_9.port_a_data_out_clear = "none",
ram_block1a_9.port_a_data_out_clock = "none",
ram_block1a_9.port_a_data_width = 1,
ram_block1a_9.port_a_first_address = 0,
ram_block1a_9.port_a_first_bit_number = 9,
ram_block1a_9.port_a_last_address = 4095,
ram_block1a_9.port_a_logical_ram_depth = 4096,
ram_block1a_9.port_a_logical_ram_width = 32,
ram_block1a_9.ram_block_type = "AUTO",
ram_block1a_9.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_10
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_10portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_10.clk0_core_clock_enable = "none",
ram_block1a_10.clk0_input_clock_enable = "none",
ram_block1a_10.connectivity_checking = "OFF",
ram_block1a_10.init_file = "Nivel1_code.mif",
ram_block1a_10.init_file_layout = "port_a",
ram_block1a_10.logical_ram_name = "ALTSYNCRAM",
ram_block1a_10.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_10.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_10.operation_mode = "rom",
ram_block1a_10.port_a_address_clear = "none",
ram_block1a_10.port_a_address_width = 12,
ram_block1a_10.port_a_data_out_clear = "none",
ram_block1a_10.port_a_data_out_clock = "none",
ram_block1a_10.port_a_data_width = 1,
ram_block1a_10.port_a_first_address = 0,
ram_block1a_10.port_a_first_bit_number = 10,
ram_block1a_10.port_a_last_address = 4095,
ram_block1a_10.port_a_logical_ram_depth = 4096,
ram_block1a_10.port_a_logical_ram_width = 32,
ram_block1a_10.ram_block_type = "AUTO",
ram_block1a_10.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_11
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_11portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_11.clk0_core_clock_enable = "none",
ram_block1a_11.clk0_input_clock_enable = "none",
ram_block1a_11.connectivity_checking = "OFF",
ram_block1a_11.init_file = "Nivel1_code.mif",
ram_block1a_11.init_file_layout = "port_a",
ram_block1a_11.logical_ram_name = "ALTSYNCRAM",
ram_block1a_11.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000A0,
ram_block1a_11.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_11.operation_mode = "rom",
ram_block1a_11.port_a_address_clear = "none",
ram_block1a_11.port_a_address_width = 12,
ram_block1a_11.port_a_data_out_clear = "none",
ram_block1a_11.port_a_data_out_clock = "none",
ram_block1a_11.port_a_data_width = 1,
ram_block1a_11.port_a_first_address = 0,
ram_block1a_11.port_a_first_bit_number = 11,
ram_block1a_11.port_a_last_address = 4095,
ram_block1a_11.port_a_logical_ram_depth = 4096,
ram_block1a_11.port_a_logical_ram_width = 32,
ram_block1a_11.ram_block_type = "AUTO",
ram_block1a_11.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_12
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_12portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_12.clk0_core_clock_enable = "none",
ram_block1a_12.clk0_input_clock_enable = "none",
ram_block1a_12.connectivity_checking = "OFF",
ram_block1a_12.init_file = "Nivel1_code.mif",
ram_block1a_12.init_file_layout = "port_a",
ram_block1a_12.logical_ram_name = "ALTSYNCRAM",
ram_block1a_12.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001,
ram_block1a_12.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_12.operation_mode = "rom",
ram_block1a_12.port_a_address_clear = "none",
ram_block1a_12.port_a_address_width = 12,
ram_block1a_12.port_a_data_out_clear = "none",
ram_block1a_12.port_a_data_out_clock = "none",
ram_block1a_12.port_a_data_width = 1,
ram_block1a_12.port_a_first_address = 0,
ram_block1a_12.port_a_first_bit_number = 12,
ram_block1a_12.port_a_last_address = 4095,
ram_block1a_12.port_a_logical_ram_depth = 4096,
ram_block1a_12.port_a_logical_ram_width = 32,
ram_block1a_12.ram_block_type = "AUTO",
ram_block1a_12.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_13
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_13portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_13.clk0_core_clock_enable = "none",
ram_block1a_13.clk0_input_clock_enable = "none",
ram_block1a_13.connectivity_checking = "OFF",
ram_block1a_13.init_file = "Nivel1_code.mif",
ram_block1a_13.init_file_layout = "port_a",
ram_block1a_13.logical_ram_name = "ALTSYNCRAM",
ram_block1a_13.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003C0,
ram_block1a_13.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_13.operation_mode = "rom",
ram_block1a_13.port_a_address_clear = "none",
ram_block1a_13.port_a_address_width = 12,
ram_block1a_13.port_a_data_out_clear = "none",
ram_block1a_13.port_a_data_out_clock = "none",
ram_block1a_13.port_a_data_width = 1,
ram_block1a_13.port_a_first_address = 0,
ram_block1a_13.port_a_first_bit_number = 13,
ram_block1a_13.port_a_last_address = 4095,
ram_block1a_13.port_a_logical_ram_depth = 4096,
ram_block1a_13.port_a_logical_ram_width = 32,
ram_block1a_13.ram_block_type = "AUTO",
ram_block1a_13.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_14
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_14portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portadatain({1{1'b0}}),
.portawe(1'b0),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbre(1'b1),
.portbwe(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_14.clk0_core_clock_enable = "none",
ram_block1a_14.clk0_input_clock_enable = "none",
ram_block1a_14.connectivity_checking = "OFF",
ram_block1a_14.init_file = "Nivel1_code.mif",
ram_block1a_14.init_file_layout = "port_a",
ram_block1a_14.logical_ram_name = "ALTSYNCRAM",
ram_block1a_14.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003E0,
ram_block1a_14.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_14.operation_mode = "rom",
ram_block1a_14.port_a_address_clear = "none",
ram_block1a_14.port_a_address_width = 12,
ram_block1a_14.port_a_data_out_clear = "none",
ram_block1a_14.port_a_data_out_clock = "none",
ram_block1a_14.port_a_data_width = 1,
ram_block1a_14.port_a_first_address = 0,
ram_block1a_14.port_a_first_bit_number = 14,
ram_block1a_14.port_a_last_address = 4095,
ram_block1a_14.port_a_logical_ram_depth = 4096,
ram_block1a_14.port_a_logical_ram_width = 32,
ram_block1a_14.ram_block_type = "AUTO",
ram_block1a_14.lpm_type = "cycloneiv_ram_block";
cycloneiv_ram_block ram_block1a_15
(
.clk0(clock0),
.portaaddr({address_a_wire[11:0]}),
.portadataout(wire_ram_block1a_15portadataout[0:0]),
.portare(1'b1),
.portbdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.portaaddrstall(1'b0),