diff --git a/.github/workflows/build-check.yml b/.github/workflows/build-check.yml index 5ee76bbc..222e8985 100644 --- a/.github/workflows/build-check.yml +++ b/.github/workflows/build-check.yml @@ -11,7 +11,7 @@ jobs: uses: actions/checkout@v4 with: submodules: recursive - + token: ${{ secrets.PAT_TOKEN }} - name: Execute Make run: | if ! make; then diff --git a/.github/workflows/format-check.yml b/.github/workflows/format-check.yml index 80a40900..e1a21c4f 100644 --- a/.github/workflows/format-check.yml +++ b/.github/workflows/format-check.yml @@ -10,6 +10,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: recursive + token: ${{ secrets.PAT_TOKEN }} - name: Run clang-format style check for C/C++ sources uses: Northeastern-Electric-Racing/clang-format-action@main with: diff --git a/.mxproject b/.mxproject index d1b3aea1..b96dd2c9 100644 --- a/.mxproject +++ b/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] 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[PreviousUsedMakefileFiles] -SourceFiles=Core/Src/main.c;Core/Src/freertos.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;;;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c; +SourceFiles=Core/Src/main.c;Core/Src/freertos.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Core/Src/stm32f4xx_hal_timebase_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;;;Middlewares/Third_Party/FreeRTOS/Source/croutine.c;Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;Middlewares/Third_Party/FreeRTOS/Source/list.c;Middlewares/Third_Party/FreeRTOS/Source/queue.c;Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;Middlewares/Third_Party/FreeRTOS/Source/tasks.c;Middlewares/Third_Party/FreeRTOS/Source/timers.c;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c; HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Middlewares/Third_Party/FreeRTOS/Source/include;Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2;Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_HAL_DRIVER;STM32F405xx;USE_HAL_DRIVER;USE_HAL_DRIVER; @@ -19,11 +19,12 @@ HeaderFiles#3=../Core/Inc/main.h HeaderFolderListSize=1 HeaderPath#0=../Core/Inc HeaderFiles=; -SourceFileListSize=4 +SourceFileListSize=5 SourceFiles#0=../Core/Src/freertos.c SourceFiles#1=../Core/Src/stm32f4xx_it.c SourceFiles#2=../Core/Src/stm32f4xx_hal_msp.c -SourceFiles#3=../Core/Src/main.c +SourceFiles#3=../Core/Src/stm32f4xx_hal_timebase_tim.c +SourceFiles#4=../Core/Src/main.c SourceFolderListSize=1 SourcePath#0=../Core/Src SourceFiles=; diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h index c1e8e9b6..41e0046f 100644 --- a/Core/Inc/FreeRTOSConfig.h +++ b/Core/Inc/FreeRTOSConfig.h @@ -51,7 +51,6 @@ #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) #include extern uint32_t SystemCoreClock; - void xPortSysTickHandler(void); #endif #ifndef CMSIS_device_header #define CMSIS_device_header "stm32f4xx.h" @@ -164,7 +163,7 @@ standard names. */ /* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ -#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 1 +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 /* USER CODE BEGIN Defines */ /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ diff --git a/Core/Inc/adi_interaction.h b/Core/Inc/adi_interaction.h new file mode 100644 index 00000000..d44e6889 --- /dev/null +++ b/Core/Inc/adi_interaction.h @@ -0,0 +1,231 @@ +#include "adBms6830Data.h" +#include "bmsConfig.h" + +// --- BEGIN SET HELPERS --- + +/** + * @brief Set the status of the REFON bit. + * + * @param chip Pointer to the chip to modify. + * @param state New state of the REFON bit. + */ +void set_REFON(cell_asic *chip, REFON state); + +/** + * @brief Set the C-ADC vs. S-ADC comparison voltage threshold + * + * @param chip Pointer to the chip to modify. + * @param threshold Threshold to set. + */ +void set_volt_adc_comp_thresh(cell_asic *chip, CTH threshold); + +void set_diagnostic_flags(cell_asic *chip, FLAG_D config); + +/** + * @brief Set the discharge state of a cell. + * + * @param chip Pointer to chip with cell to modify. + * @param cell ID of cell to modify. Cell indexes start are from 1-16 (NOT ZERO INDEXED). + * @param discharge Cell discharge state. true to discharge, false to disable discharge. + */ +void set_cell_discharge(cell_asic *chip, uint8_t cell, bool discharge); + +/** + * @brief Set the state of the SOAKON bit to either enable or disable soak times. + * + * @param chip Pointer to chip to configure + * @param state Enable or disable SOAKON + */ +void set_soak_on(cell_asic *chip, SOAKON state); + +/** + * @brief Set the soak time range. + * + * @param chip Pointer to chip to configure + * @param range The range of time over which to soak for aux and aux2 + */ +void set_aux_soak_range(cell_asic *chip, OWRNG range); + +/** + * @brief Set the open wire soak time. See data sheet for formula. + * + * @param chip Pointer to chip configuration + * @param time The amount of time to soak for. Higher OWA is a higher soak time. + */ +void set_open_wire_soak_time(cell_asic *chip, OWA time); + +/** + * @brief Set the pull of a GPIO pin on an ADBMS8630. + * + * @param chip ADBMS6830 chip + * @param gpio Number of the GPIO pin to change (1-10) + * @param input True is no pull down, False is pull down. + */ +void set_gpio_pull(cell_asic *chip, uint8_t gpio, bool input); + +/** + * @brief Set the corner frequency of the IIR filter. + * + * @param chip Pointer to chip config + * @param freq Corner frequency (see IIR_FPA enum for frequencies) + */ +void set_iir_corner_freq(cell_asic *chip, IIR_FPA freq); + +/** + * @brief Configure a chip as a break in the isoSPI daisy chain. + * + * @param chip Pointer to chip config + * @param is_break True if chip is break, false if chip is not break + */ +void set_comm_break(cell_asic *chip, bool is_break); + +/** + * @brief Enable/disable discharging through the mute discharge bit. + * + * @param chip Pointer to chip config + * @param disable_discharge True to disable discharge, false to enable discharge. + */ +void set_mute_state(cell_asic *chip, bool disable_discharge); + +/** + * @brief Set whether or not this chip is taking a snapshot. The chip will not begin reading new values unless the snapshot bit is cleared. + * + * @param chip Pointer to chip config + * @param take_snapshot True to take a snapshot, false to end the snapshot + */ +void set_snapshot(cell_asic *chip, bool take_snapshot); + +/** + * @brief Enable/disable the discharge timer monitor. + * + * @param chip Pointer to chip config + * @param enabled True if discharge timer monitor is enabled, false if otherwise + */ +void set_discharge_timer_monitor(cell_asic *chip, bool enabled); + +/** + * @brief Configure the discharge timer range, which affects the resolution. + * + * @param chip Pointer to chip config + * @param large True for large range, False for small range + */ +void set_discharge_timer_range(cell_asic *chip, bool large); + +/** + * @brief Set the discharge monitor timeout, which is dependent on the discharge timer range. + * + * @param chip Pointer to chip config + * @param timeout Base for timeout multiplicaiton. Must be below six bits. + */ +void set_discharge_timeout(cell_asic *chip, uint8_t timeout); + +// --- END SET HELPERS --- + +// --- BEGIN WRITE COMMANDS --- + +/** + * @brief Write config registers. Wakes chips before writing. + * + * @param chips Array of chips to write config registers of. + */ +void write_config_regs(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Clears all status regster C flags except the CS FLT + * + * @param chips + */ +void write_clear_flags(cell_asic chips[NUM_CHIPS]); + +// --- END WRITE COMMANDS --- + +// --- BEGIN READ COMMANDS --- + +/** + * @brief Read all filtered voltage results. IIR must be on and ADC must be continous + * + * @param chips The chips to read voltages from + */ +void read_filtered_voltage_registers(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Read every register connected to the AUX ADC. + * + * @param chips Array of chips to get voltage readings of. + */ +void adc_and_read_aux_registers(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Read voltages in every register connected to AUX2 ADC. + * + * @param chips Array of chips to get voltages of. + */ +void adc_and_read_aux2_registers(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Read status registers. + * + * @param chips Array of chips to read. + */ +void read_status_registers(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Read status and aux registers in one command. + * + * @param chips Array of chips to read. + */ +void read_status_aux_registers(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Read the serial ID of the chip. + * + * @param chips Array of chips to read. + */ +void read_serial_id(cell_asic chips[NUM_CHIPS]); + +// --- END READ COMMANDS --- + +// --- BEGIN ADC POLL --- + +/** + * @brief Get voltage readings from the C-ADCs. Takes a single shot measurement. + * + * @param chips Array of chips to get voltage readings from. + */ +void get_c_adc_voltages(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Get voltages from the S-ADCs. Makes a single shot measurement. + * + * @param chip Array of chips to get voltage readings from. + */ +void get_s_adc_voltages(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Get the avgeraged cell voltages. + * + * @param chip Array of chips to get voltage readings of. + */ +void get_avgd_cell_voltages(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Get the filtered cell volrages. + * + * @param chip Array of chips to get voltage readings of. + */ +void get_filtered_cell_voltages(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Get the c and s adc voltages. Does this with RDCSALL command. + * + * @param chips Array of chips to get voltage readings of. + */ +void get_c_and_s_adc_voltages(cell_asic chips[NUM_CHIPS]); + +/** + * @brief Starts a continous c ADC conversion with S redundancy + * + */ +void start_c_adc_conv(); + +// --- END ADC POLL --- diff --git a/Core/Inc/bmsConfig.h b/Core/Inc/bmsConfig.h index fd6e6d8d..96e8e425 100644 --- a/Core/Inc/bmsConfig.h +++ b/Core/Inc/bmsConfig.h @@ -2,6 +2,7 @@ #define BMS_CONFIG_H #define DEBUG_MODE_ENABLED true +#define DEBUG_STATS // Hardware definition #define NUM_SEGMENTS 1 diff --git a/Core/Inc/segment.h b/Core/Inc/segment.h index 98033d7e..dfc2e0b6 100644 --- a/Core/Inc/segment.h +++ b/Core/Inc/segment.h @@ -12,10 +12,15 @@ void segment_init(acc_data_t *bmsdata); /** * @brief Pulls all cell data from the segments and returns all cell data * - * @todo make sure that retrieving cell data doesn't block code too much */ void segment_retrieve_data(acc_data_t *bmsdata); +/** + * @brief Fetch extra data for segment + * + */ +void segment_retrieve_debug_data(acc_data_t *bmsdata); + /** * @brief Disables balancing for all cells. * @@ -32,15 +37,6 @@ void segment_disable_balancing(acc_data_t *bmsdata); void segment_configure_balancing( acc_data_t *bmsdata, bool discharge_config[NUM_CHIPS][NUM_CELLS_ALPHA]); -/** - * @brief Returns if a specific cell is balancing - * - * @param chip_num - * @return true - * @return false - */ -bool cell_is_balancing(uint8_t chip_num, uint8_t cell_num); - /** * @brief Returns if any cells are balancing. * @@ -73,6 +69,6 @@ void read_serial_id(cell_asic chips[NUM_CHIPS]); * * @param chips Array of chips to get voltages of. */ -void read_aux2_registers(cell_asic chips[NUM_CHIPS]); +void adc_and_read_aux2_registers(cell_asic chips[NUM_CHIPS]); #endif \ No newline at end of file diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h index e28f8b19..caa25296 100644 --- a/Core/Inc/stm32f4xx_hal_conf.h +++ b/Core/Inc/stm32f4xx_hal_conf.h @@ -214,7 +214,7 @@ #define MAC_ADDR5 0U /* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE /* buffer size for receive */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index 2b9b7aa9..78f33294 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -52,12 +52,13 @@ void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); -void SysTick_Handler(void); -void CAN1_RX0_IRQHandler(void); void DMA1_Stream4_IRQHandler(void); +void CAN1_RX0_IRQHandler(void); +void TIM3_IRQHandler(void); void UART4_IRQHandler(void); void DMA2_Stream0_IRQHandler(void); void CAN2_RX0_IRQHandler(void); +void CAN2_RX1_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/adi_interaction.c b/Core/Src/adi_interaction.c new file mode 100644 index 00000000..5a16948e --- /dev/null +++ b/Core/Src/adi_interaction.c @@ -0,0 +1,363 @@ +#include "adi_interaction.h" +#include "adBms6830CmdList.h" +#include "adBms6830GenericType.h" +#include "mcuWrapper.h" + +/** + * @brief Set a bit in a uint16 + * + * @param number uint16 to change. + * @param n Nth bit to change. + * @param x true sets, false clears. + * @return uint16_t New uint16. + */ +inline uint16_t set_uint16_bit(uint16_t number, uint16_t n, bool x) +{ + return (number & ~((uint16_t)1 << n)) | ((uint16_t)x << n); +} + +// --- BEGIN SET HELPERS --- + +void set_REFON(cell_asic *chip, REFON state) +{ + chip->tx_cfga.refon = state; +} + +void set_volt_adc_comp_thresh(cell_asic *chip, CTH threshold) +{ + chip->tx_cfga.cth = threshold; +} + +void set_diagnostic_flags(cell_asic *chip, FLAG_D config) +{ + chip->tx_cfga.flag_d = + (uint8_t)set_uint16_bit(chip->tx_cfga.flag_d, config, true); +} + +void set_cell_discharge(cell_asic *chip, uint8_t cell, bool discharge) +{ + chip->tx_cfgb.dcc = set_uint16_bit(chip->tx_cfgb.dcc, cell, discharge); +} + +void set_soak_on(cell_asic *chip, SOAKON state) +{ + chip->tx_cfga.soakon = state; +} + +void set_aux_soak_range(cell_asic *chip, OWRNG range) +{ + chip->tx_cfga.owrng = range; +} + +void set_open_wire_soak_time(cell_asic *chip, OWA time) +{ + chip->tx_cfga.owa = time; +} + +void set_gpio_pull(cell_asic *chip, uint8_t gpio, bool input) +{ + if (gpio > 10 || gpio < 1) { + printf("ERROR: Invalid GPIO pin %d\n", gpio); + return; + } + chip->tx_cfga.gpo = set_uint16_bit(chip->tx_cfga.gpo, gpio - 1, input); +} + +void set_iir_corner_freq(cell_asic *chip, IIR_FPA freq) +{ + chip->tx_cfga.fc = freq; +} + +void set_comm_break(cell_asic *chip, bool is_break) +{ + chip->tx_cfga.comm_bk = is_break; +} + +void set_mute_state(cell_asic *chip, bool disable_discharge) +{ + chip->tx_cfga.mute_st = disable_discharge; +} + +void set_snapshot(cell_asic *chip, bool take_snapshot) +{ + chip->tx_cfga.snap = take_snapshot; +} + +void set_discharge_timer_monitor(cell_asic *chip, bool enabled) +{ + chip->tx_cfgb.dtmen = enabled; +} + +void set_discharge_timer_range(cell_asic *chip, bool large) +{ + chip->tx_cfgb.dtrng = large; +} + +void set_discharge_timeout(cell_asic *chip, uint8_t timeout) +{ + if (timeout >> 6 > 0) { + printf("Invalid discharge time\n"); + return; + // TODO: Non-critical fault + } + chip->tx_cfgb.dcto = timeout; +} + +// --- END SET HELPERS --- + +// void start_cell_voltages_adc(cell_asic chips[NUM_CHIPS]) +// { +// adbms_wake(); +// adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); +// adBmsPollAdc(PLCADC); +// } + +// --- BEGIN RW --- + +extern TIM_HandleTypeDef htim2; + +/** + * @brief Delays a certain number of microseconds + * + * Approximately +50% error as seen in logic analyzer + * + * @param us the number of us to delay + */ +inline void delay_us(uint16_t us) +{ + uint16_t tickstart = __HAL_TIM_GET_COUNTER(&htim2); + uint16_t wait = us; + + while ((__HAL_TIM_GET_COUNTER(&htim2) - tickstart) < wait) { + } +} + +/** + * @brief Wake every ADBMS6830 IC in the daisy chain. Blocking wait for around 30us * NUM_CHIPS. + * + */ +void adbms_wake() +{ + for (uint8_t ic = 0; ic < NUM_CHIPS; ic++) { + adBmsCsLow(); + adBmsCsHigh(); + delay_us(20); + } +} + +/** + * @brief Write data to all chips. + * + * @param chip Array of chips to write data to. + * @param command Command to issue to the chip. + * @param type Register type to write to. + * @param group Group of registers to write to. + */ +void write_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type, + GRP group) +{ + adbms_wake(); + + for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) { + adBmsWriteData(NUM_CHIPS, &chips[chip], command, type, group); + } +} + +/** + * @brief Read data from all chips. + * + * @param chips Array of chips to read data to. + * @param command Command to issue to the chip. + * @param type Register type to write to. + * @param group Group of registers to write to. + */ +void read_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type, + GRP group) +{ + adbms_wake(); + + for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) { + adBmsReadData(NUM_CHIPS, &chips[chip], command, type, group); + } + + // Count PEC errors + uint32_t pec_error_count = 0; + for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) { + // Yes, they did separate every PEC as if that mattered. + pec_error_count += + chips[chip].cccrc.cfgr_pec + chips[chip].cccrc.sid_pec + + chips[chip].cccrc.cell_pec + + chips[chip].cccrc.acell_pec + + chips[chip].cccrc.scell_pec + + chips[chip].cccrc.fcell_pec + + chips[chip].cccrc.aux_pec + chips[chip].cccrc.raux_pec + + chips[chip].cccrc.stat_pec + + chips[chip].cccrc.comm_pec + chips[chip].cccrc.pwm_pec; + + if (pec_error_count > 0) { + printf("PEC COUNT: %ld | Chip: %d | CMD: %d\n", + pec_error_count, chip, type); + } + + chips[chip].cccrc.cfgr_pec = 0; + chips[chip].cccrc.sid_pec = 0; + chips[chip].cccrc.cell_pec = 0; + chips[chip].cccrc.acell_pec = 0; + chips[chip].cccrc.scell_pec = 0; + chips[chip].cccrc.fcell_pec = 0; + chips[chip].cccrc.aux_pec = 0; + chips[chip].cccrc.raux_pec = 0; + chips[chip].cccrc.stat_pec = 0; + chips[chip].cccrc.comm_pec = 0; + chips[chip].cccrc.pwm_pec = 0; + } + pec_error_count = 0; +} + +// --- BEGIN WRITE COMMANDS --- + +void write_config_regs(cell_asic chips[NUM_CHIPS]) +{ + write_adbms_data(chips, WRCFGA, Config, A); + write_adbms_data(chips, WRCFGB, Config, B); +} + +void write_clear_flags(cell_asic chips[NUM_CHIPS]) +{ + for (int chip = 0; chip < NUM_CHIPS; chip++) { + chips[chip].clflag.cl_sleep = 1; + chips[chip].clflag.cl_smed = 1; + chips[chip].clflag.cl_sed = 1; + chips[chip].clflag.cl_cmed = 1; + chips[chip].clflag.cl_ced = 1; + chips[chip].clflag.cl_vduv = 1; + chips[chip].clflag.cl_vdov = 1; + chips[chip].clflag.cl_vauv = 1; + chips[chip].clflag.cl_vaov = 1; + chips[chip].clflag.cl_oscchk = 1; + chips[chip].clflag.cl_tmode = 1; + chips[chip].clflag.cl_thsd = 1; + chips[chip].clflag.cl_sleep = 1; + chips[chip].clflag.cl_spiflt = 1; + chips[chip].clflag.cl_vdel = 1; + chips[chip].clflag.cl_vde = 1; + } + write_adbms_data(chips, CLRFLAG, Clrflag, NONE); +} + +// --- END WRITE COMMANDS + +// --- BEGIN READ COMMANDS --- + +void read_filtered_voltage_registers(cell_asic chips[NUM_CHIPS]) +{ + read_adbms_data(chips, RDFCALL, Rdfcall, ALL_GRP); +} + +void adc_and_read_aux_registers(cell_asic chips[NUM_CHIPS]) +{ + // TODO only poll correct GPIOs + adbms_wake(); + adBms6830_Adax(AUX_OW_OFF, PUP_DOWN, AUX_ALL); + adBmsPollAdc(PLAUX2); + + read_adbms_data(chips, RDAUXA, Aux, A); + read_adbms_data(chips, RDAUXB, Aux, B); + read_adbms_data(chips, RDAUXC, Aux, C); + read_adbms_data(chips, RDAUXD, Aux, D); +} + +void adc_and_read_aux2_registers(cell_asic chips[NUM_CHIPS]) +{ + adbms_wake(); + adBms6830_Adax2(AUX_ALL); + adBmsPollAdc(PLAUX2); + + read_adbms_data(chips, RDRAXA, RAux, A); + read_adbms_data(chips, RDRAXB, RAux, B); + read_adbms_data(chips, RDRAXC, RAux, C); + read_adbms_data(chips, RDRAXD, RAux, D); +} + +void read_status_registers(cell_asic chips[NUM_CHIPS]) +{ + read_adbms_data(chips, RDSTATA, Status, A); + read_adbms_data(chips, RDSTATB, Status, B); + read_adbms_data(chips, RDSTATC, Status, C); + read_adbms_data(chips, RDSTATD, Status, D); + read_adbms_data(chips, RDSTATE, Status, E); +} + +void read_status_aux_registers(cell_asic chips[NUM_CHIPS]) +{ + read_adbms_data(chips, RDASALL, Rdasall, ALL_GRP); +} + +void read_serial_id(cell_asic chips[NUM_CHIPS]) +{ + read_adbms_data(chips, RDSID, Sid, NONE); +} + +// --- END READ COMMANDS --- + +// --- BEGIN ADC POLL --- + +void get_c_adc_voltages(cell_asic chips[NUM_CHIPS]) +{ + adbms_wake(); + // Take single shot measurement + adBms6830_Adcv(RD_OFF, SINGLE, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); + adBmsPollAdc(PLCADC); + read_adbms_data(chips, RDCVALL, Rdcvall, ALL_GRP); +} + +void get_s_adc_voltages(cell_asic chips[NUM_CHIPS]) +{ + write_config_regs(chips); + adbms_wake(); + adBms6830_Adsv(SINGLE, DCP_OFF, OW_OFF_ALL_CH); + adBmsPollAdc(PLSADC); + + adbms_wake(); + read_adbms_data(chips, RDSALL, Rdsall, ALL_GRP); + // read_adbms_data(chip, RDSVA, S_volt, A); + // read_adbms_data(chip, RDSVB, S_volt, B); + // read_adbms_data(chip, RDSVC, S_volt, C); + // read_adbms_data(chip, RDSVD, S_volt, D); + // read_adbms_data(chip, RDSVE, S_volt, E); + // read_adbms_data(chip, RDSVF, S_volt, F); +} + +void get_avgd_cell_voltages(cell_asic chips[NUM_CHIPS]) +{ + adbms_wake(); + adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); + adBmsPollAdc(PLCADC); + + adbms_wake(); + read_adbms_data(chips, RDACALL, Rdacall, ALL_GRP); +} + +void get_filtered_cell_voltages(cell_asic chips[NUM_CHIPS]) +{ + adbms_wake(); + read_adbms_data(chips, RDFCALL, Rdfcall, ALL_GRP); +} + +void get_c_and_s_adc_voltages(cell_asic chips[NUM_CHIPS]) +{ + adbms_wake(); + adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); + adBmsPollAdc(PLCADC); + + adbms_wake(); + read_adbms_data(chips, RDCSALL, Rdcsall, ALL_GRP); +} + +void start_c_adc_conv() +{ + adbms_wake(); + adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_ON, OW_OFF_ALL_CH); +} + +// --- END ADC POLL --- diff --git a/Core/Src/analyzer.c b/Core/Src/analyzer.c index e318b6c5..4ef2bc46 100644 --- a/Core/Src/analyzer.c +++ b/Core/Src/analyzer.c @@ -169,7 +169,7 @@ void calc_cell_temps(acc_data_t *bmsdata) for (int cell = 0; cell < num_cells; cell++) { int16_t x = bmsdata->chips[chip] - .aux.a_codes[THERM_MAP[cell]]; + .raux.ra_codes[THERM_MAP[cell]]; bmsdata->chip_data[chip].cell_temp[cell] = calc_cell_temp(x); @@ -180,14 +180,14 @@ void calc_cell_temps(acc_data_t *bmsdata) if (!bmsdata->chip_data[chip].alpha) { // Take average of both onboard therms bmsdata->chip_data[chip].on_board_temp = - (calc_cell_temp(( - bmsdata->chips[chip].aux.a_codes[6])) + - calc_cell_temp( - bmsdata->chips[chip].aux.a_codes[7])) / + (calc_cell_temp((bmsdata->chips[chip] + .raux.ra_codes[6])) + + calc_cell_temp(bmsdata->chips[chip] + .raux.ra_codes[7])) / 2; } else { bmsdata->chip_data[chip].on_board_temp = calc_cell_temp( - bmsdata->chips[chip].aux.a_codes[7]); + bmsdata->chips[chip].raux.ra_codes[7]); } } @@ -304,13 +304,13 @@ void calc_pack_voltage_stats(acc_data_t *bmsdata) uint8_t num_cells = get_num_cells(&bmsdata->chip_data[c]); for (uint8_t cell = 0; cell < num_cells; cell++) { /* fings out the maximum cell voltage and location */ - if (getVoltage(bmsdata->chips[c].cell.c_codes[cell]) * + if (getVoltage(bmsdata->chips[c].fcell.fc_codes[cell]) * 10000 > bmsdata->max_voltage.val) { bmsdata->max_voltage.val = getVoltage( bmsdata->chips[c] - .cell.c_codes[cell]) * + .fcell.fc_codes[cell]) * 10000; bmsdata->max_voltage.chipIndex = c; bmsdata->max_voltage.cellNum = cell; @@ -326,13 +326,13 @@ void calc_pack_voltage_stats(acc_data_t *bmsdata) } /* finds out the minimum cell voltage and location */ - if (getVoltage(bmsdata->chips[c].cell.c_codes[cell]) * + if (getVoltage(bmsdata->chips[c].fcell.fc_codes[cell]) * 10000 < bmsdata->min_voltage.val) { bmsdata->min_voltage.val = getVoltage( bmsdata->chips[c] - .cell.c_codes[cell]) * + .fcell.fc_codes[cell]) * 10000; bmsdata->min_voltage.chipIndex = c; bmsdata->min_voltage.cellNum = cell; @@ -348,7 +348,7 @@ void calc_pack_voltage_stats(acc_data_t *bmsdata) } total_volt += getVoltage( - bmsdata->chips[c].cell.c_codes[cell]); + bmsdata->chips[c].fcell.fc_codes[cell]); total_ocv += bmsdata->chip_data[c].open_cell_voltage[cell]; } @@ -556,9 +556,11 @@ void calc_open_cell_voltage(acc_data_t *bmsdata) for (uint8_t cell = 0; cell < num_cells; cell++) { bmsdata->chip_data[chip] .open_cell_voltage[cell] = - bmsdata->chips[chip].cell.c_codes[cell]; + bmsdata->chips[chip] + .fcell.fc_codes[cell]; prev_chipdata[chip].open_cell_voltage[cell] = - bmsdata->chips[chip].cell.c_codes[cell]; + bmsdata->chips[chip] + .fcell.fc_codes[cell]; } } return; @@ -577,8 +579,8 @@ void calc_open_cell_voltage(acc_data_t *bmsdata) bmsdata->chip_data[chip] .open_cell_voltage[cell] = ((uint32_t)(bmsdata->chips[chip] - .cell - .c_codes[cell]) + + .fcell + .fc_codes[cell]) + ((uint32_t)(prev_chipdata[chip].open_cell_voltage [cell]) * (OCV_AVG - 1))) / @@ -586,7 +588,7 @@ void calc_open_cell_voltage(acc_data_t *bmsdata) bmsdata->chip_data[chip] .open_cell_voltage[cell] = bmsdata->chips[chip] - .cell.c_codes[cell]; + .fcell.fc_codes[cell]; if (bmsdata->chip_data[chip] .open_cell_voltage[cell] > diff --git a/Core/Src/main.c b/Core/Src/main.c index d0cc9a0d..f3230a68 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -74,6 +74,7 @@ SPI_HandleTypeDef hspi3; TIM_HandleTypeDef htim1; TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim5; TIM_HandleTypeDef htim8; UART_HandleTypeDef huart4; @@ -85,7 +86,7 @@ PCD_HandleTypeDef hpcd_USB_OTG_FS; osThreadId_t defaultTaskHandle; const osThreadAttr_t defaultTask_attributes = { .name = "defaultTask", - .stack_size = 128 * 8, + .stack_size = 256 * 4, .priority = (osPriority_t) osPriorityNormal, }; /* USER CODE BEGIN PV */ @@ -110,6 +111,7 @@ static void MX_TIM8_Init(void); static void MX_ADC1_Init(void); static void MX_ADC2_Init(void); static void MX_IWDG_Init(void); +static void MX_TIM5_Init(void); void StartDefaultTask(void *argument); /* USER CODE BEGIN PFP */ @@ -208,7 +210,7 @@ const void print_bms_stats(acc_data_t *acc_data) uint8_t num_cells = get_num_cells(&acc_data->chip_data[c]); for(uint8_t cell = 0; cell < num_cells; cell++) { - printf("%.3f\t", getVoltage(acc_data->chips[c].cell.c_codes[cell])); + printf("%.3f\t", getVoltage(acc_data->chips[c].fcell.fc_codes[cell])); } printf("\n"); } @@ -227,6 +229,19 @@ const void print_bms_stats(acc_data_t *acc_data) } #endif +#define DEBUG_THERM_VOLTS + #ifdef DEBUG_THERM_VOLTS + printf("THERM VOLTS: \n"); + for(uint8_t c = 0; c < NUM_CHIPS; c++) + { + for(uint8_t gpio = 0; gpio < 10; gpio++) + { + printf("%f\t", getVoltage(acc_data->chips[c].raux.ra_codes[gpio])); + } + printf("\n"); + } + #endif + #ifdef DEBUG_OTHER printf("UnFiltered Thermistor Temps:\n"); @@ -290,6 +305,7 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *phuart) */ int main(void) { + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ @@ -332,6 +348,7 @@ int main(void) MX_ADC1_Init(); MX_ADC2_Init(); MX_IWDG_Init(); + MX_TIM5_Init(); /* USER CODE BEGIN 2 */ //for (int i = 0; i < 58; i++) //{ @@ -373,7 +390,7 @@ int main(void) /* Create the thread(s) */ /* creation of defaultTask */ - defaultTaskHandle = osThreadNew(StartDefaultTask, acc_data, &defaultTask_attributes); + defaultTaskHandle = osThreadNew(StartDefaultTask, (void*) acc_data, &defaultTask_attributes); /* USER CODE BEGIN RTOS_THREADS */ @@ -411,6 +428,7 @@ int main(void) osKernelStart(); /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ /* USER CODE BEGIN WHILE */ for(;;) { @@ -811,7 +829,7 @@ static void MX_SPI3_Init(void) hspi3.Init.CLKPolarity = SPI_POLARITY_LOW; hspi3.Init.CLKPhase = SPI_PHASE_1EDGE; hspi3.Init.NSS = SPI_NSS_SOFT; - hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi3.Init.TIMode = SPI_TIMODE_DISABLE; hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; @@ -924,7 +942,7 @@ static void MX_TIM2_Init(void) /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; - htim2.Init.Prescaler = 0; + htim2.Init.Prescaler = 16; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 4294967295; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; @@ -945,11 +963,56 @@ static void MX_TIM2_Init(void) Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ - + HAL_TIM_Base_Start(&htim2); /* USER CODE END TIM2_Init 2 */ } +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 4294967295; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + /** * @brief TIM8 Initialization Function * @param None @@ -1269,6 +1332,27 @@ void StartDefaultTask(void *argument) /* USER CODE END 5 */ } +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM3 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM3) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + /** * @brief This function is executed in case of error occurrence. * @retval None diff --git a/Core/Src/segment.c b/Core/Src/segment.c index aaec32a8..065d3569 100644 --- a/Core/Src/segment.c +++ b/Core/Src/segment.c @@ -1,19 +1,11 @@ #include "segment.h" -#include "main.h" #include -#include -#include -#include #include "analyzer.h" #include "c_utils.h" -#include "common.h" -#include "adBms6830CmdList.h" -#include "adBms6830GenericType.h" #include "serialPrintResult.h" #include "adBms6830ParseCreate.h" -#include "mcuWrapper.h" -#include "cmsis_os.h" +#include "adi_interaction.h" #define T_READY 10 /* microseconds*/ #define T_IDLE 4.3 /* milliseconds, minimum. typ is 5.5, max is 6.7 */ @@ -29,263 +21,54 @@ #define GPIO_EXPANDER_ADDR 0x40 #define GPIO_REGISTER_ADDR 0x09 -// TODO ensure spi 1 is correct for talking to segs -extern SPI_HandleTypeDef hspi1; +extern TIM_HandleTypeDef htim2; uint8_t therm_avg_counter = 0; nertimer_t variance_timer; -uint32_t pec_error_count = 0; - /* private function prototypes */ -void variance_therm_check(void); -void discard_neutrals(chipdata_t segment_data[NUM_CHIPS]); -void pull_chip_configuration(void); -int16_t calc_average(chipdata_t segment_data[NUM_CHIPS]); -int8_t calc_therm_standard_dev(int16_t avg_temp); +// void variance_therm_check(void); +// void discard_neutrals(chipdata_t segment_data[NUM_CHIPS]); +// void pull_chip_configuration(void); +// int16_t calc_average(chipdata_t segment_data[NUM_CHIPS]); +// int8_t calc_therm_standard_dev(int16_t avg_temp); void init_chip(cell_asic *chip); +void write_config_regs(cell_asic chip[NUM_CHIPS]); void set_cell_discharge(cell_asic *chip, uint8_t cell, bool discharge); /** - * @brief Set a bit in a uint16 - * - * @param number uint16 to change. - * @param n Nth bit to change. - * @param x true sets, false clears. - * @return uint16_t New uint16. - */ -inline uint16_t set_uint16_bit(uint16_t number, uint16_t n, bool x) -{ - return (number & ~((uint16_t)1 << n)) | ((uint16_t)x << n); -} - -/** - * @brief Wake every ADBMS6830 IC in the daisy chain. Takes NUM_CHIPS * 8 ms to finish. - * - */ -void adbms_wake() -{ - adBmsCsLow(); - adBmsCsHigh(); - - /* - DEBUG: Theoretically, below should work for one IC, but it is not. - It shold be necessarry for multiple IC operation. - */ - - // for (uint8_t ic = 0; ic < total_ic; ic++) { - // adBmsCsLow(); - // Delay_ms(4); - // adBmsCsHigh(); - // Delay_ms(4); - // } - - // adBmsWakeupIc(NUM_CHIPS); -} - -/** - * @brief Set the status of the REFON bit. - * - * @param chip Pointer to the chip to modify. - * @param state New state of the REFON bit. - */ -void set_REFON(cell_asic *chip, REFON state) -{ - chip->tx_cfga.refon = state; -} - -/** - * @brief Set the C-ADC vs. S-ADC comparison voltage threshold - * - * @param chip Pointer to the chip to modify. - * @param threshold Threshold to set. - */ -void set_volt_adc_comp_thresh(cell_asic *chip, CTH threshold) -{ - chip->tx_cfga.cth = threshold; -} - -void set_diagnostic_flags(cell_asic *chip, FLAG_D config) -{ - chip->tx_cfga.flag_d = - (uint8_t)set_uint16_bit(chip->tx_cfga.flag_d, config, true); -} - -/** - * @brief Set the discharge state of a cell. - * - * @param chip Pointer to chip with cell to modify. - * @param cell ID of cell to modify. Cell indexes start are from 1-16 (NOT ZERO INDEXED). - * @param discharge Cell discharge state. true to discharge, false to disable discharge. - */ -void set_cell_discharge(cell_asic *chip, uint8_t cell, bool discharge) -{ - chip->tx_cfgb.dcc = set_uint16_bit(chip->tx_cfgb.dcc, cell, discharge); -} - -/** - * @brief Set the state of the SOAKON bit to either enable or disable soak times. - * - * @param chip Pointer to chip to configure - * @param state Enable or disable SOAKON - */ -void set_soak_on(cell_asic *chip, SOAKON state) -{ - chip->tx_cfga.soakon = state; -} - -/** - * @brief Set the open wire detection soak time range. - * - * @param chip Pointer to chip to configure - * @param range The range of time over which to soak for open wire detection - */ -void set_open_wire_soak_range(cell_asic *chip, OWRNG range) -{ - chip->tx_cfga.owrng = range; -} - -/** - * @brief Set the open wire soak time. See data sheet for formula. - * - * @param chip Pointer to chip configuration - * @param time The amount of time to soak for. Higher OWA is a higher soak time. - */ -void set_open_wire_soak_time(cell_asic *chip, OWA time) -{ - chip->tx_cfga.owa = time; -} - -/** - * @brief Set the mode of a GPIO pin on an ADBMS8630. - * - * @param chip ADBMS6830 chip - * @param gpio Number of the GPIO pin to change (1-10) - * @param input True is input, False is output. - */ -void set_gpio_mode(cell_asic *chip, uint8_t gpio, bool input) -{ - if (gpio > 10 || gpio < 1) { - printf("ERROR: Invalid GPIO pin %d\n", gpio); - return; - } - chip->tx_cfga.gpo = set_uint16_bit(chip->tx_cfga.gpo, gpio - 1, input); -} - -/** - * @brief Set the corner frequency of the IIR filter. - * - * @param chip Pointer to chip config - * @param freq Corner frequency (see IIR_FPA enum for frequencies) - */ -void set_iir_corner_freq(cell_asic *chip, IIR_FPA freq) -{ - chip->tx_cfga.fc = freq; -} - -/** - * @brief Configure a chip as a break in the isoSPI daisy chain. - * - * @param chip Pointer to chip config - * @param is_break True if chip is break, false if chip is not break - */ -void set_comm_break(cell_asic *chip, bool is_break) -{ - chip->tx_cfga.comm_bk = is_break; -} - -/** - * @brief Enable/disable discharging through the mute discharge bit. - * - * @param chip Pointer to chip config - * @param disable_discharge True to disable discharge, false to enable discharge. - */ -void set_mute_state(cell_asic *chip, bool disable_discharge) -{ - chip->tx_cfga.mute_st = disable_discharge; -} - -/** - * @brief Set whether or not this chip is taking a snapshot. The chip will not begin reading new values unless the snapshot bit is cleared. - * - * @param chip Pointer to chip config - * @param take_snapshot True to take a snapshot, false to end the snapshot - */ -void set_snapshot(cell_asic *chip, bool take_snapshot) -{ - chip->tx_cfga.snap = take_snapshot; -} - -/** - * @brief Enable/disable the discharge timer monitor. - * - * @param chip Pointer to chip config - * @param enabled True if discharge timer monitor is enabled, false if otherwise - */ -void set_discharge_timer_monitor(cell_asic *chip, bool enabled) -{ - chip->tx_cfgb.dtmen = enabled; -} - -/** - * @brief Configure the discharge timer range, which affects the resolution. - * - * @param chip Pointer to chip config - * @param large True for large range, False for small range - */ -void set_discharge_timer_range(cell_asic *chip, bool large) -{ - chip->tx_cfgb.dtrng = large; -} - -/** - * @brief Set the discharge monitor timeout, which is dependent on the discharge timer range. - * - * @param chip Pointer to chip config - * @param timeout Base for timeout multiplicaiton. Must be below six bits. - */ -void set_discharge_timeout(cell_asic *chip, uint8_t timeout) -{ - if (timeout >> 6 > 0) { - printf("Invalid discharge time\n"); - return; - //TODO: Non-critical fault - } - chip->tx_cfgb.dcto = timeout; -} - -/** - * @brief Initialize a chip with default values. + * @brief Initialize a chip with our default values. * * @param chip Pointer to chip to initialize. */ void init_chip(cell_asic *chip) { set_REFON(chip, PWR_UP); - set_volt_adc_comp_thresh(chip, CVT_8_1mV); + // WARNING, THE ENUM IS WRONG, CHECK TABLE 102 + set_volt_adc_comp_thresh(chip, CVT_45mV); chip->tx_cfga.flag_d = 0; - // No soak on AUX ADCs - set_soak_on(chip, SOAKON_CLR); - - // short soak time by default - set_open_wire_soak_range(chip, TIME_32US_TO_4_1MS); + // Short soak on ADAX + set_soak_on(chip, SOAKON_SET); + set_aux_soak_range(chip, SHORT); // No open wire detect soak set_open_wire_soak_time(chip, OWA0); - // All GPIOs are inputs by default - set_gpio_mode(chip, 1, true); - set_gpio_mode(chip, 2, true); - set_gpio_mode(chip, 3, true); - set_gpio_mode(chip, 4, true); - set_gpio_mode(chip, 5, true); - set_gpio_mode(chip, 6, true); - set_gpio_mode(chip, 7, true); - set_gpio_mode(chip, 8, true); - set_gpio_mode(chip, 9, true); - set_gpio_mode(chip, 10, true); + // Set therm GPIOs + set_gpio_pull(chip, 1, true); + set_gpio_pull(chip, 2, true); + set_gpio_pull(chip, 3, true); + set_gpio_pull(chip, 4, true); + set_gpio_pull(chip, 5, true); + set_gpio_pull(chip, 6, true); + set_gpio_pull(chip, 7, true); // this is a on board therm for beta only + set_gpio_pull(chip, 8, true); // this is a on board therm + + // set outputs, 9=iso led 10=bal LED + set_gpio_pull(chip, 9, false); + set_gpio_pull(chip, 10, false); // Registers are unfrozen set_snapshot(chip, SNAP_OFF); @@ -297,7 +80,7 @@ void init_chip(cell_asic *chip) set_comm_break(chip, false); // IIR filter disabled - set_iir_corner_freq(chip, IIR_FPA_OFF); + set_iir_corner_freq(chip, IIR_FPA16); // Init config B @@ -315,78 +98,6 @@ void init_chip(cell_asic *chip) chip->tx_cfgb.dcc = 0; } -/** - * @brief Write data to all chips. - * - * @param chip Array of chips to write data to. - * @param command Command to issue to the chip. - * @param type Register type to write to. - * @param group Group of registers to write to. - */ -void write_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type, - GRP group) -{ - adBmsWriteData(NUM_CHIPS, chips, command, type, group); -} - -/** - * @brief Read data from all chips. - * - * @param chips Array of chips to read data to. - * @param command Command to issue to the chip. - * @param type Register type to write to. - * @param group Group of registers to write to. - */ -void read_adbms_data(cell_asic chips[NUM_CHIPS], uint8_t command[2], TYPE type, - GRP group) -{ - adBmsReadData(NUM_CHIPS, chips, command, type, group); - - // Count PEC errors - for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) { - // Yes, they did separate every PEC as if that mattered. - pec_error_count += - chips[chip].cccrc.cfgr_pec + chips[chip].cccrc.sid_pec + - chips[chip].cccrc.cell_pec + - chips[chip].cccrc.acell_pec + - chips[chip].cccrc.scell_pec + - chips[chip].cccrc.fcell_pec + - chips[chip].cccrc.aux_pec + chips[chip].cccrc.raux_pec + - chips[chip].cccrc.stat_pec + - chips[chip].cccrc.comm_pec + chips[chip].cccrc.pwm_pec; - - if (pec_error_count > 0) { - printf("PEC COUNT: %ld | Chip: %d | CMD: %d\n", - pec_error_count, chip, type); - } - - chips[chip].cccrc.cfgr_pec = 0; - chips[chip].cccrc.sid_pec = 0; - chips[chip].cccrc.cell_pec = 0; - chips[chip].cccrc.acell_pec = 0; - chips[chip].cccrc.scell_pec = 0; - chips[chip].cccrc.fcell_pec = 0; - chips[chip].cccrc.aux_pec = 0; - chips[chip].cccrc.raux_pec = 0; - chips[chip].cccrc.stat_pec = 0; - chips[chip].cccrc.comm_pec = 0; - chips[chip].cccrc.pwm_pec = 0; - } - pec_error_count = 0; -} - -/** - * @brief Write config registers. Wakes chips before writing. - * - * @param chips Array of chips to write config registers of. - */ -void write_config_regs(cell_asic chips[NUM_CHIPS]) -{ - adbms_wake(); - write_adbms_data(chips, WRCFGA, Config, A); - write_adbms_data(chips, WRCFGB, Config, B); -} - /** * @brief Initialize chips with default values. * @@ -400,58 +111,21 @@ void segment_init(acc_data_t *bmsdata) bmsdata->chip_data[chip].alpha = chip % 2 == 0; } write_config_regs(bmsdata->chips); -} - -/** - * @brief Get voltage readings from the C-ADCs. Takes a single shot measurement. - * - * @param chips Array of chips to get voltage readings from. - */ -void get_c_adc_voltages(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - // Take single shot measurement - adBms6830_Adcv(RD_OFF, SINGLE, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLCADC); - read_adbms_data(chips, RDCVALL, Rdcvall, ALL_GRP); + start_c_adc_conv(); } -/** - * @brief Get voltages from the S-ADCs. Makes a single shot measurement. - * - * @param chip Array of chips to get voltage readings from. - */ -void get_s_adc_voltages(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adbms_wake(); - adBms6830_Adsv(SINGLE, DCP_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLSADC); - - adbms_wake(); - read_adbms_data(chips, RDSALL, Rdsall, ALL_GRP); - // read_adbms_data(chip, RDSVA, S_volt, A); - // read_adbms_data(chip, RDSVB, S_volt, B); - // read_adbms_data(chip, RDSVC, S_volt, C); - // read_adbms_data(chip, RDSVD, S_volt, D); - // read_adbms_data(chip, RDSVE, S_volt, E); - // read_adbms_data(chip, RDSVF, S_volt, F); -} - -void get_adc_comparison(acc_data_t *bmsdata) +void segment_adc_comparison(acc_data_t *bmsdata) { // TODO: S-ADC measurements are all over the place. - write_config_regs(bmsdata->chips); - // Take single shot measurement - adBms6830_Adcv(RD_ON, SINGLE, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLCADC); - read_adbms_data(bmsdata->chips, RDCVALL, Rdcvall, ALL_GRP); + // adBms6830_Adcv(RD_ON, SINGLE, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); + // adBmsPollAdc(PLCADC); + // read_adbms_data(bmsdata->chips, RDCVALL, Rdcvall, ALL_GRP); // Result of C-ADC and S-ADC comparison is stored in status register group C - read_adbms_data(bmsdata->chips, RDSTATC, Status, C); + read_status_registers(bmsdata->chips); for (uint8_t chip = 0; chip < NUM_CHIPS; chip++) { uint8_t cells = get_num_cells(&bmsdata->chip_data[chip]); @@ -460,8 +134,9 @@ void get_adc_comparison(acc_data_t *bmsdata) cell)) { printf("ADC VOLTAGE DISCREPANCY ERROR\nChip %d, Cell %d\nC-ADC: %f, S-ADC: %f\n", chip + 1, cell + 1, - getVoltage(bmsdata->chips[chip] - .cell.c_codes[cell]), + getVoltage( + bmsdata->chips[chip] + .fcell.fc_codes[cell]), getVoltage( bmsdata->chips[chip] .scell.sc_codes[cell])); @@ -470,142 +145,70 @@ void get_adc_comparison(acc_data_t *bmsdata) } } -/** - * @brief Get the avgeraged cell voltages. - * - * @param chip Array of chips to get voltage readings of. - */ -void get_avgd_cell_voltages(cell_asic chips[NUM_CHIPS]) +void segment_monitor_flts(cell_asic chips[NUM_CHIPS]) { - write_config_regs(chips); - adbms_wake(); - adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLCADC); - - adbms_wake(); - read_adbms_data(chips, RDACALL, Rdacall, ALL_GRP); -} - -/** - * @brief Get the filtered cell volrages. - * - * @param chip Array of chips to get voltage readings of. - */ -void get_filtered_cell_voltages(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adbms_wake(); - adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLCADC); - - adbms_wake(); - read_adbms_data(chips, RDFCALL, Rdfcall, ALL_GRP); -} - -/** - * @brief Get the c and s adc voltages. Does this with RDCSALL command. - * - * @param chips Array of chips to get voltage readings of. - */ -void get_c_and_s_adc_voltages(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adbms_wake(); - adBms6830_Adcv(RD_ON, CONTINUOUS, DCP_OFF, RSTF_OFF, OW_OFF_ALL_CH); - adBmsPollAdc(PLCADC); - - adbms_wake(); - read_adbms_data(chips, RDCSALL, Rdcsall, ALL_GRP); -} - -/** - * @brief Read every register connected to the AUX ADC. - * - * @param chips Array of chips to get voltage readings of. - */ -void read_aux_registers(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adBms6830_Adax(AUX_OW_OFF, PUP_DOWN, AUX_ALL); - adBmsPollAdc(PLAUX1); - - adbms_wake(); - read_adbms_data(chips, RDAUXA, Aux, A); - read_adbms_data(chips, RDAUXB, Aux, B); - read_adbms_data(chips, RDAUXC, Aux, C); - read_adbms_data(chips, RDAUXD, Aux, D); -} - -/** - * @brief Read voltages in every register connected to AUX2 ADC. - * - * @param chips Array of chips to get voltages of. - */ -void read_aux2_registers(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adBms6830_Adax2(AUX_ALL); - adBmsPollAdc(PLAUX2); - - adbms_wake(); - read_adbms_data(chips, RDRAXA, RAux, A); - read_adbms_data(chips, RDRAXB, RAux, B); - read_adbms_data(chips, RDRAXC, RAux, C); - read_adbms_data(chips, RDRAXD, RAux, D); -} - -/** - * @brief Read status registers. - * - * @param chips Array of chips to read. - */ -void read_status_registers(cell_asic chips[NUM_CHIPS]) -{ - write_config_regs(chips); - adBms6830_Adax(AUX_OW_OFF, PUP_DOWN, AUX_ALL); - adBmsPollAdc(PLAUX1); - - read_adbms_data(chips, RDSTATA, Status, A); - read_adbms_data(chips, RDSTATB, Status, B); - read_adbms_data(chips, RDSTATC, Status, C); - read_adbms_data(chips, RDSTATD, Status, D); - read_adbms_data(chips, RDSTATE, Status, E); + read_status_registers(chips); + for (int chip = 0; chip < NUM_CHIPS; chip++) { + if (chips[chip].statc.va_ov) { + printf("A OV FLT\n"); + } + if (chips[chip].statc.va_uv) { + printf("A UV FLT\n"); + } + if (chips[chip].statc.vd_ov) { + printf("D OV FLT\n"); + } + if (chips[chip].statc.vd_uv) { + printf("D OV FLT\n"); + } + if (chips[chip].statc.vde) { + printf("VDE FLT\n"); + } + if (chips[chip].statc.vdel) { + printf("VDEL FLT\n"); + } + if (chips[chip].statc.spiflt) { + printf("SPI SLV FLT\n"); + } + if (chips[chip].statc.sleep) { + printf("SLEEP OCCURED\n"); + } + if (chips[chip].statc.thsd) { + printf("THERMAL FLT\n"); + } + if (chips[chip].statc.oscchk) { + printf("OSC FLT\n"); + } + if (chips[chip].statc.otp1_med) { + printf("CMED? FLT\n"); + } + if (chips[chip].statc.otp2_med) { + printf("SMED? FLT\n"); + } + } + // clear them + write_clear_flags(chips); } -/** - * @brief Read status and aux registers in one command. - * - * @param chips Array of chips to read. - */ -void read_status_aux_registers(cell_asic chips[NUM_CHIPS]) +// ensure stuff used is in the correctfunction +void segment_retrieve_data(acc_data_t *bmsdata) { - write_config_regs(chips); - adBms6830_Adax(AUX_OW_OFF, PUP_DOWN, AUX_ALL); - adBmsPollAdc(PLAUX1); + // read from ADC convs + read_filtered_voltage_registers(bmsdata->chips); - read_adbms_data(chips, RDASALL, Rdasall, ALL_GRP); -} + // check our fault flags + segment_monitor_flts(bmsdata->chips); -/** - * @brief Read the serial ID of the chip. - * - * @param chips Array of chips to read. - */ -void read_serial_id(cell_asic chips[NUM_CHIPS]) -{ - read_adbms_data(chips, RDSID, Sid, NONE); + // read all therms using AUX 2 + adc_and_read_aux2_registers(bmsdata->chips); } - -void segment_retrieve_data(acc_data_t *bmsdata) +void segment_retrieve_debug_data(acc_data_t *bmsdata) { - // printf("Get C adc voltages\n"); - get_c_adc_voltages(bmsdata->chips); - - // The GPIOs in the AUX registers contain voltage readings from the therms. - read_status_aux_registers(bmsdata->chips); + // poll stuff like vref, etc. + adc_and_read_aux_registers(bmsdata->chips); - // If you want redundant Thermistor readings, uncomment the following. - // read_aux2_registers(bmsdata->chips); + // read the above into status registers + read_status_registers(bmsdata->chips); } bool segment_is_balancing(cell_asic chips[NUM_CHIPS]) @@ -640,7 +243,7 @@ void segment_configure_balancing( set_mute_state(&bmsdata->chips[chip], false); } } - write_config_regs(bmsdata->chips); + // write_config_regs(bmsdata->chips); } // void averaging_therm_check(chipdata_t segment_data[NUM_CHIPS]) diff --git a/Core/Src/shep_tasks.c b/Core/Src/shep_tasks.c index 0438a325..a51bd754 100644 --- a/Core/Src/shep_tasks.c +++ b/Core/Src/shep_tasks.c @@ -115,7 +115,7 @@ void vDebugMode(void *pv_params) // read_serial_id(bmsdata->chips); - read_aux2_registers(bmsdata->chips); + segment_retrieve_debug_data(bmsdata); for (int chip = 0; chip < NUM_CHIPS; chip++) { uint8_t num_cells = @@ -149,7 +149,7 @@ void vDebugMode(void *pv_params) (bmsdata->chips[chip].tx_cfgb.dcc >> (cell + 1)) & 1); - osDelay(6); + osDelay(1000 / NUM_CHIPS); } // Send chip status messages @@ -171,10 +171,11 @@ void vDebugMode(void *pv_params) .stata.itmp) / 0.0075) - 273, - 10000 * getVoltage( + 10000 * 20 * + getVoltage( // VPV is ra_code 11 w/ different scale bmsdata->chips[chip] .raux - .ra_codes[9])); + .ra_codes[11])); compute_send_beta_status_b_message( 10000 * getVoltage( bmsdata->chips[chip] @@ -186,10 +187,11 @@ void vDebugMode(void *pv_params) chip, 10000 * getVoltage(bmsdata->chips[chip] .statb.vr4k), - 10000 * getVoltage( + 10000 * 20 * + getVoltage( // VMV is ra_code 10 bmsdata->chips[chip] .raux - .ra_codes[8])); + .ra_codes[10])); } else { compute_send_alpha_status_a_message( bmsdata->chip_data->on_board_temp, chip, diff --git a/Core/Src/stateMachine.c b/Core/Src/stateMachine.c index ff4b34b8..a77906b1 100644 --- a/Core/Src/stateMachine.c +++ b/Core/Src/stateMachine.c @@ -455,7 +455,7 @@ void sm_balance_cells(acc_data_t *bmsdata) for (uint8_t cell = 0; cell < num_cells; cell++) { uint16_t delta = - bmsdata->chips[chip].cell.c_codes[cell] - + bmsdata->chips[chip].fcell.fc_codes[cell] - (uint16_t)bmsdata->min_voltage.val; if (delta > MAX_DELTA_V * 10000) balanceConfig[chip][cell] = true; diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c index 4b82fd5f..116021cd 100644 --- a/Core/Src/stm32f4xx_hal_msp.c +++ b/Core/Src/stm32f4xx_hal_msp.c @@ -20,7 +20,6 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" - /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -68,6 +67,7 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); */ void HAL_MspInit(void) { + /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ @@ -282,6 +282,8 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) /* CAN2 interrupt Init */ HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn); + HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ @@ -340,6 +342,7 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) /* CAN2 interrupt DeInit */ HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn); + HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn); /* USER CODE BEGIN CAN2_MspDeInit 1 */ /* USER CODE END CAN2_MspDeInit 1 */ @@ -379,6 +382,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ + } } @@ -609,6 +613,17 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM2_MspInit 1 */ } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ + + /* USER CODE END TIM5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } else if(htim_base->Instance==TIM8) { /* USER CODE BEGIN TIM8_MspInit 0 */ @@ -703,6 +718,17 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) /* USER CODE END TIM2_MspDeInit 1 */ } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ + + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ + + /* USER CODE END TIM5_MspDeInit 1 */ + } else if(htim_base->Instance==TIM8) { /* USER CODE BEGIN TIM8_MspDeInit 0 */ @@ -771,6 +797,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE BEGIN UART4_MspInit 1 */ /* USER CODE END UART4_MspInit 1 */ + } } @@ -847,6 +874,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ /* USER CODE END USB_OTG_FS_MspInit 1 */ + } } diff --git a/Core/Src/stm32f4xx_hal_timebase_tim.c b/Core/Src/stm32f4xx_hal_timebase_tim.c new file mode 100644 index 00000000..2e90dc2d --- /dev/null +++ b/Core/Src/stm32f4xx_hal_timebase_tim.c @@ -0,0 +1,138 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_timebase_tim.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" +#include "stm32f4xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim3; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM3 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + + HAL_StatusTypeDef status; + + /* Enable TIM3 clock */ + __HAL_RCC_TIM3_CLK_ENABLE(); + +/* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM3 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM3 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM3 */ + htim3.Instance = TIM3; + + /* Initialize TIMx peripheral as follow: + + + Period = [(TIM3CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim3.Init.Period = (1000000U / 1000U) - 1U; + htim3.Init.Prescaler = uwPrescalerValue; + htim3.Init.ClockDivision = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim3); + if (status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim3); + if (status == HAL_OK) + { + /* Enable the TIM3 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM3_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM3_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM3 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM3 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim3, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM3 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM3 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim3, TIM_IT_UPDATE); +} + diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index 5ed2a906..eea515e8 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -20,8 +20,6 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32f4xx_it.h" -#include "FreeRTOS.h" -#include "task.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "can_handler.h" @@ -63,6 +61,8 @@ extern CAN_HandleTypeDef hcan1; extern CAN_HandleTypeDef hcan2; extern DMA_HandleTypeDef hdma_uart4_tx; extern UART_HandleTypeDef huart4; +extern TIM_HandleTypeDef htim3; + /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -158,28 +158,6 @@ void DebugMon_Handler(void) /* USER CODE END DebugMonitor_IRQn 1 */ } -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); -#if (INCLUDE_xTaskGetSchedulerState == 1 ) - if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) - { -#endif /* INCLUDE_xTaskGetSchedulerState */ - xPortSysTickHandler(); -#if (INCLUDE_xTaskGetSchedulerState == 1 ) - } -#endif /* INCLUDE_xTaskGetSchedulerState */ - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - /******************************************************************************/ /* STM32F4xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ @@ -201,20 +179,6 @@ void DMA1_Stream4_IRQHandler(void) /* USER CODE END DMA1_Stream4_IRQn 1 */ } -/** - * @brief This function handles UART4 global interrupt. - */ -void UART4_IRQHandler(void) -{ - /* USER CODE BEGIN UART4_IRQn 0 */ - - /* USER CODE END UART4_IRQn 0 */ - HAL_UART_IRQHandler(&huart4); - /* USER CODE BEGIN UART4_IRQn 1 */ - - /* USER CODE END UART4_IRQn 1 */ -} - /** * @brief This function handles CAN1 RX0 interrupts. */ @@ -229,6 +193,34 @@ void CAN1_RX0_IRQHandler(void) /* USER CODE END CAN1_RX0_IRQn 1 */ } +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + +/** + * @brief This function handles UART4 global interrupt. + */ +void UART4_IRQHandler(void) +{ + /* USER CODE BEGIN UART4_IRQn 0 */ + + /* USER CODE END UART4_IRQn 0 */ + HAL_UART_IRQHandler(&huart4); + /* USER CODE BEGIN UART4_IRQn 1 */ + + /* USER CODE END UART4_IRQn 1 */ +} + /** * @brief This function handles DMA2 stream0 global interrupt. */ @@ -257,6 +249,20 @@ void CAN2_RX0_IRQHandler(void) /* USER CODE END CAN2_RX0_IRQn 1 */ } +/** + * @brief This function handles CAN2 RX1 interrupt. + */ +void CAN2_RX1_IRQHandler(void) +{ + /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ + + /* USER CODE END CAN2_RX1_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ + + /* USER CODE END CAN2_RX1_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 00000000..e33a8492 --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 00000000..246470ee --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Drivers/adbms b/Drivers/adbms index eef63db1..c0e54fe0 160000 --- a/Drivers/adbms +++ b/Drivers/adbms @@ -1 +1 @@ -Subproject commit eef63db194526432e4c004820283badae4034e04 +Subproject commit c0e54fe0f2280b90ea6176444d1e3cdbfbc2164e diff --git a/Makefile b/Makefile index 1cad36b6..91cb92ff 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Nov 08 16:32:06 EST 2024] +# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Thu Jan 23 18:47:54 EST 2025] ########################################################################################################################## # ------------------------------------------------ @@ -41,6 +41,7 @@ Core/Src/analyzer.c \ Core/Src/compute.c \ Core/Src/eepromdirectory.c \ Core/Src/segment.c \ +Core/Src/adi_interaction.c \ Core/Src/stateMachine.c \ Core/Src/can_handler.c \ Core/Src/shep_tasks.c \ @@ -94,7 +95,10 @@ Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ Middlewares/Third_Party/FreeRTOS/Source/timers.c \ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \ Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ -Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \ +Core/Src/sysmem.c \ +Core/Src/syscalls.c \ +Core/Src/stm32f4xx_hal_timebase_tim.c # ASM sources ASM_SOURCES = \ @@ -184,7 +188,7 @@ CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" # LDFLAGS ####################################### # link script -LDSCRIPT = STM32F405RGTx_FLASH.ld +LDSCRIPT = stm32f405rgtx_flash.ld # libraries LIBS = -lc -lm -lnosys diff --git a/shepherd2.ioc b/shepherd2.ioc index 35cfe3e0..028e1f8f 100644 --- a/shepherd2.ioc +++ b/shepherd2.ioc @@ -67,8 +67,9 @@ Dma.UART4_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.UART4_TX.1.PeriphInc=DMA_PINC_DISABLE Dma.UART4_TX.1.Priority=DMA_PRIORITY_LOW Dma.UART4_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode -FREERTOS.IPParameters=Tasks01,configUSE_PREEMPTION,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configTOTAL_HEAP_SIZE -FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL +FREERTOS.FootprintOK=true +FREERTOS.IPParameters=Tasks01,configUSE_PREEMPTION,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configTOTAL_HEAP_SIZE,FootprintOK +FREERTOS.Tasks01=defaultTask,24,256,StartDefaultTask,Default,acc_data,Dynamic,NULL,NULL FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2 FREERTOS.configTOTAL_HEAP_SIZE=30000 FREERTOS.configUSE_MALLOC_FAILED_HOOK=1 @@ -88,9 +89,10 @@ Mcu.IP12=SPI3 Mcu.IP13=SYS Mcu.IP14=TIM1 Mcu.IP15=TIM2 -Mcu.IP16=TIM8 -Mcu.IP17=UART4 -Mcu.IP18=USB_OTG_FS +Mcu.IP16=TIM5 +Mcu.IP17=TIM8 +Mcu.IP18=UART4 +Mcu.IP19=USB_OTG_FS Mcu.IP2=CAN1 Mcu.IP3=CAN2 Mcu.IP4=DMA @@ -99,7 +101,7 @@ Mcu.IP6=I2C1 Mcu.IP7=IWDG Mcu.IP8=NVIC Mcu.IP9=RCC -Mcu.IPNb=19 +Mcu.IPNb=20 Mcu.Name=STM32F405RGTx Mcu.Package=LQFP64 Mcu.Pin0=PC13-ANTI_TAMP @@ -150,20 +152,21 @@ Mcu.Pin49=PB9 Mcu.Pin5=PC0 Mcu.Pin50=VP_FREERTOS_VS_CMSIS_V2 Mcu.Pin51=VP_IWDG_VS_IWDG -Mcu.Pin52=VP_SYS_VS_Systick +Mcu.Pin52=VP_SYS_VS_tim3 Mcu.Pin53=VP_TIM1_VS_ClockSourceINT Mcu.Pin54=VP_TIM2_VS_ClockSourceINT -Mcu.Pin55=VP_TIM8_VS_ClockSourceINT +Mcu.Pin55=VP_TIM5_VS_ClockSourceINT +Mcu.Pin56=VP_TIM8_VS_ClockSourceINT Mcu.Pin6=PC1 Mcu.Pin7=PC2 Mcu.Pin8=PC3 Mcu.Pin9=PA0-WKUP -Mcu.PinsNb=56 +Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F405RGTx -MxCube.Version=6.10.0 -MxDb.Version=DB.6.0.100 +MxCube.Version=6.13.0 +MxDb.Version=DB.6.0.130 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.CAN1_RX0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true\:true NVIC.CAN2_RX0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true @@ -181,7 +184,10 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false NVIC.SavedPendsvIrqHandlerGenerated=true NVIC.SavedSvcallIrqHandlerGenerated=true NVIC.SavedSystickIrqHandlerGenerated=true -NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:false\:true\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true\:false +NVIC.TIM3_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.TimeBase=TIM3_IRQn +NVIC.TimeBaseIP=TIM3 NVIC.UART4_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false PA0-WKUP.Mode=Asynchronous @@ -436,11 +442,11 @@ SPI2.Mode=SPI_MODE_MASTER SPI2.NSS=SPI_NSS_SOFT SPI2.TIMode=SPI_TIMODE_DISABLE SPI2.VirtualType=VM_MASTER -SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2 +SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 SPI3.CLKPhase=SPI_PHASE_1EDGE SPI3.CLKPolarity=SPI_POLARITY_LOW SPI3.CRCCalculation=SPI_CRCCALCULATION_DISABLE -SPI3.CalculateBaudRate=8.0 MBits/s +SPI3.CalculateBaudRate=2.0 MBits/s SPI3.DataSize=SPI_DATASIZE_8BIT SPI3.Direction=SPI_DIRECTION_2LINES SPI3.FirstBit=SPI_FIRSTBIT_MSB @@ -452,6 +458,9 @@ SPI3.VirtualType=VM_MASTER TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM1.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation3 CH3 +TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE +TIM2.IPParameters=Prescaler,AutoReloadPreload +TIM2.Prescaler=16 TIM8.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM8.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 TIM8.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 @@ -475,12 +484,14 @@ VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_SYS_VS_tim3.Mode=TIM3 +VP_SYS_VS_tim3.Signal=SYS_VS_tim3 VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT +VP_TIM5_VS_ClockSourceINT.Mode=Internal +VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT VP_TIM8_VS_ClockSourceINT.Mode=Internal VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT board=custom diff --git a/stm32f405rgtx_flash.ld b/stm32f405rgtx_flash.ld new file mode 100644 index 00000000..4dcf56f0 --- /dev/null +++ b/stm32f405rgtx_flash.ld @@ -0,0 +1,208 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32F405RGTx series +** 1024Kbytes FLASH and 192Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K +CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 64K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _siccmram = LOADADDR(.ccmram); + + /* CCM-RAM section + * + * IMPORTANT NOTE! + * If initialized variables will be placed in this section, + * the startup code needs to be modified to copy the init-values. + */ + .ccmram : + { + . = ALIGN(4); + _sccmram = .; /* create a global symbol at ccmram start */ + *(.ccmram) + *(.ccmram*) + + . = ALIGN(4); + _eccmram = .; /* create a global symbol at ccmram end */ + } >CCMRAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +} + +