fix(vldff): oldvd is reserved for register granularity only when an e…

…xception is triggered

src/isa/riscv64/instr/rvv/vldst_impl.c

@@ -978,11 +978,20 @@ void vldff(Decode *s, int mode, int mmu_mode) {
           IFDEF(CONFIG_RV_SDTRIG, trigger_check(cpu.TM->check_timings.br, cpu.TM, TRIG_OP_LOAD, addr, TRIGGER_NO_VALUE));
 
           isa_vec_misalign_data_addr_check(addr, s->v_width, MEM_TYPE_READ);
-          rtl_lm(s, &vloadBuf[fn], &addr, 0, s->v_width, mmu_mode);
+          if (fofvl == 0) {
+            rtl_lm(s, &vloadBuf[fn], &addr, 0, s->v_width, mmu_mode);
+          } else {
+            rtl_lm(s, &tmp_reg[1], &addr, 0, s->v_width, mmu_mode);
+            set_vreg(vd + fn * emul, idx, tmp_reg[1], eew, 0, 0);
+          }
+
         }
-        for (fn = 0; fn < nf; fn++) {
-          set_vreg(vd + fn * emul, idx, vloadBuf[fn], eew, 0, 0);
+        if (fofvl == 0) {
+          for (fn = 0; fn < nf; fn++) {
+            set_vreg(vd + fn * emul, idx, vloadBuf[fn], eew, 0, 0);
+          }
         }
+
       }
     }