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feat: add DynCloseSC Parameter to statistic close SC before compile
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@Lawrence-ID
Lawrence-ID committed Nov 21, 2024
1 parent d7928d6 commit 26e85bc
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Showing 3 changed files with 106 additions and 49 deletions.
2 changes: 2 additions & 0 deletions src/main/scala/xiangshan/Parameters.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ case class XSCoreParameters
EnableLB: Boolean = false,
EnableLoop: Boolean = true,
EnableSC: Boolean = true,
DynCloseSC: Boolean = false,
EnbaleTlbDebug: Boolean = false,
EnableClockGate: Boolean = true,
EnableJal: Boolean = false,
Expand Down Expand Up @@ -641,6 +642,7 @@ trait HasXSParameter {
def EnableLB = coreParams.EnableLB
def EnableLoop = coreParams.EnableLoop
def EnableSC = coreParams.EnableSC
def DynCloseSC = coreParams.DynCloseSC
def EnbaleTlbDebug = coreParams.EnbaleTlbDebug
def HistoryLength = coreParams.HistoryLength
def EnableGHistDiff = coreParams.EnableGHistDiff
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35 changes: 21 additions & 14 deletions src/main/scala/xiangshan/frontend/BPU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -107,23 +107,30 @@ trait BPUUtils extends HasXSParameter {
)
}

def signedSatUpdate(old: SInt, len: Int, taken: Bool, deltaType: UInt): SInt = {
val delta = MuxLookup(deltaType, 0.S)(
Seq(
0.U -> 0.S,
1.U -> 1.S, // SC opened, SC agree and correct, can be closed
2.U -> 1.S, // SC opened, SC agree but wrong, should be closed more
3.U -> 5.S, // SC opened, SC disagree and wrong, should definitely be closed
4.U -> 50.S, // SC opened, SC disagree but correct, should stay open
5.U -> 1.S, // SC closed, TAGE pred correct, SC can be closed
6.U -> 30.S // SC closed, TAGE pred wrong, SC should be opened
)
)

def signedSatUpdate(umask: Vec[Bool], old: SInt, len: Int, deltaType: Vec[UInt]): SInt = {
val maxValue = ((1 << (len - 1)) - 1).S
val minValue = (-(1 << (len - 1))).S
val finalDelta = deltaType.zip(umask).map { case (dt, mask) =>
Mux(
mask,
MuxLookup(dt, 0.S)(
Seq(
0.U -> 0.S,
1.U -> 1.S, // SC opened, SC agree and correct, can be closed
2.U -> 1.S, // SC opened, SC agree but wrong, should be closed more
3.U -> 5.S, // SC opened, SC disagree and wrong, should definitely be closed
4.U -> -50.S, // SC opened, SC disagree but correct, should stay open
5.U -> 1.S, // SC closed, TAGE pred correct, SC can be closed
6.U -> -30.S // SC closed, TAGE pred wrong, SC should be opened
)
),
0.S
)
}.reduce(_ +& _)

val updated = old +& finalDelta

val updated = Mux(taken, old +& delta, old -& delta)
// printf(p"umask: ${umask}, old: ${old}, deltaType: ${deltaType}, finalDelta: ${finalDelta} \n")

MuxCase(
updated,
Expand Down
118 changes: 83 additions & 35 deletions src/main/scala/xiangshan/frontend/SC.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -275,7 +275,8 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
case (nRows, ctrBits, histLen) => {
val t = Module(new SCTable(nRows / TageBanks, ctrBits, histLen))
val req = t.io.req
req.valid := io.s0_fire(3) && !s0_sc_closed
req.valid := (if (DynCloseSC) { io.s0_fire(3) && !s0_sc_closed }
else { io.s0_fire(3) })
req.bits.pc := s0_pc_dup(3)
req.bits.folded_hist := io.in.bits.folded_hist(3)
req.bits.ghist := DontCare
Expand Down Expand Up @@ -334,31 +335,59 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
ParallelSingedExpandingAdd(s1_scResps map (r => getCentered(r.ctrs(w)(i)))) // TODO: rewrite with wallace tree
}
)
val s2_scTableSums = RegEnable(s1_scTableSums, io.s1_fire(3) && !s1_sc_closed)
val s2_tagePrvdCtrCentered = getPvdrCentered(RegEnable(s1_providerResps(w).ctr, io.s1_fire(3) && !s1_sc_closed))
val s2_totalSums = s2_scTableSums.map(_ +& s2_tagePrvdCtrCentered)

val s2_scTableSums = RegEnable(
s1_scTableSums,
if (DynCloseSC) { io.s1_fire(3) && !s1_sc_closed }
else { io.s1_fire(3) }
)
val s2_tagePrvdCtrCentered = getPvdrCentered(RegEnable(
s1_providerResps(w).ctr,
if (DynCloseSC) { io.s1_fire(3) && !s1_sc_closed }
else { io.s1_fire(3) }
))

val s2_totalSums = s2_scTableSums.map(_ +& s2_tagePrvdCtrCentered)
val s2_sumAboveThresholds =
VecInit((0 to 1).map(i => aboveThreshold(s2_scTableSums(i), s2_tagePrvdCtrCentered, useThresholds(w))))
val s2_scPreds = VecInit(s2_totalSums.map(_ >= 0.S))

val s2_scResps = VecInit(RegEnable(s1_scResps, io.s1_fire(3) && !s1_sc_closed).map(_.ctrs(w)))
val s2_scResps = VecInit(RegEnable(
s1_scResps,
if (DynCloseSC) { io.s1_fire(3) && !s1_sc_closed }
else { io.s1_fire(3) }
).map(_.ctrs(w)))

val s2_scCtrs = VecInit(s2_scResps.map(_(s2_tageTakens_dup(3)(w).asUInt)))
val s2_chooseBit = s2_tageTakens_dup(3)(w)

val s2_pred =
Mux(s2_provideds(w) && s2_sumAboveThresholds(s2_chooseBit), s2_scPreds(s2_chooseBit), s2_tageTakens_dup(3)(w))

val s3_disagree = RegEnable(s2_disagree, io.s2_fire(3) && !s2_sc_closed)
val s3_disagree = RegEnable(
s2_disagree,
if (DynCloseSC) { io.s2_fire(3) && !s2_sc_closed }
else { io.s2_fire(3) }
)
io.out.last_stage_spec_info.sc_disagree.map(_ := s3_disagree)

scMeta.scPreds(w) := RegEnable(s2_scPreds(s2_chooseBit), io.s2_fire(3) && !s2_sc_closed)
scMeta.ctrs(w) := RegEnable(s2_scCtrs, io.s2_fire(3) && !s2_sc_closed)
scMeta.scPreds(w) := RegEnable(
s2_scPreds(s2_chooseBit),
if (DynCloseSC) { io.s2_fire(3) && !s2_sc_closed }
else { io.s2_fire(3) }
)
scMeta.ctrs(w) := RegEnable(
s2_scCtrs,
if (DynCloseSC) { io.s2_fire(3) && !s2_sc_closed }
else { io.s2_fire(3) }
)

// Combination Logic, Wire type
when(s2_provideds(w)) {
s2_sc_used(w) := !s2_sc_closed
s2_unconf(w) := !s2_sumAboveThresholds(s2_chooseBit)
s2_conf(w) := s2_sumAboveThresholds(s2_chooseBit)
s2_sc_used(w) := (if (DynCloseSC) { !s2_sc_closed }
else { true.B })
s2_unconf(w) := !s2_sumAboveThresholds(s2_chooseBit)
s2_conf(w) := s2_sumAboveThresholds(s2_chooseBit)
// Use prediction from Statistical Corrector
XSDebug(p"---------tage_bank_${w} provided so that sc used---------\n")
when(s2_sumAboveThresholds(s2_chooseBit)) {
Expand All @@ -372,7 +401,14 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
}
}

val s3_pred_dup = io.s2_fire.map(f => RegEnable(s2_pred, f && !s2_sc_closed))
val s3_pred_dup = io.s2_fire.map(f =>
RegEnable(
s2_pred,
if (DynCloseSC) { f && !s2_sc_closed }
else { f }
)
)

val sc_enable_dup = dup(RegNext(io.ctrl.sc_enable))
for (
sc_enable & fp & s3_pred <-
Expand Down Expand Up @@ -407,28 +443,6 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
sc_corr_tage_misp(w) := scPred === taken && tagePred =/= taken && update_conf(w)
sc_misp_tage_corr(w) := scPred =/= taken && tagePred === taken && update_conf(w)

val increase = WireInit(false.B)
val deltaType = WireInit(0.U(3.W))
when(scClosed) {
increase := tagePred === taken
deltaType := Mux(tagePred === taken, 5.U, 6.U)
}.otherwise {
when(update_conf(w)) {
increase := true.B
deltaType := Mux(
tagePred === scPred,
// 1: sc agree and correct; 2: sc agree but wrong
Mux(tagePred === taken, 1.U, 2.U),
// 3: sc disagree and wrong; 4: sc disagree but correct
Mux(tagePred === taken, 3.U, 4.U)
)
}.otherwise {
increase := false.B
deltaType := 0.U
}
}
scCloseConfCounter := signedSatUpdate(scCloseConfCounter, 10, increase, deltaType)

val thres = useThresholds(w)
when(!scClosed && scPred =/= tagePred && totalSumAbs >= thres - 4.U && totalSumAbs <= thres - 2.U) {
val newThres = scThresholds(w).update(scPred =/= taken)
Expand Down Expand Up @@ -458,7 +472,8 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
val realWens = scUpdateMask.transpose.map(v => v.reduce(_ | _))
for (b <- 0 until TageBanks) {
for (i <- 0 until SCNTables) {
val realWen = realWens(i) && !s0_sc_closed
val realWen = if (DynCloseSC) { realWens(i) && !s0_sc_closed }
else { realWens(i) }
scTables(i).io.update.mask(b) := RegNext(scUpdateMask(b)(i))
scTables(i).io.update.tagePreds(b) := RegEnable(scUpdateTagePreds(b), realWen)
scTables(i).io.update.takens(b) := RegEnable(scUpdateTakens(b), realWen)
Expand All @@ -468,6 +483,37 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
}
}

if (DynCloseSC) {
val satUpdateMask = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
val deltaType = WireInit(0.U.asTypeOf(Vec(TageBanks, UInt(3.W))))
for (w <- 0 until TageBanks) {
val updateTageMeta = updateMeta
val scClosed = updateSCMeta.scClosed
when(updateValids(w) && updateTageMeta.providers(w).valid) {
satUpdateMask(w) := true.B
when(scClosed) {
deltaType(w) := Mux(updateTageMeta.takens(w) === update.br_taken_mask(w), 5.U, 6.U)
}.otherwise {
when(update_conf(w)) {
deltaType(w) := Mux(
update_agree(w),
// 1: sc agree and correct; 2: sc agree but wrong
Mux(updateTageMeta.takens(w) === update.br_taken_mask(w), 1.U, 2.U),
// 3: sc disagree and wrong; 4: sc disagree but correct
Mux(updateTageMeta.takens(w) === update.br_taken_mask(w), 3.U, 4.U)
)
}.otherwise {
deltaType(w) := 0.U
}
}
}.otherwise {
satUpdateMask(w) := false.B
deltaType(w) := 0.U
}
}
scCloseConfCounter := signedSatUpdate(satUpdateMask, scCloseConfCounter, 10, deltaType)
}

tage_perf("sc_conf", PopCount(s2_conf), PopCount(update_conf))
tage_perf("sc_unconf", PopCount(s2_unconf), PopCount(update_unconf))
tage_perf("sc_agree", PopCount(s2_agree), PopCount(update_agree))
Expand All @@ -478,6 +524,8 @@ trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
XSPerfAccumulate("sc_mispred_but_tage_correct", PopCount(sc_misp_tage_corr))
XSPerfAccumulate("sc_correct_and_tage_wrong", PopCount(sc_corr_tage_misp))

XSPerfAccumulate("sc_close_tick", PopCount(scCloseConfCounter >= 0.S))

}

override def getFoldedHistoryInfo = Some(tage_fh_info ++ sc_fh_info)
Expand Down

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