diff --git a/coupledL2 b/coupledL2
index d7df1ebefb..67e70277fb 160000
--- a/coupledL2
+++ b/coupledL2
@@ -1 +1 @@
-Subproject commit d7df1ebefb1fa1c7b880d105724285b77a3217bc
+Subproject commit 67e70277fb8960b85d7788c8e24c4849aeb10523
diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala
index 168e53aa71..c377b91790 100644
--- a/src/main/scala/xiangshan/L2Top.scala
+++ b/src/main/scala/xiangshan/L2Top.scala
@@ -173,7 +173,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
 
     val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))
 
-    beu.module.io.errors <> io.beu_errors
+    beu.module.io.errors.icache := io.beu_errors.icache
+    beu.module.io.errors.dcache := io.beu_errors.dcache
     resetDelayN.io.in := io.reset_vector.fromTile
     io.reset_vector.toCore := resetDelayN.io.out
     io.hartId.toCore := io.hartId.fromTile
@@ -234,6 +235,9 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
           io.chi.get <> l2.io_chi
         case l2cache: TL2TLCoupledL2 =>
       }
+
+      beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
+      beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
     } else {
       io.l2_hint := 0.U.asTypeOf(io.l2_hint)
       io.debugTopDown <> DontCare