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Decode related issue #3919

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4 tasks done
vincen-dev opened this issue Nov 23, 2024 · 2 comments · May be fixed by #3922
Open
4 tasks done

Decode related issue #3919

vincen-dev opened this issue Nov 23, 2024 · 2 comments · May be fixed by #3922
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bug report Bugs to be confirmed

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@vincen-dev
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Before start

  • I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
  • I have read the XiangShan Documents. 我已经阅读过香山文档。
  • I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
  • I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the bug

When executing .word 0x6781 instruction to Xiangshan, riscv64-spike-so has an exception, but Xiangshan does not. I think this is a decoding related problem .

Expected behavior

When testing with riscv64-spike-so
image
image

When I debug with spike, the .word 0x6781 instruction corresponds to c.lui a5, 0x0
image

In addition, I don't know if nemu has such a problem, because when I use nemu as a reference model, the following log message appears:
image

To Reproduce

.section .text
.globl _start
_start:
   
     li     t0, 0x8000000a0014a00     
     csrw    mstatus, t0
     .word 0x6781

Environment

  • XiangShan branch:
  • XiangShan commit id: commit f12520c (HEAD -> master, origin/master, origin/HEAD)
  • NEMU commit id: commit: ff37164781e23336ea7fc70f7bf7ea006ee9fbbc
  • SPIKE commit id:
  • ready-to-run:commit 3575e659bf3a1ed0e0de74bcef848b9be666725b (HEAD, origin/master, origin/HEAD)

Additional context

No response
@vincen-dev vincen-dev added the bug report Bugs to be confirmed label Nov 23, 2024
@lewislzh
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@vincen-dev
The critical-error currently indicates more than two traps occurring within the same privilege level. At present, XiangShan/NEMU/Spike considers this error a software issue rather than a hardware issue (i.e., it is normal for the hardware to throw a critical-error). This requires verifying the software implementation. As a result, the system will directly trigger a good trap (indicating that the hardware behavior meets expectations) and print a critical-error warning. We recommend checking the test cases for common issues, such as not setting mtvec, when this error occurs.

@NewPaulWalker
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Thank you for your issue. This is actually a bug caused by a mismatch between XiangShan and Spike. The provided Spike does not enable the Zimop and Zcmop extensions, while XiangShan supports them. As a result, Spike raised an exception, whereas XiangShan did not.

Additionally, I recommend using .half instead of .word when inserting a C-extension instruction. If you use .word but only provide 2 bytes of data, the remaining 2 bytes will be automatically set to 0. This would result in an invalid instruction, which is likely to interfere with our judgment.

@NewPaulWalker NewPaulWalker linked a pull request Nov 25, 2024 that will close this issue
submodule(ready-to-run): bump spike ref in ready-to-run #3922
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submodule(ready-to-run): bump spike ref in ready-to-run NewPaulWalker/XiangShan
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@lewislzh @NewPaulWalker @vincen-dev