diff --git a/coupledL2 b/coupledL2 index d66cd85aca..28fe702e8c 160000 --- a/coupledL2 +++ b/coupledL2 @@ -1 +1 @@ -Subproject commit d66cd85aca7164d35d409c230e2f48b857067687 +Subproject commit 28fe702e8c3c2ff4447230c1082731c05b4c4e60 diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala index 4fd63c70f1..1dce2c2fc7 100644 --- a/src/main/scala/top/Configs.scala +++ b/src/main/scala/top/Configs.scala @@ -296,6 +296,10 @@ class WithNKBL2 )), reqField = Seq(utility.ReqSourceField()), echoField = Seq(huancun.DirtyField()), + tagECC = Some("secded"), + dataECC = Some("secded"), + enableTagECC = true, + enableDataECC = true, prefetch = Seq(BOPParameters()) ++ (if (tp) Seq(TPParameters()) else Nil) ++ (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), diff --git a/src/main/scala/xiangshan/L2Top.scala b/src/main/scala/xiangshan/L2Top.scala index 6b037aaacf..a93e98e32e 100644 --- a/src/main/scala/xiangshan/L2Top.scala +++ b/src/main/scala/xiangshan/L2Top.scala @@ -177,7 +177,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) - beu.module.io.errors <> io.beu_errors + beu.module.io.errors.icache := io.beu_errors.icache + beu.module.io.errors.dcache := io.beu_errors.dcache resetDelayN.io.in := io.reset_vector.fromTile io.reset_vector.toCore := resetDelayN.io.out io.hartId.toCore := io.hartId.fromTile @@ -240,6 +241,9 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule io.chi.get <> l2.io_chi case l2cache: TL2TLCoupledL2 => } + + beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid + beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address } else { io.l2_hint := 0.U.asTypeOf(io.l2_hint) io.debugTopDown <> DontCare @@ -249,6 +253,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule io.l2_tlb_req.req_kill := DontCare io.l2_tlb_req.resp.ready := true.B io.perfEvents := DontCare + + beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2) } }