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feat(ECC): add ECC for coupledL2 and bump coupledL2 #3808

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feat(ECC): add ECC for coupledL2 and bump coupledL2 #3808

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70091d3
feat(ECC): add ECC for coupledL2 and bump coupledL2
Ma-YX Oct 29, 2024
1f78440
submodule(coupledL2): bump coupledL2
Ma-YX Nov 13, 2024
836d1a8
submodule(coupledL2): bump coupledL2
Ma-YX Nov 20, 2024
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2 changes: 1 addition & 1 deletion coupledL2
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Submodule coupledL2 updated 18 files
+1 −0 src/main/scala/coupledL2/BaseSlice.scala
+6 −0 src/main/scala/coupledL2/Common.scala
+30 −0 src/main/scala/coupledL2/CoupledL2.scala
+60 −5 src/main/scala/coupledL2/DataStorage.scala
+54 −16 src/main/scala/coupledL2/Directory.scala
+9 −1 src/main/scala/coupledL2/L2Param.scala
+2 −0 src/main/scala/coupledL2/SinkA.scala
+2 −0 src/main/scala/coupledL2/SinkC.scala
+41 −5 src/main/scala/coupledL2/tl2chi/MainPipe.scala
+5 −0 src/main/scala/coupledL2/tl2chi/RXDAT.scala
+3 −0 src/main/scala/coupledL2/tl2chi/Slice.scala
+3 −0 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+5 −1 src/main/scala/coupledL2/tl2chi/chi/Message.scala
+10 −0 src/main/scala/coupledL2/tl2tl/MSHR.scala
+41 −4 src/main/scala/coupledL2/tl2tl/MainPipe.scala
+1 −0 src/main/scala/coupledL2/tl2tl/RefillUnit.scala
+3 −0 src/main/scala/coupledL2/tl2tl/Slice.scala
+10 −2 src/test/scala/TestTop.scala
4 changes: 4 additions & 0 deletions src/main/scala/top/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -296,6 +296,10 @@ class WithNKBL2
)),
reqField = Seq(utility.ReqSourceField()),
echoField = Seq(huancun.DirtyField()),
tagECC = Some("secded"),
dataECC = Some("secded"),
enableTagECC = true,
enableDataECC = true,
prefetch = Seq(BOPParameters()) ++
(if (tp) Seq(TPParameters()) else Nil) ++
(if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil),
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8 changes: 7 additions & 1 deletion src/main/scala/xiangshan/L2Top.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule

val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5))

beu.module.io.errors <> io.beu_errors
beu.module.io.errors.icache := io.beu_errors.icache
beu.module.io.errors.dcache := io.beu_errors.dcache
resetDelayN.io.in := io.reset_vector.fromTile
io.reset_vector.toCore := resetDelayN.io.out
io.hartId.toCore := io.hartId.fromTile
Expand Down Expand Up @@ -240,6 +241,9 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
io.chi.get <> l2.io_chi
case l2cache: TL2TLCoupledL2 =>
}

beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid
beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
} else {
io.l2_hint := 0.U.asTypeOf(io.l2_hint)
io.debugTopDown <> DontCare
Expand All @@ -249,6 +253,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
io.l2_tlb_req.req_kill := DontCare
io.l2_tlb_req.resp.ready := true.B
io.perfEvents := DontCare

beu.module.io.errors.l2 := 0.U.asTypeOf(beu.module.io.errors.l2)
}
}

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