From 6ca39e31f42c10d0b57f29f9fd65ff8f84527a27 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 7 Dec 2023 07:12:24 -0800 Subject: [PATCH 1/3] NuttX with h7 adc clock Backports --- platforms/nuttx/NuttX/nuttx | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/nuttx/NuttX/nuttx b/platforms/nuttx/NuttX/nuttx index 6fdb755a5d77..693b9e782535 160000 --- a/platforms/nuttx/NuttX/nuttx +++ b/platforms/nuttx/NuttX/nuttx @@ -1 +1 @@ -Subproject commit 6fdb755a5d776de3017aa874a5e204dd1903054e +Subproject commit 693b9e782535f12e6a4ab657c7a0c3bd92b45fb1 From 2e70719046619269fb9f1839c1ade4efc4c02ccb Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 5 Dec 2023 09:19:54 -0800 Subject: [PATCH 2/3] stm32h7:ADC STM32_RCC_D3CCIPR_ADCSEL->STM32_RCC_D3CCIPR_ADCSRC --- boards/ark/fmu-v6x/nuttx-config/include/board.h | 2 +- boards/cuav/nora/nuttx-config/include/board.h | 2 +- boards/cuav/x7pro/nuttx-config/include/board.h | 2 +- boards/cubepilot/cubeorange/nuttx-config/include/board.h | 2 +- boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h | 2 +- boards/holybro/durandal-v1/nuttx-config/include/board.h | 2 +- boards/holybro/kakuteh7/nuttx-config/include/board.h | 2 +- boards/holybro/kakuteh7mini/nuttx-config/include/board.h | 2 +- boards/holybro/kakuteh7v2/nuttx-config/include/board.h | 2 +- boards/matek/h743-mini/nuttx-config/include/board.h | 2 +- boards/matek/h743-slim/nuttx-config/include/board.h | 2 +- boards/matek/h743/nuttx-config/include/board.h | 2 +- boards/modalai/fc-v2/nuttx-config/include/board.h | 2 +- boards/mro/ctrl-zero-classic/nuttx-config/include/board.h | 2 +- boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h | 2 +- boards/mro/ctrl-zero-h7/nuttx-config/include/board.h | 2 +- boards/mro/pixracerpro/nuttx-config/include/board.h | 2 +- boards/px4/fmu-v6c/nuttx-config/include/board.h | 2 +- boards/px4/fmu-v6u/nuttx-config/include/board.h | 2 +- boards/px4/fmu-v6x/nuttx-config/include/board.h | 2 +- boards/siyi/n7/nuttx-config/include/board.h | 2 +- boards/spracing/h7extreme/nuttx-config/include/board.h | 2 +- boards/spracing/h7extreme/src/rcc.c | 4 ++-- 23 files changed, 24 insertions(+), 24 deletions(-) diff --git a/boards/ark/fmu-v6x/nuttx-config/include/board.h b/boards/ark/fmu-v6x/nuttx-config/include/board.h index c3aa8d36850c..fa82671a826f 100644 --- a/boards/ark/fmu-v6x/nuttx-config/include/board.h +++ b/boards/ark/fmu-v6x/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/cuav/nora/nuttx-config/include/board.h b/boards/cuav/nora/nuttx-config/include/board.h index ad4b16fbd518..9aaf12fcdaf4 100644 --- a/boards/cuav/nora/nuttx-config/include/board.h +++ b/boards/cuav/nora/nuttx-config/include/board.h @@ -192,7 +192,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/cuav/x7pro/nuttx-config/include/board.h b/boards/cuav/x7pro/nuttx-config/include/board.h index ad4b16fbd518..9aaf12fcdaf4 100644 --- a/boards/cuav/x7pro/nuttx-config/include/board.h +++ b/boards/cuav/x7pro/nuttx-config/include/board.h @@ -192,7 +192,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/cubepilot/cubeorange/nuttx-config/include/board.h b/boards/cubepilot/cubeorange/nuttx-config/include/board.h index 3a4abd0235e8..5827b1bc81d1 100644 --- a/boards/cubepilot/cubeorange/nuttx-config/include/board.h +++ b/boards/cubepilot/cubeorange/nuttx-config/include/board.h @@ -192,7 +192,7 @@ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ /* FLASH wait states */ #define BOARD_FLASH_WAITSTATES 2 diff --git a/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h b/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h index 00a886d08601..d650c6169118 100644 --- a/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h +++ b/boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h @@ -193,7 +193,7 @@ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ /* FLASH wait states */ #define BOARD_FLASH_WAITSTATES 2 diff --git a/boards/holybro/durandal-v1/nuttx-config/include/board.h b/boards/holybro/durandal-v1/nuttx-config/include/board.h index 2a475b7b49aa..e1f43bf7b9cd 100644 --- a/boards/holybro/durandal-v1/nuttx-config/include/board.h +++ b/boards/holybro/durandal-v1/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/holybro/kakuteh7/nuttx-config/include/board.h b/boards/holybro/kakuteh7/nuttx-config/include/board.h index 83245ff925a3..4d3ed5eb4766 100644 --- a/boards/holybro/kakuteh7/nuttx-config/include/board.h +++ b/boards/holybro/kakuteh7/nuttx-config/include/board.h @@ -245,7 +245,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/holybro/kakuteh7mini/nuttx-config/include/board.h b/boards/holybro/kakuteh7mini/nuttx-config/include/board.h index 83245ff925a3..4d3ed5eb4766 100644 --- a/boards/holybro/kakuteh7mini/nuttx-config/include/board.h +++ b/boards/holybro/kakuteh7mini/nuttx-config/include/board.h @@ -245,7 +245,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/holybro/kakuteh7v2/nuttx-config/include/board.h b/boards/holybro/kakuteh7v2/nuttx-config/include/board.h index 83245ff925a3..4d3ed5eb4766 100644 --- a/boards/holybro/kakuteh7v2/nuttx-config/include/board.h +++ b/boards/holybro/kakuteh7v2/nuttx-config/include/board.h @@ -245,7 +245,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/matek/h743-mini/nuttx-config/include/board.h b/boards/matek/h743-mini/nuttx-config/include/board.h index 4bf2b6e45e0f..f8afe3e6b871 100644 --- a/boards/matek/h743-mini/nuttx-config/include/board.h +++ b/boards/matek/h743-mini/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 clock source */ diff --git a/boards/matek/h743-slim/nuttx-config/include/board.h b/boards/matek/h743-slim/nuttx-config/include/board.h index 4bf2b6e45e0f..f8afe3e6b871 100644 --- a/boards/matek/h743-slim/nuttx-config/include/board.h +++ b/boards/matek/h743-slim/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 clock source */ diff --git a/boards/matek/h743/nuttx-config/include/board.h b/boards/matek/h743/nuttx-config/include/board.h index 4bf2b6e45e0f..f8afe3e6b871 100644 --- a/boards/matek/h743/nuttx-config/include/board.h +++ b/boards/matek/h743/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 clock source */ diff --git a/boards/modalai/fc-v2/nuttx-config/include/board.h b/boards/modalai/fc-v2/nuttx-config/include/board.h index 34a8d2c2af74..b196e7a68c72 100644 --- a/boards/modalai/fc-v2/nuttx-config/include/board.h +++ b/boards/modalai/fc-v2/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h b/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h index 9b1ae6342d33..d5ffa2c5848e 100644 --- a/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-classic/nuttx-config/include/board.h @@ -192,7 +192,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h index 9b1ae6342d33..d5ffa2c5848e 100644 --- a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h @@ -192,7 +192,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h index 78a0048760b6..cdbd3dd3e629 100644 --- a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h @@ -191,7 +191,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/mro/pixracerpro/nuttx-config/include/board.h b/boards/mro/pixracerpro/nuttx-config/include/board.h index 2377d529f46b..5edda931dc10 100644 --- a/boards/mro/pixracerpro/nuttx-config/include/board.h +++ b/boards/mro/pixracerpro/nuttx-config/include/board.h @@ -191,7 +191,7 @@ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/px4/fmu-v6c/nuttx-config/include/board.h b/boards/px4/fmu-v6c/nuttx-config/include/board.h index 8042d466a7bb..1951031cb825 100644 --- a/boards/px4/fmu-v6c/nuttx-config/include/board.h +++ b/boards/px4/fmu-v6c/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/px4/fmu-v6u/nuttx-config/include/board.h b/boards/px4/fmu-v6u/nuttx-config/include/board.h index a82a7bf098a8..826c5df337b4 100644 --- a/boards/px4/fmu-v6u/nuttx-config/include/board.h +++ b/boards/px4/fmu-v6u/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* CAN FD clock source */ #define STM32_FDCANCLK STM32_HSE_FREQUENCY diff --git a/boards/px4/fmu-v6x/nuttx-config/include/board.h b/boards/px4/fmu-v6x/nuttx-config/include/board.h index eb3004183b02..5057ed713ecb 100644 --- a/boards/px4/fmu-v6x/nuttx-config/include/board.h +++ b/boards/px4/fmu-v6x/nuttx-config/include/board.h @@ -248,7 +248,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* FDCAN 1 2 clock source */ diff --git a/boards/siyi/n7/nuttx-config/include/board.h b/boards/siyi/n7/nuttx-config/include/board.h index d6b690c29325..1df145ed26db 100644 --- a/boards/siyi/n7/nuttx-config/include/board.h +++ b/boards/siyi/n7/nuttx-config/include/board.h @@ -222,7 +222,7 @@ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ diff --git a/boards/spracing/h7extreme/nuttx-config/include/board.h b/boards/spracing/h7extreme/nuttx-config/include/board.h index 91edb4e650c3..117edb76a749 100644 --- a/boards/spracing/h7extreme/nuttx-config/include/board.h +++ b/boards/spracing/h7extreme/nuttx-config/include/board.h @@ -241,7 +241,7 @@ /* ADC 1 2 3 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* QSPI clock source */ #define STM32_RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_PLL2 diff --git a/boards/spracing/h7extreme/src/rcc.c b/boards/spracing/h7extreme/src/rcc.c index 9fc05848163a..cd4299b880ea 100644 --- a/boards/spracing/h7extreme/src/rcc.c +++ b/boards/spracing/h7extreme/src/rcc.c @@ -503,10 +503,10 @@ __ramfunc__ void stm32_board_clockconfig(void) /* Configure ADC source clock */ -#if defined(STM32_RCC_D3CCIPR_ADCSEL) +#if defined(STM32_RCC_D3CCIPR_ADCSRC) regval = getreg32(STM32_RCC_D3CCIPR); regval &= ~RCC_D3CCIPR_ADCSEL_MASK; - regval |= STM32_RCC_D3CCIPR_ADCSEL; + regval |= STM32_RCC_D3CCIPR_ADCSRC; putreg32(regval, STM32_RCC_D3CCIPR); #endif From 70e90c2d0474c1c09db9b023249fb2081c32a558 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 7 Dec 2023 07:08:26 -0800 Subject: [PATCH 3/3] stm32h7:adc Dynamically set clock prescaler & BOOST The ADC peripheral can only support up to 50MHz on rev V silicon and 36MHz on Y silicon. The existing driver always used no prescaler and kept boost setting at 0. --- .../nuttx/src/px4/stm/stm32h7/adc/adc.cpp | 159 ++++++++++++++---- 1 file changed, 130 insertions(+), 29 deletions(-) diff --git a/platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp b/platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp index 80f98c564fd1..2a25cf6eeed5 100644 --- a/platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp +++ b/platforms/nuttx/src/px4/stm/stm32h7/adc/adc.cpp @@ -37,6 +37,7 @@ #include #include +#include "stm32_dbgmcu.h" #include #include @@ -96,35 +97,123 @@ #define ADC_MAX_FADC 36000000 -#if STM32_PLL2P_FREQUENCY <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_NOT_DIV -#elif STM32_PLL2P_FREQUENCY/2 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV2 -#elif STM32_PLL2P_FREQUENCY/4 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV4 -#elif STM32_PLL2P_FREQUENCY/6 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV6 -#elif STM32_PLL2P_FREQUENCY/8 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV8 -#elif STM32_PLL2P_FREQUENCY/10 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV10 -#elif STM32_PLL2P_FREQUENCY/12 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV12 -#elif STM32_PLL2P_FREQUENCY/16 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV16 -#elif STM32_PLL2P_FREQUENCY/32 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV32 -#elif STM32_PLL2P_FREQUENCY/64 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV64 -#elif STM32_PLL2P_FREQUENCY/128 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV128 -#elif STM32_PLL2P_FREQUENCY/256 <= ADC_MAX_FADC -# define ADC_CCR_PRESC_DIV ADC_CCR_PRESC_DIV256 -#else -# error "ADC STM32_PLL2P_FREQUENCY too high - no divisor found " +#define ADC3_INTERNAL_TEMP_SENSOR_CHANNEL 18 //define to map the internal temperature channel. + + +/**************************************************************************** + * Name: adc_getclocks + ****************************************************************************/ + +static int adc_getclocks(uint32_t *prescaler, uint32_t *boost) +{ + uint32_t max_clock = ADC_MAX_FADC; + uint32_t src_clock = STM32_PLL2P_FREQUENCY; + uint32_t adc_clock; + int rv = OK; + +#if STM32_RCC_D3CCIPR_ADCSRC == RCC_D3CCIPR_ADCSEL_PLL3 + src_clock = STM32_PLL3R_FREQUENCY; +#elif STM32_RCC_D3CCIPR_ADCSRC == RCC_D3CCIPR_ADCSEL_PER +# error ADCSEL_PER not supported #endif -#define ADC3_INTERNAL_TEMP_SENSOR_CHANNEL 18 //define to map the internal temperature channel. + /* The maximum clock is different for rev Y devices and rev V devices. + * rev V can support an ADC clock of up to 50MHz. rev Y only supports + * up to 36MHz. + */ + + if ((getreg32(STM32_DEBUGMCU_BASE) & DBGMCU_IDCODE_REVID_MASK) == + STM32_IDCODE_REVID_V) { + /* The max fadc is 50MHz, but there is an always-present /2 divider + * after the configurable prescaler. Therefore, the max clock out of + * the prescaler block is 2*50=100MHz + */ + + max_clock = 100000000; + } + + if (src_clock <= max_clock) { + *prescaler = ADC_CCR_PRESC_NOT_DIV; + adc_clock = src_clock; + + } else if (src_clock / 2 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV2; + adc_clock = src_clock / 2; + + } else if (src_clock / 4 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV4; + adc_clock = src_clock / 4; + + } else if (src_clock / 6 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV6; + adc_clock = src_clock / 6; + + } else if (src_clock / 8 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV8; + adc_clock = src_clock / 8; + + } else if (src_clock / 10 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV10; + adc_clock = src_clock / 10; + + } else if (src_clock / 12 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV12; + adc_clock = src_clock / 12; + + } else if (src_clock / 16 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV16; + adc_clock = src_clock / 16; + + } else if (src_clock / 32 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV32; + adc_clock = src_clock / 32; + + } else if (src_clock / 64 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV64; + adc_clock = src_clock / 64; + + } else if (src_clock / 128 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV128; + adc_clock = src_clock / 128; + + } else if (src_clock / 256 <= max_clock) { + *prescaler = ADC_CCR_PRESC_DIV256; + adc_clock = src_clock / 256; + + } else { + rv = -1; + } + + if ((getreg32(STM32_DEBUGMCU_BASE) & DBGMCU_IDCODE_REVID_MASK) == + STM32_IDCODE_REVID_V) { + if (adc_clock >= 25000000) { + *boost = ADC_CR_BOOST_50_MHZ; + + } else if (adc_clock >= 12500000) { + *boost = ADC_CR_BOOST_25_MHZ; + + } else if (adc_clock >= 6250000) { + *boost = ADC_CR_BOOST_12p5_MHZ; + + } else { + *boost = ADC_CR_BOOST_6p25_MHZ; + } + + } else { + if (adc_clock >= 20000000) { + *boost = ADC_CR_BOOST; + + } else { + *boost = 0; + } + } + + return rv; +} + +/**************************************************************************** + * Name: px4_arch_adc_init + ****************************************************************************/ int px4_arch_adc_init(uint32_t base_address) { @@ -158,9 +247,21 @@ int px4_arch_adc_init(uint32_t base_address) *free = base_address; + /* Get cloking for this version of Siicon */ + + uint32_t boost = ADC_CR_BOOST; + uint32_t prescaler = ADC_CCR_PRESC_DIV256; + + if (adc_getclocks(&prescaler, &boost) != OK) { + + /* ERROR: source clock too high */ + + PANIC(); + } + /* do calibration if supported */ - rCR(base_address) = ADC_CR_ADVREGEN | ADC_CR_BOOST; + rCR(base_address) = ADC_CR_ADVREGEN | boost; /* Wait for voltage regulator to power up */ @@ -169,7 +270,7 @@ int px4_arch_adc_init(uint32_t base_address) /* enable the temperature sensor, VREFINT channel and VBAT */ rCCR(base_address) = (ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN | - ADC_CCR_CKMODE_ASYCH | ADC_CCR_PRESC_DIV); + ADC_CCR_CKMODE_ASYCH | prescaler); /* Enable ADC calibration. ADCALDIF == 0 so this is only for * single-ended conversions, not for differential ones.