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cpu.c
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/* CPU.C (C) Copyright Roger Bowler, 1994-2012 */
/* (C) Copyright Jan Jaeger, 1999-2012 */
/* (C) and others 2013-2023 */
/* ESA/390 CPU Emulator */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
/* Interpretive Execution - (C) Copyright Jan Jaeger, 1999-2012 */
/* z/Architecture support - (C) Copyright Jan Jaeger, 1999-2012 */
/*-------------------------------------------------------------------*/
/* This module implements the CPU instruction execution function of */
/* the S/370 and ESA/390 architectures, as described in the manuals */
/* GA22-7000-03 System/370 Principles of Operation */
/* SA22-7201-06 ESA/390 Principles of Operation */
/* SA22-7832-00 z/Architecture Principles of Operation */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* Nullification corrections by Jan Jaeger */
/* Set priority by Reed H. Petty from an idea by Steve Gay */
/* Corrections to program check by Jan Jaeger */
/* Light optimization on critical path by Valery Pogonchenko */
/* OSTAILOR parameter by Jay Maynard */
/* CPU timer and clock comparator interrupt improvements by */
/* Jan Jaeger, after a suggestion by Willem Konynenberg */
/* Instruction decode rework - Jan Jaeger */
/* Modifications for Interpretive Execution (SIE) by Jan Jaeger */
/* Basic FP extensions support - Peter Kuschnerus */
/* ASN-and-LX-reuse facility - Roger Bowler, June 2004 */
/*-------------------------------------------------------------------*/
#include "hstdinc.h"
// #define SIE_DEBUG
#define _CPU_C_
#define _HENGINE_DLL_
#include "hercules.h"
#include "opcode.h"
#include "inline.h"
/*-------------------------------------------------------------------*/
/* ARCH_DEP section: compiled multiple times, once for each arch. */
/*-------------------------------------------------------------------*/
//-------------------------------------------------------------------
// ARCH_DEP() code
//-------------------------------------------------------------------
// ARCH_DEP (build-architecture / FEATURE-dependent) functions here.
// All BUILD architecture dependent (ARCH_DEP) function are compiled
// multiple times (once for each defined build architecture) and each
// time they are compiled with a different set of FEATURE_XXX defines
// appropriate for that architecture. Use #ifdef FEATURE_XXX guards
// to check whether the current BUILD architecture has that given
// feature #defined for it or not. WARNING: Do NOT use _FEATURE_XXX.
// The underscore feature #defines mean something else entirely. Only
// test for FEATURE_XXX. (WITHOUT the underscore)
//-------------------------------------------------------------------
/*-------------------------------------------------------------------*/
/* Forward references to internal static helper functions at end. */
/*-------------------------------------------------------------------*/
#if !defined( FWD_REFS)
#define FWD_REFS
static void CPU_Wait( REGS* regs );
static void* cpu_uninit( int cpu, REGS* regs );
#endif
/*-------------------------------------------------------------------*/
/* Put all the CPUs in the configuration in check-stop state */
/* Caller *MUST* hold INTLOCK! */
/*-------------------------------------------------------------------*/
void ARCH_DEP( checkstop_all_cpus )( REGS* regs )
{
int i;
if (!IS_INTLOCK_HELD( regs ))
CRASH();
for (i=0; i < sysblk.maxcpu; i++)
{
if (IS_CPU_ONLINE(i))
{
sysblk.regs[i]->cpustate = CPUSTATE_STOPPING;
sysblk.regs[i]->checkstop = 1;
ON_IC_INTERRUPT( sysblk.regs[i] );
}
}
WAKEUP_CPUS_MASK( sysblk.waiting_mask );
}
/*-------------------------------------------------------------------*/
/* Store current PSW at a specified absolute address in main storage */
/*-------------------------------------------------------------------*/
void ARCH_DEP( store_psw )( REGS* regs, BYTE* addr )
{
/* Ensure psw.IA is set */
if (!regs->psw.zeroilc)
MAYBE_SET_PSW_IA_FROM_IP( regs );
#if defined( FEATURE_BCMODE )
if (ECMODE( ®s->psw ))
#endif
// 390 or 370 EC-mode
#if !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
STORE_DW( addr, make_psw64( regs, 390, false ));
#endif
#if defined( FEATURE_BCMODE )
else // 370 BC-mode
STORE_DW( addr, make_psw64( regs, 370, true ));
#elif defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
// 64-bit z/Architecture mode
STORE_DW( addr + 0, make_psw64( regs, 900, false ));
STORE_DW( addr + 8, regs->psw.IA_G );
#endif
} /* end function ARCH_DEP(store_psw) */
/*-------------------------------------------------------------------*/
/* Load current PSW from a specified address in main storage */
/* Returns 0 if valid, 0x0006 if specification exception */
/*-------------------------------------------------------------------*/
int ARCH_DEP(load_psw) (REGS *regs, BYTE *addr)
{
INVALIDATE_AIA(regs);
regs->psw.zeroilc = 1;
regs->psw.sysmask = addr[0];
regs->psw.pkey = (addr[1] & 0xF0);
regs->psw.states = (addr[1] & 0x0F);
#if defined(FEATURE_BCMODE)
if ( ECMODE(®s->psw) ) {
#endif /*defined(FEATURE_BCMODE)*/
SET_IC_ECMODE_MASK(regs);
/* Processing for EC mode PSW */
regs->psw.intcode = 0;
regs->psw.asc = (addr[2] & 0xC0);
regs->psw.cc = (addr[2] & 0x30) >> 4;
regs->psw.progmask = (addr[2] & 0x0F);
regs->psw.amode = (addr[4] & 0x80) ? 1 : 0;
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
regs->psw.zerobyte = addr[3] & 0xFE;
regs->psw.amode64 = addr[3] & 0x01;
regs->psw.zeroword = fetch_fw(addr+4) & 0x7FFFFFFF;
regs->psw.IA = fetch_dw (addr + 8);
regs->psw.AMASK = regs->psw.amode64 ? AMASK64
: regs->psw.amode ? AMASK31 : AMASK24;
#else
regs->psw.zerobyte = addr[3];
regs->psw.amode64 = 0;
regs->psw.IA = fetch_fw(addr + 4) & 0x7FFFFFFF;
regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
#endif
/* Bits 0 and 2-4 of system mask must be zero */
if ((addr[0] & 0xB8) != 0)
return PGM_SPECIFICATION_EXCEPTION;
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/* For ESAME, bit 12 must be zero */
if (NOTESAME(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
/* Bits 24-30 must be zero */
if (regs->psw.zerobyte)
return PGM_SPECIFICATION_EXCEPTION;
/* Bits 33-63 must be zero */
if ( regs->psw.zeroword )
return PGM_SPECIFICATION_EXCEPTION;
#else /* !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
/* Bits 24-31 must be zero */
if ( regs->psw.zerobyte )
return PGM_SPECIFICATION_EXCEPTION;
/* For ESA/390, bit 12 must be one */
if (!ECMODE(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif /* !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
#ifndef FEATURE_DUAL_ADDRESS_SPACE
/* If DAS feature not installed then bit 16 must be zero */
if (SPACE_BIT(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif
#ifndef FEATURE_ACCESS_REGISTERS
/* If not ESA/370 or ESA/390 then bit 17 must be zero */
if (AR_BIT(®s->psw))
return PGM_SPECIFICATION_EXCEPTION;
#endif
/* Check validity of amode and instruction address */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/* For ESAME, bit 32 cannot be zero if bit 31 is one */
if (regs->psw.amode64 && !regs->psw.amode)
return PGM_SPECIFICATION_EXCEPTION;
/* If bit 32 is zero then IA cannot exceed 24 bits */
if (!regs->psw.amode && regs->psw.IA > 0x00FFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
/* If bit 31 is zero then IA cannot exceed 31 bits */
if (!regs->psw.amode64 && regs->psw.IA > 0x7FFFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
#else /* !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
#ifdef FEATURE_BIMODAL_ADDRESSING
/* For 370-XA, ESA/370, and ESA/390,
if amode=24, bits 33-39 must be zero */
if (!regs->psw.amode && regs->psw.IA > 0x00FFFFFF)
return PGM_SPECIFICATION_EXCEPTION;
#else
/* For S/370, bits 32-39 must be zero */
if (addr[4] != 0x00)
return PGM_SPECIFICATION_EXCEPTION;
#endif
#endif /* !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
#if defined( FEATURE_BCMODE )
} else {
SET_IC_BCMODE_MASK(regs);
/* Processing for S/370 BC mode PSW */
regs->psw.intcode = fetch_hw (addr + 2);
regs->psw.cc = (addr[4] & 0x30) >> 4;
regs->psw.progmask = (addr[4] & 0x0F);
FETCH_FW(regs->psw.IA, addr + 4);
regs->psw.IA &= 0x00FFFFFF;
regs->psw.AMASK = AMASK24;
regs->psw.zerobyte = 0;
regs->psw.asc = 0;
regs->psw.amode64 = regs->psw.amode = 0;
}
#endif /* defined( FEATURE_BCMODE ) */
#if defined( FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE )
/* Bits 5 and 16 must be zero in XC mode */
if( SIE_STATE_BIT_ON(regs, MX, XC)
&& ( (regs->psw.sysmask & PSW_DATMODE) || SPACE_BIT(®s->psw)) )
return PGM_SPECIFICATION_EXCEPTION;
#endif
regs->psw.zeroilc = 0;
/* Check for wait state PSW */
if (1
&& WAITSTATE( ®s->psw )
&& CPU_STEPPING_OR_TRACING_ALL
&& !TXF_INSTR_TRACING()
)
{
if (regs->insttrace && sysblk.traceFILE)
tf_0800( regs );
else
{
char buf[40];
STR_PSW( regs, buf );
// "Processor %s%02X: loaded wait state PSW %s"
WRMSG( HHC00800, "I", PTYPSTR( regs->cpuad ), regs->cpuad, buf );
}
}
TEST_SET_AEA_MODE(regs);
return 0;
} /* end function ARCH_DEP(load_psw) */
#if defined( FEATURE_PER3 )
/*-------------------------------------------------------------------*/
/* Set the Breaking-Event-Address Register */
/*-------------------------------------------------------------------*/
DLL_EXPORT void ARCH_DEP( Set_BEAR_Reg )( U64* bear, REGS* regs, BYTE* ip )
{
/* "If the instruction causing the breaking event is the
target of an execute-type instruction (EX or EXRL),
then the instruction address used to fetch the EX/EXRL
instruction is placed in the BEAR."
*/
if (1
&& bear != ®s->bear_ex /* NOT saving EX/EXRL address? */
&& regs->execflag /* EX/EXRL target caused event? */
)
{
regs->bear = regs->bear_ex; /* BEAR = EX/EXRL instr address */
PTT_INF( "bear = ex", regs->bear_ex, 0, 0 );
}
else if (ip)
{
/* BEAR = Address of the beginning of virtual ('aiv') page
plus same displacement from begin of mainstor ('ip') page
also know as 'aip'.
HOWEVER, since the 'ip' value passed to us might not match
regs->ip (it might have been passed to us as "regs->ip - 4"),
we cannot blindly rely on the 'ip' value passed to us being
on the same mainstor page as regs->aip. It could be pointing
before where regs->aip is currently pointing if regs->ip
was pointing to the first instruction on the page and thus
after backing up 4 bytes would cause it to point before
where regs->aip points. The below logic takes situations
such as that into consideration.
*/
BYTE* aip = regs->aip; /* Begin of mainstor page */
U64 aiv = regs->AIV; /* Begin of virtual page */
if (ip < regs->aip) /* pointing to prev page? */
{
/* The instruction pointer that was passed to us
points somewhere in the PREVIOUS mainstor page */
PTT_INF( "ip < aip", ip, aip, aiv );
aip -= PAGEFRAME_PAGESIZE;
aiv -= PAGEFRAME_PAGESIZE;
}
else if (ip >= (regs->aip + PAGEFRAME_PAGESIZE))
{
/* The instruction pointer that was passed to us
points somewhere in the NEXT mainstor page */
PTT_INF( "ip >= aip+page", ip, aip, aiv );
aip += PAGEFRAME_PAGESIZE;
aiv += PAGEFRAME_PAGESIZE;
}
/* Calculate and set BEAR appropriately */
*bear = aiv + (ip - aip); /* Save virtual address */
*bear &= ADDRESS_MAXWRAP( regs ); /* of the breaking event */
if (bear == ®s->bear)
PTT_INF( "bear =", *bear, 0, 0 );
else
PTT_INF( "bear_ex =", *bear, 0, 0 );
}
}
#endif
/*-------------------------------------------------------------------*/
/* SuccessfulBranch */
/*-------------------------------------------------------------------*/
void ARCH_DEP( SuccessfulBranch )( REGS* regs, VADR vaddr )
{
vaddr &= ADDRESS_MAXWRAP( regs );
/* Set BEAR to branch instruction. Note: for branch instructions
regs->ip is not updated to point to the next instruction and
thus is still pointing to the branch instruction itself.
*/
SET_BEAR_REG( regs, regs->ip );
/* Branch target still within same page as branch instruction? */
if (1
&& !regs->permode
&& !regs->execflag
&& (vaddr & (PAGEFRAME_PAGEMASK | 0x01)) == regs->AIV
)
{
/* Branch directly to the new instruction */
regs->ip = regs->aip + (vaddr - regs->AIV);
PTT_INF( "branch", vaddr, regs->AIV, regs->ip );
return;
}
/* Branch target is in another page: point the PSW to the target
instruction and force a new "regs->ip" value to get set by
forcing a full instruction fetch from the new target address.
*/
regs->psw.IA = vaddr; /* Point PSW to target instr */
regs->aie = INVALID_AIE; /* Force a fresh 'instfetch' */
PTT_INF( "branch", vaddr, regs->AIV, 0 );
PER_SB( regs, regs->psw.IA );
}
/*-------------------------------------------------------------------*/
/* SuccessfulRelativeBranch */
/*-------------------------------------------------------------------*/
void ARCH_DEP( SuccessfulRelativeBranch )( REGS* regs, S64 offset )
{
/* Set BEAR to branch instruction. Note: for branch instructions
regs->ip is not updated to point to the next instruction and
thus is still pointing to the branch instruction itself.
*/
SET_BEAR_REG( regs, regs->ip );
/* Branch target still within same page as branch instruction? */
if (1
&& !regs->permode
&& !regs->execflag
&& offset > -4096
&& offset < +4096
&& (regs->ip + offset) >= regs->aip
&& (regs->ip + offset) < regs->aie
)
{
/* Branch directly to the new instruction */
regs->ip = regs->ip + offset;
PTT_INF( "rbranch <", regs->ip, offset, regs->aip );
return;
}
/* Branch target is in another page: point the PSW to the target
instruction and force a new "regs->ip" value to get set by
forcing a full instruction fetch from the new target address.
*/
PTT_INF( "rbranch >", regs->psw.IA, offset, regs->execflag );
/* Point PSW to target instruction */
if (!regs->execflag)
regs->psw.IA = PSW_IA_FROM_IP( regs, offset );
else
{
regs->psw.IA = regs->ET + offset;
regs->psw.IA &= ADDRESS_MAXWRAP( regs );
}
regs->aie = INVALID_AIE; /* Force a fresh 'instfetch' */
PTT_INF( "rbranch >", regs->psw.IA, offset, regs->execflag );
PER_SB( regs, regs->psw.IA );
}
/*-------------------------------------------------------------------*/
/* trace_program_interrupt */
/*-------------------------------------------------------------------*/
DLL_EXPORT void ARCH_DEP( trace_program_interrupt )( REGS* regs, int pcode, int ilc )
{
char sie_mode_str [ 10] = {0}; // maybe "SIE: "
char sie_debug_arch [ 32] = {0}; // "370", "390" or "900" if defined( SIE_DEBUG )
char txf_why [256] = {0}; // TXF "why" string if txf pgmint
char dxcstr [ 8] = {0}; // data exception code if PGM_DATA_EXCEPTION
BYTE* ip; /* ptr to instr that program checked or NULL */
/* Just the low byte of program interrupt code itself please */
int code = (pcode & 0xFF);
/* If the program interrupt code is zero, or if it's not, if the
code isn't one they're interested in seeing (as determiend by
OSTAILOR/pgmtrace) AND instruction tracing is NOT active, then
there's nothing for us to do.
*/
if (0
|| !code
|| (1
&& !(sysblk.pgminttr & ((U64) 1 << ((code - 1) & 0x3F)))
&& !CPU_STEPPING_OR_TRACING( regs, ilc )
)
)
{
return; // (nothing to do; quick exit)
}
/*
First things first: backup the 'ip' by the 'ilc' value to point
to the actual instruction that actually program checked.
If 'instinvalid' is set it means an instruction fetch error
occurred so we shouldn't rely on the value of regs->ip.
Otherwise if the instruction that program checked (i.e. after
backing up 'ip' by 'ilc' amount) appears to be in the previous
mainstor page (meaning the instruction itself crossed a page
boundary), use the the copy of the instruction that was saved
in regs->inst for our instruction pointer instead.
If neither condition is true (the most common case) then we
simply use current regs->ip value backed up by the ilc amount.
*/
PTT_PGM( "tr PGM int", regs->ip, regs->aip, ilc );
ip =
(
/* Instruction fetch error? (least likely) */
regs->instinvalid ? NULL
/* Instruction crossed page boundary? (unlikely) */
: ((regs->ip - ilc) < regs->aip) ? regs->inst
/* Instruction still on same page (most likely) */
: (regs->ip - ilc)
);
PTT_PGM( "tr PGM int", ip, regs->aip, ilc );
#if defined( OPTION_FOOTPRINT_BUFFER )
if (!(sysblk.insttrace || sysblk.instbreak))
{
U32 n;
for (n = sysblk.footprptr[ regs->cpuad ] + 1;
n != sysblk.footprptr[ regs->cpuad ];
n++, n &= OPTION_FOOTPRINT_BUFFER - 1
)
{
ARCH_DEP( display_inst )(
&sysblk.footprregs[ regs->cpuad ][n],
sysblk.footprregs[ regs->cpuad ][n].inst );
}
}
#endif
/* Suppress LRA Special Operation Exception tracing if requested */
if (1
&& code == PGM_SPECIAL_OPERATION_EXCEPTION
&& ip && ip[0] == 0xB1 // LRA
&& sysblk.nolrasoe // suppression enabled
)
{
return; // (nothing to do; quick exit)
}
/* Trace this program interrupt... */
#if defined( _FEATURE_SIE )
if (SIE_MODE( regs ))
STRLCPY( sie_mode_str, "SIE: " );
#endif
#if defined( SIE_DEBUG )
STRLCPY( sie_debug_arch, QSTR( _GEN_ARCH ));
STRLCAT( sie_debug_arch, " " );
#endif
#if defined( FEATURE_073_TRANSACT_EXEC_FACILITY )
if (1
&& pcode & PGM_TXF_EVENT
&& regs->txf_why
)
txf_why_str( txf_why, sizeof( txf_why ), regs->txf_why );
#endif
if (code == PGM_DATA_EXCEPTION)
MSGBUF( dxcstr, " DXC=%2.2X", regs->dxc );
if (regs->insttrace && sysblk.traceFILE)
tf_0801( regs, pcode, ilc );
// "Processor %s%02X: %s%s %s interruption code %4.4X ilc %d%s%s"
WRMSG( HHC00801, "I",
PTYPSTR( regs->cpuad ), regs->cpuad,
sie_mode_str, sie_debug_arch,
PIC2Name( code ), pcode,
ilc, dxcstr, txf_why );
// HHC02324 "PSW=... INST=... OPCODE operands name"
ARCH_DEP( display_pgmint_inst )( regs, ip );
} /* end function ARCH_DEP( trace_program_interrupt ) */
/*-------------------------------------------------------------------*/
/* fix_program_interrupt_PSW */
/*-------------------------------------------------------------------*/
DLL_EXPORT int ARCH_DEP( fix_program_interrupt_PSW )( REGS* regs )
{
/* Determine the instruction length code (ilc).
The 'zeroilc' flag is set when the Instruction Length Code
should be reported as zero (such as when instruction-fetching
nullification PER option is set in CR9 or when the load PSW
instruction results in an invalid PSW being loaded).
The PSW 'ilc' value can also be specifically set to '0' when
a BALR, BASR or BASSM program checks during 'trace_br' call.
*/
int ilc =
(
/* If zeroilc flag is set, then we MUST use zero for the ilc */
regs->psw.zeroilc ? 0
/* Otherwise use either the ilc value set in the PSW or the
length of the EX/EXRL instruction is the instruction is
being executed.
*/
: REAL_ILC( regs )
);
PTT_PGM( "fxpiPSW ilc", 0, 0, ilc );
/* If our resulting ilc is still 0 but the zeroilc flag is NOT set,
then we're left with no choice but to GUESS the 'ilc' value
based on whether the instruction was being executed or not.
*/
if (regs->psw.ilc == 0 && !regs->psw.zeroilc)
{
ilc = (!regs->execflag ? 2 : (regs->exrl ? 6 : 4));
PTT_PGM( "fxpiPSW ilc", regs->ip, regs->psw.IA, ilc );
/* Now ADVANCE the 'ip' mainstor instruction pointer and
psw 'IA' instruction address by that ilc amount so that
the 'trace_program_interrupt' can then back them both up
by the same amount to point to the actual instruction
that actually program checked.
*/
regs->psw.ilc = ilc; // (guessed value)
regs->ip += ilc; // (so trace_program_interrupt can undo)
regs->psw.IA += ilc; // (so trace_program_interrupt can undo)
PTT_PGM( "fxpiPSW ilc", regs->ip, regs->psw.IA, ilc );
}
/* Return ilc value to be passed to 'trace_program_interrupt' */
PTT_PGM( "fxpiPSW ret", 0, 0, ilc );
return ilc;
}
/*-------------------------------------------------------------------*/
/* program_interrupt */
/*-------------------------------------------------------------------*/
/* The purpose of this function is to store the current PSW into the */
/* Program interrupt old PSW field in low core followed by loading */
/* the Program interrupt new PSW and then jumping via regs->progjmp */
/* back to the run_cpu instruction execution loop to begin executing */
/* instructions at the Progran new PSW location. */
/*-------------------------------------------------------------------*/
void (ATTR_REGPARM(2) ARCH_DEP( program_interrupt ))( REGS* regs, int pcode )
{
PSA *psa; /* -> Prefixed storage area */
REGS *realregs; /* True regs structure */
RADR px; /* host real address of pfx */
int code; /* pcode without PER ind. */
int ilc; /* instruction length */
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
/* FIXME : SEE ISW20090110-1 */
void *zmoncode = NULL; /* mon call SIE intercept;
special reloc for z/Arch */
/* FIXME : zmoncode not being
initialized here raises a
potentially non-initialized
warning in GCC.. can't find
why. ISW 2009/02/04 */
#endif
#if defined( FEATURE_SIE )
int sie_ilc=0; /* SIE instruction length */
#endif
#if defined( _FEATURE_SIE )
bool intercept; /* False for virtual pgmint */
/* (True for host interrupt?)*/
#endif
/* If called with ghost registers (ie from hercules command
then ignore all interrupt handling and report the error
to the caller */
if (regs->ghostregs)
longjmp( regs->progjmp, pcode );
PTT_PGM("PGM", pcode, regs->TEA, regs->psw.IA );
/* program_interrupt() may be called with a shadow copy of the
regs structure, realregs is the pointer to the real structure
which must be used when loading/storing the psw, or backing up
the instruction address in case of nullification
*/
#if defined( _FEATURE_SIE )
realregs = SIE_MODE( regs )
? GUEST( sysblk.regs[ regs->cpuad ])
: HOST( sysblk.regs[ regs->cpuad ]);
#else
realregs = HOST( sysblk.regs[ regs->cpuad ]);
#endif
PTT_PGM( "PGM (r)h,g,a", realregs->host, realregs->guest, realregs->sie_active );
/* Prevent machine check when in (almost) interrupt loop */
realregs->instcount++;
UPDATE_SYSBLK_INSTCOUNT( 1 );
/* Release any locks */
if (IS_INTLOCK_HELD( realregs ))
RELEASE_INTLOCK( realregs );
/* Unlock the main storage lock if held */
if (sysblk.mainowner == realregs->cpuad)
RELEASE_MAINLOCK_UNCONDITIONAL( realregs );
/* Ensure psw.IA is set and aia invalidated */
INVALIDATE_AIA(realregs);
#if defined( FEATURE_SIE )
if (realregs->sie_active)
ARCH_DEP( invalidate_guest_aia )( GUEST( realregs ));
#endif
/* Fix PSW and get instruction length (ilc) */
ilc = ARCH_DEP( fix_program_interrupt_PSW )( realregs );
PTT_PGM( "PGM ilc", 0, 0, ilc );
#if defined( FEATURE_SIE )
if (realregs->sie_active)
{
sie_ilc = GUEST( realregs )->psw.zeroilc ? 0 : REAL_ILC( GUEST( realregs ));
if (GUEST( realregs )->psw.ilc == 0 && !GUEST( realregs )->psw.zeroilc)
{
sie_ilc = likely( !GUEST( realregs )->execflag) ? 2 : GUEST( realregs )->exrl ? 6 : 4;
GUEST( realregs )->psw.ilc = sie_ilc;
}
PTT_PGM( "PGM sie_ilc", 0, 0, sie_ilc );
}
#endif
/* Trace the program interrupt right away */
ARCH_DEP( trace_program_interrupt )( regs, pcode, ilc );
/* Remove PER indication from program interrupt code
such that interrupt code specific tests may be done.
The PER indication will be stored in the PER handling
code */
code = pcode & ~PGM_PER_EVENT;
#if defined( FEATURE_073_TRANSACT_EXEC_FACILITY )
/* If transaction is active, check if interrupt can be filtered */
if (realregs->txf_tnd)
{
/* Indicate TXF related program interrupt */
pcode |= PGM_TXF_EVENT;
/* Always reset the NTSTG indicator on any program interrupt */
regs->txf_NTSTG = false;
/* Save the program interrupt and data exception codes */
realregs->txf_piid = pcode;
realregs->txf_piid |= (ilc << 16);
realregs->txf_dxc_vxc =
(0
|| pcode == PGM_DATA_EXCEPTION
|| pcode == PGM_VECTOR_PROCESSING_EXCEPTION
)
? realregs->dxc : 0;
PTT_TXF( "TXF PIID", realregs->txf_piid, realregs->txf_dxc_vxc, 0 );
/* 'txf_do_pi_filtering' does not return for filterable
program interrupts. It returns only if the program
interrupt is unfilterable, and when it returns, the
active transaction has already been aborted.
*/
PTT_TXF( "TXF PROG?", (code & 0xFF), realregs->txf_contran, realregs->txf_tnd );
ARCH_DEP( txf_do_pi_filtering )( realregs, pcode );
if (realregs->txf_tnd ) // (sanity check)
CRASH(); // (sanity check)
PTT_TXF( "*TXF UPROG!", (code & 0xFF), 0, 0 );
/* Set flag for sie_exit */
realregs->txf_UPGM_abort = true;
}
else /* (no transaction is CURRENTLY active) */
{
/* While no transaction is CURRENTLY active, it's possible
that a previously active transaction was aborted BEFORE
we were called, so we need to check for that.
*/
if ((code & 0xFF) == PGM_TRANSACTION_CONSTRAINT_EXCEPTION)
{
/* Indicate TXF related program interrupt */
pcode |= PGM_TXF_EVENT;
PTT_TXF( "*TXF 218!", pcode, 0, 0 );
/* Set flag for sie_exit */
realregs->txf_UPGM_abort = true;
}
}
#endif /* defined( FEATURE_073_TRANSACT_EXEC_FACILITY ) */
/* Set 'execflag' to 0 in case EXecuted instruction program-checked */
PTT_PGM( "PGM execflag", realregs->execflag, realregs->sie_active, 0 );
realregs->execflag = 0;
#if defined( FEATURE_SIE )
if (realregs->sie_active)
GUEST( realregs )->execflag = 0;
#endif
PTT_PGM( "PGM execflag", realregs->execflag, realregs->sie_active, 0 );
/* If this is a concurrent PER event
then we must add the PER bit to the interrupts code */
if (OPEN_IC_PER (realregs ))
pcode |= PGM_PER_EVENT;
/* Perform serialization and checkpoint synchronization */
PERFORM_SERIALIZATION( realregs );
PERFORM_CHKPT_SYNC( realregs );
#if defined( FEATURE_SIE )
/* Host protection and addressing exceptions
must be reflected to the guest */
if (1
&& realregs->sie_active
&& (0
|| code == PGM_PROTECTION_EXCEPTION
|| code == PGM_ADDRESSING_EXCEPTION
#if defined( _FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE )
|| code == PGM_ALET_SPECIFICATION_EXCEPTION
|| code == PGM_ALEN_TRANSLATION_EXCEPTION
|| code == PGM_ALE_SEQUENCE_EXCEPTION
|| code == PGM_EXTENDED_AUTHORITY_EXCEPTION
#endif
)
)
{
/* Pass this interrupt to the guest */
#if defined( SIE_DEBUG )
LOGMSG( "program_int() passing to guest code=%4.4X\n", pcode );
#endif
switch (GUEST( realregs )->arch_mode)
{
case ARCH_370_IDX: GUEST( realregs )->TEA_370 = realregs->TEA; break;
case ARCH_390_IDX: GUEST( realregs )->TEA_390 = realregs->TEA; break;
case ARCH_900_IDX: GUEST( realregs )->TEA_900 = realregs->TEA; break;
default: CRASH();
}
GUEST( realregs )->excarid = realregs->excarid;
GUEST( realregs )->opndrid = realregs->opndrid;
#if defined(_FEATURE_PROTECTION_INTERCEPTION_CONTROL)
GUEST( realregs )->hostint = 1;
#endif
GUEST( realregs )->program_interrupt( GUEST( realregs ), pcode );
}
#endif /* defined( FEATURE_SIE ) */
/* Back up the PSW for exceptions which cause nullification,
unless the exception occurred during instruction fetch
*/
PTT_PGM( "PGM psw.IA", realregs->psw.IA, realregs->instinvalid, ilc );
if (1
&& !realregs->instinvalid
&& (0
|| code == PGM_PAGE_TRANSLATION_EXCEPTION
|| code == PGM_SEGMENT_TRANSLATION_EXCEPTION
#if defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
|| code == PGM_ASCE_TYPE_EXCEPTION
|| code == PGM_REGION_FIRST_TRANSLATION_EXCEPTION
|| code == PGM_REGION_SECOND_TRANSLATION_EXCEPTION
|| code == PGM_REGION_THIRD_TRANSLATION_EXCEPTION
#endif
|| code == PGM_TRACE_TABLE_EXCEPTION
|| code == PGM_AFX_TRANSLATION_EXCEPTION
|| code == PGM_ASX_TRANSLATION_EXCEPTION
|| code == PGM_LX_TRANSLATION_EXCEPTION
|| code == PGM_LFX_TRANSLATION_EXCEPTION
|| code == PGM_LSX_TRANSLATION_EXCEPTION
|| code == PGM_LSTE_SEQUENCE_EXCEPTION
|| code == PGM_EX_TRANSLATION_EXCEPTION
|| code == PGM_PRIMARY_AUTHORITY_EXCEPTION
|| code == PGM_SECONDARY_AUTHORITY_EXCEPTION
|| code == PGM_ALEN_TRANSLATION_EXCEPTION
|| code == PGM_ALE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_VALIDITY_EXCEPTION
|| code == PGM_ASTE_SEQUENCE_EXCEPTION
|| code == PGM_ASTE_INSTANCE_EXCEPTION
|| code == PGM_EXTENDED_AUTHORITY_EXCEPTION
|| code == PGM_STACK_FULL_EXCEPTION
|| code == PGM_STACK_EMPTY_EXCEPTION
|| code == PGM_STACK_SPECIFICATION_EXCEPTION
|| code == PGM_STACK_TYPE_EXCEPTION
|| code == PGM_STACK_OPERATION_EXCEPTION
|| code == PGM_VECTOR_OPERATION_EXCEPTION
)
)
{
realregs->psw.IA -= ilc;
realregs->psw.IA &= ADDRESS_MAXWRAP(realregs);
PTT_PGM( "PGM IA-ilc", realregs->psw.IA, realregs->instinvalid, ilc );
#if defined( FEATURE_SIE )
/* When in SIE mode the guest instruction
causing this host exception must also be nullified
*/
if (realregs->sie_active && !GUEST( realregs )->instinvalid)
ARCH_DEP( update_guest_psw_ia )( GUEST( realregs ), -sie_ilc );
#endif
}
/* The OLD PSW must be incremented
on the following exceptions during instfetch
*/
if (1
&& realregs->instinvalid
&& (0
|| code == PGM_PROTECTION_EXCEPTION
|| code == PGM_ADDRESSING_EXCEPTION
|| code == PGM_SPECIFICATION_EXCEPTION
|| code == PGM_TRANSLATION_SPECIFICATION_EXCEPTION
)
)
{
realregs->psw.IA += ilc;
realregs->psw.IA &= ADDRESS_MAXWRAP( realregs );
PTT_PGM( "PGM IA+ilc", realregs->psw.IA, realregs->instinvalid, ilc );
}
/* Store the interrupt code in the PSW */
realregs->psw.intcode = pcode;
/* Call debugger if active */
HDC2( debug_program_interrupt, regs, pcode );
realregs->instinvalid = 0;
PTT_PGM( "PGM inval=0", 0, 0, 0 );
#if defined( FEATURE_SIE )
/*---------------------------------------------------------*/
/* If this is a host exception in SIE state then leave SIE */
/*---------------------------------------------------------*/
if (realregs->sie_active)
{
PTT_PGM( "PGM >sie_exit", SIE_HOST_PGM_INT, 0, 0 );
ARCH_DEP( sie_exit )( realregs, SIE_HOST_PGM_INT );
}
#endif
/* Absolute address of prefix page */
px = realregs->PX;
/* If under SIE use translated to host absolute prefix */
#if defined( _FEATURE_SIE )
if (SIE_MODE( regs ))
px = regs->sie_px;
#endif
#if defined( _FEATURE_SIE )
/*---------------------------------------------------------------*/
/* If we're in SIE mode, then we need to determine whether */
/* we must, or must not, intercept this program interrupt, */
/* and by intercept, we mean pass it on to the SIE host so */
/* that it (not the guest!) can decide what action to take. */
/*---------------------------------------------------------------*/
if (0
/* If not in SIE mode, then we (duh!) must not intercept it */
|| !SIE_MODE( regs )
/* Interception is mandatory for the following exceptions,
so if ANY of the below conditions are false, then we MUST
intercept this program interrupt.
The below tests/checks are for "not this condition" where
the "condition" is the condition which we MUST intercept.
Thus if any of them fail, then we MUST intercept.
Only if ALL of them are true (only if no condition exists
that REQUIRES an intercept) should we then NOT intercept.
*/
|| (1
&& code != PGM_ADDRESSING_EXCEPTION
&& code != PGM_SPECIFICATION_EXCEPTION
&& code != PGM_SPECIAL_OPERATION_EXCEPTION
#if defined( FEATURE_S370_S390_VECTOR_FACILITY )
&& code != PGM_VECTOR_OPERATION_EXCEPTION
#endif
#ifdef FEATURE_BASIC_FP_EXTENSIONS
&& !(code == PGM_DATA_EXCEPTION && (regs->dxc == 1 || regs->dxc == 2) && (regs->CR(0) & CR0_AFP) && !(HOSTREGS->CR(0) & CR0_AFP))
#endif
&& !SIE_FEAT_BIT_ON( regs, IC0, PGMALL )
#if !defined( _FEATURE_PROTECTION_INTERCEPTION_CONTROL )
&& code != PGM_PROTECTION_EXCEPTION
#else
&& !(code == PGM_PROTECTION_EXCEPTION && (!SIE_FEAT_BIT_ON( regs, EC2, PROTEX ) || realregs->hostint ))
#endif
#if defined( _FEATURE_PER2 )
&& !((pcode & PGM_PER_EVENT) && SIE_FEAT_BIT_ON( regs, M, GPE ))
#endif
#if defined( FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE )
&& !(code == PGM_ALEN_TRANSLATION_EXCEPTION && SIE_FEAT_BIT_ON( regs, MX, XC ))