VSD-Physical-Verification-using-SKY130

Repo for 5 day(10-14 Oct 2022) VSD-IAT Workshop: Physical Verification using SKY130.

Day-1

Installing Sky130 PDK to local machine

git clone https://github.com/RTimothyEdwards/open_pdks
cd open_pdks
configure --enable-sky130-pdk
make
sudo make install

Tools supported by open_pdks

Magic: It does extraction, DRC, handles .def .gds .lef
Klayout: Alternate layout editor and viewer(also do DRC)
Openlane: Synthesis & PnR package based on Openroad tools
Xschem: Schematic editing tool
Netgen: LVS tool
Ngspice: Analog simulation tool
Xcircuit: alt. schematic capture tool
IRsim: Switch level simulation and power analyzer
qflow: alt. digital synthesis flow
Iverilog: Verilog simulation and synthesis tool

Links to tools

Tool	links
Magic	http://opencircuitdesign.com/magic
Klayout	https://www.klayout.de
Openlane	https://github.com/efabless/openlane
Xschem	https://github.com/StefanSchippers/xschem
Netgen	http://opencircuitdesign.com/netgen
iverilog	https://iverilog.icarus.com
qflow	http://opencircuitdesign.com/qflow
IRSIM	http://opencircuitdesign.com/irsim
Xcircuit	http://opencircuitdesign.com/xcircuit

LAB for Day-1(INVERTER)

Getting started...

Check the installation by simply typing the name of the tool
Making a directory inverter
Creating folders mag,xschem,ngspice

Checking installations

Making directories and files...Setting up

Setup Commands

ln -s /usr/share/pdk/sky130A/libs.tech/xschem/xschemrc

ln -s /usr/share/pdk/sky130A/libs.tech/ngspice/spinit .spiceinit

ln -s /usr/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc .magicrc

ln -s /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl setup.tcl

Xschem

Commands

cd ../xschem
xschem

Magic

Commands

cd ../mag
magic

Making Inverter Schematic on Xschem

Making a New Schematic

Press Insert key to open the insert symbol dialog box

Insert the pfet3 , nfet, ipin, iopins, opin and join them with wire(W key)

Also change the W/L and number of fingers for the pfet and nfet by right clicking on the symbol

Now go to symbol>make symbol from new schematic

then go to File>New Schematic

Create New Schematic by adding inverter symbol, voltage sources, opins, GND and connect them with wires.

Add the voltage value for Vdd, input pulse, code for transient analysis and add the lib

".lib /usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt"

".control tran 1n 1u plot V(in) V(out) .endc"

Generate netlist, Save the Schematic as inverter_tb, and simulate!

The result came out as expected! >> Now lets go to making the layout for inverter

Importing Schematic to layout

cd ../mag
magic -d XR

then go File >> import SPICE >> inverter.spice

Change the top, bottom guard rings; Source, drain coverage

For pfet select top guard ring via coverage and type 100. source via coverage =+40 drain via coverage = -40

and for nfet bottom guard ring via coverage = 100 source via covergae = +40 drain via coverage = -40

Now complete the layout

Now click Save >> Autowrite

In Command window type following commands extraction, generate a spice netlist and then quit

extract do local
extract all
ext2spice lvs
ext2spice
quit

Now for LVS..

cd ../netgen
netgen -batch lvs "../mag/inverter.spice inverter" "../xschem/inverter.spice inverter"

Due to some error my netlist didnt match...working on it(will update here once done)

Day-2

DRC & LVS

Basics

DRC : ensure the design meet all the fab rules for the mask
LVS : ensure the layout matches the design schematic or any other similar form that define the design spec
Data Formats : .cif, .GDSII(industry standard), OASIS
Extraction : 2 step process(LAYOUT .mag file >> INTERMEDIATE .ext file >> NETLIST .spice file)
Extraction options in magic

ext2spice lvs
ext2spice cthresh value
ext2spice scale on|off
ext2spice hierarchy on|off
ext2spice subcircuit top on|off
ext2spice global on|off
ext2spicemerge on|off

LAB DAY-2

Create a proj directory

cif styles in magic

see the available top level cell useing `cellname top`

or by navigating Options >> Cell manager

Then choose and2_1

we load the layout

use `cif istyle sky130(vendor)` & then read gds file from lib (labels are blue coz they're being traeated as ports)

Ports & Index

To enquire about ports use `port index` for more enquiry about say port with index 1... use `port first` then..

port 1 name
port 1 class
port 1 use

and2_1 subckt definition

Abstract views

read lef lib using `lef read /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef` . Load and2_1 from cell manager, and the abstract view is shown...

port order metadate isnt present

use `load test` & instantiate the cell with command `getcell sky130_fd_sc_hd__and2_1` ....the abstract view is shown

we see layout....

start new session..

cell edited is from skywater pdks...check using `path`

write into gds file

LVS

  mkdir netgen 
  cd netgen
  cp /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl ./setup.tcl
  cd ../mag
  magic -d XR sky130_fd_sc_hd__and2_1
  ext2spice lvs
  ext2spice lvs
  ext2spice
  quit
  cd ../netgen
  netgen -batch lvs "../mag/sky130_fd_sc_hd__and2_1.spice sky130_fd_sc_hd__and2_1" "/usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice sky130_fd_sc_hd__and2_1"

Setup the XOR

  cd ../mag
magic -d XR
load sky130_fd_sc_hd__and2_1
save altered
load altered
erase li
flatten -nolabels xor_test
load sky130_fd_sc_hd__and2_1
xor -nolabels xor_test
load xor_test
quit
magic -d XR
load test3
flatten -nolabels xor_test
xor -nolabels xor_test
load xor_test

Day-3 (About DRC)

Rules:

1.Backend metal layer rules

Width rule
Spacing rule
Wide spacing rule
Notch rule
Min & max area rules
Min hole area rule
Contact cut rules

2.LI rules

3.Frontend rules

4.Wells, Taps and Net Rules

5.Deeps N-Well and High Voltage Rules

6.Device Rules(R,C,Diodes)

7.Miscellaneous Rules and Latch-up, Antenna and Stress Rules

8.Density rules

9.Recomm manufac. and ERC rules

Width rules
Spacing (notch) rules
Minimum area rules
Overlap (surround) rules
Extension rules
Angle and off-grid rules
Density rules (acceptable, rarely)

ERC

ELectromigration
Overvoltage conditions

Lab DAY-3

Exercise-1

Getting started...

Select and hit '?' on keyboard to get DRC report

Press 'B' to check dimensions of the cursor box. Here the width was 0.06um but the min width should be 0.14 microns. To increase the width of the metal layer, we can either manually set the cursor box to the size required, then paint it using the middle mouse button/hover to the layer and hit 'P' on keyboard. Or we can do it with console commands by typing...

box width 0.14um

paint m2

Exercise 1b....DRC report

Its a spacing error...it can be resolved by moving either of the rectangles away. Select a rectangles, and move it using 2-4-6-8 num keys (can also be done using the command move e 0.14um ...it moves the box 0.14um towards east>>)

Exercise 1c...check the error

Resolve this by increasing the seperation to by 0.4um either manually or by commands...your call

Another width rule example(Notch rule)....resolve this my selecting half part('A') and stretching it(shift+num key)...increasing the width Another way to do it is with stretch command..... stretch <direction> <measure>

Exercise-2

2a. Via size error. Can be solved by simply stretching the via both horiz and vert.

2b. We got a large via with an array of contact cuts. To see the contact cuts >> run cif see xxx to check the cif layer names. To see MCON(li for metal1), by using cif see MCON

Use feedback why to get info about cif layer, and feedback clear to stop viewing the contact cuts.

2c. We got an overlap error. Fix by selecting the layer then use the box grow <direction> <measure> command as shown {'c' -> centre}.Then paint in a layer of metal1 to fix the overlap error.

Now fix the size error by growing the box in e and w direction and paint it with m1

2d. Generate via automatically >> use the wiring tool (spacebar). By SHIFT+ left click >> we can move up a metal layer till metal5. Similarly, we can move down layers with the SHIFT+right click until the metal interconnect. To see vias use...

Cif see MCON
Cif see VIA1
Cif see VIA2
Cif see VIA3
Cif see VIA4

Exercise-3

3a.Min area rule... simply stretch to fix it

3b. Min. hole area rule...To see this error >> run Magic in the full DRC mode(menu button DRC >> DRC complete). Then run a DRC report.

Fix this by manually erasing sections of metal till the hole is big enough to pass DRC.

Exercise-4

4a. Its a well error(the wells don't have taps). N-well shows an error coz its floating(the P-well doesn't since p-wells aren't actually considered... unless they're in deep n-wells(instead treated as psub).

fix this by adding n-type material(nsubstratendiff) into the n-well. Then connect a layer of local interconnect to tap(nsubstratencontact).

Leads to new errors..solve these overlap and surround errors by stretching, adding li.

4b. The p well has to be connected to a contact if it has a tap. Add psubstratepcontact, some li, and adjust the areas of the layers, we get a DRC correct layout.

4c. Error in deep n-well

Grow the deep n-well >> move it away from the n-well(4b) {its interacting with it}. Add an n-well overlap around the deep n-well(wire tool) >> add in a tap layer with an interconnect.