From 309f8d67ae93e432f90d589f7d562ac71a045ae3 Mon Sep 17 00:00:00 2001 From: Feng Zhang Date: Thu, 19 Oct 2023 20:29:07 +0800 Subject: [PATCH 1/2] cm3 io: add radxa 8hd display Signed-off-by: Feng Zhang --- .../arm64/boot/dts/rockchip/overlays/Makefile | 1 + .../radxa-cm3-io-radxa-display-8hd.dts | 455 ++++++++++++++++++ 2 files changed, 456 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts diff --git a/arch/arm64/boot/dts/rockchip/overlays/Makefile b/arch/arm64/boot/dts/rockchip/overlays/Makefile index ee94dece..e59a7ce7 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/Makefile @@ -193,6 +193,7 @@ dtb-$(CONFIG_CPU_RK3568) += \ radxa-cm3-io-radxa-10p1inch-display.dtbo \ radxa-cm3-io-sharp-lq133t1jw01-without-hdmi.dtbo \ radxa-cm3-io-hd101boe9365-display.dtbo \ + radxa-cm3-io-radxa-display-8hd.dtbo \ radxa-5inch-touchscreen-on-cm3-sodimm-io.dtbo \ radxa-cm3-sodimm-io-radxa-display-8hd.dtbo \ radxa-cm3-sodimm-io-raspberrypi-7inch-touchscreen.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts new file mode 100644 index 00000000..bff8dde6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts @@ -0,0 +1,455 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title = "Enable Radxa Display 8HD"; + compatible = "radxa,cm3-io"; + category = "display"; + exclusive = "video_phy1", "dsi1"; + description = "Enable Radxa Display 8HD"; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + vcc_mipi: vcc-mipi { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_mipi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_mipi_pin>; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd_tp: vcc-lcd-tp { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd_tp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_tp_pin>; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + enable-active-low; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_backlight_en>; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + }; + }; + + fragment@1 { + target = <&dsi1>; + + __overlay__ { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply = <&vcc_mipi>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_lcd_rst_gpio>; + + width-mm = <107>; + height-mm = <199>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <2>; + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 80 03 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 72 + 15 00 02 03 00 + 15 00 02 04 65 + 15 00 02 0C 74 + 15 00 02 17 00 + 15 00 02 18 B7 + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B B7 + 15 00 02 1C 00 + 15 00 02 24 FE + 15 00 02 37 19 + 15 00 02 38 05 + 15 00 02 39 00 + 15 00 02 3A 01 + 15 00 02 3B 01 + 15 00 02 3C 70 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F FF + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 43 1E + 15 00 02 44 0F + 15 00 02 45 28 + 15 00 02 4B 04 + 15 00 02 55 02 + 15 00 02 56 01 + 15 00 02 57 A9 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 37 + 15 00 02 5B 19 + 15 00 02 5D 78 + 15 00 02 5E 63 + 15 00 02 5F 54 + 15 00 02 60 48 + 15 00 02 61 45 + 15 00 02 62 38 + 15 00 02 63 3D + 15 00 02 64 28 + 15 00 02 65 43 + 15 00 02 66 41 + 15 00 02 67 43 + 15 00 02 68 62 + 15 00 02 69 50 + 15 00 02 6A 57 + 15 00 02 6B 49 + 15 00 02 6C 44 + 15 00 02 6D 37 + 15 00 02 6E 23 + 15 00 02 6F 10 + 15 00 02 70 78 + 15 00 02 71 63 + 15 00 02 72 54 + 15 00 02 73 49 + 15 00 02 74 45 + 15 00 02 75 38 + 15 00 02 76 3D + 15 00 02 77 28 + 15 00 02 78 43 + 15 00 02 79 41 + 15 00 02 7A 43 + 15 00 02 7B 62 + 15 00 02 7C 50 + 15 00 02 7D 57 + 15 00 02 7E 49 + 15 00 02 7F 44 + 15 00 02 80 37 + 15 00 02 81 23 + 15 00 02 82 10 + 15 00 02 E0 02 + 15 00 02 00 47 + 15 00 02 01 47 + 15 00 02 02 45 + 15 00 02 03 45 + 15 00 02 04 4B + 15 00 02 05 4B + 15 00 02 06 49 + 15 00 02 07 49 + 15 00 02 08 41 + 15 00 02 09 1F + 15 00 02 0A 1F + 15 00 02 0B 1F + 15 00 02 0C 1F + 15 00 02 0D 1F + 15 00 02 0E 1F + 15 00 02 0F 5F + 15 00 02 10 5F + 15 00 02 11 57 + 15 00 02 12 77 + 15 00 02 13 35 + 15 00 02 14 1F + 15 00 02 15 1F + 15 00 02 16 46 + 15 00 02 17 46 + 15 00 02 18 44 + 15 00 02 19 44 + 15 00 02 1A 4A + 15 00 02 1B 4A + 15 00 02 1C 48 + 15 00 02 1D 48 + 15 00 02 1E 40 + 15 00 02 1F 1F + 15 00 02 20 1F + 15 00 02 21 1F + 15 00 02 22 1F + 15 00 02 23 1F + 15 00 02 24 1F + 15 00 02 25 5F + 15 00 02 26 5F + 15 00 02 27 57 + 15 00 02 28 77 + 15 00 02 29 35 + 15 00 02 2A 1F + 15 00 02 2B 1F + 15 00 02 58 40 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 10 + 15 00 02 5C 06 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 03 + 15 00 02 64 6B + 15 00 02 65 05 + 15 00 02 66 0C + 15 00 02 67 73 + 15 00 02 68 09 + 15 00 02 69 03 + 15 00 02 6A 56 + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 04 + 15 00 02 6E 04 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 F8 + 15 00 02 76 00 + 15 00 02 77 D5 + 15 00 02 78 2E + 15 00 02 79 12 + 15 00 02 7A 03 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 00 0E + 15 00 02 02 B3 + 15 00 02 09 60 + 15 00 02 0E 2A + 15 00 02 36 59 + 15 00 02 E0 00 + 15 00 02 80 01 + 15 00 02 E0 00 + 15 00 02 11 00 + 15 78 02 29 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <70000000>; + hactive = <800>; + vactive = <1280>; + hsync-len = <20>; + hback-porch = <20>; + hfront-porch = <40>; + vsync-len = <4>; + vback-porch = <28>; + vfront-porch = <30>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&dsi1_in_vp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&video_phy1>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&hdmi_in_vp0>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@5 { + target = <&hdmi>; + + __overlay__ { + status = "disabled"; + }; + }; + + fragment@6 { + target = <&route_dsi1>; + + __overlay__ { + status = "okay"; + connect = <&vp0_out_dsi1>; + }; + }; + + fragment@7 { + target = <&i2c2>; + + __overlay__ { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + gt9xx: gt9xx@14 { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + max-x = <800>; + max-y = <1280>; + tp-size = <9112>; + tp-supply = <&vcc_lcd_tp>; + }; + }; + }; + + fragment@8 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@9 { + target = <&pinctrl>; + + __overlay__ { + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-vcc { + vcc_mipi_pin: vcc-mipi-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc_tp_pin: vcc-tp-pin { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + dsi1-lcd { + dsi1_lcd_rst_gpio: dsi1-lcd-rst-gpio { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + dsi1_backlight_en: dsi1-backlight-en { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + }; +}; From bde8a824059ef871fe6e60de6b333002a0ddf566 Mon Sep 17 00:00:00 2001 From: ZHANG Yuntian Date: Thu, 19 Oct 2023 20:41:18 +0800 Subject: [PATCH 2/2] Remove non-existing enable-active-low --- .../dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts b/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts index bff8dde6..b3b4711b 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/radxa-cm3-io-radxa-display-8hd.dts @@ -44,7 +44,6 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc_tp_pin>; gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; - enable-active-low; regulator-always-on; regulator-state-mem { regulator-off-in-suspend;