From cefabf58762205590ab17a542dc946b73b81de06 Mon Sep 17 00:00:00 2001 From: Chuang Ma Date: Tue, 10 Oct 2023 11:59:19 +0800 Subject: [PATCH 1/2] Add rock-pi-e overlay support Signed-off-by: Chuang Ma --- .../dts/rockchip/overlays/rk3328-pwm2.dts | 20 +++++++++++++ .../rockchip/overlays/rk3328-spi0-spidev.dts | 28 +++++++++++++++++++ .../dts/rockchip/overlays/rk3328-uart1.dts | 20 +++++++++++++ .../dts/rockchip/overlays/rk3328-uart2-m0.dts | 20 +++++++++++++ 4 files changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts new file mode 100644 index 00000000..6198a323 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable PWM2"; + compatible = "rockchip,rk3328"; + category = "misc"; + exclusive = "GPIO2_A6"; + description = "Enable PWM2.\nOn Rock Pi E this is pin 33."; + }; + + fragment@0 { + target = <&pwm2>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts new file mode 100644 index 00000000..0944a1fc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts @@ -0,0 +1,28 @@ +/dts-v1/; +/plugin/; + +/{ + metadata { + title = "Enable spidev on SPI0"; + compatible = "rockchip,rk3328"; + category = "misc"; + exclusive = "GPIO3_A0", "GPIO3_A1", "GPIO3_A2", "GPIO3_B0"; + description = "Enable spidev on SPI0 on pin 19, 21, 23 & 24."; + }; + + fragment@0 { + target = <&spi0>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts new file mode 100644 index 00000000..7ad4d319 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART1"; + compatible = "rockchip,rk3328"; + category = "misc"; + exclusive = "GPIO3_A4", "GPIO3_A5"; + description = "Enable UART1"; + }; + + fragment@0 { + target = <&uart1>; + + __overlay__ { + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts new file mode 100644 index 00000000..baa3f2b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts @@ -0,0 +1,20 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable UART2-M0"; + compatible = "rockchip,rk3328"; + category = "misc"; + exclusive = "GPIO1_A0", "GPIO1_A1"; + description = "Enable UART2-M0"; + }; + + fragment@0 { + target = <&uart2>; + + __overlay__ { + status = "okay"; + }; + }; +}; From 4c31668b4746e9d65b08d8d04c7a09f2eae31ad0 Mon Sep 17 00:00:00 2001 From: Chuang Ma Date: Tue, 10 Oct 2023 16:48:51 +0800 Subject: [PATCH 2/2] Add pinctrl definition Signed-off-by: Chuang Ma --- arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts | 2 ++ arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts | 2 ++ arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts | 2 ++ arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts index 6198a323..dc954927 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-pwm2.dts @@ -15,6 +15,8 @@ __overlay__ { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts index 0944a1fc..ddc26f73 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-spi0-spidev.dts @@ -15,6 +15,8 @@ __overlay__ { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts index 7ad4d319..e2c62337 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart1.dts @@ -15,6 +15,8 @@ __overlay__ { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts index baa3f2b9..be8e6720 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3328-uart2-m0.dts @@ -15,6 +15,8 @@ __overlay__ { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; }; }; };