-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathFPGAaudio.flow.rpt
132 lines (111 loc) · 8.93 KB
/
FPGAaudio.flow.rpt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Flow report for FPGAaudio
Tue Apr 26 23:01:37 2022
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Tue Apr 26 23:01:37 2022 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; FPGAaudio ;
; Top-level Entity Name ; FPGAaudio ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Total logic elements ; 116 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 114 / 114,480 ( < 1 % ) ;
; Dedicated logic registers ; 75 / 114,480 ( < 1 % ) ;
; Total registers ; 75 ;
; Total pins ; 9 / 529 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/26/2022 23:00:58 ;
; Main task ; Compilation ;
; Revision Name ; FPGAaudio ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+-------------------------------------------+---------------+-------------+----------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+-------------------------------------------+---------------+-------------+----------------------+
; COMPILER_SIGNATURE_ID ; 93383146214527.165102845802624 ; -- ; -- ; -- ;
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Custom ; <None> ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ;
; EDA_INPUT_DATA_FORMAT ; Edif ; -- ; -- ; eda_design_synthesis ;
; EDA_NETLIST_WRITER_OUTPUT_DIR ; C:/altera/13.1/FPGAaudio/simulation/qsim/ ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+-------------------------------------------+---------------+-------------+----------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4619 MB ; 00:00:02 ;
; Fitter ; 00:00:21 ; 1.3 ; 5375 MB ; 00:00:25 ;
; Assembler ; 00:00:06 ; 1.0 ; 4609 MB ; 00:00:06 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.5 ; 4709 MB ; 00:00:03 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4554 MB ; 00:00:01 ;
; Total ; 00:00:32 ; -- ; -- ; 00:00:37 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-0L208J0 ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-0L208J0 ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-0L208J0 ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-0L208J0 ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-0L208J0 ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off FPGAaudio -c FPGAaudio
quartus_fit --read_settings_files=off --write_settings_files=off FPGAaudio -c FPGAaudio
quartus_asm --read_settings_files=off --write_settings_files=off FPGAaudio -c FPGAaudio
quartus_sta FPGAaudio -c FPGAaudio
quartus_eda --read_settings_files=off --write_settings_files=off FPGAaudio -c FPGAaudio