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lis2duxs12_reg.c
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/*
******************************************************************************
* @file lis2duxs12_reg.c
* @author Sensors Software Solution Team
* @brief LIS2DUXS12 driver file
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2022 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "lis2duxs12_reg.h"
/**
* @defgroup LIS2DUXS12
* @brief This file provides a set of functions needed to drive the
* lis2duxs12 sensor.
* @{
*
*/
/**
* @defgroup LIS2DUXS12_Interfaces_Functions
* @brief This section provide a set of functions used to read and
* write a generic register of the device.
* MANDATORY: return 0 -> no Error.
* @{
*
*/
/**
* @brief Read generic device register
*
* @param ctx read / write interface definitions(ptr)
* @param reg register to read
* @param data pointer to buffer that store the data read(ptr)
* @param len number of consecutive register to read
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak lis2duxs12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len)
{
if (ctx == NULL)
{
return -1;
}
return ctx->read_reg(ctx->handle, reg, data, len);
}
/**
* @brief Write generic device register
*
* @param ctx read / write interface definitions(ptr)
* @param reg register to write
* @param data pointer to data to write in register reg(ptr)
* @param len number of consecutive register to write
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t __weak lis2duxs12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
uint16_t len)
{
if (ctx == NULL)
{
return -1;
}
return ctx->write_reg(ctx->handle, reg, data, len);
}
/**
* @}
*
*/
/**
* @defgroup LIS2DUXS12_Sensitivity
* @brief These functions convert raw-data into engineering units.
* @{
*
*/
float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb)
{
return (float_t)lsb * 0.061f;
}
float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb)
{
return (float_t)lsb * 0.122f;
}
float_t lis2duxs12_from_fs8g_to_mg(int16_t lsb)
{
return (float_t)lsb * 0.244f;
}
float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb)
{
return (float_t)lsb * 0.488f;
}
float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb)
{
return ((float_t)lsb / 355.5f) + 25.0f;
}
float_t lis2duxs12_from_lsb_to_mv(int16_t lsb)
{
return ((float_t)lsb) / 74.4f;
}
/**
* @}
*
*/
/**
* @defgroup Common
* @brief Common
* @{/
*
*/
/**
* @brief Device ID.[get]
*
* @param ctx read / write interface definitions
* @param val Device ID.
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WHO_AM_I, val, 1);
return ret;
}
/**
* @brief Configures the bus operating mode.[get]
*
* @param ctx communication interface handler.(ptr)
* @param val configures the bus operating mode.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val)
{
lis2duxs12_ctrl1_t ctrl1;
lis2duxs12_ctrl4_t ctrl4;
lis2duxs12_status_t status;
uint8_t cnt = 0;
int32_t ret = 0;
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
switch (val)
{
case LIS2DUXS12_BOOT:
ctrl4.boot = PROPERTY_ENABLE;
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
if (ret != 0)
{
break;
}
do
{
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
if (ret != 0)
{
break;
}
/* boot procedure ended correctly */
if (ctrl4.boot == 0U)
{
break;
}
if (ctx->mdelay != NULL)
{
ctx->mdelay(25); /* 25 ms of boot time */
}
} while (cnt++ < 5U);
if (cnt >= 5U)
{
ret = -1; /* boot procedure failed */
}
break;
case LIS2DUXS12_RESET:
ctrl1.sw_reset = PROPERTY_ENABLE;
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
if (ret != 0)
{
break;
}
do
{
ret = lis2duxs12_status_get(ctx, &status);
if (ret != 0)
{
break;
}
/* sw-reset procedure ended correctly */
if (status.sw_reset == 0U)
{
break;
}
if (ctx->mdelay != NULL)
{
ctx->mdelay(1); /* should be 50 us */
}
} while (cnt++ < 5U);
if (cnt >= 5U)
{
ret = -1; /* sw-reset procedure failed */
}
break;
case LIS2DUXS12_SENSOR_ONLY_ON:
/* no embedded funcs are used */
ctrl4.emb_func_en = PROPERTY_DISABLE;
ctrl4.bdu = PROPERTY_ENABLE;
ctrl1.if_add_inc = PROPERTY_ENABLE;
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
break;
case LIS2DUXS12_SENSOR_EMB_FUNC_ON:
/* complete configuration is used */
ctrl4.emb_func_en = PROPERTY_ENABLE;
ctrl4.bdu = PROPERTY_ENABLE;
ctrl1.if_add_inc = PROPERTY_ENABLE;
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
break;
default:
ctrl1.sw_reset = PROPERTY_ENABLE;
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
break;
}
return ret;
}
/**
* @brief Get the status of the device.[get]
*
* @param ctx communication interface handler.(ptr)
* @param val the status of the device.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val)
{
lis2duxs12_status_register_t status_register;
lis2duxs12_ctrl1_t ctrl1;
lis2duxs12_ctrl4_t ctrl4;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS,
(uint8_t *)&status_register, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
val->sw_reset = ctrl1.sw_reset;
val->boot = ctrl4.boot;
val->drdy = status_register.drdy;
return ret;
}
/**
* @brief Get the status of the embedded funcs.[get]
*
* @param ctx communication interface handler.(ptr)
* @param val the status of the embedded funcs.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val)
{
lis2duxs12_emb_func_status_t status;
int32_t ret;
ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t *)&status, 1);
ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK);
val->is_step_det = status.is_step_det;
val->is_tilt = status.is_tilt;
val->is_sigmot = status.is_sigmot;
return ret;
}
/**
* @brief Enables pulsed data-ready mode (~75 us).[set]
*
* @param ctx read / write interface definitions
* @param val DRDY_LATCHED, DRDY_PULSED,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val)
{
lis2duxs12_ctrl1_t ctrl1;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
if (ret == 0)
{
ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U);
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
}
return ret;
}
/**
* @brief Enables pulsed data-ready mode (~75 us).[get]
*
* @param ctx read / write interface definitions
* @param val DRDY_LATCHED, DRDY_PULSED,
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val)
{
lis2duxs12_ctrl1_t ctrl1;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1);
switch ((ctrl1.drdy_pulsed))
{
case 0x0:
*val = LIS2DUXS12_DRDY_LATCHED;
break;
case 0x1:
*val = LIS2DUXS12_DRDY_PULSED;
break;
default:
*val = LIS2DUXS12_DRDY_LATCHED;
break;
}
return ret;
}
/**
* @brief Sensor mode.[set]
*
* @param ctx communication interface handler.(ptr)
* @param val set the sensor FS and ODR.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val)
{
lis2duxs12_ctrl3_t ctrl3;
lis2duxs12_ctrl5_t ctrl5;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
ctrl5.odr = (uint8_t)val->odr & 0xFU;
ctrl5.fs = (uint8_t)val->fs;
/* set the bandwidth */
switch (val->odr)
{
/* no anti-aliasing filter present */
case LIS2DUXS12_OFF:
case LIS2DUXS12_1Hz6_ULP:
case LIS2DUXS12_3Hz_ULP:
case LIS2DUXS12_25Hz_ULP:
ctrl5.bw = 0x0;
break;
/* low-power mode with ODR < 50 Hz */
case LIS2DUXS12_6Hz_LP:
switch (val->bw)
{
default:
case LIS2DUXS12_ODR_div_2:
case LIS2DUXS12_ODR_div_4:
case LIS2DUXS12_ODR_div_8:
/* value not allowed */
ret = -1;
break;
case LIS2DUXS12_ODR_div_16:
ctrl5.bw = 0x3;
break;
}
break;
case LIS2DUXS12_12Hz5_LP:
switch (val->bw)
{
default:
case LIS2DUXS12_ODR_div_2:
case LIS2DUXS12_ODR_div_4:
/* value not allowed */
ret = -1;
break;
case LIS2DUXS12_ODR_div_8:
ctrl5.bw = 0x2;
break;
case LIS2DUXS12_ODR_div_16:
ctrl5.bw = 0x3;
break;
}
break;
case LIS2DUXS12_25Hz_LP:
switch (val->bw)
{
default:
case LIS2DUXS12_ODR_div_2:
/* value not allowed */
ret = -1;
break;
case LIS2DUXS12_ODR_div_4:
ctrl5.bw = 0x1;
break;
case LIS2DUXS12_ODR_div_8:
ctrl5.bw = 0x2;
break;
case LIS2DUXS12_ODR_div_16:
ctrl5.bw = 0x3;
break;
}
break;
/* standard cases */
case LIS2DUXS12_50Hz_LP:
case LIS2DUXS12_100Hz_LP:
case LIS2DUXS12_200Hz_LP:
case LIS2DUXS12_400Hz_LP:
case LIS2DUXS12_800Hz_LP:
case LIS2DUXS12_TRIG_PIN:
case LIS2DUXS12_TRIG_SW:
case LIS2DUXS12_6Hz_HP:
case LIS2DUXS12_12Hz5_HP:
case LIS2DUXS12_25Hz_HP:
case LIS2DUXS12_50Hz_HP:
case LIS2DUXS12_100Hz_HP:
case LIS2DUXS12_200Hz_HP:
case LIS2DUXS12_400Hz_HP:
case LIS2DUXS12_800Hz_HP:
default:
ctrl5.bw = (uint8_t)val->bw;
break;
}
if (ret != 0)
{
return ret;
}
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U;
if (ret == 0)
{
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
}
return ret;
}
/**
* @brief Sensor mode.[get]
*
* @param ctx communication interface handler.(ptr)
* @param val get the sensor FS and ODR.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val)
{
lis2duxs12_ctrl3_t ctrl3;
lis2duxs12_ctrl5_t ctrl5;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
switch (ctrl5.odr)
{
case 0x00:
val->odr = LIS2DUXS12_OFF;
break;
case 0x01:
val->odr = LIS2DUXS12_1Hz6_ULP;
break;
case 0x02:
val->odr = LIS2DUXS12_3Hz_ULP;
break;
case 0x03:
val->odr = LIS2DUXS12_25Hz_ULP;
break;
case 0x04:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_6Hz_HP : LIS2DUXS12_6Hz_LP;
break;
case 0x05:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_12Hz5_HP : LIS2DUXS12_12Hz5_LP;
break;
case 0x06:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_25Hz_HP : LIS2DUXS12_25Hz_LP;
break;
case 0x07:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_50Hz_HP : LIS2DUXS12_50Hz_LP;
break;
case 0x08:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_100Hz_HP : LIS2DUXS12_100Hz_LP;
break;
case 0x09:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_200Hz_HP : LIS2DUXS12_200Hz_LP;
break;
case 0x0A:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_400Hz_HP : LIS2DUXS12_400Hz_LP;
break;
case 0x0B:
val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_800Hz_HP : LIS2DUXS12_800Hz_LP;
break;
case 0xe:
val->odr = LIS2DUXS12_TRIG_PIN;
break;
case 0xf:
val->odr = LIS2DUXS12_TRIG_SW;
break;
default:
val->odr = LIS2DUXS12_OFF;
break;
}
switch (ctrl5.fs)
{
case 0:
val->fs = LIS2DUXS12_2g;
break;
case 1:
val->fs = LIS2DUXS12_4g;
break;
case 2:
val->fs = LIS2DUXS12_8g;
break;
case 3:
val->fs = LIS2DUXS12_16g;
break;
default:
val->fs = LIS2DUXS12_2g;
break;
}
switch (ctrl5.bw)
{
case 0:
val->bw = LIS2DUXS12_ODR_div_2;
break;
case 1:
val->bw = LIS2DUXS12_ODR_div_4;
break;
case 2:
val->bw = LIS2DUXS12_ODR_div_8;
break;
case 3:
val->bw = LIS2DUXS12_ODR_div_16;
break;
default:
val->bw = LIS2DUXS12_ODR_div_2;
break;
}
return ret;
}
/**
* @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[set]
*
* @param ctx read / write interface definitions
* @param val 1: disable temp acquisition - 0: enable temp acquisition
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2duxs12_self_test_t temp;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
if (ret == 0)
{
temp.t_ah_qvar_dis = val;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
}
return ret;
}
/**
* @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[get]
*
* @param ctx read / write interface definitions
* @param val 1: disable temp acquisition - 0: enable temp acquisition
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val)
{
lis2duxs12_self_test_t temp;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1);
*val = temp.t_ah_qvar_dis;
return ret;
}
/**
* @brief Enter deep power down[set]
*
* @param ctx read / write interface definitions
* @param val Enter deep power down
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2duxs12_sleep_t sleep;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
if (ret == 0)
{
sleep.deep_pd = val;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SLEEP, (uint8_t *)&sleep, 1);
}
return ret;
}
/**
* @brief Enter soft power down in SPI case[set]
*
* @param ctx read / write interface definitions
* @param val Enter soft power down in SPI case
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_exit_deep_power_down(const stmdev_ctx_t *ctx)
{
lis2duxs12_en_device_config_t en_device_config = {0};
int32_t ret;
en_device_config.soft_pd = PROPERTY_ENABLE;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EN_DEVICE_CONFIG, (uint8_t *)&en_device_config, 1);
if (ctx->mdelay != NULL)
{
ctx->mdelay(25); /* See AN5812 - paragraphs 3.1.1.1 and 3.1.1.2 */
}
return ret;
}
/**
* @brief Software trigger for One-Shot.[get]
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md)
{
lis2duxs12_ctrl4_t ctrl4;
int32_t ret = 0;
if (md->odr == LIS2DUXS12_TRIG_SW)
{
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
ctrl4.soc = PROPERTY_ENABLE;
if (ret == 0)
{
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1);
}
}
return ret;
}
int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val)
{
lis2duxs12_status_register_t status;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t *)&status, 1);
val->drdy = status.drdy;
if (ret == 0 && status.int_global == 0x1U)
{
lis2duxs12_wake_up_src_t wu_src;
lis2duxs12_tap_src_t tap_src;
lis2duxs12_sixd_src_t sixd_src;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t *)&sixd_src, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t *)&tap_src, 1);
val->six_d = sixd_src.d6d_ia;
val->six_d_xl = sixd_src.xl;
val->six_d_xh = sixd_src.xh;
val->six_d_yl = sixd_src.yl;
val->six_d_yh = sixd_src.yh;
val->six_d_zl = sixd_src.zl;
val->six_d_zh = sixd_src.zh;
val->wake_up = wu_src.wu_ia;
val->wake_up_z = wu_src.z_wu;
val->wake_up_y = wu_src.y_wu;
val->wake_up_x = wu_src.x_wu;
val->free_fall = wu_src.ff_ia;
val->sleep_change = wu_src.sleep_change_ia;
val->sleep_state = wu_src.sleep_state;
val->single_tap = tap_src.single_tap_ia;
val->double_tap = tap_src.double_tap_ia;
val->triple_tap = tap_src.triple_tap_ia;
}
return ret;
}
/**
* @brief Accelerometer data.[get]
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
* @param data data retrived from the sensor.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md,
lis2duxs12_xl_data_t *data)
{
uint8_t buff[6];
int32_t ret;
uint8_t i;
uint8_t j;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_X_L, buff, 6);
/* acceleration conversion */
j = 0U;
for (i = 0U; i < 3U; i++)
{
data->raw[i] = (int16_t)buff[j + 1U];
data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j];
j += 2U;
switch (md->fs)
{
case LIS2DUXS12_2g:
data->mg[i] = lis2duxs12_from_fs2g_to_mg(data->raw[i]);
break;
case LIS2DUXS12_4g:
data->mg[i] = lis2duxs12_from_fs4g_to_mg(data->raw[i]);
break;
case LIS2DUXS12_8g:
data->mg[i] = lis2duxs12_from_fs8g_to_mg(data->raw[i]);
break;
case LIS2DUXS12_16g:
data->mg[i] = lis2duxs12_from_fs16g_to_mg(data->raw[i]);
break;
default:
data->mg[i] = 0.0f;
break;
}
}
return ret;
}
/**
* @brief OUTT data.[get]
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
* @param data data retrived from the sensor.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx,
lis2duxs12_outt_data_t *data)
{
uint8_t buff[2];
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
data->heat.raw = (int16_t)buff[1U];
data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0];
/* temperature conversion */
data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw);
return ret;
}
/**
* @brief AH_QVAR data.[get]
*
* @param ctx communication interface handler.(ptr)
* @param md the sensor conversion parameters.(ptr)
* @param data data retrived from the sensor.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx,
lis2duxs12_ah_qvar_data_t *data)
{
uint8_t buff[2];
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_OUT_T_AH_QVAR_L, buff, 2);
data->raw = (int16_t)buff[1U];
data->raw = (data->raw * 256) + (int16_t) buff[0];
data->mv = lis2duxs12_from_lsb_to_mv(data->raw);
return ret;
}
/**
* @brief Configures the self test.[set]
*
* @param ctx communication interface handler.(ptr)
* @param val self test mode.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val)
{
lis2duxs12_ctrl3_t ctrl3;
lis2duxs12_wake_up_dur_t wkup_dur;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
switch (val)
{
case LIS2DUXS12_XL_ST_POSITIVE:
ctrl3.st_sign_x = 1;
ctrl3.st_sign_y = 1;
wkup_dur.st_sign_z = 0;
break;
case LIS2DUXS12_XL_ST_NEGATIVE:
ctrl3.st_sign_x = 0;
ctrl3.st_sign_y = 0;
wkup_dur.st_sign_z = 1;
break;
case LIS2DUXS12_XL_ST_DISABLE:
default:
ret = -1;
break;
}
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1);
ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
return ret;
}
/**
* @brief Configures the self test.[start]
*
* @param ctx communication interface handler.(ptr)
* @param val valid values 2 (1st step) or 1 (2nd step)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val)
{
lis2duxs12_self_test_t self_test;
int32_t ret;
if (val != 1U && val != 2U)
{
return -1;
}
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
if (ret == 0)
{
self_test.st = (uint8_t) val;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
}
return ret;
}
/**
* @brief Configures the self test.[stop]
*
* @param ctx communication interface handler.(ptr)
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_self_test_stop(const stmdev_ctx_t *ctx)
{
lis2duxs12_self_test_t self_test;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
if (ret == 0)
{
self_test.st = 0;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1);
}
return ret;
}
/**
* @brief Configures I3C bus.[set]
*
* @param ctx communication interface handler.(ptr)
* @param val configuration params
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/
int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i3c_cfg_t *val)
{
lis2duxs12_i3c_if_ctrl_t i3c_cfg;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
if (ret == 0)
{
i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel;
i3c_cfg.dis_drstdaa = val->drstdaa_en;
i3c_cfg.asf_on = val->asf_on;
ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
}
return ret;
}
/**
* @brief Configures I3C bus.[get]
*
* @param ctx communication interface handler.(ptr)
* @param val configuration params
* @retval interface status (MANDATORY: return 0 -> no Error)
*
*/int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val)
{
lis2duxs12_i3c_if_ctrl_t i3c_cfg;
int32_t ret;
ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
val->drstdaa_en = i3c_cfg.dis_drstdaa;
val->asf_on = i3c_cfg.asf_on;
switch (val->bus_act_sel)
{
case LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US:
val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US;
break;
case LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US:
val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US;
break;
case LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS:
val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS;
break;